Memory training method and device, electronic equipment and storage medium

Abstract

The application provides a memory training method and device, electronic equipment and a storage medium, wherein the method comprises: dividing memory training code in a BIOS startup process of a server based on a plurality of memory modules in the server to obtain memory training code corresponding to each memory module; distributing the memory training code corresponding to each memory module to each core of a processor in the server, so that each core executes a memory training process of the corresponding memory module based on the distributed code in the BIOS startup process; and determining that the memory training of the server is completed based on the value of a memory training flag bit of each core. Each core executes the memory training process of the plurality of memory modules in the server in parallel in the BIOS startup process, thereby quickly completing the memory training process. The memory training is executed in parallel by enabling multiple cores, thereby shortening the memory training time and further shortening the BIOS startup time.

Description

Technical Field

[0001] This invention relates to the field of server technology, and in particular to a memory training method, apparatus, electronic device, and storage medium. Background Technology

[0002] When a server boots up the Basic Input Output System (BIOS), especially during a cold boot, it needs to perform memory training.

[0003] Server memory training involves numerous testing algorithms and scenarios, accounting for a significant proportion of the total BIOS boot time. Therefore, enabling memory to complete training quickly and shorten BIOS boot time is a crucial issue that the industry urgently needs to address. Summary of the Invention

[0004] This invention provides a memory training method, apparatus, electronic device, and storage medium to achieve rapid memory training, thereby shortening BIOS boot time.

[0005] This invention provides a memory training method, comprising the following steps: Based on multiple memory modules in the server, the memory training code in the BIOS boot process of the server's basic input / output system is divided to obtain the memory training code corresponding to each memory module. The memory training code corresponding to each memory module is allocated to each core of the processor in the server, so that each core executes the memory training process of the corresponding memory module based on the allocated code during the BIOS boot process. Based on the values ​​of the memory training flags of each kernel, it is determined that the memory training of the server is complete. The memory training flags are stored in the kernel registers and are used to mark the memory training status of the memory modules corresponding to the kernels.

[0006] According to a memory training method provided by the present invention, the memory training code in the BIOS boot process of the server is divided based on multiple memory modules in the server to obtain memory training code corresponding to each memory module, including: Based on the multiple memory modules in the server, the starting position code for memory training of each memory module is determined by searching in the memory training code of the BIOS boot process. Based on the starting position code, the memory training code in the BIOS boot process is divided to obtain the memory training code corresponding to each memory module.

[0007] According to a memory training method provided by the present invention, the step of allocating memory training code corresponding to each memory module to each core of the processor in the server, so that each core executes the memory training process of the corresponding memory module based on the allocated code during the BIOS boot process, includes: The starting position code for memory training is based on each memory module. The starting code address is allocated in the reset address register of each core of the processor. The starting code address is used to determine the address corresponding to the code to be executed. Each kernel is de-reset so that after the kernel is de-reset, it can execute the memory training process of the corresponding memory module. The kernel executes the memory training process for the corresponding memory module, including: The kernel number stored in the kernel register is read, and based on the kernel number and the starting code address stored in the kernel's reset address register, the execution location of the memory training code in the BIOS boot process is determined. Based on the execution location, the allocated execution code is determined to execute the memory training process of the corresponding memory module.

[0008] According to a memory training method provided by the present invention, before allocating the memory training code corresponding to each memory module to each core of the processor in the server, the method further includes: The code of the BIOS boot process is divided into BIOS pre-initialization code and memory training code during the BIOS boot process. The BIOS pre-initialization code is used to perform the initialization process before memory training. It is confirmed that the initialization code has been executed successfully.

[0009] According to a memory training method provided by the present invention, determining the completion of memory training of the server based on reading the values ​​of memory training flag bits of each kernel includes: The system continuously reads the values ​​of the memory training flags of each kernel. Based on the values ​​of the memory training flags of all kernels in the server, and if it is determined that the memory module corresponding to each kernel has completed training, then the memory training of the server is considered complete.

[0010] According to the memory training method provided by the present invention, The step of allocating the memory training code corresponding to each memory module to each core of the processor in the server includes: Obtain the non-uniform memory access NUMA topology mapping of the processor; Based on the NUMA topology correspondence, the correspondence between the kernels and memory in the processor is determined, and based on the correspondence between the kernels and memory, the memory training code corresponding to each memory module is allocated to each kernel of the processor in the server.

[0011] According to a memory training method provided by the present invention, after determining that the memory training of the server is complete, the method further includes: The master core is determined from multiple cores in the processor, and the subsequent BIOS boot process is executed based on the master core. All slave cores are stopped from running until the BIOS boot is complete. The slave cores are the cores in the processor other than the master core.

[0012] The present invention also provides a memory training device, comprising the following modules: The partitioning module is used to partition the memory training code in the BIOS boot process of the server based on multiple memory modules in the server, so as to obtain the memory training code corresponding to each memory module. The allocation module is used to allocate the memory training code corresponding to each memory module to each core of the processor in the server, so that each core can execute the memory training process of the corresponding memory module based on the allocated code during the BIOS boot process. The memory training module is used to determine the completion of memory training of the server based on the value of the memory training flag bit of each kernel. The memory training flag bit is stored in the kernel register and is used to mark the memory training status of the memory module corresponding to the kernel.

[0013] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the memory training method described above.

[0014] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the memory training method as described above.

[0015] The memory training method, apparatus, electronic device, and storage medium provided by this invention divide the memory training code during the BIOS boot process and allocate the memory training code corresponding to each memory module to various cores of the processor. This allows each core to execute the memory training process for multiple memory modules in the server in parallel based on the allocated code during the BIOS boot process, achieving rapid completion of the memory training process. By enabling multi-core parallel execution of memory training, the memory training time is shortened, thereby reducing BIOS boot time and improving user experience and work efficiency. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the BIOS boot process in the relevant methods.

[0018] Figure 2 This is a flowchart illustrating the memory training method provided by the present invention.

[0019] Figure 3 This is a schematic diagram of the structure of the BIOS boot code provided by this invention in the storage medium.

[0020] Figure 4 This is a schematic diagram of the memory training execution process of a multi-core processor provided by the present invention.

[0021] Figure 5 This is a schematic diagram of the memory training device provided by the present invention.

[0022] Figure 6 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0024] When a server boots into the BIOS, especially during a cold boot (where power is turned off and then on again), it needs to perform memory training. The reasons are as follows: Different memory modules (even those of the same specifications and model) may have subtle differences in physical characteristics. Memory training helps ensure that the memory controller can communicate with the memory modules in an optimal manner, thereby improving system stability and compatibility; memory training fine-tunes various parameters of the memory controller (such as timing and voltage) to achieve the best performance of the memory subsystem; memory training helps ensure the integrity and accuracy of data during the transfer from the memory controller to the memory modules; control signals, command signals, and clock signals arrive at Dual-Inline-Memory-Modules (DIMMs) at inconsistent times, and memory training aligns these signals; the memory access link consists of multiple parts, each of which can introduce clock asynchrony and sampling delay issues. Through memory training, each part can be aligned separately, making the hundreds of connections of the memory DIMM uniform.

[0025] The server memory training process involves a large number of test algorithms and test scenarios, accounting for a significant proportion of the total time spent in the entire BIOS boot process; however, memory training is usually an unavoidable and omitting process. For customers with requirements on server boot time, the long memory training time is a significant bottleneck.

[0026] The Unified Extensible Firmware Interface (UEFI) is a single-core, single-threaded framework. In related methods, the server BIOS uses the UEFI framework, meaning the entire BIOS boot process, including memory training, is completed by a single CPU core, denoted as CORE 0. Figure 1 This is a schematic diagram of the BIOS boot process in the relevant methods. Figure 1 The left side shows the BIOS boot process. Figure 1 The right side shows the structure of the BIOS code in the storage medium; After Core 0 boots, it fetches BIOS instruction code from Address A, the starting address of the BIOS initialization process, and executes it. The BIOS begins booting, but at this point, the CPU is still uninitialized and can only execute some simple basic instructions. Core 0 cannot directly begin memory training. Core 0 needs to perform initialization of some internal CPU buses and internal links before the CPU can function fully. Since the BIOS is based on the UEFI framework, Core 0 also needs to prepare the UEFI environment; after initializing UEFI, it can be used normally. These processes that Core 0 needs to complete before memory training are collectively referred to as BIOS pre-initialization. BIOS pre-initialization is completed independently by Core 0. After CORE 0 completes the initial BIOS initialization, it fetches and executes code from address B in the memory initialization code. CORE 0 then begins memory training until it completes training all memory. The entire process from startup to completion of memory training is handled solely by CORE 0.

[0027] After memory training is complete, CORE 0 continues to execute the BIOS until the BIOS boot process is complete.

[0028] The drawbacks of the relevant methods are: Since UEFI is a single-core, single-threaded framework, and the server BIOS adopts the UEFI architecture, the entire BIOS boot process, including memory training, can only be executed sequentially by CORE 0 alone. Since memory training itself is time-consuming, this results in a long BIOS boot time. Because the memory training process takes a long time, the BIOS startup time is also long. Some customers are sensitive to server startup time, which will significantly reduce their satisfaction with the company's products. This, in turn, reduces the company's competitiveness in the market and has a negative impact on the company's profits.

[0029] To address the shortcomings of related methods, this invention provides a memory training method. Figure 2 This is a flowchart illustrating the memory training method provided by the present invention, as shown below. Figure 2 As shown, the method includes the following: Step 210: Based on multiple memory modules in the server, divide the memory training code in the BIOS boot process of the server to obtain the memory training code corresponding to each memory module. Step 220: Distribute the memory training code corresponding to each memory module to each core of the processor in the server, so that each core can execute the memory training process of the corresponding memory module based on the distributed code during the BIOS startup process. Step 230: Based on reading the values ​​of the memory training flags of each kernel, determine that the memory training of the server is complete. The memory training flags are stored in the kernel registers and are used to mark the memory training status of the memory modules corresponding to the kernels.

[0030] The following example, using the execution of the memory training method provided by this invention by a processor core in a server, illustrates the technical solution of this invention in detail.

[0031] In step 210, based on multiple memory modules in the server, the memory training code in the BIOS boot process of the server is divided to obtain the memory training code corresponding to each memory module.

[0032] Servers contain multiple memory modules. Memory modules, also known as memory sticks or memory boards, are an important form of computer memory specifically designed for storing and retrieving data and instructions. They are a crucial component of computer memory; through memory modules, the CPU can quickly access data in memory, thereby improving system performance.

[0033] Obtain all code from the BIOS boot process in the server, and extract the memory training code from within that code. This memory training code is used during the server's BIOS boot process to train the memory modules within the server.

[0034] Based on the server's memory modules, the memory training code during the BIOS boot process is divided into memory training codes corresponding to each memory module. It should be noted that executing the memory training code corresponding to each memory module completes the memory training process for that module.

[0035] In step 220, the memory training code corresponding to each memory module is allocated to each core of the processor in the server, so that each core executes the memory training process of the corresponding memory module based on the allocated code during the BIOS startup process.

[0036] After dividing the memory training code throughout the BIOS boot process, the memory training code corresponding to each memory module is allocated to each core of the server's processor. The server's processor contains multiple cores.

[0037] Optionally, the allocation process can be implemented based on the Non-Uniform Memory Access (NUMA) topology mapping of the processor cores. Topology mapping is a core concept in NUMA architecture, describing the organization between processor (CPU) cores and memory modules. In NUMA architecture, the system is divided into multiple nodes, each containing memory modules and a set of associated CPU cores.

[0038] In a NUMA architecture, each processor core directly accesses the memory modules of its NUMA node. During the allocation process, based on the correspondence between memory and cores in the NUMA architecture, the memory training code corresponding to each memory module is allocated to each core of the processor in the server.

[0039] After allocation is completed, each kernel executes the allocated code during the BIOS boot process to implement the memory training process of the corresponding memory module.

[0040] Understandably, by using multiple kernels to perform the memory training process on multiple memory modules in the server in parallel, the efficiency of memory training during the BIOS boot process of the entire server can be greatly improved, and the BIOS boot time can be shortened.

[0041] In step 230, based on reading the values ​​of the memory training flags of each kernel, it is determined that the memory training of the server is complete. The memory training flags are stored in the kernel registers and are used to mark the memory training status of the memory modules corresponding to the kernels.

[0042] Optionally, a memory training flag can be set in the registers of each kernel. The initial value for the memory training flag is 0.

[0043] After the kernel executes the training code, the value of the memory training flag in that kernel is changed from 0 to 1. By traversing the memory training flags in all kernel registers, it can be determined whether all memory modules of the server have completed memory training, thereby determining whether the memory training process during the server BIOS boot process has been completed.

[0044] Optionally, the cores in the server's processor can be divided into CORE 0 to CORE n. CORE 0 is the master core, and CORE 1 to CORE n are slave cores. Memory training for the BIOS boot process can be implemented based on the master core CORE 0. The storage structure of the BIOS boot code in the storage medium can be divided into three parts, such as... Figure 3The schematic diagram of the BIOS boot code in the storage medium provided by this invention is shown. It is mainly divided into three parts: BIOS start position code, denoted as Address_A; BIOS initialization code; and BIOS memory training code, which is further divided into n parts, denoted as part(1,n). The addresses of these n parts in the storage medium are Address_B(1,n). These n training codes, part(1,n), are executed separately by the n CPU cores in the processor.

[0045] Specifically, the specific execution process can be as follows: Figure 4 The schematic diagram of the memory training execution process of the multi-core processor provided by this invention is shown.

[0046] Each CPU core has an MPID register, which stores the core number of the core. The MPID register value of core 0 is 0, the MPID register value of core 1 is 1, and so on. The MPID register value of core n is n. The CPU core determines which core is currently running and executing code by reading the value of its own MPID register. Figure 3 The BIOS start code Address_A is a piece of code that determines and jumps to different CPU cores. Its function is as follows: CPU Core reads the value of the MPID register. Based on the MPID value, CPU Core determines which CPU core is currently executing the code. If it's Core 0, Core doesn't jump and continues executing the code sequentially. If it's Core 1, Core 1 jumps directly to... Figure 3 In memory training code part 1, execution begins at address Address_B1; similarly, if it's CORE n, CORE n will directly jump to... Figure 3 The memory training code, part n, begins execution at address Address_Bn. Each CPU core has a reset address register, which specifies the starting address of the code execution after the CPU core is reset. Core 0's reset address register stores the starting address of the BIOS code, Address_A. Core 0 starts fetching code from Address_A and begins execution. Core 0 reads the MPID register; if the MPID value is 0, Core 0 confirms that it is currently executing code and continues executing the initial BIOS initialization code. This part of the code is executed independently by Core 0. After CORE 0 completes the initial BIOS initialization, it does not immediately begin memory training. After setting the reset address registers of all CORE (1,n) cores to Address_A, CORE 0 de-resets these n slave cores CORE (1,n). Taking CORE 1 as an example, CORE 1 starts up and fetches instructions from the BIOS starting address Address_A. CORE 1 reads the MPID register and confirms that it is currently fetching and executing instructions. CORE 1 then jumps directly to memory training code part 1 to fetch and execute instructions. After CORE 1 completes memory training code part 1, it sets Finish_Flag_1 to 1 (the default value of Finish_Flag_1 is 0) to mark that CORE 1 has completed memory training code part 1. Similar to CORE 1, all slave cores CORE (1,n) execute their respective memory training part (1,n) code in parallel; that is, CORE 2 executes part 2, and CORE n executes part n. CORE 0 continuously checks the value of Finish_Flag_(1,n) until all flags are 1, indicating that all slave cores have completed their respective memory training code. Only when all flags are 1 will CORE 0 continue execution; otherwise, CORE 0 will continue to wait. CORE 0 resets CORE (1,n), and all slave cores stop running; CORE 0 continues to run until the BIOS boot process is complete.

[0047] The memory training method provided by this invention divides the memory training code during the BIOS boot process and distributes the memory training code corresponding to each memory module to various cores of the processor. This allows each core to execute the memory training process for multiple memory modules in the server in parallel based on the allocated code during the BIOS boot process, achieving rapid completion of the memory training process. By enabling multi-core parallel execution of memory training, the memory training time is shortened, thereby reducing BIOS boot time and improving user experience and work efficiency.

[0048] In one embodiment, based on multiple memory modules in the server, the memory training code in the BIOS boot process of the server is divided to obtain the memory training code corresponding to each memory module. This includes: searching in the memory training code of the BIOS boot process based on the multiple memory modules in the server to determine the starting position code for memory training of each memory module; and dividing the memory training code in the BIOS boot process based on the starting position code to obtain the memory training code corresponding to each memory module.

[0049] Obtain the complete code of the server's BIOS boot process and identify the memory training code within it. After identifying the memory training code in the BIOS boot process, it's possible to determine the memory training code for each memory module from the memory training code within the BIOS boot process.

[0050] Search within the memory training code during the BIOS boot process to determine the starting location code for memory training of each memory module.

[0051] After determining the starting position code for memory training of each memory model, the memory training code in the BIOS boot process is divided based on multiple starting position codes to obtain the memory training code corresponding to each memory module.

[0052] In one embodiment, the memory training code corresponding to each memory module is allocated to each core of the processor in the server, so that each core executes the memory training process of the corresponding memory module based on the allocated code during the BIOS boot process. This includes: allocating a start code address in the reset address register of each core of the processor based on the start position code of the memory training of each memory module, wherein the start code address is used to determine the address corresponding to the code to be jumped to; resetting each core so that the core executes the memory training process of the corresponding memory module after the resetting is completed; the core executing the memory training process of the corresponding memory module includes: reading the core number stored in the core's register, and determining the execution position of the memory training code in the BIOS boot process based on the core number and the start code address stored in the reset address register of the core, and determining the allocated execution code based on the execution position to execute the memory training process of the corresponding memory module.

[0053] Based on the previously determined memory training start location code for each memory module, a corresponding start code address is assigned to each kernel.

[0054] Configure the reset address registers for each kernel. These registers store the starting address of the code that the kernel should jump to execute after a reset. For memory training, this starting address is a pointer to the code segment used for memory training during BIOS startup.

[0055] The starting code address of each kernel is written into its reset address register. This way, when the kernel is de-reset, it jumps to the corresponding memory training code based on this address.

[0056] After configuration is complete, the kernels in the processor are de-reset one by one. The de-reset operation causes the kernel to begin executing the code stored in the reset address register.

[0057] Each kernel can read its MPID register or other similar identifier at startup to determine its own kernel number or location. This kernel number is then used to determine which memory module's memory training code should be executed.

[0058] The MPID (Multiprocessor ID Register) is an important register in a multiprocessor system used to identify processor cores. It is typically used in multi-core or multiprocessor architectures to ensure that each processor can be uniquely identified and communicate with each other.

[0059] The kernel calculates the specific memory location to jump to for the execution of the training code based on its kernel number and the starting code address in the reset address register.

[0060] Once the kernel jumps to the correct execution location, it begins executing the memory training code for the corresponding memory module. This code performs a series of memory read, write, and test operations to verify the reliability and stability of the memory module.

[0061] In one embodiment, before allocating the memory training code corresponding to each memory module to each core of the processor in the server, the method further includes: dividing the code of the BIOS startup process to obtain BIOS pre-initialization code and memory training code during the BIOS startup process, wherein the BIOS pre-initialization code is used to execute the initialization process before memory training; and determining that the pre-initialization code has been executed.

[0062] Understandably, a series of initialization operations must be performed before the BIOS can be trained on memory.

[0063] The BIOS boot process code is divided into BIOS pre-initialization code and memory training code. First, the BIOS pre-initialization code is executed to complete the BIOS pre-initialization process.

[0064] After the BIOS completes the initial initialization process, the memory training process of the BIOS is completed based on the memory training code obtained in the BIOS boot process.

[0065] In one embodiment, determining the completion of memory training of the server based on reading the values ​​of the memory training flags of each kernel includes: cyclically reading the values ​​of the memory training flags of each kernel, and determining the completion of memory training of the server when the memory module corresponding to each kernel is determined to be trained based on the values ​​of the memory training flags of all kernels of the server.

[0066] Based on the values ​​of the memory training flags of all kernels of the server, the completion of memory module training for each kernel is determined, including: determining that the memory training of the server is complete when the memory training flags of all kernels of the server are 1; the memory training flags of each kernel are initialized to 0, and after the kernel completes the memory training of the corresponding memory module, the memory training flags in the kernel register are changed from 0 to 1.

[0067] During memory training, each kernel has a specific memory training flag to indicate whether the kernel has completed memory training. This flag's value (usually 0 or 1) indicates the memory training status: 0 indicates incomplete, and 1 indicates complete.

[0068] First, the memory training flags of all kernels are initialized to 0, indicating that memory training is not yet complete. Each kernel updates its memory training flag from 0 to 1 after completing memory training for its corresponding memory module. The status of each kernel's memory training flag is checked periodically.

[0069] By repeatedly reading the memory training flags of each kernel, it can be determined whether all kernels have completed memory training. When all kernel flags are 1, the server's memory training can be confirmed as successful. If any kernel's flag is still 0, the system needs to continue reading in a loop, waiting for all kernels to complete memory training.

[0070] In one embodiment, the step of allocating the memory training code corresponding to each memory module to each core of the processor in the server includes: obtaining the non-uniform memory access NUMA topology mapping relationship of the processor; determining the mapping relationship between the cores and memory in the processor based on the NUMA topology mapping relationship; and allocating the memory training code corresponding to each memory module to each core of the processor in the server based on the mapping relationship between the cores and memory.

[0071] The allocation process is implemented based on the Non-Uniform Memory Access (NUMA) topology mapping of processor cores. Topology mapping is a core concept in NUMA architecture, describing the organization between processor (CPU) cores and memory modules. In NUMA architecture, the system is divided into multiple nodes, each containing memory modules and a set of associated CPU cores.

[0072] After obtaining the NUMA topology mapping, it is necessary to further analyze the mapping relationship between each NUMA node and the processor. Based on the mapping relationship between NUMA nodes and processors, the mapping relationship between kernels and memory in the processor can be further determined.

[0073] Based on the kernel-memory mapping, the memory training code corresponding to the memory module is allocated to the corresponding kernel of the processor, thus realizing the allocation process of memory training code. It can be understood that by obtaining the processor's NUMA topology mapping, determining the kernel-memory mapping, and allocating memory training code based on the determined mapping, system resources can be utilized to the maximum extent and performance can be improved.

[0074] In one embodiment, after determining that the memory training of the server is complete, the method further includes: determining the master core from multiple cores in the processor, executing the subsequent BIOS boot process based on the master core, and stopping all slave cores from running until the BIOS boot is complete, wherein the slave cores are the cores in the processor other than the master core.

[0075] Once memory training is complete, the BIOS needs to continue with the subsequent boot process, during which it needs to manage the processor's multiple cores effectively.

[0076] The BIOS determines the master core from among the processor's multiple cores and then delegates the subsequent boot process to the master core. This includes a series of complex operations such as loading the operating system bootloader, initializing hardware devices, and configuring system parameters.

[0077] Slave cores are the processor's cores other than the master core. After memory training is complete, to optimize system resource usage and reduce potential interference, these slave cores are stopped from running until the BIOS boot process is complete. This strategy helps ensure that the master core can focus on executing the boot process without being affected by other core activities.

[0078] The memory training apparatus provided by the present invention will be described below. The memory training apparatus described below can be referred to in correspondence with the memory training method described above.

[0079] like Figure 5 As shown, the device includes: The partitioning module 510 is used to partition the memory training code in the BIOS boot process of the server based on multiple memory modules in the server, so as to obtain the memory training code corresponding to each memory module. The allocation module 520 is used to allocate the memory training code corresponding to each memory module to each core of the processor in the server, so that each core can execute the memory training process of the corresponding memory module based on the allocated code during the BIOS startup process. The memory training module 530 is used to determine the completion of memory training of the server based on the value of the memory training flag bit of each kernel. The memory training flag bit is stored in the kernel register and is used to mark the memory training status of the memory module corresponding to the kernel.

[0080] The memory training device provided by this invention divides the memory training code during the BIOS boot process and distributes the memory training code corresponding to each memory module to various cores of the processor. This allows each core to execute the memory training process for multiple memory modules in the server in parallel based on the allocated code during the BIOS boot process, achieving rapid completion of the memory training process. By enabling multi-core parallel execution of memory training, the memory training time is shortened, thereby reducing BIOS boot time and improving user experience and work efficiency.

[0081] In one embodiment, the partitioning module 510 is specifically used for: The memory training code in the BIOS boot process of the server is divided based on multiple memory modules in the server to obtain the memory training code corresponding to each memory module, including: Based on the multiple memory modules in the server, the starting position code for memory training of each memory module is determined by searching in the memory training code of the BIOS boot process. Based on the starting position code, the memory training code in the BIOS boot process is divided to obtain the memory training code corresponding to each memory module.

[0082] In one embodiment, the partitioning module 510 is further specifically used for: The step of allocating the memory training code corresponding to each memory module to each core of the processor in the server, so that each core executes the memory training process of the corresponding memory module based on the allocated code during the BIOS boot process, includes: The starting position code for memory training is based on each memory module. The starting code address is allocated in the reset address register of each core of the processor. The starting code address is used to determine the address corresponding to the code to be executed. Each kernel is de-reset so that after the kernel is de-reset, it can execute the memory training process of the corresponding memory module. The kernel executes the memory training process for the corresponding memory module, including: The kernel number stored in the kernel register is read, and based on the kernel number and the starting code address stored in the kernel's reset address register, the execution location of the memory training code in the BIOS boot process is determined. Based on the execution location, the allocated execution code is determined to execute the memory training process of the corresponding memory module.

[0083] In one embodiment, the allocation module 520 is specifically used for: Before allocating the memory training code corresponding to each memory module to each core of the processor in the server, the method further includes: The code of the BIOS boot process is divided into BIOS pre-initialization code and memory training code during the BIOS boot process. The BIOS pre-initialization code is used to perform the initialization process before memory training. It is confirmed that the initialization code has been executed successfully.

[0084] In one embodiment, the memory training module 530 is specifically used for: The step of determining the completion of memory training for the server based on the values ​​of the memory training flags of each kernel includes: The system continuously reads the values ​​of the memory training flags of each kernel. Based on the values ​​of the memory training flags of all kernels in the server, and if it is determined that the memory module corresponding to each kernel has completed training, then the memory training of the server is considered complete.

[0085] In one embodiment, the allocation module 520 is further configured to: The step of allocating the memory training code corresponding to each memory module to each core of the processor in the server includes: Obtain the non-uniform memory access NUMA topology mapping of the processor; Based on the NUMA topology correspondence, the correspondence between the kernels and memory in the processor is determined, and based on the correspondence between the kernels and memory, the memory training code corresponding to each memory module is allocated to each kernel of the processor in the server.

[0086] In one embodiment, the memory training module 530 is further configured to: After confirming that the server's memory training is complete, the process also includes: The master core is determined from multiple cores in the processor, and the subsequent BIOS boot process is executed based on the master core. All slave cores are stopped from running until the BIOS boot is complete. The slave cores are the cores in the processor other than the master core.

[0087] Figure 6 An example is a schematic diagram of the physical structure of an electronic device, such as... Figure 6 As shown, the electronic device may include: a processor 610, a communications interface 620, a memory 630, and a communication bus 640, wherein the processor 610, the communications interface 620, and the memory 630 communicate with each other through the communication bus 640. The processor 610 can call logical instructions in the memory 630 to execute a memory training method, which includes: dividing the memory training code in the BIOS boot process of the server based on multiple memory modules in the server to obtain the memory training code corresponding to each memory module; The memory training code corresponding to each memory module is allocated to each core of the processor in the server, so that each core executes the memory training process of the corresponding memory module based on the allocated code during the BIOS boot process. Based on the values ​​of the memory training flags of each kernel, it is determined that the memory training of the server is complete. The memory training flags are stored in the kernel registers and are used to mark the memory training status of the memory modules corresponding to the kernels.

[0088] Furthermore, the logical instructions in the aforementioned memory 630 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0089] On the other hand, the present invention also provides a computer program product, the computer program product including a computer program, the computer program being able to be stored on a non-transitory computer-readable storage medium, the computer program being executed by a processor, the computer being able to execute the memory training method provided by the above methods, the method including: based on multiple memory modules in a server, dividing the memory training code in the basic input / output system BIOS boot process of the server to obtain the memory training code corresponding to each memory module; The memory training code corresponding to each memory module is allocated to each core of the processor in the server, so that each core executes the memory training process of the corresponding memory module based on the allocated code during the BIOS boot process. Based on the values ​​of the memory training flags of each kernel, it is determined that the memory training of the server is complete. The memory training flags are stored in the kernel registers and are used to mark the memory training status of the memory modules corresponding to the kernels.

[0090] In another aspect, the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which is implemented by a processor to perform the memory training method provided by the above methods, the method comprising: dividing the memory training code in the basic input / output system BIOS boot process of the server based on multiple memory modules in the server, to obtain the memory training code corresponding to each memory module; The memory training code corresponding to each memory module is allocated to each core of the processor in the server, so that each core executes the memory training process of the corresponding memory module based on the allocated code during the BIOS boot process. Based on the values ​​of the memory training flags of each kernel, it is determined that the memory training of the server is complete. The memory training flags are stored in the kernel registers and are used to mark the memory training status of the memory modules corresponding to the kernels.

[0091] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0092] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0093] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory training method, characterized in that, The method includes: Based on multiple memory modules in the server, the memory training code in the BIOS boot process of the server's basic input / output system is divided to obtain the memory training code corresponding to each memory module. The memory training code corresponding to each memory module is allocated to each core of the processor in the server, so that each core executes the memory training process of the corresponding memory module based on the allocated code during the BIOS boot process. Based on the values ​​of the memory training flags of each kernel, it is determined that the memory training of the server is complete. The memory training flags are stored in the kernel registers and are used to mark the memory training status of the memory modules corresponding to the kernels. The step of allocating the memory training code corresponding to each memory module to each core of the processor in the server includes: Obtain the non-uniform memory access NUMA topology mapping of the processor; Based on the NUMA topology correspondence, the correspondence between the kernels and memory in the processor is determined, and based on the correspondence between the kernels and memory, the memory training code corresponding to each memory module is allocated to each kernel of the processor in the server.

2. The memory training method according to claim 1, characterized in that, The memory training code in the BIOS boot process of the server is divided based on multiple memory modules in the server to obtain the memory training code corresponding to each memory module, including: Based on the multiple memory modules in the server, the starting position code for memory training of each memory module is determined by searching in the memory training code of the BIOS boot process. Based on the starting position code, the memory training code in the BIOS boot process is divided to obtain the memory training code corresponding to each memory module.

3. The memory training method according to claim 2, characterized in that, The step of allocating the memory training code corresponding to each memory module to each core of the processor in the server, so that each core executes the memory training process of the corresponding memory module based on the allocated code during the BIOS boot process, includes: The starting position code for memory training is based on each memory module. The starting code address is allocated in the reset address register of each core of the processor. The starting code address is used to determine the address corresponding to the code to be executed. Each kernel is de-reset so that after the kernel is de-reset, it can execute the memory training process of the corresponding memory module. The kernel executes the memory training process for the corresponding memory module, including: The kernel number stored in the kernel register is read, and based on the kernel number and the starting code address stored in the kernel's reset address register, the execution location of the memory training code in the BIOS boot process is determined. Based on the execution location, the allocated execution code is determined to execute the memory training process of the corresponding memory module.

4. The memory training method according to claim 1, characterized in that, Before allocating the memory training code corresponding to each memory module to each core of the processor in the server, the method further includes: The code of the BIOS boot process is divided into BIOS pre-initialization code and memory training code during the BIOS boot process. The BIOS pre-initialization code is used to perform the initialization process before memory training. It is confirmed that the initialization code has been executed successfully.

5. The memory training method according to claim 1, characterized in that, The step of determining the completion of memory training for the server based on the values ​​of the memory training flags of each kernel includes: The system continuously reads the values ​​of the memory training flags of each kernel. Based on the values ​​of the memory training flags of all kernels in the server, and if it is determined that the memory module corresponding to each kernel has completed training, then the memory training of the server is considered complete.

6. The memory training method according to claim 1, characterized in that, After determining that the server's memory training is complete, the process further includes: The master core is determined from multiple cores in the processor, and the subsequent BIOS boot process is executed based on the master core. All slave cores are stopped from running until the BIOS boot is complete. The slave cores are the cores in the processor other than the master core.

7. A memory training device, characterized in that, include: The partitioning module is used to partition the memory training code in the BIOS boot process of the server based on multiple memory modules in the server, so as to obtain the memory training code corresponding to each memory module. The allocation module is used to allocate the memory training code corresponding to each memory module to each core of the processor in the server, so that each core can execute the memory training process of the corresponding memory module based on the allocated code during the BIOS boot process. The memory training module is used to determine the completion of memory training of the server based on the value of the memory training flag bit of each kernel. The memory training flag bit is stored in the kernel register and is used to mark the memory training status of the memory module corresponding to the kernel. The step of allocating the memory training code corresponding to each memory module to each core of the processor in the server includes: Obtain the non-uniform memory access NUMA topology mapping of the processor; Based on the NUMA topology correspondence, the correspondence between the kernels and memory in the processor is determined, and based on the correspondence between the kernels and memory, the memory training code corresponding to each memory module is allocated to each kernel of the processor in the server.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the memory training method as described in any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the memory training method as described in any one of claims 1 to 6.

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