Shift register and driving method thereof, gate driving circuit and display device

Abstract

The present disclosure provides a shift register and a driving method thereof, a gate driving circuit and a display device, and belongs to the technical field of display. The shift register comprises an input control sub-circuit configured to control the potential of a first node in response to an input signal transmitted by a signal input end, control the potential of a second node in response to a first clock signal transmitted by a first clock signal end, a cascade transmission sub-circuit configured to write the signal of the first node into a third node in response to a first control signal transmitted by a first control signal end, output a second clock signal transmitted by a second clock signal end through a cascade transmission end in response to the signal of the third node, and an output sub-circuit comprising a plurality of output units, wherein each output unit is configured to write the signal of the first node into a fourth node in response to a second control signal transmitted by a second control signal end, and output a third clock signal transmitted by a third clock signal end through a first output end in response to the signal of the fourth node.

Description

Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a shift register and its driving method, a gate driving circuit, and a display device. Background Technology

[0002] As display panel resolution (Pixels Per Inch, PPI) increases, the layout of Gate Drive on Array (GOA) circuits becomes increasingly difficult. In small-sized display panels, the vertical dimension of the GOA sub-circuit is typically roughly the same as the vertical dimension of a row of pixels. However, with the increase in PPI, in large-sized display panels, the vertical dimension of pixels shrinks, while the vertical dimension of the GOA sub-circuit (such as a shift register) remains unchanged. Therefore, the vertical dimension of a row of pixels cannot be aligned with the vertical dimension of a GOA sub-circuit. In large-sized display panels, as the number of pixel rows increases, the number of GOA sub-circuits also increases. This leads to insufficient vertical layout space for the GOA sub-circuits while maintaining a narrow bezel. Using a multi-column GOA sub-circuit layout inevitably increases the bezel size. Therefore, current technologies cannot achieve a GOA sub-circuit layout for high-PPI display panels while maintaining a narrow bezel. Summary of the Invention

[0003] This disclosure aims to at least solve one of the technical problems existing in the prior art, and to provide a shift register and its driving method, gate driving circuit and display device.

[0004] Firstly, the technical solution adopted to solve the technical problem of this disclosure is a shift register, including an input control sub-circuit, a cascaded transfer sub-circuit, and an output sub-circuit;

[0005] The input control sub-circuit is configured to control the potential of the first node in response to an input signal transmitted at the signal input terminal; and to control the potential of the second node in response to a first clock signal transmitted at the first clock signal terminal.

[0006] The cascaded transmission sub-circuit is configured to, in response to a first control signal transmitted from a first control signal terminal, write the signal of the first node into a third node; in response to a signal from the third node, output the second clock signal transmitted from a second clock signal terminal through the cascaded transmission terminal; or, in response to a signal from the second node, output the first power signal transmitted from a first power supply terminal through the cascaded transmission terminal.

[0007] The output sub-circuit includes multiple output units; each output unit is configured to, in response to a second control signal transmitted from a second control signal terminal, write the signal of the first node into a fourth node; in response to the signal of the fourth node, output the third clock signal transmitted from a third clock signal terminal through a first output terminal; or, in response to the signal of the second node, output the second power signal transmitted from a second power supply terminal through the first output terminal.

[0008] In some embodiments, the first output terminals of each of the output units are different; the different first output terminals are electrically connected to different gate lines.

[0009] In some embodiments, both the first control signal and the second control signal are AC signals.

[0010] In some embodiments, the effective potential of the second clock signal is the first voltage, and the invalid potential is the second voltage; the effective potential of the third clock signal is the first voltage, and the invalid potential is the second voltage; the first voltage is higher than the second voltage.

[0011] The effective potential of the first control signal is a third voltage, and the invalid potential is a fourth voltage; the effective potential of the second control signal is a third voltage, and the invalid potential is a fourth voltage; the third voltage is higher than the fourth voltage.

[0012] The third voltage is equal to the first voltage; the fourth voltage is higher than the sum of the second voltage and the threshold voltage.

[0013] In some embodiments, the second clock signal terminal is different from the third clock signal terminal; the third clock signal terminals of each of the output units are different.

[0014] In some embodiments, the effective potential of the first clock signal is a first voltage, and the invalid potential is the second voltage; the first voltage is higher than the second voltage.

[0015] The effective potential of the second clock signal is the first voltage, and the invalid potential is the second voltage;

[0016] The effective potential of the third clock signal is the first voltage, and the invalid potential is the second voltage.

[0017] In some embodiments, the first control signal terminal of the cascaded transmission sub-circuit and the second control signal terminal of each of the output units are the same.

[0018] In some embodiments, the cascaded transmission sub-circuit includes a ninth transistor, a third transistor, a fourth transistor, and a first capacitor;

[0019] The control electrode of the ninth transistor is electrically connected to the first control signal terminal, the first electrode is electrically connected to the third node, and the second electrode is electrically connected to the first node;

[0020] The control electrode of the third transistor is electrically connected to the third node, the first electrode is electrically connected to the second clock signal terminal, and the second electrode is electrically connected to the cascaded transmission terminal.

[0021] The control electrode of the fourth transistor is electrically connected to the second node, the first electrode is electrically connected to the cascaded transmission terminal, and the second electrode is electrically connected to the first power supply terminal.

[0022] The first plate of the first capacitor is electrically connected to the third node, and the second plate is electrically connected to the cascaded transmission end.

[0023] In some embodiments, the output unit includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a second capacitor;

[0024] The control electrode of the tenth transistor is electrically connected to the second control signal terminal, the first electrode is electrically connected to the fourth node, and the second electrode is electrically connected to the first node.

[0025] The control electrode of the eleventh transistor is electrically connected to the fourth node, the first electrode is electrically connected to the third clock signal terminal, and the second electrode is electrically connected to the first output terminal.

[0026] The control electrode of the twelfth transistor is electrically connected to the second node, the first electrode is electrically connected to the first output terminal, and the second electrode is electrically connected to the second power supply terminal.

[0027] The first plate of the second capacitor is electrically connected to the fourth node, and the second plate is electrically connected to the first output terminal.

[0028] In some embodiments, the input control sub-circuit includes a first transistor, a second transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a third capacitor;

[0029] The control electrode of the first transistor is electrically connected to the signal input terminal, the first electrode is electrically connected to the third power supply terminal, and the second electrode is electrically connected to the first node.

[0030] The control electrode of the second transistor is electrically connected to the first reset control terminal, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the fourth power supply terminal.

[0031] The control electrode of the fifth transistor is electrically connected to the second node, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the first power supply terminal.

[0032] The control electrode of the sixth transistor is electrically connected to the first node, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the first power supply terminal.

[0033] The control electrode of the seventh transistor is electrically connected to the first clock signal terminal, the first electrode is electrically connected to the first clock signal terminal, and the second electrode is electrically connected to the second node;

[0034] The first plate of the third capacitor is electrically connected to the second node, and the second plate is electrically connected to the first power supply terminal.

[0035] In some embodiments, the shift register further includes a frame reset sub-circuit; the frame reset sub-circuit includes an eighth transistor;

[0036] The control electrode of the eighth transistor is electrically connected to the second reset control terminal, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the first power supply terminal.

[0037] In a second aspect, embodiments of this disclosure also provide a gate driving circuit, which includes N cascaded shift registers as described in any one of the first aspects;

[0038] Except for the first-stage shift register, the signal input terminal of the (i+1)th stage shift register is electrically connected to the cascade transfer terminal of the i-th stage shift register; N is a positive integer greater than 1, and i is a positive integer less than or equal to N.

[0039] In some embodiments, the first clock signal terminal of the i-th stage shift register is electrically connected to the second clock signal terminal of the (i+1)-th stage shift register; the second clock signal terminal of the i-th stage shift register is electrically connected to the first clock signal terminal of the (i+1)-th stage shift register.

[0040] Thirdly, embodiments of this disclosure also provide a method for driving a shift register, wherein the shift register is a shift register as described in any one of the first aspects; the method for driving the shift register includes:

[0041] During the input phase, the input control sub-circuit responds to the input signal transmitted at the signal input terminal and controls the potential of the first node to a first voltage; the cascaded transmission sub-circuit responds to the third voltage of the first control signal and writes the first voltage of the first node into the third node; the output unit responds to the third voltage of the second control signal and writes the first voltage of the first node into the fourth node.

[0042] During the output phase, the cascaded transmission sub-circuit responds to the first voltage of the third node and outputs the second clock signal transmitted from the second clock signal terminal through the cascaded transmission terminal; the output unit responds to the first voltage of the fourth node and outputs the third clock signal transmitted from the third clock signal terminal through the first output terminal.

[0043] During the reset phase, the input control subcircuit responds to the first clock signal transmitted from the first clock signal terminal, controls the potential of the second node to a first voltage, and controls the potential of the first node to a second voltage; the cascaded transmission subcircuit responds to the first voltage of the second node, outputs the first power signal transmitted from the first power supply terminal through the cascaded transmission terminal; responds to the third voltage of the first control signal, writes the second voltage of the first node into the third node; the output unit responds to the first voltage of the second node, outputs the second power signal transmitted from the second power supply terminal through the first output terminal; responds to the third voltage of the second control signal, writes the second voltage of the first node into the fourth node;

[0044] During the holding phase, the cascaded transmission sub-circuit responds to the fourth voltage of the first control signal by writing the second voltage of the first node into the third node; the output unit responds to the fourth voltage of the second control signal by writing the second voltage of the first node into the fourth node.

[0045] The first voltage is higher than the second voltage; the third voltage is higher than the fourth voltage; the third voltage is equal to the first voltage; the fourth voltage is higher than the sum of the second voltage and the threshold voltage.

[0046] In some embodiments, the output phase further includes:

[0047] Under the control of the first voltage of the third node and the first voltage of the second clock signal, the cascaded transmission sub-circuit uses the first capacitor to pull up the first voltage of the third node to the fifth voltage.

[0048] The output unit, under the control of the first voltage of the fourth node and the first voltage of the third clock signal, uses the first capacitor to pull up the first voltage of the fourth node to the fifth voltage.

[0049] In some embodiments, the timing of the third clock signal of each of the output units is different.

[0050] In some embodiments, the timing of the third clock signal of some of the output units is the same, while the timing of the third clock signal of the remaining output units is different.

[0051] In some embodiments, both the first control signal and the second control signal are AC signals; the timing of the first control signal and the second control signal is the same.

[0052] Fourthly, embodiments of this disclosure also provide a display device, which includes a gate driving circuit as described in the second aspect. Attached Figure Description

[0053] Figure 1a This is a schematic diagram showing the correspondence between shift registers and pixel positions in a small-sized display panel.

[0054] Figure 1b This is a schematic diagram showing the correspondence between shift registers and pixel positions in a large-size display panel.

[0055] Figure 2 A schematic diagram of a shift register provided in an embodiment of this disclosure;

[0056] Figure 3 A scanning effect diagram within the human eye's gaze range under the timing control of a third clock signal, provided in an embodiment of this disclosure;

[0057] Figure 4 A schematic diagram of a circuit structure of a shift register provided in an embodiment of this disclosure;

[0058] Figure 5 A schematic diagram of another circuit structure of the shift register provided in the embodiments of this disclosure;

[0059] Figure 6 Timing diagram of the shift register operation phase provided in the embodiments of this disclosure

[0060] Figure 7 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present disclosure;

[0061] Figure 8 This is a schematic diagram of another gate drive circuit provided in an embodiment of the present disclosure;

[0062] Figure 9 A schematic diagram of the shift register cascade structure provided in the embodiments of this disclosure;

[0063] Figure 10 for Figure 9 Timing diagram of the cascaded structure shown;

[0064] Figure 11 This is a schematic diagram illustrating the correspondence between shift registers and pixel position layouts provided in embodiments of this disclosure. Detailed Implementation

[0065] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. The components of the embodiments of this disclosure described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure.

[0066] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0067] In this disclosure, "multiple or several" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0068] It should be noted that the transistors used in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no distinction between their source and drain. In the embodiments of this disclosure and the following description, to distinguish the source and drain of the transistor, one of the terminals is called the first terminal, the other is called the second terminal, and the gate is called the control terminal. In addition, according to the characteristics of the transistor, transistors can be divided into N-type and P-type. When a P-type transistor is used, the first terminal is the source of the P-type transistor, the second terminal is the drain of the P-type transistor, and the source and drain are turned on when a low-level signal is input to the gate. When an N-type transistor is used, the first terminal is the source of the N-type transistor, the second terminal is the drain of the N-type transistor, and the source and drain are turned on when a high-level signal is input to the gate.

[0069] In related technologies, typically one GOA sub-circuit is used to drive one row of pixels. For example... Figure 1a As shown, in a small-sized display panel, the vertical dimension Py2 of the GOA sub-circuit 01 is basically the same as the vertical dimension Py1 of a row of pixels 02. However, with the increase of PPI, as... Figure 1b As shown, in a large-size display panel, the vertical dimension Py1 of pixel 02 is reduced, denoted as Py3, while the vertical dimension of GOA sub-circuit 01 remains unchanged at its original size Py2. Therefore, the vertical dimension Py3 of a row of pixels 02 cannot be aligned with the vertical dimension Py2 of a single GOA sub-circuit 01; that is, the vertical dimension Py2 of a single GOA sub-circuit 01 is greater than the vertical dimension Py3 of a row of pixels 02. To achieve a high PPI, a portion of the bezel needs to be enlarged, requiring a dual-row layout to drive the pixels. Therefore, related technologies cannot achieve a high PPI display panel GOA sub-circuit layout while maintaining a narrow bezel.

[0070] In view of this, the present disclosure provides a shift register, which essentially changes the circuit structure of the original shift register and adds multiple output units to drive multiple rows of pixels respectively. That is, multiple rows of pixels can be driven by a single shift register, which can achieve a higher PPI while ensuring a narrow bezel.

[0071] Figure 2 A schematic diagram of a shift register provided in an embodiment of this disclosure, as shown below. Figure 2 As shown, the shift register includes an input control subcircuit 1, a cascaded transfer subcircuit 2, and an output subcircuit 33. The output subcircuit 33 includes multiple output units 31. The input control subcircuit 1 includes a signal input terminal Input and a first clock signal terminal CKB; the cascaded transfer subcircuit 2 includes a first control signal terminal VGH_G, a second clock signal terminal CKC, and a first power supply terminal L. VGLThe output unit 31 includes a second control signal terminal VGH_n, a third clock signal terminal CLK_n, a second power supply terminal VGL_G, and a first output terminal Out_n. Here, n represents the number of output units, meaning the output sub-circuit 33 includes n output units, where n is an integer greater than or equal to 2. For example, when n is 4, it means the output sub-circuit 3 includes 4 output units. The second control signal terminal of the first output unit 31 is denoted as VGH_1, the third clock signal terminal as CLK_1, the second power supply terminal as VGL_1, and the first output terminal as Out_1; the second control signal terminal of the second output unit 31 is denoted as VGH_2, the third clock signal terminal as CLK_2, the second power supply terminal as VGL_2, and the first output terminal as Out_2; the second control signal terminal of the third output unit 31 is denoted as VGH_3, the third clock signal terminal as CLK_3, the second power supply terminal as VGL_3, and the first output terminal as Out_3; the second control signal terminal of the fourth output unit 31 is denoted as VGH_4, the third clock signal terminal as CLK_4, the second power supply terminal as VGL_4, and the first output terminal as Out_4. Similarly, the second control signal terminal of the nth output unit 31 is denoted as VGH_n, the third clock signal terminal as CLK_n, the second power supply terminal as VGL_n, and the first output terminal as Out_n.

[0072] The Input terminal is used to receive input signals. For the first-stage shift register, the input signal is the start signal (STV). For the second to Nth-stage shift registers, the input signal is the signal output from the cascade transmission terminal of the previous-stage shift register. The first clock signal terminal CKB is used to receive the first clock signal; the second clock signal terminal CKC is used to receive the second clock signal; and the third clock signal terminal CKL_n is used to receive the third clock signal. The first clock signal terminal CKB, the second clock signal terminal CKC, and the third clock signal terminal CKL_n are different, therefore the first, second, and third clock signals are controlled independently. The first control signal terminal VGH_G is used to receive the first control signal; and the second control signal terminal VGH_n is used to receive the second control signal. The first power supply terminal L... VGL The first control signal terminal (VGH_G) is used to receive the first power signal; the second power signal terminal (VGH_G) is used to receive the second power signal. The first control signal terminal (VGH_G), the second control signal terminal (VGH_n), and the third control signal terminal can be the same or different.

[0073] Input control subcircuit 1 is configured to control the potential of the first node PUCN in response to the input signal transmitted at the signal input terminal Input; and to control the potential of the second node PD in response to the first clock signal transmitted at the first clock signal terminal CKB. Here, the potentials of the first node PUCN and the second node PD are opposite. For example, if the potential of the first node PUCN is a valid first voltage V1, the potential of the second node PD is an invalid second voltage V2; or if the potential of the first node PUCN is an invalid second voltage V2, the potential of the second node PD is a valid first voltage V1. Whether the potential of the first node PUCN is valid or invalid, or whether the potential of the second node PD is valid or invalid, determines the output result of the cascaded transfer subcircuit 2 and the output result of the output unit 31.

[0074] The cascaded transfer sub-circuit 2 and each output unit 31 share the same first node PUCN and the same second node PD.

[0075] Cascaded transfer sub-circuit 2 is configured to, in response to the first control signal transmitted at the first control signal terminal VGH_G, write the signal of the first node PUCN to the third node (not shown in the figure, see PUC in the figure below); in response to the signal of the third node, output the second clock signal transmitted at the second clock signal terminal CKC through the cascaded transfer terminal OutC; or, in response to the signal of the second node PD, output the first power supply terminal L... VGL The first power signal is output through the cascaded transmission terminal OutC. In one scenario, the potential of the first node PUCN is the first voltage V1, and the potential of the second node PD is the second voltage V2. In this case, the cascaded transmission sub-circuit 2, responding to the first control signal transmitted by the first control signal terminal VGH_G, writes the first voltage V1 of the first node PUCN into the third node. At this time, the voltage of the third node is valid; therefore, it can continue to respond to the first voltage V1 of the third node and output the second clock signal transmitted by the second clock signal terminal CKC through the cascaded transmission terminal OutC. Since the potential of the second node PD is the second voltage V2 at this time, the cascaded transmission sub-circuit 2 cannot output the first power supply terminal L. VGL The first power signal is transmitted. In another case, the potential of the first node PUCN is the second voltage V2, and the potential of the second node PD is the first voltage V1. The cascaded transmission sub-circuit 2 responds to the first control signal transmitted by the first control signal terminal VGH_G, writing the second voltage V2 of the first node PUCN into the third node. Since the voltage of the third node is invalid at this time, it cannot output the second clock signal transmitted by the second clock signal terminal CKC. However, the voltage of the second node PD is valid at this time, so the cascaded transmission sub-circuit 2 can respond to the first voltage V1 of the second node PD and output the first power terminal L using the cascaded transmission terminal OutC. VGL The first power signal transmitted.

[0076] Here, the cascaded transfer sub-circuit 2 mainly uses the cascaded transfer terminal OutC to output the cascaded signal (second clock signal or first power signal) as the input signal of the next stage (or several stages) shift register.

[0077] For any output unit 31, it is configured to, in response to the second control signal transmitted by the second control signal terminal VGH_n, write the signal of the first node PUCN into the fourth node (not shown in the figure, see PUn in the figure below); in response to the signal of the fourth node, output the third clock signal transmitted by the third clock signal terminal CKL_n through the first output terminal Out_n; or, in response to the signal of the second node PD, output the second power signal transmitted by the second power supply terminal VGL_G through the first output terminal Out_n. In one case, the potential of the first node PUCN is the first voltage V1, and the potential of the second node PD is the second voltage V2; at this time, the output unit 31, in response to the second control signal transmitted by the second control signal terminal VGH_n, writes the first voltage V1 of the first node PUCN into the fourth node. At this time, the voltage of the fourth node is valid, therefore, in response to the first voltage V1 of the fourth node, the third clock signal transmitted by the third clock signal terminal CKL_n can continue to be output through the first output terminal Out_n. Since the potential of the second node PD is the second voltage V2 at this time, the output unit 31 cannot output the second power signal transmitted by the second power supply terminal VGL_G. In another scenario, the potential of the first node PUCN is the second voltage V2, and the potential of the second node PD is the first voltage V1. The output unit 31, responding to the second control signal transmitted via the second control signal terminal VGH_n, writes the second voltage V2 of the first node PUCN into the fourth node. Since the voltage of the fourth node is invalid at this time, it cannot output the third clock signal transmitted via the third clock signal terminal CKL_n. However, the voltage of the second node PD is valid at this time, so the output unit 31 can respond to the first voltage V1 of the second node PD and output the second power signal transmitted via the second power supply terminal VGL_G via the first output terminal Out_n.

[0078] Here, a single output unit 31 primarily utilizes the signal (third clock signal or second power supply signal) output from its first output terminal Out_n as the gate drive signal for a specific row of pixels corresponding to the shift register. Optionally, the first output terminals Out_n of each output unit 31 are different; different first output terminals Out_n are electrically connected to different gate lines, that is, electrically connected to different rows of pixels. The same shift register can connect to multiple rows of pixels through multiple different first output terminals Out_n, and provide gate drive signals to multiple rows of pixels.

[0079] Here, the cascaded output terminal OutC is different from the first output terminal Out_n.

[0080] In this embodiment, the cascaded transfer sub-circuit 2 and the output unit 31 are independently configured, ensuring that the signals output by the cascaded transfer sub-circuit 2 and the output units 31 do not interfere with each other. Similarly, each output unit 31 is independently configured, ensuring that the signals output by each output unit 31 do not interfere with each other. Furthermore, multiple output units 31 can provide gate drive signals to multiple rows of pixels; that is, multiple rows of pixels can be driven using a single shift register, achieving a higher PPI while maintaining a narrow bezel.

[0081] In some embodiments, the second clock signal terminal CKC is different from the third clock signal terminal CKL_n; the third clock signal terminal CKL_n of each output unit 31 is also different. This allows the cascaded transmission sub-circuit and each output unit 31 to be independently controlled, ensuring that the cascaded signal and the output of each row gate drive signal, as well as the output of each row gate drive signal, do not interfere with each other. Furthermore, the different clock signal terminals allow for independent control of each clock signal, enabling flexible adjustment of the clock signal output timing.

[0082] Optionally, the timing of the third clock signal of each output unit 31 is different. It should be noted that timing in a circuit refers to the sequential switching of signals between high and low potentials. Different timing means that the potential transition times of the compared signals are inconsistent, but it does not mean that their potentials are different at the same time point. For example, the time when the third clock signal of the preceding output unit 31 transitions from an invalid potential to an effective potential is earlier than the time when the third clock signal of the following output unit transitions from an invalid potential to an effective potential. For example, as... Figure 2 As shown, the time when the third clock signal of the first output unit 31 transitions from an invalid potential to an effective potential is earlier than the time when the third clock signal of the second output unit 31 transitions from an invalid potential to an effective potential; the time when the third clock signal of the second output unit 31 transitions from an invalid potential to an effective potential is earlier than the time when the third clock signal of the third output unit 31 transitions from an invalid potential to an effective potential; and so on, the time when the third clock signal of the (n-1)th output unit 31 transitions from an invalid potential to an effective potential is earlier than the time when the third clock signal of the nth output unit 31 transitions from an invalid potential to an effective potential. Here, the timing sequence of the third clock signals of each output unit 31 is different, which enables line-by-line scanning of pixels, avoids loss of pixel resolution, and ensures high-definition display effect.

[0083] Optionally, the timing of the third clock signal of some output units 31 is the same, while the timing of the third clock signal of the remaining output units 31 is different. Same timing means that the potential transition time points of the compared signals are consistent, but it does not mean that the potentials at the same time point are necessarily the same. This disclosure embodiment uses the example of same timing, consistent potential transition time points, and the same potential at the same time point for illustration. This solution can be applied to application scenarios that dynamically adjust pixel resolution, such as when the human eye observes a screen, its viewing range is limited, such as... Figure 3 As shown, for pixels near the point of human eye fixation (e.g., within the fixation range Q), the timing of the third clock signal of their respective output units 31 is different. This allows for line-by-line scanning of pixels within the fixation range, ensuring high-definition display. For pixels outside the point of human eye fixation (e.g., outside the fixation range Q), the timing of the third clock signal of their respective output units 31 is the same, i.e., multi-line scanning. Even if some sharpness is lost, since this area is not the location of human eye fixation, the human eye cannot perceive whether the image is clear or not, thus not affecting the user's viewing experience. Simultaneously, because the timing of the third clock signal of some output units 31 is the same, the charging time of the effective level of each third clock signal can be increased for the same third clock signal. This can improve a series of problems such as inaccurate grayscale caused by insufficient pixel charging, affecting display quality. Alternatively, for the same third clock signal, without increasing the charging time of the effective level, the saved charging time can be allocated to third clock signals with different timing sequences. This increases the charging time of the effective level of the third clock signals with different timing sequences, further improving the image clarity within the viewing range Q. Furthermore, having different third clock signal terminals CKL_n receive the same third clock signal, such as the same clock signal, can save on clock signal transmission, thereby reducing the power consumption of the clock driver.

[0084] Optionally, the timing of the second clock signal and the third clock signal are different. The time s for the second clock signal to transition from an invalid potential to an effective potential is between s1 and s2. Wherein, s1 represents the time for the third clock signal of the first output unit 31 to transition from an invalid potential to an effective potential, and s2 represents the time for the third clock signal of the nth output unit 31 to transition from an invalid potential to an effective potential.

[0085] Optionally, the timing of the second clock signal is the same as that of the third clock signal of a certain output unit 31. For example, the time for the second clock signal to transition from an invalid potential to an effective potential is the time for the third clock signal of the k-th output unit 31 to transition from an invalid potential to an effective potential; when n is odd, k = (n+1) / 2; when n is even, k = n / 2+1. When n is 4, k is 3.

[0086] In some embodiments, the first clock signal, the second clock signal, and the third clock signal are all square wave signals. Optionally, the effective potentials of the first clock signal, the second clock signal, and the third clock signal are all the same; the ineffective potentials of the first clock signal, the second clock signal, and the third clock signal are all the same.

[0087] It should be noted that the values ​​of the effective and ineffective potentials of the aforementioned clock signal are related to the characteristics of the transistors in the shift register. This disclosure uses an N-type transistor as an example in the shift register.

[0088] Optionally, the effective potential of the first clock signal, the second clock signal, and the third clock signal is all the first voltage V1. The ineffective potential of the first clock signal, the second clock signal, and the third clock signal is all the second voltage V2. The first voltage V1 is higher than the second voltage V2. For example, the first voltage V1 is 8V, and the second voltage V2 is -8V.

[0089] In some embodiments, both the first control signal and the second control signal are AC signals. The first control signal, being an AC signal, enables the cascaded transfer sub-circuit 2 to flexibly control whether the signal of the first node PUCN is written to the third node PUC, and to prevent the signal of the third node PUC from affecting the output unit 31 during specific stages (e.g., output stage t2 and hold stage t4). The second control signal, also an AC signal, enables the output unit 31 to flexibly control whether the signal of the first node PUCN is written to the fourth node PUn, and to prevent the signal of the fourth node PUn from affecting the cascaded transfer sub-circuit 2 during specific stages (e.g., output stage t2 and hold stage t4).

[0090] Optionally, both the first control signal and the second control signal are square wave signals. The effective potential of both the first and second control signals is a third voltage V3, and the ineffective potential is a fourth voltage V4. The third voltage V3 is higher than the fourth voltage V4. The effective potential of the first control signal can control the signal of the first node PUCN to be written to the third node PUC. The ineffective potential of the first control signal can block the signal of the first node PUCN from being written to the third node PUC, thus preventing the signal of the third node PUC from affecting the potential of the first node PUCN. Similarly, the effective potential of the second control signal can control the signal of the first node PUCN to be written to the fourth node PUn. The ineffective potential of the second control signal can block the signal of the first node PUCN from being written to the fourth node PUn, thus preventing the signal of the fourth node PUn from affecting the potential of the first node PUCN.

[0091] Optionally, the timing of the first control signal and the second control signal is the same. Thus, the first control signal and the second control signal are simultaneously effective and simultaneously ineffective. When the first control signal and the second control signal are simultaneously effective, that is, when both are pulled high from the fourth voltage V4 to the third voltage V3, the signal controlling the first node PUCN of the cascaded transfer sub-circuit 2 is written to the third node PUC, and simultaneously, the signal controlling the first node PUCN of the output unit 31 is written to the fourth node PUn. When the first control signal and the second control signal are simultaneously ineffective, that is, when both are pulled low from the third voltage V3 to the fourth voltage V4, the electrical connection between the third node PUC and the first node PUCN is broken, and the electrical connection between the fourth node PUn and the first node PUCN is broken, thus isolating the third node PUC and the fourth node PUn, preventing their potentials from affecting each other, and achieving independent control of the cascaded transfer sub-circuit 2 and the output unit 31.

[0092] This embodiment differs from the scheme that uses conventional DC signals for the first and second control signals. It avoids the situation where the cascaded transfer circuit 2 in the output stage t2 raises the potential of the third node PUC, which would affect the potential of the fourth node PUn of the output unit 31, causing the output unit 31 to output signals in a stage where it should not be outputting, thus affecting pixel driving.

[0093] In some embodiments, the third voltage V3 is equal to or lower than the first voltage V1 and higher than the second voltage V2. The fourth voltage V4 is higher than the second voltage V2 and lower than the third voltage V3.

[0094] Optionally, the third voltage V3 is equal to the first voltage V1; the fourth voltage V4 is higher than the sum of the second voltage V2 and the threshold voltage. Here, the threshold voltage refers to the threshold voltage of the transistor in the shift register. For example, the third voltage V3 is +8V, and the fourth voltage V4 is greater than -8V + Vth, where Vth represents the threshold voltage, for example, 1V. That is, the fourth voltage V4 is greater than -7V and less than +8V. For example, the fourth voltage V4 can be set to -7V, -6V, -5V, -4V, -3V, -2V, -1V, or 0V.

[0095] Here, the third voltage V3 is equal to the first voltage V1, such as 8V. In the input stage t1, the cascaded transfer sub-circuit 2 can effectively control the signal (first voltage V1) of the first node PUCN to be written to the third node PUC, and the output unit 31 can effectively control the signal (first voltage V1) of the first node PUCN to be written to the fourth node PUn. In the output stage t2, since the third node PUC and the fourth node PUn are both at high potentials (first voltage V1), the fourth voltage V4 is set to be higher than the sum of the second voltage V2 and the threshold voltage, such as 0V. This allows the cascaded transfer sub-circuit 2 to be affected by the transistor switching characteristics (for example, the gate-source voltage Vgs of the ninth transistor T9 and the tenth transistor T10 = V4 - V1 = 0 - 8 = -8V), which is much less than the threshold voltage of 1V. This ensures that the electrical connection between the first node PUCN and the third node PUC, as well as the electrical connection between the first node PUCN and the fourth node PUn, is completely disconnected in the output stage t2, avoiding mutual interference between the high potentials of the third node PUC and the fourth node PUn. During the reset phase t3, the cascaded transfer sub-circuit 2 can effectively control the signal (second voltage V2) of the first node PUCN and write it into the third node PUC, and the output unit 31 can effectively control the signal (second voltage V2) of the first node PUCN and write it into the fourth node PUn. Meanwhile, during the holding phase t4, since both the third node PUC and the fourth node PUn are at low potentials (second voltage V2), the fourth voltage V4 is set to be higher than the sum of the second voltage V2 and the threshold voltage, such as 0V. This allows the cascaded transmission sub-circuit 2 to be affected by the transistor switching characteristics (for example, the gate-source voltage Vgs of the ninth transistor T9 and the tenth transistor T10 = V4 - V2 = 0 - (-8) = 8V), which is much greater than the threshold voltage of 1V. This ensures that even if the first control signal and the second control signal apply the fourth voltage V4 (low potential) during the holding phase t4, the first node PUCN and the third node PUC, as well as the first node PUCN and the fourth node PUn, can still be turned on. This allows the second voltage V2 of the first node PUCN to be continuously written to the third node PUC and the fourth node PUn, thereby maintaining the continuous output of the first power signal at the cascaded transmission terminal OutC and the continuous output of the second power signal at the first output terminal Out_n.

[0096] In some embodiments, based on the fact that the timing of the first control signal and the second control signal are the same, the first control signal terminal VGH_G of the cascaded transmission sub-circuit 2 and the second control signal terminal VGH_n of each output unit 31 can be set to be the same, which can reduce the layout space and facilitate the realization of a narrow bezel.

[0097] In some embodiments, Figure 4 This is a schematic diagram of a circuit structure of a shift register provided in an embodiment of the present disclosure, such as... Figure 4 As shown, the cascaded transmission sub-circuit 2 includes a ninth transistor T9, a third transistor T3, a fourth transistor T4, and a first capacitor C1. Specifically, the control electrode of the ninth transistor T9 is electrically connected to the first control signal terminal VGH_G, the first electrode is electrically connected to the third node PUC, and the second electrode is electrically connected to the first node PUCN; the control electrode of the third transistor T3 is electrically connected to the third node PUC, the first electrode is electrically connected to the second clock signal terminal CKC, and the second electrode is electrically connected to the cascaded transmission terminal OutC; the control electrode of the fourth transistor T4 is electrically connected to the second node PD, the first electrode is electrically connected to the cascaded transmission terminal OutC, and the second electrode is electrically connected to the first power supply terminal L. VGL The first plate of the first capacitor C1 is electrically connected to the third node PUC, and the second plate is electrically connected to the cascaded transmission terminal OutC. Specifically, the first control signal transmitted by the first control signal terminal VGH_G can control the on / off state of the ninth transistor T9. For example, when the ninth transistor T9 responds to the first control signal being the third voltage V3, it conducts and can write the signal of the first node PUCN into the third node PUC. At the same time, the signal of the third node PUC can control the on / off state of the third transistor T3. For example, when the potential of the third node PUC is the first voltage V1, the third transistor T3 conducts. The second clock signal transmitted by the second clock signal terminal CKC uses the first capacitor C1 to further couple and pull the first voltage V1 of the third node PUC to the fifth voltage V5, thereby maintaining the conducting state of the third transistor T3. This allows the first voltage V1 of the second clock signal to be stably output through the cascaded transmission terminal OutC until the second clock signal jumps to the second voltage V2 and then cuts off. For example, the third transistor T3 turns off when the potential of the third node PUC is the second voltage V2; at this time, the fourth transistor T4 turns on when the potential of the second node PD is the first voltage V1, thereby turning on the first power supply terminal L. VGL The first power supply signal is output through the cascaded output terminal OutC. Here, the first power supply signal is a low-level signal, such as the second voltage V2 (-8V).

[0098] In some embodiments, continue as follows Figure 4As shown, output unit 31 includes a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, and a second capacitor C2. The control electrode of the tenth transistor T10 is electrically connected to the second control signal terminal VGH_n, the first electrode is electrically connected to the fourth node PUn, and the second electrode is electrically connected to the first node PUCN. The control electrode of the eleventh transistor T11 is electrically connected to the fourth node PUn, the first electrode is electrically connected to the third clock signal terminal CKL_n, and the second electrode is electrically connected to the first output terminal Out_n. The control electrode of the twelfth transistor T12 is electrically connected to the second node PD, the first electrode is electrically connected to the first output terminal Out_n, and the second electrode is electrically connected to the second power supply terminal VGL_G. The first plate of the second capacitor C2 is electrically connected to the fourth node PUn, and the second plate is electrically connected to the first output terminal Out_n. Specifically, the second control signal transmitted by the second control signal terminal VGH_n can control the on / off state of the tenth transistor T10. For example, when the tenth transistor T10 turns on in response to the second control signal being the third voltage V3, the signal of the first node PUCN can be written to the fourth node PUn. Meanwhile, the signal from the fourth node PUn can control the on / off state of the eleventh transistor T11. For example, when the potential of the fourth node PUn is the first voltage V1, the eleventh transistor T11 turns on. The third clock signal transmitted from the third clock signal terminal CKL_n uses the second capacitor C2 to further couple and pull the first voltage V1 of the fourth node PUn to the fifth voltage V5, thereby maintaining the conducting state of the eleventh transistor T11. This allows the first voltage V1 of the third clock signal to be stably output through the first output terminal Out_n until the third clock signal jumps to the second voltage V2 and then turns off. Alternatively, when the eleventh transistor T11 turns off when the potential of the fourth node PUn is the second voltage V2, the twelfth transistor T12 turns on in response to the first voltage V1 of the second node PD, thereby outputting the second power supply signal transmitted from the second power supply terminal VGL_G through the first output terminal Out_n. Here, the second power supply signal is a low-level signal, such as the second voltage V2 (-8V).

[0099] The embodiments of this disclosure include multiple output units 31. The working principle of any output unit 31 is the same, but the timing of the third clock signal of each output unit 31 is different, which leads to the timing of the third clock signal output by each output unit 31 through the first output terminal Out_n being different, that is, the timing of the output gate drive signal is different, thereby realizing line-by-line scanning.

[0100] In some embodiments, continue as follows Figure 4As shown, the input control sub-circuit 1 includes a first transistor T1, a second transistor T2, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a third capacitor C3. The control electrode of the first transistor T1 is electrically connected to the signal input terminal Input, the first electrode is electrically connected to the third power supply terminal CN, and the second electrode is electrically connected to the first node PUCN. The control electrode of the second transistor T2 is electrically connected to the first reset control terminal Reset, the first electrode is electrically connected to the first node PUCN, and the second electrode is electrically connected to the fourth power supply terminal CNB. The control electrode of the fifth transistor T5 is electrically connected to the second node PD, the first electrode is electrically connected to the first node PUCN, and the second electrode is electrically connected to the third voltage V3 of the first power supply terminal. The control electrode of the sixth transistor T6 is electrically connected to the first node PUCN, the first electrode is electrically connected to the second node PD, and the second electrode is electrically connected to the third voltage V3 of the first power supply terminal. The control electrode of the seventh transistor T7 is electrically connected to the first clock signal terminal CKB, the first electrode is electrically connected to the first clock signal terminal CKB, and the second electrode is electrically connected to the second node PD. The first plate of the third capacitor C3 is electrically connected to the second node PD, and the second plate is electrically connected to the third voltage V3 of the first power supply terminal.

[0101] Specifically, the input signal transmitted at the input terminal can control the on / off state of the first transistor T1. For example, the first transistor T1 turns on in response to the input signal being the first voltage V1, writing the third power signal transmitted at the third power supply terminal CN into the first node PUCN. Here, the third power signal is a high-level signal, i.e., the first voltage V1 (+8V). The first reset control signal transmitted at the first reset control terminal Reset can control the on / off state of the second transistor T2. For example, the second transistor T2 turns on in response to the first reset control signal being the first voltage V1, writing the fourth power signal transmitted at the fourth power supply terminal CNB into the first node PUCN. Here, the effective potential of the first reset control signal is the first voltage V1, and the ineffective potential is the second voltage V2. The fourth power signal is a low-level signal, for example, the second voltage V2 (-8V). The signal at the second node PD can control the on / off state of the fifth transistor T5. For example, the fifth transistor T5 turns on in response to the second node PD being the first voltage V1, writing the first power signal transmitted at the third voltage V3 of the first power supply terminal into the first node PUCN. The signal from the first node PUCN can control the on / off state of the sixth transistor T6. For example, when the first node PUCN is at the first voltage V1, the sixth transistor T6 turns on and writes the first power supply signal provided by the third voltage V3 at the first power supply terminal to the second node PD. The first clock signal provided by the first clock signal terminal CKB is used to control the on / off state of the seventh transistor T7. For example, when the seventh transistor T7 turns on in response to the first clock signal being at the first voltage V1, it simultaneously writes the first clock signal, which is at the first voltage V1 at this time, to the second node PD.

[0102] In some embodiments, Figure 5A schematic diagram of another circuit structure of the shift register provided in the embodiments of this disclosure is shown below. Figure 5 As shown, with Figure 4 Compared to the previous circuit structure, a frame reset sub-circuit has been added. This frame reset sub-circuit includes an eighth transistor T8. The control electrode of the eighth transistor T8 is electrically connected to the second reset control terminal TRST, the first electrode is electrically connected to the first node PUCN, and the second electrode is electrically connected to the first power supply terminal, the third voltage V3. Specifically, the second reset signal provided by the second reset control terminal TRST is used to control the on / off state of the eighth transistor T8. For example, the eighth transistor T8 turns on in response to the second reset signal being the first voltage V1, writing the first power supply signal into the first node PUCN. The first power supply signal is a low-level signal (second voltage V2) to reset the first node PUCN before the frame start phase.

[0103] For example, in the shift register provided in this embodiment, the output units 31 are arranged side-by-side along the gate line extension direction on the horizontal reference plane. The shift register includes a first conductive layer, a second conductive layer, and a semiconductor layer. The control electrodes of the ninth transistor T9 and the tenth transistor T10 are both located on the first conductive layer, and the control electrodes of the ninth transistor T9 and the tenth transistor T10 are formed using a single mask. The first and second electrodes of the ninth transistor T9 and the tenth transistor T10 are both located on the second conductive layer and formed using a single mask, which greatly saves fabrication process and helps to reduce fabrication costs.

[0104] The above is a detailed description of the circuit structure of the shift register provided in the embodiments of this disclosure. The working principle of the shift register provided in the embodiments of this disclosure will be further described in detail below.

[0105] This disclosure also provides a method for driving a shift register. Figure 6 Timing diagrams of the shift register operation phases provided in embodiments of this disclosure, such as... Figure 6 As shown, the shift register's operating stages specifically include input stage t1, output stage t2, reset stage t3, and hold stage t4. Here, we will take the example where the timing of the control signals output by the first control signal terminal VGH_G and the second control signal terminals VGH1~n of each output unit 31 is the same, i.e., VGH'.

[0106] During the input phase t1, the input control sub-circuit 1 responds to the input signal transmitted by the signal input terminal Input and controls the potential of the first node PUCN to the first voltage V1; the cascade transmission sub-circuit 2 responds to the third voltage V3 of the first control signal and writes the first voltage V1 of the first node PUCN into the third node PUC; the output unit 31 responds to the third voltage V3 of the second control signal and writes the first voltage V1 of the first node PUCN into the fourth node PUn.

[0107] by Figure 4 The circuit structure of the shift register shown is illustrated, with n=4 as an example. Figure 6 As shown, in input phase t1, the first transistor T1 turns on in response to the input signal being the first voltage V1. At this time, the first node PUCN introduces the third power supply signal (high-level signal), which is the first voltage V1. Subsequently, the first control signal terminal VGH_G and the second control signal terminal VGH_n of each input unit simultaneously transmit the third voltage V3. The ninth transistor T9 and the tenth transistor T10 of each input unit are both turned on, writing the first voltage V1 into the third node PUC and the fourth node PUn. The fourth node PUn can represent any one of PU1 to PU4.

[0108] In the output stage t2, the cascaded transmission sub-circuit 2 responds to the first voltage V1 of the third node PUC and outputs the second clock signal transmitted by the second clock signal terminal CKC through the cascaded transmission terminal OutC; the output unit 31 responds to the first voltage V1 of the fourth node PUn and outputs the third clock signal transmitted by the third clock signal terminal CKL_n through the first output terminal Out_n.

[0109] by Figure 4 The circuit structure of the shift register shown is illustrated, with n=4 as an example. Figure 6As shown, in the output stage t2, the first control signal terminal VGH_G and the second control signal terminal VGH_n of each input unit simultaneously transmit the fourth voltage V4. That is, the control electrode of the ninth transistor T9 and the control electrode of the tenth transistor T10 of each input unit are both the fourth voltage V4. Since the source of the ninth transistor T9 (third node PUC) and the source of the tenth transistor T10 of each input unit (fourth node PUn) are respectively written with the first voltage V1 of the previous stage, the gate-source voltage Vgs of the ninth transistor T9 (tenth transistor T10) at this time is V4-V1. Since V4 is preset to be greater than V2+Vth, for example, the fourth voltage V4 is set to -7V, -6V, -5V, -4V, -3V, -2V, -1V or 0V. Therefore, the gate-source voltage Vgs of the ninth transistor T9 (tenth transistor T10) is < -8V, which is much less than the threshold voltage of 1V. This ensures that the ninth transistor T9 and the tenth transistor T10 are completely disconnected during the output stage t2, preventing leakage current in the ninth transistor T9 and the tenth transistor T10. This also prevents the high potential of the third node PUC and the fourth node PUn from affecting the signal of the first node PUCN. Furthermore, the third transistor T3 turns on in response to the first voltage V1 of the third node PUC, and the cascaded transfer terminal OutC outputs the second clock signal. Since the second clock signal is an AC signal, during the output stage t2, the cascaded transfer terminal OutC may output either the first voltage V1 or the second voltage V2, but only the first voltage V1 is output as the valid input signal for the next stage shift register. The eleventh transistor T11 turns on in response to the first voltage V1 of the fourth node PUn. The first output terminal Out_n outputs the third clock signal. Since the third clock signal is an AC signal, during the output stage t2, the first output terminal Out_n may output the first voltage V1 or the second voltage V2, but only the first voltage V1 is output as the effective gate drive signal for a row of pixels.

[0110] During the reset phase t3, the input control sub-circuit 1 responds to the first clock signal transmitted at the first clock signal terminal CKB, controls the potential of the second node PD to the first voltage V1, and controls the potential of the first node PUCN to the second voltage V2; the cascade transmission sub-circuit 2 responds to the first voltage V1 of the second node PD, outputs the first power signal transmitted by the third voltage V3 of the first power supply terminal through the cascade transmission terminal OutC; responds to the third voltage V3 of the first control signal, writes the second voltage V2 of the first node PUCN into the third node PUC; the output unit 31 responds to the first voltage V1 of the second node PD, outputs the second power signal transmitted by the second power supply terminal VGL_G through the first output terminal Out_n; responds to the third voltage V3 of the second control signal, writes the second voltage V2 of the first node PUCN into the fourth node PUn.

[0111] by Figure 4 The circuit structure of the shift register shown is illustrated, with n=4 as an example. Figure 6 As shown, during the reset phase t3, the seventh transistor T7 turns on in response to the first voltage V1 of the first clock signal and writes the first voltage V1 to the second node PD. Simultaneously, the fifth transistor T5 turns on in response to the first voltage V1 of the second node PD and writes the second voltage V2 of the third power supply signal (low-level signal) to the first node PUCN to reset the first node PUCN. At the same time, the ninth transistor T9 turns on in response to the third voltage V3 of the first control signal and writes the second voltage V2 of the first node PUCN to the third node PUC, while the third transistor T3 turns off. Similarly, the tenth transistor T10 turns on in response to the third voltage V3 of the second control signal and writes the second voltage V2 of the first node PUCN to the fourth node PUn, while the eleventh transistor T11 turns off. The fourth transistor T4 turns on in response to the first voltage V1 of the second node PD, and the cascaded output terminal OutC outputs the second voltage V2 of the first power supply signal (low-level signal). The twelfth transistor T12 turns on in response to the first voltage V1 of the second node PD, and the first output terminal Out_n outputs the second voltage V2 of the second power supply signal (low-level signal).

[0112] During the holding phase t4, the cascaded transfer sub-circuit 2 responds to the fourth voltage V4 of the first control signal and writes the second voltage V2 of the first node PUCN into the third node PUC; the output unit 31 responds to the fourth voltage V4 of the second control signal and writes the second voltage V2 of the first node PUCN into the fourth node PUn; the first voltage V1 is higher than the second voltage V2; the third voltage V3 is higher than the fourth voltage V4; the third voltage V3 is equal to the first voltage V1; the fourth voltage V4 is higher than the sum of the second voltage V2 and the threshold voltage.

[0113] by Figure 4 The circuit structure of the shift register shown is illustrated, with n=4 as an example. Figure 6As shown, during the holding phase t4, the voltage at the control electrode of the ninth transistor T9 is the fourth voltage V4, and the voltage at the first electrode of the ninth transistor T9 (i.e., the voltage of the third node PUC) is the second voltage V2 written in the previous phase (reset phase t3). At this time, the gate-source voltage Vgs of the ninth transistor T9 is V4 - V2. Since V4 is preset to be greater than V2 + Vth, Vgs > Vth. The ninth transistor T9 is an N-type transistor, and due to its switching characteristics, Vgs > Vth satisfies the conduction condition. That is, even if the control electrode of the ninth transistor T9 receives a low-level fourth voltage V4, it will still conduct, so that the cascaded transmission sub-circuit 2 continues to write a low-level second voltage V2 to the third node PUC during the holding phase t4, ensuring that the third transistor T3 is completely turned off and avoiding leakage to the cascaded transmission terminal OutC due to the AC characteristics of the second clock signal.

[0114] During the holding phase t4, the voltage at the control electrode of the tenth transistor T10 is the fourth voltage V4, and the voltage at the first electrode of the tenth transistor T10 (i.e., the voltage at the fourth node PUn) is the second voltage V2 written in the previous phase (reset phase t3). At this time, the gate-source voltage Vgs of the tenth transistor T10 is V4 - V2. Since V4 > V2 + Vth is preset, Vgs > Vth. The tenth transistor T10 is an N-type transistor, and due to its switching characteristics, Vgs > Vth satisfies the conduction condition. That is, even if the control electrode of the tenth transistor T10 receives a low-level fourth voltage V4, it will still conduct, causing the output unit 31 to continuously write a low-level second voltage V2 to the fourth node PUn during the holding phase t4, ensuring that the eleventh transistor T11 is completely turned off, and preventing the eleventh transistor T11 from leaking current to the first output terminal Out_n due to the influence of the AC characteristics of the third clock signal.

[0115] During the holding phase t4, the second node PD holds the first voltage V1 written in the previous phase (reset phase t3), the fourth transistor T4 is continuously turned on, and the cascaded transmission terminal OutC continuously outputs the second voltage V2 of the first power signal; the twelfth transistor T12 is continuously turned on, and the first output terminal Out_n continuously outputs the second voltage V2 of the second power signal.

[0116] In some embodiments, during the output stage t2, the cascaded transmission sub-circuit 2, under the control of the first voltage V1 of the third node PUC and the first voltage V1 of the second clock signal, uses the first capacitor C1 to pull up the first voltage V1 of the third node PUC to the fifth voltage V5; and the output unit 31, under the control of the first voltage V1 of the fourth node PUn and the first voltage V1 of the third clock signal, uses the first capacitor C1 to pull up the first voltage V1 of the fourth node PUn to the fifth voltage V5.

[0117] by Figure 4The circuit structure of the shift register shown is illustrated, with n=4 as an example. Figure 6 As shown, the third transistor T3 is turned on under the control of the first voltage V1. At this time, the voltage of the first terminal of the third transistor T3 is the first voltage V1 of the second clock signal. Through the third transistor T3, it charges the second plate of the first capacitor C1. The first capacitor C1 is coupled and pulls the potential of the first plate high, that is, from the first voltage V1 to the fifth voltage V5. The fifth voltage V5 is approximately twice the first voltage V1, so that the gate-source voltage Vgs of the third transistor T3 is V5-V1≈V1>Vth, and it continues to conduct, thereby ensuring the stable output of the cascaded transmission terminal OutC in the output stage t2.

[0118] The eleventh transistor T11 is turned on under the control of the first voltage V1. At this time, the voltage of the first terminal of the eleventh transistor T11 is the first voltage V1 of the third clock signal. Through the eleventh transistor T11, it charges the second plate of the second capacitor C2. The second capacitor C2 is coupled and pulls the potential of the first plate high, that is, from the first voltage V1 to the fifth voltage V5. The fifth voltage V5 is approximately twice the first voltage V1, so that the gate-source voltage Vgs of the eleventh transistor T11 is V5-V1≈V1>Vth, and it continues to conduct, thereby ensuring the stable output of the first output terminal Out_n in the output stage t2.

[0119] In some embodiments, the timing of the third clock signal of each output unit 31 is different. For example... Figure 6 As shown, the time when the third clock signal transmitted by the third clock signal terminal CLK_1 transitions from an invalid potential to an effective potential is earlier than the time when the third clock signal transmitted by the third clock signal terminal CLK_2 transitions from an invalid potential to an effective potential; the time when the third clock signal transmitted by the third clock signal terminal CLK_2 transitions from an invalid potential to an effective potential is earlier than the time when the third clock signal transmitted by the third clock signal terminal CLK_3 transitions from an invalid potential to an effective potential; and the time when the third clock signal transmitted by the third clock signal terminal CLK_3 transitions from an invalid potential to an effective potential is earlier than the time when the third clock signal transmitted by the third clock signal terminal CLK_4 transitions from an invalid potential to an effective potential. Here, the timing of the third clock signals of each output unit 31 is different, which enables line-by-line scanning of pixels, avoids loss of pixel resolution, and ensures high-definition display effect.

[0120] In some embodiments, the timing of the third clock signals of some output units 31 is the same, while the timing of the third clock signals of the remaining output units 31 is different. This scheme can be applied to application scenarios that dynamically adjust pixel resolution, such as when the human eye observes a screen, where the viewing range is limited. Figure 3As shown, for pixels near the eye's gaze point (e.g., within the gaze range Q), the timing of the third clock signal of their respective output units 31 is different. This allows for line-by-line scanning of pixels within the gaze range, ensuring high-definition display. For pixels outside the eye's gaze point (e.g., outside the gaze range Q), the timing of the third clock signal of their respective output units 31 is the same. Even if some sharpness is lost, since this area is not the location the eye is focused on, the human eye cannot perceive whether the image is clear or not, thus not affecting the user's viewing experience. Simultaneously, because the timing of the third clock signals of some output units 31 is the same, the charging time of the effective level of each third clock signal can be increased for the same third clock signal, thereby improving a series of problems such as inaccurate grayscale caused by insufficient pixel charging, affecting display quality. Alternatively, for the same third clock signal, without increasing the charging time of the effective level, the saved charging time can be distributed to third clock signals with different timings to increase the charging time of the effective level of the third clock signals with different timings, further improving the image sharpness within the gaze range Q. In addition, different third clock signal terminals CKL_n can receive the same third clock signal, such as the same clock signal, which can save the amount of clock signal transmission and thus save the power consumption of the clock driver.

[0121] In some embodiments, both the first control signal and the second control signal are AC signals; the timing of the first control signal and the second control signal is the same. Thus, the first control signal and the second control signal are simultaneously effective and simultaneously ineffective. When the first control signal and the second control signal are simultaneously effective, that is, when both are pulled high from the fourth voltage V4 to the third voltage V3, the cascaded transfer sub-circuit 2 controls the signal of the first node PUCN to be written to the third node PUC, and simultaneously, the output unit 31 controls the signal of the first node PUCN to be written to the fourth node PUn. When the first control signal and the second control signal are simultaneously ineffective, that is, when both are pulled low from the third voltage V3 to the fourth voltage V4, the electrical connection between the third node PUC and the first node PUCN is broken, and the electrical connection between the fourth node PUn and the first node PUCN is broken, thus isolating the third node PUC and the fourth node PUn, preventing their potentials from affecting each other, and realizing independent control of the cascaded transfer sub-circuit 2 and the output unit 31. This embodiment differs from the scheme that uses conventional DC signals for the first and second control signals. It avoids the situation where the cascaded transfer circuit 2 in the output stage t2 raises the potential of the third node PUC, which would affect the potential of the fourth node PUn of the output unit 31, causing the output unit 31 to output signals in a stage where it should not be outputting, thus affecting pixel driving.

[0122] In addition, this disclosure also provides a gate driving circuit. Figure 7 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present disclosure, as shown below. Figure 7 As shown, the gate drive circuit includes N cascaded shift registers configured as described in any of the above embodiments and their structures. Specifically, except for the first-stage shift register, the signal input terminal Input of the (i+1)th stage shift register is electrically connected to the cascade pass terminal OutC of the i-th stage shift register; N is a positive integer greater than 1, and i is a positive integer less than or equal to N.

[0123] In some embodiments, such as Figure 7 As shown, the gate drive circuit includes a first clock signal line CK1, a second clock signal line CK2, n third clock signal lines CLKn, a first control line VHH11, and a second control line VHH21. The first clock signal line CK1 is electrically connected to the first clock signal terminal CKB, the second clock signal line CK2 is electrically connected to the second clock signal terminal CKC, and the multiple third clock signal lines CLKn are electrically connected to the third clock signal terminals CKL_n of different output units 31; for example, the third clock signal line CLK1 is electrically connected to the third clock signal terminal CKL_1, the third clock signal line CLK2 is electrically connected to the third clock signal terminal CKL_2, the third clock signal line CLK3 is electrically connected to the third clock signal terminal CKL_3, and the third clock signal line CLK4 is electrically connected to the third clock signal terminal CKL_4. The first control line VHH11 is electrically connected to the first control signal terminal VGH_G (also known as VGH') and the second control terminal VGH_n (also known as VGH') in the shift register with an odd number of bits; the second control line VHH21 is electrically connected to the first control signal terminal VGH_G (also known as VGH') and the second control terminal VGH_n (also known as VGH') in the shift register with an even number of bits.

[0124] Optionally, the first control line VGH11 and the second control line VGH2 are a pair of AC signal lines, and the control signals provided by the two are alternately connected to the shift register.

[0125] Optionally, continue as follows Figure 7 As shown, the cascade pass terminal OutC of the (i+1)th stage shift register is multiplexed as the first reset control terminal Reset of the i-th stage shift register.

[0126] Optionally, the cascade pass terminal OutC of the (i+2)th stage shift register is multiplexed as the first reset control terminal Reset of the i-th stage shift register.

[0127] In some embodiments, Figure 8 This is a schematic diagram of another gate drive circuit provided in an embodiment of the present disclosure, as shown below. Figure 8 As shown, it is similar to Figure 7The difference lies in the fact that the gate drive circuit includes multiple groups of third clock signal lines CLKn, each group of third clock signal lines CLKn comprising n third clock signal lines CLKn. Taking two groups of third clock signal lines CLKn as an example, for instance, the first group of third clock signal lines 51 includes third clock signal lines CLK1 to 4; the second group of third clock signal lines 52 includes third clock signal lines CLK5 to 8. The n third clock signal lines CLKn in the first group of third clock signal lines 51 are used to electrically connect to the respective third clock signal terminals CKL_n in shift registers with odd-numbered bit widths. The n third clock signal lines CLKn in the second group of third clock signal lines 52 are used to electrically connect to the respective third clock signal terminals CKL_n in shift registers with even-numbered bit widths.

[0128] Optionally, the cascade pass terminal OutC of the (i+2)th stage shift register is multiplexed as the first reset control terminal Reset of the i-th stage shift register.

[0129] In some embodiments, Figure 9 This is a schematic diagram of the shift register cascade structure provided in the embodiments of this disclosure, as shown below. Figure 9 As shown, the first clock signal terminal CKB of the i-th stage shift register is electrically connected to the second clock signal terminal CKC of the (i+1)-th stage shift register; the second clock signal terminal CKC of the i-th stage shift register is electrically connected to the first clock signal terminal CKB of the (i+1)-th stage shift register.

[0130] Figure 10 for Figure 9 The timing diagram of the cascaded structure shown is as follows: Figure 11 As shown, it includes input stage t1, output stage t2, reset stage t3, and hold stage t4. The timing control of the i-th stage shift register can be found in [reference needed]. Figure 6 The timing control principle of the i-th stage shift register is the same as that described in the above embodiments, and repeated parts will not be repeated.

[0131] In addition, embodiments of this disclosure also provide a display device including the gate driving circuit as described above. Further, the display device also includes pixels and a pixel driving circuit for driving the pixels; the gate driving circuit is electrically connected to the pixel driving circuit to provide a gate driving signal to the pixel driving circuit.

[0132] Figure 11 This is a schematic diagram illustrating the correspondence between shift registers and pixel position layouts provided in embodiments of this disclosure, such as... Figure 11 As shown, the vertical dimension Py2 of a shift register 100 can correspond to multiple rows of pixels. For example, Py2 = n × Py3, where Py3 represents the vertical dimension of a row of pixels. This can achieve a higher PPI while ensuring a narrow border.

[0133] For example, the display device can be any product with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or in-vehicle device. Other essential components of the display device are those that should be understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0134] The display device provided in this disclosure can be applied to large-size, high-resolution display scenarios.

[0135] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A shift register, comprising an input control subcircuit, a cascaded transfer subcircuit, and an output subcircuit; the output subcircuit includes multiple output units; the cascaded transfer subcircuit and each of the output units share the same first node; The input control sub-circuit is configured to control the potential of the first node in response to an input signal transmitted from the signal input terminal; The potential of the second node is controlled in response to the first clock signal transmitted at the first clock signal terminal; The cascaded transmission sub-circuit is configured to write the signal of the first node into the third node in response to the first control signal transmitted from the first control signal terminal. In response to the signal from the third node, the second clock signal transmitted from the second clock signal terminal is output through the cascaded transmission terminal; Alternatively, in response to the signal from the second node, the first power signal transmitted from the first power supply terminal is output through the cascaded transmission terminal; The output unit is configured to write the signal of the first node into the fourth node in response to the second control signal transmitted from the second control signal terminal; In response to the signal from the fourth node, the third clock signal transmitted from the third clock signal terminal is output through the first output terminal; or, in response to the signal from the second node, the second power signal transmitted from the second power supply terminal is output through the first output terminal. Both the first control signal and the second control signal are AC signals; The effective potential of the second clock signal is the first voltage, and the invalid potential is the second voltage; the effective potential of the third clock signal is the first voltage, and the invalid potential is the second voltage. The first voltage is higher than the second voltage; The effective potential of the first control signal is a third voltage, and the invalid potential is a fourth voltage; the effective potential of the second control signal is the third voltage, and the invalid potential is the fourth voltage; the third voltage is higher than the fourth voltage. The third voltage is equal to the first voltage; the fourth voltage is higher than the sum of the second voltage and the threshold voltage.

2. The shift register according to claim 1, wherein, The first output terminals of each of the output units are different; the different first output terminals are electrically connected to different gate lines.

3. The shift register according to claim 1, wherein, The second clock signal terminal is different from the third clock signal terminal; the third clock signal terminals of each of the output units are different.

4. The shift register according to claim 1, wherein, The effective potential of the first clock signal is a first voltage, and the invalid potential is a second voltage; the first voltage is higher than the second voltage. The valid potential of the second clock signal is the first voltage, and the invalid potential is the second voltage; The effective potential of the third clock signal is the first voltage, and the invalid potential is the second voltage.

5. The shift register according to claim 1, wherein, The first control signal terminal of the cascaded transmission sub-circuit and the second control signal terminal of each output unit are the same.

6. The shift register according to any one of claims 1 to 5, wherein, The cascaded transmission sub-circuit includes a ninth transistor, a third transistor, a fourth transistor, and a first capacitor; The control electrode of the ninth transistor is electrically connected to the first control signal terminal, the first electrode is electrically connected to the third node, and the second electrode is electrically connected to the first node; The control electrode of the third transistor is electrically connected to the third node, the first electrode is electrically connected to the second clock signal terminal, and the second electrode is electrically connected to the cascaded transmission terminal. The control electrode of the fourth transistor is electrically connected to the second node, the first electrode is electrically connected to the cascaded transmission terminal, and the second electrode is electrically connected to the first power supply terminal. The first plate of the first capacitor is electrically connected to the third node, and the second plate is electrically connected to the cascaded transmission end.

7. The shift register according to any one of claims 1 to 5, wherein, The output unit includes a tenth transistor, an eleventh transistor, a twelfth transistor, and a second capacitor; The control electrode of the tenth transistor is electrically connected to the second control signal terminal, the first electrode is electrically connected to the fourth node, and the second electrode is electrically connected to the first node. The control electrode of the eleventh transistor is electrically connected to the fourth node, the first electrode is electrically connected to the third clock signal terminal, and the second electrode is electrically connected to the first output terminal. The control electrode of the twelfth transistor is electrically connected to the second node, the first electrode is electrically connected to the first output terminal, and the second electrode is electrically connected to the second power supply terminal. The first plate of the second capacitor is electrically connected to the fourth node, and the second plate is electrically connected to the first output terminal.

8. The shift register according to any one of claims 1 to 5, wherein, The input control sub-circuit includes a first transistor, a second transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a third capacitor; The control electrode of the first transistor is electrically connected to the signal input terminal, the first electrode is electrically connected to the third power supply terminal, and the second electrode is electrically connected to the first node. The control electrode of the second transistor is electrically connected to the first reset control terminal, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the fourth power supply terminal. The control electrode of the fifth transistor is electrically connected to the second node, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the first power supply terminal. The control electrode of the sixth transistor is electrically connected to the first node, the first electrode is electrically connected to the second node, and the second electrode is electrically connected to the first power supply terminal. The control electrode of the seventh transistor is electrically connected to the first clock signal terminal, the first electrode is electrically connected to the first clock signal terminal, and the second electrode is electrically connected to the second node; The first plate of the third capacitor is electrically connected to the second node, and the second plate is electrically connected to the first power supply terminal.

9. The shift register according to claim 8, wherein, The shift register further includes a frame reset sub-circuit; the frame reset sub-circuit includes an eighth transistor; The control electrode of the eighth transistor is electrically connected to the second reset control terminal, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the first power supply terminal.

10. A gate drive circuit comprising N cascaded shift registers as described in any one of claims 1 to 9; Except for the first-stage shift register, the signal input terminal of the (i+1)th stage shift register is electrically connected to the cascade transfer terminal of the i-th stage shift register; N is a positive integer greater than 1, and i is a positive integer less than or equal to N.

11. The gate driving circuit according to claim 10, wherein, The first clock signal terminal of the shift register of stage i is electrically connected to the second clock signal terminal of the shift register of stage i+1; the second clock signal terminal of the shift register of stage i is electrically connected to the first clock signal terminal of the shift register of stage i+1.

12. A method for driving a shift register, wherein, The shift register is the shift register as described in any one of claims 1 to 9; the driving method of the shift register includes: During the input phase, the input control sub-circuit responds to the input signal transmitted at the signal input terminal and controls the potential of the first node to a first voltage; the cascaded transmission sub-circuit responds to the third voltage of the first control signal and writes the first voltage of the first node into the third node; the output unit responds to the third voltage of the second control signal and writes the first voltage of the first node into the fourth node. During the output phase, the cascaded transmission sub-circuit responds to the first voltage of the third node and outputs the second clock signal transmitted from the second clock signal terminal through the cascaded transmission terminal; the output unit responds to the first voltage of the fourth node and outputs the third clock signal transmitted from the third clock signal terminal through the first output terminal. During the reset phase, the input control subcircuit responds to the first clock signal transmitted from the first clock signal terminal, controls the potential of the second node to a first voltage, and controls the potential of the first node to a second voltage; the cascaded transmission subcircuit responds to the first voltage of the second node, outputs the first power signal transmitted from the first power supply terminal through the cascaded transmission terminal; responds to the third voltage of the first control signal, writes the second voltage of the first node into the third node; the output unit responds to the first voltage of the second node, outputs the second power signal transmitted from the second power supply terminal through the first output terminal; responds to the third voltage of the second control signal, writes the second voltage of the first node into the fourth node; During the holding phase, the cascaded transmission sub-circuit responds to the fourth voltage of the first control signal by writing the second voltage of the first node into the third node; the output unit responds to the fourth voltage of the second control signal by writing the second voltage of the first node into the fourth node. The first voltage is higher than the second voltage; the third voltage is higher than the fourth voltage; the third voltage is equal to the first voltage; the fourth voltage is higher than the sum of the second voltage and the threshold voltage.

13. The method for driving a shift register according to claim 12, wherein, The output stage also includes: Under the control of the first voltage of the third node and the first voltage of the second clock signal, the cascaded transmission sub-circuit uses the first capacitor to pull up the first voltage of the third node to the fifth voltage. The output unit, under the control of the first voltage of the fourth node and the first voltage of the third clock signal, uses the first capacitor to pull up the first voltage of the fourth node to the fifth voltage.

14. The method for driving a shift register according to claim 12, wherein, The timing of the third clock signal of each of the output units is different.

15. The method for driving a shift register according to claim 12, wherein, The timing of the third clock signal of some of the output units is the same, while the timing of the third clock signal of the remaining output units is different.

16. The method for driving a shift register according to claim 12, wherein, Both the first control signal and the second control signal are AC signals; the timing of the first control signal and the second control signal is the same.

17. A display device, wherein, Includes a gate drive circuit as described in claim 10 or 11.

Images