An operating method of a phase change memory, a control circuit and a phase change memory

Abstract

The embodiment of the present disclosure provides an operating method, circuit and phase change memory. The method comprises the following steps: determining a life cycle in which a phase change memory cell is located; adjusting a value of a preset parameter according to the life cycle; the preset parameter is a parameter related to a write operation. The embodiment of the present disclosure can maintain stable performance of the phase change memory cell in the whole life cycle, and improve performance loss.

Description

Technical Field

[0001] This disclosure relates to the field of memory technology, and in particular to an operation method, control circuit, and phase-change memory. Background Technology

[0002] Phase change memory (PCM) uses the difference in conductivity or impedance between crystalline and amorphous states of a specific phase change material to store data, and is a type of non-volatile memory. The read and write operations of a phase change memory (PCM) cell involve applying voltage or current pulse signals of varying widths and heights to the PCM cell. For a write-to-zero operation (RESET), a short, strong pulse is applied to raise the temperature of the phase change material in the PCM cell above its melting point, followed by rapid cooling to achieve the transition from a polycrystalline to an amorphous state (from state "1" to state "0"). For a write-to-one operation (SET), a long, medium-intensity pulse is applied to raise the temperature of the phase change material below its melting point but above its crystallization point, maintaining this temperature for a period to promote crystal growth, thus achieving the transition from an amorphous to a polycrystalline state (from state "0" to state "1"). For a read operation, a very weak pulse signal that does not affect the state of the phase change material is applied, and its state is read by measuring the resistance value of the PCM cell.

[0003] When the PCM cell is written with data a certain number of times, it enters the middle and late stages of its life cycle. Due to the changes in characteristics after device fatigue, some performance loss will occur. Summary of the Invention

[0004] This disclosure provides an operation method, circuit, and phase change memory.

[0005] In a first aspect, embodiments of this disclosure provide an operating method for a phase-change memory, the phase-change memory comprising a plurality of phase-change memory cells, the method comprising:

[0006] Determine the lifecycle of the phase-change memory unit;

[0007] The values ​​of preset parameters are adjusted according to the lifecycle; the preset parameters are parameters related to write operations.

[0008] In some embodiments, determining the lifecycle of the phase-change memory cell includes:

[0009] Determine the cumulative number of write operations performed on the phase-change memory cell;

[0010] If the cumulative number of times does not reach the preset threshold, the life cycle is determined to be in the early stage of the life cycle;

[0011] If the cumulative number of times reaches the preset threshold, the life cycle is determined to be in the later stage of the life cycle.

[0012] In some embodiments, adjusting the value of the preset parameter according to the lifecycle includes:

[0013] If the life cycle is in the early stage of the life cycle, then the value of the preset parameter is set to the baseline value;

[0014] If the lifecycle is in its later stage, then the value of the preset parameter is set to be greater than the baseline value.

[0015] In some embodiments, the later stage of the lifecycle includes at least one sub-stage, wherein the value of the preset parameter corresponding to the j-th sub-stage is greater than or equal to the value of the preset parameter corresponding to the i-th sub-stage; wherein j and i are both integers greater than 0, and j is greater than i.

[0016] In some embodiments, setting the value of the preset parameter to be greater than the benchmark value includes:

[0017] Determine the step value corresponding to the current sub-stage, and superimpose the step value with the baseline value to obtain the value of the preset parameter corresponding to the current sub-stage.

[0018] In some embodiments, the step value corresponding to the j-th sub-stage is greater than or equal to the step value corresponding to the i-th sub-stage.

[0019] In some embodiments, the reference value includes a pulse duration reference value and a heating current reference value corresponding to the write operation signal received by the phase change memory unit, and the step value includes a corresponding pulse duration step value and a heating current step value.

[0020] The process of determining the step value corresponding to the current sub-stage and superimposing the step value with the reference value to obtain the value of the preset parameter corresponding to the current sub-stage includes:

[0021] Determine the pulse duration step value corresponding to the current sub-stage; superimpose the pulse duration step value with the pulse duration reference value to obtain the pulse duration corresponding to the current sub-stage;

[0022] And / or, determine the heating current step value corresponding to the current sub-stage; superimpose the heating current step value with the heating current reference value to obtain the magnitude of the heating current corresponding to the current sub-stage.

[0023] Secondly, embodiments of this disclosure provide a control circuit for a phase-change memory, used to execute the steps of the operation method as described in any one of the first aspects, including:

[0024] The first control circuit is used to determine the life cycle of the phase-change memory unit;

[0025] The second control circuit is used to adjust the value of a preset parameter according to the life cycle; the preset parameter is a parameter related to the write operation.

[0026] In some embodiments, the second control circuit is configured to: set the value of the preset parameter to a reference value if the life cycle is in the early stage of the life cycle; and set the value of the preset parameter to be greater than the reference value if the life cycle is in the later stage of the life cycle.

[0027] The reference values ​​include a pulse duration reference value and a heating current reference value corresponding to the write operation signal received by the phase change memory unit.

[0028] Thirdly, embodiments of this disclosure provide a phase-change memory, including a control circuit for the phase-change memory as described in any of the second aspects.

[0029] This disclosure provides an operation method, control circuit, and phase-change memory (PCM) according to embodiments. The method includes: determining the lifecycle of a PCM cell; and adjusting the values ​​of preset parameters based on the lifecycle. The preset parameters are parameters related to write operations. Thus, this disclosure first determines the current lifecycle of the PCM cell and then adjusts the values ​​of relevant parameters used when writing data to the PCM cell based on the lifecycle, thereby ensuring that the performance of the PCM remains stable throughout its entire lifecycle and avoiding performance loss. This disclosure also allows for increasing the pulse duration of the write operation signal or adding a heating current at different lifecycle stages of the PCM device to reduce the write error rate and thus improve device lifespan. Attached Figure Description

[0030] Figure 1 A schematic diagram of an equivalent circuit of a PCM unit provided in an embodiment of this disclosure;

[0031] Figure 2 This is a waveform diagram of a write operation signal provided in an embodiment of the present disclosure;

[0032] Figure 3 A waveform diagram of a heating pulse provided in an embodiment of this disclosure;

[0033] Figure 4 A flowchart illustrating an operation method of a phase-change memory provided in this embodiment of the present disclosure;

[0034] Figure 5 This disclosure provides a block diagram of a system including a phase-change memory.

[0035] Figure 6 A schematic diagram of a memory including peripheral circuitry provided in an embodiment of this disclosure;

[0036] Figure 7 A waveform comparison diagram of a write operation signal provided in an embodiment of this disclosure;

[0037] Figure 8 A waveform comparison diagram of a heating pulse provided in an embodiment of this disclosure;

[0038] Figure 9 A schematic diagram of the composition structure of the operation circuit of a phase-change memory provided in an embodiment of this disclosure;

[0039] Figure 10 A block diagram of a memory provided in an embodiment of this disclosure;

[0040] Figure 11 This is a circuit diagram illustrating a write operation performed on a PCM cell, as provided in an embodiment of this disclosure. Detailed Implementation

[0041] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0043] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0044] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0045] In a PCM (Phase Change Module), the low resistance state of a PCM cell is the set state, or the stored data is logic "1"; the high resistance state of a PCM cell is the reset state, or the stored data is logic "0". Different states of the PCM cell are achieved by applying a certain current to heat the phase change material within it.

[0046] See Figure 1 It shows an equivalent circuit diagram of a PCM unit provided in an embodiment of this disclosure, such as... Figure 1 As shown, this PCM cell is a 1-transistor-1-resistor (1T1R) cell structure. The word line WL is connected to the gate of transistor T. One end of the PCM cell is connected to transistor T, and the other end of the variable resistor R is connected to the bit line BL. The other end of transistor T is grounded. When a write operation is performed on this PCM cell, the PCM cell is selected, and both the word line WL and the bit line BL are activated. The signal transmitted through the word line WL (denoted as the write operation signal) turns on transistor T, thereby connecting the branch of bit line BL to the variable resistor R. The heating pulse transmitted through bit line BL forms a heating current I within the variable resistor R. cell The variable resistor R is heated to change its state. Based on different write operation signals and heating pulses, it can write 1 or write 0.

[0047] like Figure 2 As shown, the waveform of a write-0 operation (reset operation) in a PCM cell is typically a short pulse with a duration of 1-100 ns (nanoseconds), while the waveform of a write-1 operation (set operation) is typically a long pulse with a duration of 300 ns-1 μs, and may contain three or more stages, for example... Figure 1 The three stages are T1, T2, and T3. For example, Figure 3 The diagrams show the heating pulses for a write 0 operation (reset heating pulse) and a write 1 operation (set heating pulse), respectively. Their waveforms are similar to the write operation signal, but the timing differs. The write operation pulse can be a voltage pulse, and the heating pulse can be a current pulse or a voltage pulse.

[0048] Typically, the waveform of the write operation signal for a PCM cell remains unchanged throughout the entire lifespan of the device; that is, regardless of the PCM cell's lifecycle stage, each write operation uses the same waveform. Figure 2 and / or Figure 3The waveform shown illustrates that while this method can achieve good performance in the early stages of a device's lifespan, in the middle and later stages of the device's lifespan, due to changes in the device's characteristics after fatigue, the waveform of the write operation signal used in the initial state may no longer be applicable, resulting in some performance loss.

[0049] Based on this, this disclosure provides an operation method for a phase-change memory (PCM). The PCM includes multiple PCM cells. The method includes: determining the lifecycle of a PCM cell; and adjusting the values ​​of preset parameters based on the lifecycle. The preset parameters are parameters related to write operations. Thus, this disclosure first determines the current lifecycle of the PCM cell, and then adjusts the values ​​of relevant parameters used when writing data to the PCM cell based on the lifecycle, thereby ensuring that the performance of the PCM remains stable throughout its entire lifecycle and avoiding performance loss. Specifically, in the later stages of the PCM device's fatigue life, the write operation can be optimized by increasing the pulse duration of the write operation signal or increasing the current value of the heating current, thereby reducing the write error rate and improving device stability.

[0050] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0051] In one embodiment of this disclosure, see [link to embodiment]. Figure 4 This illustrates a flowchart of an operation method for a phase-change memory provided in an embodiment of this disclosure. Figure 4 As shown, the method may include:

[0052] S101: Determine the lifecycle of the phase-change memory cell.

[0053] S102: Adjust the value of the preset parameters according to the lifecycle; the preset parameters are parameters related to write operations.

[0054] It should be noted that, Figure 5 This disclosure provides an exemplary block diagram of a system 200 including a phase-change memory. The system 200 can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 2As shown, system 200 may include host 201 and memory system 202, wherein memory system 202 has one or more memories 203 and memory controller 204; host 201 may be a processor of an electronic device, such as a central processing unit (CPU) or a system-on-chip (SoC), wherein the SoC may be, for example, an application processor (AP). Host 201 may be configured to send data to memory 203 or receive data from memory 203.

[0055] For example, memory 203 may be a phase-change memory, such as phase-change random access memory (PCRAM). In some embodiments, memory controller 204 is coupled to memory 203 and host 201, and is configured to control memory 203. Memory controller 204 can manage data stored in memory 203 and communicate with host 201. Memory controller 204 can be configured to control erase, read, write, and other operations on memory 203.

[0056] Figure 6 This is an exemplary structural diagram of a memory 203 including peripheral circuitry, provided for embodiments of the present disclosure. The memory 203 can be a three-dimensional phase-change memory (PCM), or it can be planar. It may include a phase-change memory array 601 and peripheral circuitry 602 coupled to the phase-change memory array 601. The phase-change memory array 601 may include word lines WL, bit lines BL, and PCM cells 6013 formed between the word lines WL and BL. In some embodiments, each PCM cell 6013 may include a PCM element (containing phase-change material, not shown) connected in series with a selector. To operate the phase-change memory array 601, a word line voltage can be applied to the selected word line WL, and a bit line voltage can be applied to the selected bit line BL.

[0057] In this embodiment of the disclosure, the PCM unit can be Figure 1 The 1T1R structure shown can also be a 1-diode-1-resistor (1D1R) structure, etc., and is not specifically limited thereto. The following will only use the 1T1R structure as an example to describe in detail the implementation flow of the phase-change memory operation method provided in this disclosure embodiment.

[0058] It should be noted that the performance of a PCM cell may vary at different stages of its lifecycle. It is understandable that towards the end of the PCM's lifecycle, due to numerous operations performed, device fatigue may occur, leading to performance degradation, such as write or read data errors. Therefore, in this embodiment of the present disclosure, when operating the phase-change memory, for example, before or after writing data to a selected PCM cell, the current lifecycle of the PCM cell is first determined, and then the values ​​of preset parameters related to the write operation are adjusted according to the lifecycle.

[0059] Here, preset parameter values ​​that ensure no performance loss of the PCM unit at different lifecycle stages can be determined in advance through experiments or other methods. Then, when performing related operations, the preset parameter values ​​are adjusted to ensure that the PCM unit's performance is not compromised. In this way, by dynamically adjusting the preset parameter values, data writing remains accurate throughout, thereby reducing the write error rate and improving stability throughout the entire lifecycle of the PCM unit.

[0060] It should also be noted that, in some embodiments, the preset parameters related to the write operation include, but are not limited to, one or more of the following: the pulse duration of the write operation signal received by the word line connected to the PCM unit; and the magnitude of the heating current used to heat the PCM unit during the write operation.

[0061] Here, we can combine Figures 1 to 3 As shown, the write operation signal can be the signal on the word line WL during the write operation, and the heating current can be the current I flowing through the variable resistor R during the write operation. cell The magnitude of the heating current can be controlled by the heating pulse. Write operations include set and reset operations. The waveform of the write operation signal under normal conditions (i.e., the PCM unit performance is not damaged and no adjustment is required) is as follows: Figure 2 Heating pulses, such as Figure 3 .

[0062] In this embodiment of the disclosure, the adjustment of the write operation signal can be an adjustment of the pulse duration, such as... Figure 2 As shown, the pulse of the set waveform includes several stages, and the pulse duration can be adjusted by adjusting the duration of any one or more stages.

[0063] For heating current I cell The adjustment can be made by adjusting the current value, specifically by adjusting the intensity of the heating pulse. The heating pulse can be either a voltage pulse or a current pulse; no specific limitation is made here. Voltage pulses can be generated by a voltage generator, while current pulses can be generated by a current mirror.

[0064] For step S101, in some embodiments, determining the lifecycle of the phase-change memory cell may include:

[0065] Determine the cumulative number of write operations performed on the PCM cell;

[0066] The lifespan is determined based on the cumulative number of times.

[0067] It should be noted that the write operation performed on the PCM unit includes set operation and reset operation. The cumulative count here can be the total number of set operation and reset operation. In some cases, it can refer only to the number of set operation, or only to the number of reset operation, or one set operation and one reset operation can be combined as one cycle. Alternatively, the cumulative count can include the count of read operation in addition to the count of write operation.

[0068] In this embodiment of the disclosure, taking the total number of set and reset operations as an example, a counter can be used to count the number of write operations, and then the current life cycle of the PCM unit can be determined based on the accumulated number of counts.

[0069] In some embodiments, determining the lifecycle based on the cumulative number of times may include:

[0070] If the cumulative number of occurrences does not reach the preset threshold, the lifecycle is determined to be in the early stage of the lifecycle.

[0071] If the cumulative number of occurrences reaches a preset threshold, the lifecycle is determined to be in the later stage of the lifecycle.

[0072] It should be noted that, in the embodiments disclosed herein, the lifecycle of the PCM unit can be divided into the early stage of the lifecycle and the late stage of the lifecycle (or the middle and late stages of the lifecycle) using a preset threshold.

[0073] For example, the preset threshold can be determined as follows: When the PCM unit is operated on at a reference value while maintaining the same operating method, after a certain number of cyclic operations on the PCM unit (denoted as the critical value), the PCM unit experiences some performance loss, such as errors in data writing or writing failures. The number of cyclic operations can be the number of write operations, the number of read operations, or the sum of the number of write and read operations. Here, the sum of the number of set and reset operations is taken as an example.

[0074] Thus, a critical value is determined. To ensure timely and reliable handling of PCM units with impaired performance, a preset threshold is set to a value less than or equal to this critical value. That is, under normal circumstances, the PCM unit performance is not impaired when the cumulative number of read / write cycles does not reach the preset threshold; however, when the cumulative number of read / write cycles reaches the preset threshold, the PCM unit performance may be impaired. It should also be noted that PCM unit performance impairment is not only related to the number of write or read cycles but can also be related to environmental factors, which are not considered typical cases.

[0075] It should also be noted that in phase-change memory (PCM) memory, the critical values ​​for PCM cells at different locations are often different. For example, whether the PCM cell is located in the boundary region of the memory array, or its distance from the peripheral circuitry, can all have an impact. Typically, the critical values ​​for multiple PCM cells in a phase-change memory follow a certain probability distribution, such as a normal distribution.

[0076] After determining the lifecycle of the PCM unit, the values ​​of its preset parameters are adjusted according to the PCM unit's lifecycle. As mentioned above, in this embodiment of the disclosure, the preset parameters mainly refer to the parameters of the write operation, that is, the values ​​of the parameters involved when performing a write operation on the PCM unit.

[0077] It should be noted that writing data to a PCM unit typically involves a series of steps, including addressing, control, and driving, which will not be elaborated upon in this embodiment. Only the adjustment of preset parameters will be described in detail.

[0078] In some embodiments, adjusting the value of a preset parameter according to the lifecycle may include:

[0079] If the lifecycle is in the early stage, the value of the preset parameter will be set to the baseline value;

[0080] If the lifecycle is in its later stages, the value of the preset parameter will be set to be greater than the baseline value.

[0081] It should be noted that if the PCM unit is determined to be in the early stage of its lifecycle, meaning the probability of performance degradation is very low, then there is no need to adjust the preset parameter values; maintaining the baseline values ​​is sufficient. Here, the baseline value can refer to the fixed value preset by the manufacturer when writing data to the PCM unit.

[0082] It should also be noted that, in conjunction with the foregoing description, the preset parameters may include the pulse duration of the write operation signal, specifically the pulse duration of the set operation (which can be denoted as the set pulse) and the pulse duration of the reset operation (which can be denoted as the reset pulse). The corresponding reference values ​​are denoted as pulse duration reference values, specifically the set pulse reference value and the reset pulse reference value. For example, the reset pulse reference value is 30ns, and the set pulse reference value is 500ns. The preset parameters may also include the magnitude of the heating current, specifically the magnitude of the heating current for the set operation (which can be denoted as the set current) and the heating current for the reset operation (which can be denoted as the reset current). The corresponding reference values ​​are denoted as heating current reference values, specifically the set current reference value and the reset current reference value. For example, the set current reference value is 30μA, and the reset current reference value is 100μA.

[0083] If the PCM unit is determined to be in the late stage of its lifecycle, with a high probability of performance degradation, then the values ​​of the preset parameters need to be adjusted. Here, based on theoretical and experimental verification, the approach is to increase the values ​​of the preset parameters, making them greater than the baseline values. Specifically, during the late stage of the lifecycle, when performing a write operation on the PCM unit, the pulse duration of the write operation signal is prolonged, and / or the heating current value is increased.

[0084] It should be noted that in the later stages of the PCM unit's lifespan, due to numerous cycles, the PCM unit exhibits fatigue. If data is still written to the PCM unit according to the reference value, insufficient heating time or temperature may prevent the phase change material from undergoing a state change, leading to errors. This embodiment extends the pulse duration of the write operation signal and / or increases the heating current value to ensure sufficient heating time and / or intensity for the phase change material to undergo a state change, thus ensuring correct data writing.

[0085] For the later stages of the lifecycle, in some embodiments, the later stages of the lifecycle include at least one sub-stage, and the method further includes:

[0086] Determine the preset interval to which the cumulative count belongs;

[0087] If the cumulative number of times belongs to the nth preset interval, then the PCM unit is determined to be in the nth sub-stage of the later stage of its life cycle; where n is an integer greater than 0.

[0088] In some embodiments, the value of the preset parameter corresponding to the j-th sub-stage is greater than or equal to the value of the preset parameter corresponding to the i-th sub-stage; where j and i are both integers greater than 0, and j is greater than i.

[0089] It should be noted that, in order to ensure that the performance of the PCM unit is not compromised as it approaches the end of its lifespan, the preset parameter values ​​are set to be larger, or the preset parameter values ​​stop increasing and remain unchanged once they reach a certain threshold. In other words, the later the lifespan, the larger the cycle count node, and the current increase may be linear or progressively increasing, depending on the actual test data.

[0090] Therefore, in addition to the aforementioned preset threshold, one or more second thresholds can be set according to actual conditions. For example, N second thresholds can be set, where each second threshold is an integer greater than 0. The first to the Nth second thresholds increase sequentially, and there are N+1 corresponding preset intervals.

[0091] It should also be noted that the number of iterations usually increases exponentially. For two adjacent preset intervals, the length of the latter preset interval is usually greater than the length of the former preset interval.

[0092] In some embodiments, setting the value of the preset parameter to be greater than the baseline value may include:

[0093] Determine the step value corresponding to the current sub-stage, and superimpose the step value of the current sub-stage with the baseline value to obtain the value of the preset parameter corresponding to the current sub-stage.

[0094] In some embodiments, the step value corresponding to the j-th sub-stage is greater than or equal to the step value corresponding to the i-th sub-stage, where j and i are both integers greater than 0, and j is greater than i.

[0095] For example, the reference values ​​include the pulse duration reference value and the heating current reference value corresponding to the write operation signal received by the phase change memory unit, and the step values ​​include the corresponding pulse duration step value and the heating current step value.

[0096] Determine the step value corresponding to the current sub-stage; superimpose the step value with the baseline value to obtain the value of the preset parameter corresponding to the current sub-stage, which may include:

[0097] Determine the pulse duration step value corresponding to the current sub-stage; superimpose the pulse duration step value with the pulse duration reference value to obtain the pulse duration corresponding to the current sub-stage;

[0098] And / or, determine the heating current step value corresponding to the current sub-stage; superimpose the heating current step value with the heating current reference value to obtain the magnitude of the heating current corresponding to the current sub-stage.

[0099] It should be noted that the increase in the value of the preset parameter can be based on the base value plus a step value. In this case, starting from the first sub-stage, the step value can be gradually increased or increased to a certain value and then remain unchanged. For example, considering the early stage of the lifecycle as the 0th sub-stage and the later stage of the lifecycle starting from the 1st sub-stage, for the write operation signal, the step value for increasing the pulse duration (i.e., the pulse duration step value, which can be further divided into the set duration step value for the corresponding set operation and the reset duration step value for the corresponding reset operation) can be between 0-100ns, for example, 0 / 50 / 100ns sequentially starting from the 0th sub-stage. For the heating current, the heating current step value can be further divided into the set current step value corresponding to the set operation and the reset current step value corresponding to the reset operation. Starting from the first sub-stage, the set current step value can be between 0 and 10 μA, for example, starting from the 0th sub-stage, it is 0 / 2 / 4 / 6 / 8 / 10 μA in sequence; the reset current step value can be between 0 and 10 μA, for example, starting from the 0th sub-stage, it is 0 / 10 / 20 / 30 / 10 μA in sequence.

[0100] Assuming the first threshold is 100k (kilo), N=2, the first second threshold is 300k, and the second second threshold is 1M (mega), there are three corresponding preset intervals and sub-stages: the first preset interval with a cumulative count of 100k to 300k (corresponding to the first sub-stage, with pulse duration step, set current step, and reset current step values ​​of 50ns, 2μA, and 10μA, respectively); the second preset interval with a cumulative count of 300k to 1M (corresponding to the second sub-stage, with pulse duration step, set current step, and reset current step values ​​of 100ns, 4μA, and 20μA, respectively); and the third preset interval with a cumulative count greater than 1M (corresponding to the third sub-stage, with pulse duration step, set current step, and reset current step values ​​of 100ns, 6μA, and 30μA, respectively). The boundaries of each preset interval can belong to the preceding or following interval, which is not specifically limited here.

[0101] If the cumulative count is less than 100k, it indicates that the PCM unit is in the early stage of its lifecycle (sub-stage 0), and there is no need to adjust the preset parameter values. Alternatively, the preset parameter values ​​can be incremented by 0. Assuming the set pulse reference value is 500ns, the reset pulse reference value is 30ns, the set current reference value is 30μA, and the reset current reference value is 100μA, then if the cumulative count is greater than or equal to 100k and less than or equal to 300k, corresponding to sub-stage 1, then after adding the corresponding step value to each reference value, the values ​​of the set pulse, reset pulse, set current, and reset current are 550ns, 80μA, and 100μA, respectively. The values ​​of the set pulse, reset pulse, set current, and reset current are 600ns, 130ns, 34μA, and 120uA, respectively, after adding the corresponding step value to the base value. If the cumulative number of times is greater than or equal to 300k and less than or equal to 1M, the corresponding sub-stage is the second sub-stage. If the cumulative number of times is greater than 1M, the corresponding sub-stage is the third sub-stage. If the cumulative number of times is greater than 1M, the corresponding sub-stage is the third sub-stage. If the cumulative number of times is greater than or equal to ...

[0102] Thus, the embodiments of this disclosure reduce the write error rate and improve stability in the later stages of the PCM device life through optimized write operations, thereby extending the device life.

[0103] In some embodiments, setting the value of the preset parameter to be greater than the baseline value may include:

[0104] Determine the second step value corresponding to the current sub-stage, and add the value of the preset parameter corresponding to the previous sub-stage to the second step value to obtain the value of the preset parameter corresponding to the current sub-stage.

[0105] It should be noted that, in another implementation, increasing the value of the preset parameter can be done by adding the second step value corresponding to the current sub-stage to the preset parameter of the previous sub-stage. In this case, the second step value corresponding to each sub-stage can be the same value or a gradually decreasing value.

[0106] Still assuming the first threshold is 100k, N=2, the first second threshold is 300k, and the second second threshold is 1M, there are three corresponding preset intervals and sub-stages: the first preset interval with a cumulative count of 100k to 300k (corresponding to the first sub-stage, the second step values ​​for the write pulse, set current, and reset current are 50ns, 2μA, and 10μA, respectively); the second preset interval with a cumulative count of 300k to 1M (corresponding to the second sub-stage, the second step values ​​for the write pulse, set current, and reset current are 50ns, 2μA, and 10μA, respectively); and the third preset interval with a cumulative count greater than 1M (corresponding to the third sub-stage, the second step values ​​for the write pulse, set current, and reset current are 50ns, 2μA, and 10μA, respectively). The boundaries of each preset interval can belong to the previous interval or the next interval, which is not specifically limited here.

[0107] If the cumulative count is less than 100k, it indicates that the PCM unit is in the early stage of its lifecycle (sub-stage 0), and there is no need to adjust the preset parameter values. Alternatively, the preset parameter values ​​can be incremented by 0. Assuming the set pulse reference value is 500ns, the reset pulse reference value is 30ns, the set current reference value is 30μA, and the reset current reference value is 100μA, then if the cumulative count is greater than or equal to 100k and less than or equal to 300k, corresponding to sub-stage 1, then after adding the corresponding second step value to the reference values, the values ​​of the set pulse, reset pulse, set current, and reset current are 550ns, 80ns, and 32μA, respectively. A. 110uA; If the cumulative number of times is greater than or equal to 300k and less than or equal to 1M, the corresponding sub-stage is the second sub-stage. After adding the corresponding second step value to the values ​​of the first sub-stage, the values ​​of the set pulse, reset pulse, set current, and reset current are 600ns, 130ns, 34μA, and 120uA, respectively. If the cumulative number of times is greater than 1M, the corresponding sub-stage is the third sub-stage. After adding the corresponding second step value to the values ​​of the second sub-stage, the values ​​of the set pulse, reset pulse, set current, and reset current are 650ns, 180ns, 36μA, and 130μA, respectively.

[0108] For example, Figure 7 and Figure 8 This diagram illustrates a comparison of write operation signals and heating pulses during set and reset operations in a sub-stage of the early and late lifecycle.

[0109] It should also be noted that when adjusting the pulse duration or heating current of the write operation signal, the other can also be adjusted according to actual needs to ensure that the increase in heating duration or intensity is effective.

[0110] In addition, the aforementioned division of sub-stages and the setting of step value / second step value are all exemplary, and the specific values ​​depend on the actual test data of the specific device.

[0111] In short, embodiments of this disclosure can gradually increase the pulse duration of the write operation signal in the later stages of the PCM device's (i.e., PCM cell) lifecycle, with cycle number nodes at 100k / 300k / 1M, etc., and waveform duration increment steps ranging from 0-100ns. And / or, the heating current at each stage can be gradually increased in the later stages of the device lifecycle, with cycle number nodes at 100k / 300k / 1M, etc., and pulse duration increment steps ranging from 0-10μA. Here, the lifecycle parameter refers to the division of the device lifecycle; exemplarily, 100k / 300k / 1M is used as the division point. For write operations: the duration of the set and reset waveforms increases as the lifecycle progresses, with each increment step between 0-100ns, for example, 0 / 50 / 100ns. The current of the set waveform increases as the lifecycle progresses, with each increment step between 0-10μA, for example, 0 / 2 / 4 / 6 / 8 / 10μA. The current of the set waveform increases as the lifespan progresses, with each step increasing by a increment between 0 and 40 μA, for example, 0 / 10 / 20 / 30 / 40 μA.

[0112] In summary, the embodiments of this disclosure provide an operation method for a phase-change memory (PCM). The characteristics of the PCM change with the number of operations at different stages of its life cycle. Therefore, the optimal heating current and pulse time required for write operations are different at different life cycles. By optimizing the pulse time and heating current of the write operation, the device can maintain the best write operation effect at different life cycles, thereby reducing the device's error rate and improving device stability.

[0113] In another embodiment of this disclosure, see Figure 9 This illustrates a schematic diagram of the composition of a control circuit 90 for a phase-change memory provided in an embodiment of this disclosure. For example... Figure 9 As shown, the circuit 90 includes a first control circuit 901 and a second control circuit 902, wherein:

[0114] The first control circuit 901 is used to determine the life cycle of the phase change memory unit 903.

[0115] The second control circuit 902 is used to adjust the value of preset parameters according to the life cycle; the preset parameters are parameters related to the write operation.

[0116] In some embodiments, the preset parameters include at least one of the following: the pulse duration of the write operation signal received by the word line connected to the phase change memory cell; and the magnitude of the heating current used to heat the phase change memory cell during the write operation.

[0117] In some embodiments, the second control circuit 902 is configured to set the value of the preset parameter to a reference value if the life cycle is in the early stage of the life cycle; and to set the value of the preset parameter to be greater than the reference value if the life cycle is in the later stage of the life cycle.

[0118] The reference values ​​include the pulse duration reference value and the heating current reference value corresponding to the write operation signal received by the phase change memory unit.

[0119] In some embodiments, the second control circuit 902 includes a first pulse generation circuit 9021 and / or a second pulse generation circuit 9022, wherein:

[0120] The first control circuit 901 is used to count the write operations of the phase change memory unit 6013 and generate a first control signal and / or a second control signal based on the counting result.

[0121] The first pulse generation circuit 9021 is used to generate a write operation signal based on the first control signal;

[0122] The second pulse generation circuit 9022 is used to generate a heating pulse signal according to the second control signal.

[0123] It should be noted that the control circuit 90 of the phase-change memory is used to execute the steps of the operation method as described in any of the foregoing embodiments.

[0124] It should also be noted that, for ease of understanding the working process of circuit 90, in the aforementioned... Figure 5 and Figure 6 Based on this, please continue to refer to Figure 10 This is an exemplary block diagram of a memory 203 including a storage array 601 and peripheral circuitry 602, provided in an embodiment of this disclosure. Figure 10 As shown, the memory 203 includes a phase-change memory array 601 and peripheral circuitry 602, wherein the memory array 601 has been previously integrated with... Figure 6 Please provide an explanation. For example... Figure 10 As shown, the peripheral circuit 602 may include: control logic 6021, address register 6022, voltage generator 6023, row decoder / word line driver 6024, page buffer / sensor amplifier circuit 6025, column decoder / bit line driver / data latch 6026, and data register / data I / O 6027, wherein;

[0125] Page buffer / sensor amplifier circuit 6025 can be configured to read data from phase-change memory array 601 and program (write) data to phase-change memory array 601 according to control signals from control logic 6021. In one example, page buffer / sensor amplifier 6025 can store a page of programming data (write data) to be programmed into a page of phase-change memory array 601. In another example, page buffer / sensor amplifier 6025 can perform a programming verification operation to ensure that data has been correctly programmed into phase-change memory cell 4013 coupled to a selected word line. In yet another example, page buffer / sensor amplifier 6025 can also sense a low-power signal from a selected bit line representing a data bit stored in phase-change memory cell 6013 and amplify a small voltage swing to a recognizable logic level during a read operation. In some embodiments, page buffer / sensor amplifier 6025 may include a comparator (e.g., a voltage comparator) for comparing a voltage signal (e.g., a read voltage) with a reference voltage signal (e.g., a predetermined threshold voltage of a memory cell in a "set" state). The column decoder / bit line driver / data latch 6026 can be configured to be controlled by control logic 6021 and to select one or more phase-change memory cells 6013 and bit lines. The column decoder / bit line driver / data latch 6026 can be further configured to drive the selected bit lines. The column decoder / bit line driver / data latch 6026 can be further configured to drive bit lines 4012 using bit line voltages generated from voltage generator 6023. The column decoder / bit line driver / data latch 6026 can be a temporary binary data storage device for storing bits. In some embodiments, the column decoder / bit line driver / data latch 6026 may include a read data latch to temporarily store read data. The data register / data I / O 6027 may be coupled to the page buffer / sensor amplifier 6025 and / or the column decoder / bit line driver / data latch 6026, and is configured to route data input from the data bus 6028 to the desired phase-change memory cell 6013 of the phase-change memory array 601, and to route data output from the desired memory cell to the data bus 6028.

[0126] The row decoder / word line driver 6024 can be configured to be controlled by control logic 6021 and to select one or more phase-change memory cells 4013 and word lines of the phase-change memory array 601. The row decoder / word line driver 6024 can be further configured to drive the selected word lines. The row decoder / word line driver 6024 can be further configured to drive the word lines using word line voltages generated from voltage generator 6023.

[0127] The voltage generator 6023 can be configured to be controlled by the control logic 6021 according to the control signals from the control logic 6021, and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the phase-change memory array 601.

[0128] Control logic 6021 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Control logic 6021 is configured to receive clock signals, command signals, address signals, and data signals from the host, wherein command signals are received via command bus 6029 and data signals are received via data bus 6028. In some embodiments, control logic 6021 can be implemented by a microprocessor, microcontroller (also known as a microcontroller unit (MCU)), digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable logic gate array (FPGA), programmable logic device (PLD), state machine, gating logic, discrete hardware circuitry, and other suitable hardware, firmware, and / or software configured to perform the various functions described.

[0129] Based on this, Figure 11 This is a circuit diagram illustrating a write operation to a PCM cell. Taking a reset operation as an example... Figure 10 As shown, once control logic 6021 determines that the command is a reset command, it triggers a reset operation. The word line voltage is connected to the word line WL of the selected phase-change memory cell via the word line driver, and the bit line voltage is connected to the bit line BL of the selected phase-change memory via the bit line driver. Under the influence of the word line voltage and the bit line voltage, the selector of the selected phase-change memory cell 6013 is turned on. Then, a current (such as that provided by current source I in the figure) is provided to the selected phase-change memory for reset (conversion to amorphous state) to perform the reset operation on the selected phase-change memory cell. The set operation is similar and will not be described further here.

[0130] Based on this (but not limited to) Figure 10 and Figure 11 (Structure shown), such as Figure 9As shown, the first control circuit 901 can be integrated into the control logic 6021 to count the received write commands (including reset commands for writing 0 and set commands for writing 1), with one write command corresponding to one write operation. Based on the counting result and the specific type of the current write command (set command or reset command), a first control signal is generated to control the pulse duration of the write operation signal, and / or, a heating pulse signal is generated to control the heating current.

[0131] The first pulse generation circuit 9021 can be integrated into the voltage generator 6023. It is used to generate a write operation signal based on the control of the first control signal and transmit the write operation signal to the word line WL. The second pulse generation circuit 9022 can be the aforementioned current source I. It is used to generate a heating pulse signal based on the control of the second control signal and transmit the heating pulse signal to the PCM unit 6013 via the bit line BL to heat the phase change material in the PCM unit 6013. The current source I can be a current mirror.

[0132] It should also be noted that the circuit 90 provided in this embodiment is used to implement the operation method in the foregoing embodiment. For details not disclosed in this embodiment, please refer to the description of the foregoing embodiment for understanding, and will not be repeated here.

[0133] In another embodiment of this disclosure, a phase-change memory (PCM) is provided, including a control circuit 90 for the PCM as described in any of the foregoing embodiments. Thus, by dynamically adjusting the values ​​of preset parameters related to write operations as the PCM cell's lifespan increases, the error write rate of the PCM cell is reduced, thereby improving the lifespan of the PCM.

[0134] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0135] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0136] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0137] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0138] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0139] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0140] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for operating a phase-change memory, characterized in that, The phase-change memory includes multiple phase-change memory cells, and the method includes: Determine the cumulative number of write operations performed on the phase-change memory cell; If the cumulative number of times does not reach the preset threshold, the life cycle is determined to be in the early stage of the life cycle, and the value of the preset parameter is set to the baseline value; wherein, the preset threshold is the critical value at which the phase change memory cell experiences write performance loss, and the preset threshold is different for phase change memory cells located in different regions of the phase change memory; If the cumulative number of times reaches the preset threshold, the lifecycle is determined to be in the later stage of the lifecycle; the step value corresponding to the current sub-stage is determined, and the step value is superimposed with the baseline value to obtain the value of the preset parameter corresponding to the current sub-stage; the preset parameter is a parameter related to the write operation; The later stage of the life cycle includes at least two sub-stages, wherein the interval length corresponding to the j-th sub-stage is greater than or equal to the interval length corresponding to the i-th sub-stage, the step value corresponding to the j-th sub-stage is greater than or equal to the step value corresponding to the i-th sub-stage, and j and i are both integers greater than 0, and j is greater than i.

2. The operating method according to claim 1, characterized in that, The reference value includes a pulse duration reference value and a heating current reference value corresponding to the write operation signal received by the phase change memory unit, and the step value includes a corresponding pulse duration step value and a heating current step value. The step of determining the step value corresponding to the current sub-stage and superimposing the step value with the reference value to obtain the value of the preset parameter corresponding to the current sub-stage includes: Determine the pulse duration step value corresponding to the current sub-stage; superimpose the pulse duration step value with the pulse duration reference value to obtain the pulse duration corresponding to the current sub-stage; And / or, determine the heating current step value corresponding to the current sub-stage; superimpose the heating current step value with the heating current reference value to obtain the magnitude of the heating current corresponding to the current sub-stage.

3. A control circuit for a phase-change memory, characterized in that, The steps for performing the operation method as described in any one of claims 1 to 2 include: A first control circuit is used to determine the cumulative number of write operations performed on the phase-change memory cell; if the cumulative number of operations does not reach a preset threshold, the life cycle is determined to be in the early stage of the life cycle; if the cumulative number of operations reaches the preset threshold, the life cycle is determined to be in the late stage of the life cycle; wherein, the preset threshold is a critical value at which the phase-change memory cell experiences write performance loss, and the preset threshold is different for phase-change memory cells located in different regions of the phase-change memory. The second control circuit is configured to: if the lifecycle is in the early stage of the lifecycle, set the value of the preset parameter to a reference value; if the lifecycle is in the later stage of the lifecycle, determine the step value corresponding to the current sub-stage, and superimpose the step value with the reference value to obtain the value of the preset parameter corresponding to the current sub-stage; the preset parameter is a parameter related to the write operation; the preset parameter is a parameter related to the write operation. The later stage of the life cycle includes at least two sub-stages, wherein the interval length corresponding to the j-th sub-stage is greater than or equal to the interval length corresponding to the i-th sub-stage, the step value corresponding to the j-th sub-stage is greater than or equal to the step value corresponding to the i-th sub-stage, and j and i are both integers greater than 0, and j is greater than i.

4. The circuit according to claim 3, characterized in that, The reference values ​​include a pulse duration reference value and a heating current reference value corresponding to the write operation signal received by the phase change memory unit.

5. A phase-change memory, characterized in that, Includes the control circuit of the phase-change memory as described in claim 3 or 4.

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