Method of manufacturing semiconductor device and semiconductor device, memory system

Abstract

Embodiments of the present application provide a method for manufacturing a semiconductor device, and a semiconductor device, a memory system. The method includes: providing a semiconductor structure, wherein the semiconductor structure includes a stack structure, a contact connection portion penetrating the stack structure, and a gate line gap structure, wherein the gate line gap structure has a protruding portion protruding the stack structure along a stacking direction of the stack structure, and the semiconductor structure further includes a semiconductor layer covering the stack structure, the contact connection portion, and the protruding portion of the gate line gap structure; removing at least part of the semiconductor layer to expose the contact connection portion and the protruding portion; removing at least part of the protruding portion; and forming a dielectric layer covering the semiconductor layer, the contact connection portion, and the gate line gap structure.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more specifically, to a method for manufacturing semiconductor devices and semiconductor devices and memory systems. Background Technology

[0002] In semiconductor manufacturing, wafer planarization is an indispensable process, and the flatness of the wafer surface directly affects product yield. Current wafer planarization methods typically involve multiple steps, including etching and chemical mechanical polishing (CMP), resulting in a complex and costly process. Therefore, there is a need to explore a method for manufacturing semiconductor devices and memory systems that can achieve wafer surface planarization and a simple structure. Summary of the Invention

[0003] The various aspects disclosed in this application, and the embodiments included in each aspect, are used to address or partially address some of the above-mentioned or other deficiencies in the prior art.

[0004] In a first aspect, embodiments of this application provide a method for manufacturing a semiconductor device. The method includes: providing a semiconductor structure, wherein the semiconductor structure includes a stacked structure, a contact connection portion penetrating the stacked structure, and a gate line slot structure, wherein the gate line slot structure has a protrusion protruding from the stacked structure along a stacking direction of the stacked structure, and the semiconductor structure further includes a semiconductor layer covering the stacked structure, the contact connection portion, and the protrusion of the gate line slot structure; removing at least a portion of the semiconductor layer to expose the contact connection portion and the protrusion; removing at least a portion of the protrusion; and forming a dielectric layer covering the semiconductor layer, the contact connection portion, and the gate line slot structure.

[0005] In one embodiment, removing at least a portion of the semiconductor layer to expose the contact connection and the protrusion includes: forming a patterned mask layer on a surface of the semiconductor layer away from the stacked structure, the mask layer including a first opening and a second opening, wherein the first opening exposes a portion of the semiconductor layer covering the contact connection, and the second opening exposes a portion of the semiconductor layer covering the gate gap structure; and etching the semiconductor layer through the first opening and the second opening to expose the contact connection and the protrusion.

[0006] In one embodiment, the projection of the first opening overlaps the projection of the contact connection in a plane perpendicular to the stacking direction.

[0007] In one embodiment, the protrusion has a first end away from the stacked structure and a second end close to the stacked structure; and on a plane perpendicular to the stacking direction, the projection of the second end overlaps the projection of the second opening, and the projection of the second opening overlaps the projection of the first end.

[0008] In one embodiment, after removing at least a portion of the protrusion, the size of the protrusion along the stacking direction is less than or equal to 150 nm.

[0009] Secondly, embodiments of this application provide a semiconductor device comprising: a stacked structure having a core region and a contact connection region; a contact connection portion located in and extending through the contact connection region; a gate line slot structure located in and extending through the core region; a semiconductor layer covering a first side of the stacked structure and disconnected at the locations of the contact connection portion and the gate line slot structure; and a dielectric layer covering the semiconductor layer, the contact connection portion, and the gate line slot structure.

[0010] In one embodiment, the gate gap structure further includes a portion extending into the dielectric layer, wherein the dimension of the portion of the gate gap structure extending into the dielectric layer along the stacking direction is less than or equal to 150 nm.

[0011] In one embodiment, the semiconductor layer is made of polycrystalline silicon, and the dielectric layer is made of silicon dioxide.

[0012] In one embodiment, the semiconductor device further includes: a peripheral circuit structure located on a second side of the stacked structure opposite to the first side, and electrically connected to the core region and the contact connection region.

[0013] Thirdly, embodiments of this application provide a memory system comprising: a three-dimensional memory including at least one semiconductor device as described in the embodiments above; and a controller coupled to the three-dimensional memory for controlling the storage of data in the three-dimensional memory.

[0014] According to the method for manufacturing a semiconductor device according to the embodiments of this application, by adding a second opening on the mask layer to expose the protrusion of the covered gate gap structure of the semiconductor layer, the protrusion is exposed through the second opening and the height of the protrusion is reduced, thereby improving the morphology of the dielectric layer surface, saving the chemical mechanical polishing process, and also reducing the thickness requirement of the dielectric layer, simplifying the semiconductor device fabrication method and saving manufacturing costs.

[0015] Furthermore, the semiconductor device and memory system according to the embodiments of this application improve the problem of excessive surface undulation of the dielectric layer covering the semiconductor layer, contact connection and gate gap structure by controlling the size of the portion of the gate gap structure extending into the dielectric layer along the stacking direction within a preset threshold range, thereby saving the chemical mechanical polishing process, reducing the thickness requirement of the dielectric layer, simplifying the semiconductor device fabrication method and saving manufacturing costs. Attached Figure Description

[0016] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0017] Figure 1 It is a schematic flowchart of the manufacturing of semiconductor devices according to the implementation of related technologies;

[0018] Figures 2A to 2E This is a schematic diagram of the intermediate structure of a semiconductor device during the manufacturing process, according to an implementation of related technologies;

[0019] Figure 3 This is a method for fabricating a semiconductor device according to another embodiment of the present disclosure;

[0020] Figures 4A to 4D This is a schematic diagram of an intermediate structure of a semiconductor device during the manufacturing process according to another embodiment of the present disclosure;

[0021] Figure 5 This is a system block diagram of an exemplary embodiment of the present application having a memory system; and

[0022] Figure 6A and Figure 6B This is a schematic diagram of a memory system according to an exemplary embodiment of this application. Detailed Implementation

[0023] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements.

[0024] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale.

[0025] Generally, terms can be understood at least partly from their use in context. For example, depending at least partly on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage, depending at least partly on the context.

[0026] Relative terms such as “below” or “bottom” and “above” or “top” may be used herein to describe the relationship between one element and another as shown in the figures. It should be understood that relative terms are intended to encompass different orientations of the device beyond those depicted in the figures. In an exemplary embodiment, when the device in one of the figures is flipped, an element described as being “below” the other element will be oriented “above” the other element. Thus, depending on the specific orientation of the figure, the exemplary term “below” can encompass both “below” and “above” orientations. Similarly, when the device in one of the figures is flipped, an element described as being “below” or “under” the other element will be oriented “above” the other element. Thus, the exemplary term “below” or “under” can encompass both “above” and “below” orientations.

[0027] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire upper or lower structure, or may have a extent smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or non-homogeneous continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers.

[0028] In this application, the use of “connection” or “linkage” may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0029] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0030] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0031] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0032] In the fabrication of three-dimensional memory (e.g., 3D NAND memory), the gate line gap structure has a portion extending into the substrate. After the substrate is removed, the gate line gap structure has protrusions protruding from the surface of the stacked structure, resulting in a highly undulating morphology for the subsequently formed dielectric layer. To bring out the electrical properties of the three-dimensional memory, the surface of the dielectric layer needs to be planarized (i.e., wafer surface planarization) for subsequent metal wiring. Related technologies require at least several steps for surface planarization, including etching and chemical mechanical polishing (CMP), making the process complex and costly.

[0033] Figure 1 A schematic flowchart illustrating the manufacturing of a semiconductor device according to the related technology of this application is shown. Figure 1 As shown, the method 1000 for manufacturing a semiconductor device provided by the related technology of this application may include:

[0034] S110 provides a semiconductor structure, wherein the semiconductor structure includes a stacked structure, a contact connection portion penetrating the stacked structure, and a gate line slot structure, wherein the gate line slot structure has a protrusion protruding from the stacked structure along the stacking direction of the stacked structure, and the semiconductor structure further includes a semiconductor layer covering the stacked structure, the contact connection portion, and the protrusion of the gate line slot structure.

[0035] S120, at least a portion of the semiconductor layer is removed to expose the contact connection.

[0036] S130, forming a dielectric layer covering the semiconductor layer and the contact connection portion.

[0037] S140, planarization of the dielectric layer.

[0038] The following will combine Figures 2A to 2EThe specific process steps S110-S140 of the above-described method for manufacturing semiconductor devices are described in detail.

[0039] Step S110

[0040] Figure 2A The diagram shows a specific example of a semiconductor structure provided in step S110 according to one embodiment of this application.

[0041] like Figure 2A As shown, the semiconductor structure provided in step S210 may include a stacked structure 10, a contact connection portion 40 penetrating the stacked structure 10, and a gate line slot structure 30. The gate line slot structure 30 has a protrusion 301 protruding from the stacked structure 10 along the stacking direction of the stacked structure 10. The semiconductor structure also includes a semiconductor layer 20 covering the stacked structure 10, the contact connection portion 40, and the protrusion 301 of the gate line slot structure 30. This semiconductor structure is suitable for fabricating semiconductor devices such as three-dimensional memory. Exemplarily, the semiconductor structure may also include multiple channel structures 101. In a three-dimensional memory, the area where the channel structures 101 are located is typically referred to as the core region of the three-dimensional memory, and the area where the contact connection portion 40 is located is typically referred to as the contact connection region of the three-dimensional memory.

[0042] In some embodiments of this application, along the stacking direction of the stacked structure 10, the size H of the protrusion 301 of the gate gap structure 30 protruding from the semiconductor layer 20 can be in the range of 200 nm to 500 nm.

[0043] In some embodiments of this application, the material of the gate gap structure 30 may include, for example, silicon (e.g., single-crystal silicon, polycrystalline silicon), silicon-germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), glass, III-V compound semiconductors, or any combination thereof.

[0044] In some embodiments of this application, the contact connection portion 40 penetrates the stacked structure 10 and serves as an electrical connection. Exemplarily, the contact connection portion 40 can be fabricated by first forming a conductive channel, and then filling the conductive channel with conductive material to form a conductive channel pillar. Exemplarily, the material of the conductive channel pillar can be any one or a combination of conductive materials, such as tungsten (W), cobalt (Co), copper (Cu), and aluminum (Al). In some embodiments, the contact connection portion 40 may only contain a solid conductive channel pillar; in other embodiments, such as... Figure 2A As shown, the contact connection portion 40 may also include a filling portion 401, that is, a filling portion 401 is made inside the conductive channel post, and the material of the filling portion 401 may be an insulating material.

[0045] In some embodiments of this application, the semiconductor layer 20 may include multiple layers of different materials. Figure 2A Only two layers are shown as an example. The material of semiconductor layer 20 may include, for example, silicon (e.g., monocrystalline silicon, polycrystalline silicon), silicon germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), glass, III-V compound semiconductors, or any combination thereof.

[0046] In some embodiments of this application, the semiconductor structure provided in step S110 is applicable to the fabrication of semiconductor devices such as three-dimensional memories. The semiconductor structure may further include a peripheral circuit structure 50, which is electrically connected to the core region and contact connection region of the three-dimensional memory via multiple interconnecting contacts 501. Therefore, the process for fabricating semiconductor devices such as three-dimensional memories also includes numerous steps, such as fabricating the core region and peripheral circuit structure 50 of the three-dimensional memory. However, to highlight the key points of the invention, this application does not describe the formation steps of the aforementioned semiconductor structure. Those skilled in the art can determine, based on their knowledge, the fabrication methods of the semiconductor devices disclosed in this application and other structures of three-dimensional memories. The embodiments and process flows in this application only show an intermediate form for forming a three-dimensional memory with a core region and contact connection region.

[0047] Step S120

[0048] At least a portion of the semiconductor layer 20 is removed to expose the contact connection portion 40.

[0049] According to one embodiment of this application, such as Figure 2B As shown, a patterned mask layer 60 is formed on the surface of the semiconductor layer 20 away from the stacked structure 10. This mask layer 60 has a first opening 601 that exposes the covering contact connection portion 40 of the semiconductor layer 20. Exemplarily, the mask layer 60 is a photoresist layer, and the first opening 601 can be formed using a photolithography process. Subsequently, as... Figure 2C As shown, the portion of the semiconductor layer 20 covering the contact connection portion 40 is etched through the first opening 601 to form a shallow isolation trench 201 exposing the contact connection portion 40. In an exemplary embodiment, a dry etching process or a wet etching process can be used to remove the portion of the semiconductor layer 20 covering the contact connection portion 40, but it is not limited thereto.

[0050] In an exemplary embodiment, on a plane perpendicular to the stacking direction, the projection of the first opening 601 covers the projection of the contact connection portion 40. This arrangement helps to ensure that the shallow isolation trench 201 formed by etching the semiconductor layer 20 can fully expose the contact connection portion 40, and ensures that the contact connection portion 40 and the semiconductor layer 20 maintain a certain distance, thereby achieving good and reliable electrical isolation.

[0051] Step S130

[0052] A dielectric layer 70 is formed covering the semiconductor layer 20 and the contact connection portion 40. Figure 2D The diagram shows a specific example of a semiconductor structure provided in step S130 according to one embodiment of this application.

[0053] In an exemplary embodiment, a dielectric layer 70 may be deposited on the surface of the semiconductor layer 20 and the contact connection portion 40 away from the stacked structure 10 by means of, for example, CVD, PVD, ALD or any combination thereof.

[0054] For example, the material of the dielectric layer 70 can be either silicon nitride or silicon oxide, but is not limited thereto; the dielectric layer 70 can also be other suitable materials.

[0055] because Figures 2A to 2C Semiconductor layer 20 is shown only as an example of two layers, where the material of dielectric layer 70 is the same as the material of a layer in semiconductor layer 20 that is farther away from stacked structure 10, for example... Figure 2D and subsequent Figure 2E In the diagram, only one semiconductor layer 20 is shown, but in reality, there are two semiconductor layers 20. The semiconductor layer 20 that is far from the stacked structure 10 has the same color as the dielectric layer 70, so it is not shown.

[0056] Since the gate gap structure 30 of the semiconductor structure provided in step S110 has a protrusion 301 protruding from the stacked structure 10 along the stacking direction of the stacked structure 10, the dielectric layer covering the semiconductor layer 20 and the contact connection portion 40 formed in step S130 also has a protruding morphology.

[0057] In the manufacturing process of semiconductor devices such as three-dimensional memory, in order to bring out the electrical performance of the channel structure 101 or the peripheral circuit structure 50, it is necessary to planarize the surface of the dielectric layer 70 so that metal wiring can be fabricated subsequently.

[0058] Step S140

[0059] In an exemplary embodiment of step S140, the dielectric layer 70 may be planarized using, for example, a chemical mechanical polishing (CMP) process.

[0060] Figure 2E The diagram illustrates a specific example of a semiconductor structure provided in step S140 according to one embodiment of this application. The dielectric layer 70 should have a certain thickness requirement to ensure that the remaining dielectric layer 70 after planarization can cover the protrusion 301 of the gate slot structure 30. Therefore, along the stacking direction of the stacked structure 10, the thickness of the dielectric layer 70 must be at least greater than the dimension H (refer to the reference dimension) of the protrusion 301 of the gate slot structure 30 protruding from the semiconductor layer 20. Figure 2A ).

[0061] The aforementioned method 1000 requires a chemical mechanical polishing process to planarize the surface of the dielectric layer 70, and it has high requirements for the thickness of the dielectric layer 70. The process is complex and costly. Therefore, to reduce costs and simplify processes, some embodiments of this application provide different methods than those described above. Figures 1 to 2E The method for fabricating semiconductor devices is shown. Figure 3 A flowchart illustrating a method for fabricating a semiconductor device 2000 in another embodiment is shown schematically. (See attached diagram.) Figure 3 As shown, method 2000 includes:

[0062] S210: Provides a semiconductor structure, wherein the semiconductor structure includes a stacked structure, a contact connection portion penetrating the stacked structure, and a gate line slot structure, wherein the gate line slot structure has a protrusion portion protruding from the stacked structure along the stacking direction of the stacked structure, and the semiconductor structure further includes a semiconductor layer covering the stacked structure, the contact connection portion, and the protrusion portion of the gate line slot structure.

[0063] S220: Remove at least a portion of the semiconductor layer to expose the contact connection and the protrusion;

[0064] S230: Remove at least a portion of the protrusion; and

[0065] S240: A dielectric layer that forms the semiconductor layer, contact connection portion and gate line gap structure.

[0066] It should be understood that the steps shown in method 2000 are not exclusive, and other steps may be performed before, after, or between any of the steps shown. Furthermore, some of the steps may be performed simultaneously or in a manner different from [the steps described]. Figure 3 The execution is performed in the order shown.

[0067] Figures 4A to 4D This is a cross-sectional schematic diagram of a semiconductor device fabrication method 2000 according to an embodiment of this application. The following is in conjunction with... Figures 4A to 4D The above steps S210 to S240 are further described.

[0068] Step S210

[0069] Figure 4A The diagram shows a specific structural example of the semiconductor structure provided in step S210 according to one embodiment of this application. Exemplarily, Figure 4A Can be with Figure 2A Exactly the same.

[0070] It should be noted that the following is based on... Figure 4A and Figure 2A Using the exact same scenario as an example, the semiconductor structure provided in step S110 can be fully applied to step S210, but it should be understood that this application is not limited to this. Figure 4A or Figure 2A The situation is shown.

[0071] Step S220

[0072] At least a portion of the semiconductor layer 20 is removed to expose the contact connection portion 40 and the protrusion portion 301.

[0073] According to one embodiment of this application, such as Figure 4B As shown, a patterned mask layer 60 is formed on the surface of the semiconductor layer 20 away from the stacked structure 10. The mask layer 60 has a first opening 601 and a second opening 602. The first opening 601 exposes a portion of the semiconductor layer 20 that covers the contact connection portion 40, and the second opening 602 exposes a portion of the semiconductor layer 20 that covers the gate line slot structure 30.

[0074] In an exemplary embodiment, the mask layer 60 is a photoresist layer, and the first opening 601 and the second opening 602 can be formed using a photolithography process. The fabrication process and method of the first opening 601 and the second opening 602 can be the same, that is, the first opening 601 and the second opening 602 can be formed simultaneously using the same mask.

[0075] Subsequently, as Figure 4C As shown, the semiconductor layer 20 is etched through the first opening 601 and the second opening 602 to expose the contact connection portion 40 and the protrusion portion 301. In an exemplary embodiment, the semiconductor layer 20 can be etched through the first opening 601 and the second opening 602 using either a dry etching process or a wet etching process, but is not limited thereto.

[0076] In an exemplary embodiment, on a plane perpendicular to the stacking direction, the projection of the first opening 601 covers the projection of the contact connection portion 40. This arrangement helps to ensure that the shallow isolation trench 201 formed by etching the semiconductor layer 20 can fully expose the contact connection portion 40, and ensures that the contact connection portion 40 and the semiconductor layer 20 maintain a certain distance, thereby achieving good and reliable electrical isolation.

[0077] In an exemplary embodiment, the protrusion 301 has a first end away from the stacked structure 10 and a second end close to the stacked structure 10; on a plane perpendicular to the stacking direction, the projection of the second end overlaps the projection of the second opening 602, and the projection of the second opening 602 overlaps the projection of the first end. Exemplarily, the protrusion 301 may resemble a raised hill, with the first end away from the stacked structure 10 (i.e., the top end) being small and the second end close to the stacked structure 10 (i.e., the bottom end) being large.

[0078] For example, the etching of the semiconductor layer 20 through the first opening 601 and the second opening 602 can be performed simultaneously, exposing the contact connection portion 40 while also exposing the first end of the protrusion 301 away from the stacked structure 10.

[0079] Step S230

[0080] After the contact connection portion 40 and the protrusion portion 301 are exposed in step S220, step S230 is performed to remove at least a portion of the protrusion portion 301. Figure 4C A specific structural example of the semiconductor structure provided in step S230 according to one embodiment of this application is also shown.

[0081] For example, at least a portion of the protrusion 301 can be removed using a process such as wet etching. Since the contact connection portion 40 and the protrusion 301 are made of different materials and have different etching selectivity ratios, the contact connection portion 40 will not be further etched away when at least a portion of the protrusion 301 is removed using a process such as wet etching.

[0082] For example, the material of the contact connection portion 40 is a conductive material, such as any one or combination of tungsten (W), cobalt (Co), copper (Cu), and aluminum (Al), while the material of the protrusion portion 301 may include, for example, silicon (e.g., single crystal silicon, polycrystalline silicon), silicon germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), glass, III-V compound semiconductors, or any combination thereof.

[0083] In an exemplary embodiment, the protrusion 301 may resemble a raised hill, with a smaller first end (i.e., top end) away from the stacked structure 10 and a larger second end (i.e., bottom end) closer to the stacked structure 10. The projection of the bottom end covers the projection of the second opening 602, and the projection of the second opening 602 covers the projection of the top end. In other words, the size of the second opening 602 is between the top and bottom dimensions of the protrusion 301. This arrangement ensures that at least a portion of the top end of the protrusion 301 is etched through the second opening 602.

[0084] In an exemplary embodiment, after removing at least a portion of the protrusion 301, the remaining protrusion 301 protrudes by a dimension h (refer to) of the semiconductor layer 20 along the stacking direction. Figure 4C The amplified portion is less than or equal to 150nm.

[0085] Step S240

[0086] A dielectric layer 70 is formed covering the semiconductor layer 20, the contact connection portion 40, and the gate line gap structure 30. Figure 4D The diagram shows a specific example of a semiconductor structure provided in step S240 according to one embodiment of this application.

[0087] In an exemplary embodiment, a dielectric layer 70 may be deposited on the surface of the semiconductor layer 20, the contact connection portion 40, and the gate line gap structure 30 away from the stacked structure 10 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), ALD, or any combination thereof.

[0088] For example, the material of the dielectric layer 70 can be either silicon nitride or silicon oxide, but is not limited thereto; the dielectric layer 70 can also be other suitable materials.

[0089] Since the protrusions 301 of the gate gap structure 30 have been substantially removed after step S230, and the semiconductor structure does not have obvious protrusions, the dielectric layer 70 covering the semiconductor layer 20, contact connection portion 40, and gate gap structure 30 formed in step S240 also does not have obvious protrusion morphology. Furthermore, in the manufacturing process of semiconductor devices such as three-dimensional memory, when the electrical properties of the channel structure 101 or peripheral circuit structure 50 of the three-dimensional memory are brought out, the step of planarizing the dielectric layer 70 using, for example, a chemical mechanical polishing process can be omitted.

[0090] It is worth noting that even in some cases, if the protrusion 301 of the grid line slot structure 30 does not meet the planarization requirements after step S230, then the planarization correction of the dielectric layer 70 can be achieved simply by using a small amount of chemical mechanical polishing process.

[0091] Furthermore, since the protrusions 301 of the gate slot structure 30 have been substantially removed after step S230, and the semiconductor structure no longer has obvious protrusions, the thickness requirement for the dielectric layer 70 covering the semiconductor layer 20, the contact connection portion 40, and the gate slot structure 30 is significantly reduced. Along the stacking direction of the stacked structure 10, the thickness of the dielectric layer 70 only needs to be greater than the remaining protrusion 301 protruding from the semiconductor layer 20 by the dimension h (refer to...) along the stacking direction. Figure 4C (The enlarged portion) is sufficient.

[0092] The above disclosure of this application provides a method for fabricating a semiconductor device 2000. According to at least one embodiment of this application, by adding a second opening 602 to the mask layer 60 to expose the protrusion 301 of the cover gate gap structure 30 of the semiconductor layer 20, the protrusion 301 is exposed through the second opening 602 and the height of the protrusion 301 is reduced, thereby improving the morphology of the dielectric layer 70 surface, saving the chemical mechanical polishing process, and also reducing the thickness requirement of the dielectric layer 70, simplifying the semiconductor device fabrication method and saving manufacturing costs.

[0093] Another aspect of this application provides a semiconductor device. Figure 4D This is a cross-sectional view showing a semiconductor device 400 according to an embodiment of the present disclosure. Reference will be made below. Figure 4D The semiconductor device 400 is described in detail. The semiconductor device 400 can be fabricated using any of the methods described above.

[0094] The semiconductor device 400 may include a stacked structure 10 having a core region 110 and a contact connection region 120.

[0095] The semiconductor device 400 also includes a contact connection portion 40 located in and passing through the contact connection area 120, and a gate line slot structure 30 located in and passing through the core area 110.

[0096] The semiconductor device 400 also includes a semiconductor layer 20 that covers a first side of the stacked structure 10 and is disconnected at the locations of the contact connection portion 40 and the gate line gap structure 30. Figure 4D The semiconductor layer 20 is shown as a single layer only, but in some embodiments, the semiconductor layer 20 may include multiple layers of different materials. The materials of the semiconductor layer 20 may include, for example, silicon (e.g., single crystal silicon, polycrystalline silicon), silicon germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), glass, III-V compound semiconductors, or any combination thereof.

[0097] The semiconductor device 400 also includes a dielectric layer 70, which covers the semiconductor layer 20, the contact connection portion 40, and the gate line gap structure 30. Exemplarily, the material of the dielectric layer 70 can be any one of silicon nitride and silicon oxide, but is not limited thereto; the dielectric layer 70 can also be other suitable materials.

[0098] The gate line slot structure 30 also includes a portion (i.e., a protrusion 301) extending into the dielectric layer 70. Exemplarily, the portion of the gate line slot structure 30 extending into the dielectric layer 70 has a dimension h' along the stacking direction (refer to...). Figure 4DThe amplified portion is less than or equal to 150nm.

[0099] like Figure 4D As shown, the semiconductor device 400 may further include a peripheral circuit structure 50, which is located on the second side of the stacked structure 10 opposite to the first side and is electrically connected to the core region 110 and the contact connection region 120 through a plurality of interconnecting contacts 501.

[0100] In some embodiments of this application, the contact connection portion 40 penetrates the stacked structure 10 and serves as an electrical connection. Exemplarily, the contact connection portion 40 can be fabricated by first forming a conductive channel, and then filling the conductive channel with conductive material to form a conductive channel pillar. Exemplarily, the material of the conductive channel pillar can be any one or a combination of conductive materials, such as tungsten (W), cobalt (Co), copper (Cu), and aluminum (Al). In some embodiments, the contact connection portion 40 may only contain a solid conductive channel pillar; in other embodiments, such as... Figure 4D As shown, the contact connection portion 40 may also include a filling portion 401, that is, a filling portion 401 is made inside the conductive channel post, and the material of the filling portion 401 may be an insulating material.

[0101] Since the content and structure described in the above description of preparation methods 1000 and 2000 can be fully or partially applied to the semiconductor devices described here, related or similar content will not be repeated.

[0102] Although exemplary fabrication methods and structures of semiconductor devices have been described herein, it will be understood that one or more features may be omitted, substituted, or added to the structure of the semiconductor device. For example, the peripheral circuit structure 50 may be configured as needed.

[0103] According to one embodiment of the present application, the semiconductor structure provides that by controlling the dimension of the portion of the gate gap structure 30 extending into the dielectric layer 70 along the stacking direction within a preset threshold range, the problem of excessive surface undulation of the dielectric layer 70 covering the semiconductor layer 20, the contact connection portion 40, and the gate gap structure 30 is improved. This saves on chemical mechanical polishing processes and also reduces the thickness requirement of the dielectric layer 70, simplifying the fabrication method of the semiconductor device and saving manufacturing costs.

[0104] Some embodiments of this application also provide a memory system. Figure 5 This is a block diagram of a system 10 having a memory system 12 according to an exemplary embodiment of this application.

[0105] System 10 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a memory system 12 located therein). Figure 5 As shown, system 10 may include a host 18 and a memory system 12, the memory system 12 having one or more three-dimensional memories 14 and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to and from the three-dimensional memories 14.

[0106] The three-dimensional memory 14 may include the semiconductor devices described in any embodiment of this application, for example, Figure 4DThe semiconductor device 400 is shown. According to some embodiments, a controller 16 is coupled to the three-dimensional memory 14 and the host 18, and is configured to control the three-dimensional memory 14. The controller 16 can manage data stored in the three-dimensional memory 14 and communicate with the host 18. In some embodiments, the controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the controller 16 is designed to operate in a high duty cycle environment, such as an SSD or embedded multi-media card (eMMC) used as a data storage device in mobile devices such as smartphones, tablets, laptops, etc. The controller 16 can be configured to control the operation of the three-dimensional memory 14, such as read, erase, and program operations. The controller 16 may also be configured to manage various functions related to data stored in or to be stored in the 3D memory 14, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the controller 16 is further configured to process error correction codes (ECCs) related to data read from or written to the 3D memory 14. The controller 16 may also perform any other appropriate functions, such as formatting the 3D memory 14. The controller 16 may communicate with external devices (e.g., the host 18) according to a specific communication protocol. For example, the controller 16 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0107] The controller 16 and one or more three-dimensional memories 14 can be integrated into various types of memory systems, for example, included in the same package (such as a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 12 can be implemented and packaged into different types of end electronic products. Figure 6AIn one example shown, the controller 16 and a single three-dimensional memory 14 may be integrated into the memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 22 may further include a connection between the memory card 22 and a host (e.g., Figure 5 The host 18) is coupled to the memory card connector 24. In such a way... Figure 6B In another example shown, the controller 16 and multiple 3D memories 14 may be integrated into the SSD 26. The SSD 26 may further include a connection between the SSD 26 and a host (e.g., Figure 5 The SSD connector 28 is coupled to the host 18. In some embodiments, the storage capacity and / or operating speed of the SSD 26 is higher than that of the memory card 22.

[0108] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the described technical concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions in this application.

Claims

1. A method for fabricating a semiconductor device, wherein, The method includes: A semiconductor structure is provided, wherein the semiconductor structure includes a stacked structure, a contact connection portion penetrating the stacked structure, and a gate line slot structure, wherein the gate line slot structure has a protrusion protruding from the stacked structure along the stacking direction of the stacked structure, and the semiconductor structure further includes a semiconductor layer covering the stacked structure, the contact connection portion, and the protrusion of the gate line slot structure; Remove at least a portion of the semiconductor layer to expose the contact connection and the protrusion; Remove at least a portion of the protrusion; and A dielectric layer is formed covering the semiconductor layer, the contact connection portion, and the gate line gap structure.

2. The method according to claim 1, wherein, Removing at least a portion of the semiconductor layer to expose the contact connection and the protrusion includes: A patterned mask layer is formed on the surface of the semiconductor layer away from the stacked structure. The mask layer includes a first opening and a second opening, wherein the first opening exposes the portion of the semiconductor layer covering the contact connection, and the second opening exposes the portion of the semiconductor layer covering the gate gap structure. The semiconductor layer is etched through the first opening and the second opening to expose the contact connection portion and the protrusion portion.

3. The method according to claim 2, wherein, On a plane perpendicular to the stacking direction, the projection of the first opening overlaps the projection of the contact connection.

4. The method according to claim 2, wherein, The protrusion has a first end away from the stacked structure and a second end close to the stacked structure; as well as On a plane perpendicular to the stacking direction, the projection of the second end overlaps the projection of the second opening, and the projection of the second opening overlaps the projection of the first end.

5. The method according to any one of claims 1 to 4, wherein, After removing at least a portion of the protrusion, the size of the protrusion along the stacking direction is less than or equal to 150 nm.

6. A semiconductor device, comprising: The stacked structure has a core area and a contact connection area; A contact connection portion is located in and extends through the contact connection area; A grid line slot structure is located in and penetrates the core region; A semiconductor layer covers the first side of the stacked structure and is disconnected at the locations of the contact connection and the gate gap structure; as well as A dielectric layer that covers the semiconductor layer, the contact connection portion, and the gate line gap structure.

7. The semiconductor device according to claim 6, wherein, The gate wire slot structure also includes a portion extending into the dielectric layer. The portion of the gate gap structure extending into the dielectric layer along the stacking direction has a dimension of less than or equal to 150 nm.

8. The semiconductor device according to claim 6, wherein, The semiconductor layer is made of polycrystalline silicon, and the dielectric layer is made of silicon dioxide.

9. The semiconductor device according to claim 6, wherein, The semiconductor device further includes: The peripheral circuit structure is located on the second side of the stacked structure opposite to the first side, and is electrically connected to the core area and the contact connection area.

10. A memory system, characterized in that, include: A three-dimensional memory, comprising at least one semiconductor device as described in any one of claims 6 to 9; as well as A controller, coupled to the three-dimensional memory, is used to control the storage of data in the three-dimensional memory.

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