Chip and electronic device

Abstract

Embodiments of the present application provide a chip and an electronic device, the chip comprising: a plurality of chip ports, a port multiplexing logic module and a scan test logic module, the port multiplexing logic module having a plurality of groups of first ports and a plurality of groups of second ports, the plurality of chip ports being divided into a plurality of groups according to a preset granularity; each group of chip ports being connected to at least one of the plurality of groups of first ports and the plurality of groups of second ports of the port multiplexing logic module, the plurality of groups of first ports or the plurality of groups of second ports of the port multiplexing logic module being connected to the scan test logic module; the port multiplexing logic module being configured to control the gating of a path between the chip ports and the scan test logic module according to a control instruction in units of the preset granularity. Embodiments of the present application can solve the problem of unreasonable I / O distribution and long test time of large-scale complex chips in the related art, improve the degree of freedom of I / O distribution by setting the granularity of I / O distribution, dynamically adjust the I / O resources in the test phase, and reduce the chip test time.

Description

Technical Field

[0001] This application relates to the field of chip design, and more specifically, to a chip and an electronic device. Background Technology

[0002] As the complexity of integrated circuits continues to increase, scan chain testing technology plays a crucial role in effectively screening for chip faults and reducing test time. With the continuous development of integrated circuit scale, to avoid excessively long scan chains hindering testing, it is necessary to introduce embedded deterministic testing (EDT) compression technology to increase the number of scan chains while reducing their length. However, with the number of scan chains constantly increasing, and the chip's input / output (I / O) resources relatively limited, time-sharing multiplexing of I / O resources is required.

[0003] The commonly used pin multiplexing (PinMux) method in the industry involves grouping different modules and allocating fixed I / O resources to them. However, in the early stages of chip design, it is impossible to accurately determine the complexity and power consumption distribution of each module. The optimal grouping strategy can only be obtained after signoff or even tape-out. Traditional grouping methods have fixed I / O allocations, making it impossible to adjust the design based on the optimal grouping. This can easily lead to unreasonable I / O allocation, resulting in complex modules not receiving enough I / O resources, causing long testing times, uneven power consumption distribution, and device voltage drops.

[0004] In summary, there is still no good solution to the problems of unreasonable I / O allocation and long testing time in large-scale complex chips in related technologies. Summary of the Invention

[0005] This application provides a chip and electronic device to at least solve the problems of unreasonable I / O allocation and long testing time in large-scale complex chips in related technologies.

[0006] According to one embodiment of this application, a chip is provided, the chip including a plurality of chip ports, a port multiplexing logic module, and a scan test logic module, wherein: the port multiplexing logic module has a plurality of first ports and a plurality of second ports, the plurality of chip ports are divided into multiple groups according to a preset granularity; each group of chip ports is connected to at least one of the plurality of first ports and the plurality of second ports of the port multiplexing logic module, and the plurality of first ports or the plurality of second ports of the port multiplexing logic module are connected to the scan test logic module; the port multiplexing logic module is used to control the selection of the path between the chip ports and the scan test logic module according to control instructions in units of the preset granularity.

[0007] According to yet another embodiment of this application, an electronic device is also provided, including the chip in any of the above embodiments.

[0008] Through the embodiments of this application, a chip is designed that improves the freedom of I / O allocation by setting the granularity of I / O allocation. The conduction relationship between input ports and output ports is controlled in units of granularity, which can solve the problems of unreasonable I / O allocation and long test time in large-scale complex chips in related technologies. I / O resources can also be dynamically adjusted during the testing phase, effectively reducing chip testing time. Attached Figure Description

[0009] Figure 1 This is a structural block diagram of the chip according to an embodiment of this application;

[0010] Figure 2 This is a structural block diagram of another chip according to an embodiment of this application;

[0011] Figure 3 This is a schematic diagram of the circuit structure of the chip according to an embodiment of this application;

[0012] Figure 4 This is a schematic diagram of the circuit structure of a port multiplexing logic module according to an embodiment of this application (I);

[0013] Figure 5 This is a schematic diagram of the circuit structure of a port multiplexing logic module according to an embodiment of this application (II);

[0014] Figure 6 This is a schematic diagram of the circuit structure of a port multiplexing logic module according to an embodiment of this application (III);

[0015] Figure 7 This is a schematic diagram of the circuit structure of a port multiplexing logic module according to an embodiment of this application (IV). Detailed Implementation

[0016] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0017] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0018] This application provides a chip for embedded deterministic testing. As chip size continues to increase, the number of scan chains to be tested also increases. However, the chip's I / O resources are relatively limited. The chip under test designed according to the following embodiments can readjust the connection relationship between the chip port and the scan chain to be tested inside the chip during the chip testing phase, realizing dynamic adjustment and flexible allocation of I / O resources.

[0019] Figure 1 This is a structural block diagram of the chip according to an embodiment of this application, such as... Figure 1 As shown, the chip includes the following structure:

[0020] Multiple chip ports 12, port multiplexing logic module 14 and scan test logic module 16.

[0021] In this embodiment, the port multiplexing logic module has multiple sets of first ports and multiple sets of second ports, and the multiple chip ports are divided into multiple groups according to a preset granularity.

[0022] In this embodiment, each group of chip ports is connected to at least one of the multiple groups of first ports and multiple groups of second ports of the port multiplexing logic module, and the multiple groups of first ports or multiple groups of second ports of the port multiplexing logic module are connected to the scan test logic module.

[0023] In this embodiment, the port multiplexing logic module is used to control the selection of the path between the chip port and the scan test logic module in units of preset granularity according to control instructions.

[0024] Through the embodiments of this application, port grouping can be achieved by preset granularity, which improves the degree of freedom of I / O allocation. The conduction relationship between input ports and output ports can be controlled in units of granularity, which can solve the problems of unreasonable I / O allocation and long test time in large-scale complex chips in related technologies. I / O resources can also be dynamically adjusted during the testing phase, effectively reducing chip testing time.

[0025] In some embodiments, the plurality of chip ports are divided into i+1 groups, and the number of port groups of the scan test logic module is j+1, where i is less than j, and i and j are positive integers. When the chip port is a chip input port, the plurality of first ports of the port multiplexing logic module are plurality of input ports, and the plurality of second ports of the port multiplexing logic module are plurality of output ports, each group of chip ports is connected to at least one of the plurality of first ports of the port multiplexing logic module, the plurality of second ports of the port multiplexing logic module are connected to the scan test logic module, the number of input port groups of the port multiplexing logic module is i+1, and the number of output port groups of the port multiplexing logic module is j+1.

[0026] In some embodiments, the port multiplexing logic module includes j+1 first multiplexer groups, wherein each first multiplexer group is connected to i+1 input port groups of the port multiplexing logic module, and each first multiplexer group is connected to one output port group of the port multiplexing logic module; the first multiplexer group is used to select one target input port group and the corresponding target output port group from the i+1 input port groups according to the control instruction.

[0027] In some embodiments, when the preset granularity is N, each input port group contains N input ports, each output port group contains N output ports, and each first multiplexer group contains N first multiplexers.

[0028] In some embodiments, the port multiplexing logic module further includes: i+1 input register groups and j+1 input channel register groups; the i+1 input port groups are connected to each of the first multiplexer groups through the i+1 input register groups; each of the first multiplexer groups is connected to one output port group through one of the input channel register groups.

[0029] In some embodiments, the port multiplexing logic module includes i+1 first multiplexer groups and j+1 OR operation modules, wherein each first multiplexer group is connected to one input port group of the port multiplexing logic module, each first multiplexer group is connected to the j+1 OR operation modules, and each OR operation module is connected to one output port group of the port multiplexing logic module; the first multiplexer groups are used to select one target output port group and the corresponding target input port group from the j+1 output port groups according to the control instruction.

[0030] In some embodiments, when the preset granularity is N, each input port group contains N input ports, each output port group contains N output ports, and each first multiplexer group contains N first multiplexers.

[0031] In some embodiments, the port multiplexing logic module further includes: i+1 input register groups and j+1 input channel register groups; each input port group is connected to a first multiplexer group through one input register group; each OR operation module is connected to an output port group through one input channel register group.

[0032] In some embodiments, the plurality of chip ports are divided into i+1 groups, and the number of port groups in the scan test logic module is j+1, where i is less than j, and i and j are positive integers. When the chip port is a chip output port, the plurality of second ports of the port multiplexing logic module are plurality of output ports, and the plurality of first ports of the port multiplexing logic module are plurality of input ports, each group of chip ports is connected to at least one of the plurality of second ports of the port multiplexing logic module, the plurality of first ports of the port multiplexing logic module are connected to the scan test logic module, the number of input port groups of the port multiplexing logic module is j+1, and the number of output port groups of the port multiplexing logic module is i+1.

[0033] In some embodiments, the port multiplexing logic module includes i+1 second multiplexer groups, wherein each second multiplexer group is connected to j+1 input port groups of the port multiplexing logic module, and each second multiplexer group is connected to one output port group of the port multiplexing logic module; the second multiplexer group is used to select one target input port group and the corresponding target output port group from the j+1 input port groups according to the control instruction.

[0034] In some embodiments, when the preset granularity is N, each input port group contains N input ports, each output port group contains N output ports, and each second multiplexer group contains N second multiplexers.

[0035] In some embodiments, the port multiplexing logic module further includes: j+1 output channel register groups and i+1 output register groups; each input port group is connected to each of the second multiplexer groups through one of the output channel register groups, and each of the second multiplexer groups is connected to one output port group through one output register group.

[0036] In some embodiments, the port multiplexing logic module includes j+1 second multiplexer groups and i+1 OR operation modules, wherein each second multiplexer group is connected to one input port group of the port multiplexing logic module, each second multiplexer group is connected to the i+1 OR operation modules, and each OR operation module is connected to one output port group of the port multiplexing logic module; the second multiplexer groups are used to select one target output port group and the corresponding target input port group from the i+1 output port groups according to the control instruction.

[0037] In some embodiments, when the preset granularity is N, each input port group contains N input ports, each output port group contains N output ports, and each second multiplexer group contains N second multiplexers.

[0038] In some embodiments, the port multiplexing logic module further includes: j+1 output channel register groups and i+1 output register groups; each input port group is connected to a second multiplexer group through one output channel register group; each OR operation module is connected to one output port group through one output register group.

[0039] This application also provides a test chip in its embodiments.

[0040] Figure 2 This is a structural block diagram of another chip according to an embodiment of this application, such as... Figure 2 As shown, the chip includes:

[0041] Chip port 22, controller 24, port multiplexing logic module 26 and scan test logic module 28.

[0042] In this embodiment, the chip port is connected to the port of the scan test logic module through the port multiplexing logic module, wherein the number of chip ports is less than the number of ports of the scan test logic module.

[0043] In this embodiment, the controller is used to send control commands to the port multiplexing logic module.

[0044] In this embodiment, the port multiplexing logic module is the port multiplexing logic module in any of the above embodiments, and can be a port multiplexing logic module and / or a port multiplexing logic module.

[0045] In this embodiment, the scan test logic module includes: multiple embedded deterministic test EDT channel chains, wherein the port of the scan test logic module is the port of the EDT channel chain.

[0046] Furthermore, the scanning test logic module is used to test the EDT channel chain that is connected to the chip port.

[0047] In some embodiments, the scan test logic module may include multiple scan test modules, wherein each scan test module includes at least one EDT channel chain; the scan test logic module is used to test each of the multiple test groups at different times, wherein each test group includes at least one EDT channel chain group, wherein the multiple EDT channel chains are divided into multiple EDT channel chain groups according to the preset granularity, and the multiple test groups are allocated according to the attribute parameters of the multiple scan test modules.

[0048] Through the embodiments of this application, test groups can be dynamically adjusted according to the attribute parameters of the test modules during the chip testing stage, effectively reducing test time and thus solving the problems of unreasonable I / O allocation and long test time in large-scale complex chips in related technologies.

[0049] Figure 3 This is a schematic diagram of the circuit structure of the chip in an embodiment of this application, as shown below. Figure 3 As shown, the chip includes the following structure:

[0050] Multiple general-purpose input ports 100, port multiplexing logic module 200, scan test logic module 300, port multiplexing logic module 400, multiple general-purpose output ports 500, and controller 600.

[0051] In this embodiment, the plurality of general-purpose input ports 100 are equivalent to the chip input ports in the above embodiments, and the plurality of general-purpose output ports 500 are equivalent to the chip output ports in the above embodiments.

[0052] In this embodiment, multiple general-purpose input ports and multiple general-purpose output ports are divided into multiple I / O groups according to a preset granularity.

[0053] Furthermore, data is input to the port multiplexing logic module from the general-purpose input / output (GPIO) port, and after passing through the scan test logic module, the test results are output from the general-purpose output port.

[0054] In this embodiment, multiple general-purpose input ports are connected to multiple input terminals of the port multiplexing logic module, multiple output terminals of the port multiplexing logic module are connected to multiple input terminals of the scan test logic module, multiple output terminals of the scan test logic module are connected to multiple input terminals of the port multiplexing logic module, multiple output terminals of the port multiplexing logic module are connected to the multiple general-purpose output ports, and the controller is connected to the port multiplexing logic module and the port multiplexing logic module respectively.

[0055] In this embodiment, granularity is used to describe the I / O grouping situation, that is, the number of I / Os contained in each group. The size of the granularity directly affects the degree of freedom of I / O allocation and the logic increment in the I / O multiplexing logic module during scan testing. The minimum granularity can be set to 1.

[0056] Furthermore, finer granularity allows for greater freedom in I / O allocation, but also necessitates the introduction of more scan I / O reuse logic. Conversely, larger granularity simplifies scan I / O reuse logic but limits the freedom of I / O allocation during scan testing. Therefore, granularity should be appropriately configured during chip design to achieve a balance between the freedom of I / O allocation and the amount of I / O reuse logic.

[0057] In this embodiment, the grouping of logic units in each port or module within the chip is done in granularity.

[0058] In this embodiment, the scanning test logic module is used to test the embedded deterministic test (EDT) channel chain that is connected to the general input port and the general output port.

[0059] Specifically, the EDT channel chain is obtained by compressing the scan chain and is the basic unit of Embedded Deterministic Testing (EDT).

[0060] In this embodiment, the controller is used to send control commands to the port multiplexing logic module and the port multiplexing logic module respectively.

[0061] In this embodiment, the port multiplexing logic module is used to connect the plurality of general-purpose input ports and a portion of the input terminals of the scan test logic module in units of the I / O groups according to the control instructions, wherein the number of the plurality of general-purpose input ports is less than the number of the plurality of input terminals of the scan test logic module.

[0062] In this embodiment, the port multiplexing logic module is used to connect a portion of the output terminals of the scan test logic module to the plurality of general-purpose output ports in units of the I / O groups according to the control instructions, wherein the number of the plurality of general-purpose output ports is less than the number of the plurality of output terminals of the scan test logic module.

[0063] Furthermore, the port multiplexing logic module is used to implement time-division multiplexing of general-purpose input ports, and the port multiplexing logic module is used to implement time-division multiplexing of general-purpose output ports.

[0064] Specifically, the number of general-purpose output / output ports is less than the number of input / output terminals of the scan test logic module. By instructing the port multiplexing logic module through the controller, the general-purpose output / output ports can be connected to different input / output terminals in the scan test logic module at different times, thus realizing time-division multiplexing of the general-purpose output / output ports, thereby ensuring the test effect of the scan test logic module under the condition of limited I / O resources.

[0065] In some embodiments, the controller 600 may be a Test Access Port (TAP) controller, or other device that can output control signals and control multiplexers / demultiplexers, and this application does not limit this.

[0066] Through the embodiments of this application, dynamic adjustment of I / O resources is realized during the testing phase, so that I / O allocation is not limited by the chip design phase. It can even dynamically adjust the grouping of test modules in different test modes according to the actual situation of the module under test, thereby effectively reducing chip testing time and solving the problems of unreasonable I / O allocation and long testing time of large-scale complex chips in related technologies.

[0067] In some embodiments, the preset granularity is N, and each I / O group contains N general-purpose input ports and N general-purpose output ports, where N is a positive integer.

[0068] In some embodiments, the scan test logic module includes a plurality of scan test modules, wherein each scan test module includes at least one EDT channel chain, the input of each EDT channel chain is an input of the scan test logic module, and the output of each EDT channel chain is an output of the scan test logic module.

[0069] In some embodiments, a scan test logic module is configured to test each of a plurality of test groups at different times, wherein each test group contains at least one EDT channel chain group, each EDT channel chain group contains N EDT channel chains, and the plurality of test groups are allocated according to attribute parameters of the plurality of scan test modules.

[0070] Furthermore, the number of ports in each I / O group and the number of EDT channel chains in each EDT channel chain group are the same as the preset granularity. When a port in an I / O group is connected to an EDT channel chain in an EDT channel chain group, the other ports in that I / O group are connected to the other EDT channel chains in that EDT channel chain group.

[0071] In this embodiment, the number of general-purpose input / output ports is less than the number of EDT channel chains to be tested. By configuring the controller, the conduction status of the general-purpose input / output ports and the EDT channel chains can be dynamically adjusted to realize data transmission between I / O and the EDT channel chains.

[0072] In some embodiments, the attribute parameters of the scan test module may include, but are not limited to, any one or a combination of the following parameters: number of EDT channels, crosstalk paths between scan test modules, test mode, number of test vector patterns, and power consumption. The attribute parameters may also include any other parameters that can affect the test process or test results.

[0073] In some embodiments, the port multiplexing logic module and the port multiplexing logic module can be implemented by a multiplexer or a demultiplexer. Those skilled in the art can also implement time-division multiplexing of I / O input / output ports using selectors or other logic operation modules; this application does not impose any limitations on this.

[0074] Figure 4 This is a schematic diagram of the circuit structure of a port multiplexing logic module according to an embodiment of this application (I), as shown below. Figure 4 As shown, the port multiplexing logic module may include the following structure:

[0075] Multiple first multiplexer groups 240.

[0076] In this embodiment, the number of the plurality of first multiplexer groups is the same as the number of the plurality of EDT channel chain groups.

[0077] In this embodiment, each first multiplexer group includes multiple input terminals and one output terminal, and can select one input terminal and one output terminal under the control of control instructions.

[0078] In some embodiments, according to a preset granularity, the input ports of the port multiplexing logic module are divided into i+1 groups, including dft_edt_in_0 to dft_edt_in_i, with each group of input ports connected to a set of general-purpose input ports. The output ports of the port multiplexing logic module are divided into j+1 groups, including dft_edt_in_channel_0 to dft_edt_in_channel_j, with each group of output ports connected to an EDT channel chain group. Correspondingly, the number of the first multiplexer groups is j+1, where i is less than j.

[0079] In some embodiments, the port multiplexing logic module may further include multiple input registers 220 and multiple input channel registers 260.

[0080] In some embodiments, the preset granularity is N, the input / output port group (I / O group) contains N input / output ports, each first multiplexer group contains N first multiplexers, and each EDT channel chain group contains N EDT channel chains.

[0081] Furthermore, Figure 4 The circuit connections are made in a bus manner, with each bus containing a group of N lines. Figure 4 The number of input registers 220 and input channel registers 260 in the text has been omitted. In fact, each line can be connected to one register.

[0082] In this embodiment, the input (dft_edt_in) register is located on the input port side within the port multiplexing logic module, and the input channel (dft_edt_in_channel) register is located on the output port side within the port multiplexing logic module. The logic between the input register and the input channel register is the I / O multiplexing logic in the port multiplexing logic module.

[0083] In this embodiment, each group of general-purpose input ports is connected to the plurality of first multiplexer groups through the input register, and each first multiplexer group is connected to an EDT channel chain group through the input channel register. Each first multiplexer in the first multiplexer group corresponds to an EDT channel chain in an EDT channel chain group.

[0084] In this embodiment, the first multiplexer group is used to select one of the plurality of I / O groups and the corresponding target EDT channel chain group according to the control instruction, wherein the N general-purpose input ports in the target I / O group are connected to the input terminals of the N EDT channel chains in the target EDT channel chain group.

[0085] In some embodiments, when the granularity is N, each first multiplexer group contains N first multiplexers. Each first multiplexer has i+1 inputs and one output. The i+1 inputs are connected to one general-purpose input port from each of the i+1 I / O groups, and the one output is connected to the input of one EDT channel chain. The first multiplexer can select one of the i+1 general-purpose input ports as the target general-purpose input port and connect it to the corresponding uniquely connected EDT channel chain, thereby enabling the testing of the EDT channel chain.

[0086] In some embodiments, the N first multiplexers in each group can be controlled by a single control signal to select N paths. For example, the input of the first first multiplexer in the first multiplexer group can be connected to the first port in each bus (or each group of general-purpose input ports), selecting one from multiple first ports to connect to the first output port in the output port group of the first multiplexer group. Correspondingly, the other first multiplexers in the first multiplexer group are sequentially connected to the corresponding ports in each bus (or each group of general-purpose input ports).

[0087] Furthermore, Figure 4 The first multiplexer in each first multiplexer group can be connected to ports such as dft_edt_in_0[0], dft_edt_in_1[N], and dft_edt_in_i[N·i], and one of these ports can be connected to the first port in the corresponding output port group. The second first multiplexer can be connected to ports such as dft_edt_in_0[1], dft_edt_in_1[N+1], and dft_edt_in_i[N·i+1], and the other first multiplexers can be connected in the same way.

[0088] In some embodiments, the logic of the scan io reuse module is controlled by the configuration chain in the tap controller. The configuration chain can control the conduction logic of the first multiplexer or the first multiplexer group, thereby realizing dynamic I / O multiplexing allocation.

[0089] In this embodiment, the configure chain in the tap controller is connected to the selection terminal dft_edt_in_sel of each multiplexer, so that only one path from dft_edt_in to dft_edt_in_channel is selected in the multiplexer, thereby realizing the dynamic allocation and time-division multiplexing of the scan I / O input terminal. The bit width of the dft_edt_in_sel signal is related to the I / O granularity N.

[0090] In some embodiments, the control instructions include a first serial instruction and a second serial instruction.

[0091] In some embodiments, the controller is configured to control a plurality of first multiplexer groups or a plurality of first demultiplexer groups in the port multiplexing logic module to select the plurality of general-purpose input ports and a portion of the input terminals of the scan test logic module via the first serial instruction.

[0092] In some embodiments, the controller is further configured to control a plurality of second multiplexer groups or a plurality of second demultiplexer groups in the port multiplexing logic module to select a portion of the output terminals of the scan test logic module and the plurality of general-purpose output ports via the second serial instruction.

[0093] In this embodiment, by controlling the I / O multiplexing logic through the controller, time-division multiplexing of the chip's general-purpose input / output ports can be achieved, and the I / O grouping can be adjusted during the test, thereby effectively reducing the EDT test time.

[0094] Figure 5 This is a schematic diagram (II) of the circuit structure of a port multiplexing logic module according to an embodiment of this application, as shown below. Figure 5 As shown, the port multiplexing logic module may include the following structure:

[0095] Multiple first multiplexer groups 230 and multiple OR operation modules 250.

[0096] In this embodiment, the number of the plurality of first multiplexer groups is the same as the number of the plurality of I / O groups.

[0097] In this embodiment, each first multiplexer group includes a set of input terminals and multiple sets of output terminals, and can select one set of input terminals and one set of output terminals under the control of control instructions.

[0098] In some embodiments, according to a preset granularity, the input ports of the port multiplexing logic module are divided into i+1 groups, including dft_edt_in_0 to dft_edt_in_i, with each group of input ports connected to a set of general-purpose input ports. The output ports of the port multiplexing logic module are divided into j+1 groups, including dft_edt_in_channel_0 to dft_edt_in_channel_j, with each group of output ports connected to an EDT channel chain group. Multiple EDT channel chains are divided into j+1 EDT channel chain groups. Correspondingly, the number of the first demultiplexer groups is i+1, where i is less than j.

[0099] In some embodiments, the port multiplexing logic module may further include multiple input registers 220 and multiple input channel registers 260.

[0100] In some embodiments, the preset granularity is N, the input / output port group (I / O group) contains N input / output ports, each first multiplexer group contains N first multiplexers, and each EDT channel chain group contains N EDT channel chains.

[0101] Furthermore, Figure 5 The circuit connections are made in a bus manner, with each bus containing a group of N lines. Figure 5 The number of input registers 220 and input channel registers 260 in the text has been omitted. In fact, each line can be connected to one register.

[0102] In this embodiment, each group of general input ports is connected to a first multiplexer group through the input register, each first multiplexer group is connected to the plurality of OR operation modules, and each OR operation module is connected to an EDT channel chain group through the input channel register.

[0103] In this embodiment, the first multiplexer group is used to select one of the multiple EDT channel chain groups and the corresponding target I / O group according to the control command, wherein the N general-purpose input ports in the target I / O group are connected to the input terminals of the N EDT channel chains in the target EDT channel chain group.

[0104] In some embodiments, when the granularity is N, each first demultiplexer group contains N first demultiplexers. Each first demultiplexer has one input and j+1 outputs. The one input is connected to a general-purpose input port in one I / O group, and each output is connected to multiple OR operation modules respectively.

[0105] Furthermore, each first multiplexer selects a target output from j+1 outputs under the control of the control command, connects the input to the target output, and then transmits it to a target EDT channel chain in the corresponding EDT channel chain group through the OR operation module, thereby realizing the testing of the target EDT channel chain.

[0106] In some embodiments, the N first demultiplexers in each group can be controlled by a single control signal to select N paths. For example, the input of the first first demultiplexer in the first demultiplexer group can be connected to the first port in each bus (or each group of general-purpose input ports), selecting one from multiple first ports to connect to the first output port in the output port group of the first demultiplexer group. Correspondingly, the other first demultiplexers in the first demultiplexer group are sequentially connected to the corresponding ports in each bus (or each group of general-purpose input ports).

[0107] Furthermore, Figure 5 The input of the first demultiplexer in the first demultiplexer group is connected to dft_edt_in_0[0], and the output can be connected to ports such as dft_edt_in_channel_0[0], dft_edt_in_channel_1[N], and dft_edt_in_channel_j[N·j], and one of these ports can be selected to be turned on. The other first demultiplexers can be deduced in the same way.

[0108] In some embodiments, each OR operation module consists of multiple OR gates, and each OR operation module may have i+1 sets of input ports and one set of output ports, which are respectively connected to i+1 first multiplexer groups and one EDT channel chain group. Combined with the controller's control of the i+1 first multiplexer groups, the OR operation module can transmit any input signal from the i+1 sets of input ports to the corresponding EDT channel chain group, wherein each OR operation module can only receive one set of on signals at a time.

[0109] In this embodiment, the configure chain in the tap controller is connected to the selection terminal dft_edt_in_sel of each demultiplexer, so that only one path from dft_edt_in to dft_edt_in_channel is selected in the demultiplexer, thereby realizing the dynamic allocation and time-division multiplexing of the scan I / O input terminal. The bit width of the dft_edt_in_sel signal is related to the I / O granularity N.

[0110] In some embodiments, with Figure 4 and Figure 5 Taking the structure of the port multiplexing logic module as an example, Figure 4 The first multiplexer group is located on the side closest to the scan test logic module, and its number is equal to the number of groups in the EDT channel chain. Figure 5The first demultiplexer group in is located on the side close to the general-purpose input port, and the quantity thereof is consistent with the grouping number of the general-purpose input ports. Since the number of general-purpose input ports is small while the number of internal EDT channel chains in the module is large, under the same other conditions, Figure 5 the quantity of the first demultiplexer group in is less than that of Figure 4 the first multiplexer group in, and the internal gating logic of the first demultiplexer group is more complex.

[0111] Further, since the bit width of the gating terminal of the multiplexer group / demultiplexer group has an exponential corresponding relationship with the number of internal paths thereof, selecting a multiplexer group / demultiplexer group with more complex internal logic is beneficial to compressing the bit width of the gating terminal.

[0112] In some embodiments, Figure 4 , Figure 5 the total number of bits N required by the selection terminal of the multiplexer group / demultiplexer group in bit1 , N bit2 are respectively:

[0113] N bit1 =(j+1)log2(i+1);

[0114] N bit2 =(i+1)log2(j+1);

[0115] Since i<<j in general cases, N bit1 >>N bit2 , that is, Figure 5 the chain length of the configure chain in will be shorter.

[0116] Figure 6 is a third schematic diagram of the circuit structure of a port multiplexing logic module according to an embodiment of the present application. As shown in Figure 6 , the port multiplexing logic module may include the following structures:

[0117] a plurality of second multiplexer groups 440.

[0118] In this embodiment, the number of the plurality of second multiplexer groups is the same as the number of the plurality of EDT channel chain groups.

[0119] In this embodiment, each second multiplexer group includes multiple sets of input terminals and one set of output terminals, and can gate one set of input terminals and one set of output terminals under the control of a control instruction.

[0120] In some embodiments, when the granularity is N, the input ports of the port multiplexing logic module are divided into j+1 groups, including dft_edt_out_channel_0 to dft_edt_out_channel_j. Each group of input ports is connected to a set of EDT channel chains. Multiple EDT channel chains are divided into j+1 EDT channel chain groups, and each EDT channel chain group contains N EDT channel chains. The output ports of the port multiplexing logic module are divided into i+1 groups, including dft_edt_out_0 to dft_edt_out_i. Each group of output ports is connected to a set of general-purpose output ports. Multiple general-purpose output ports are divided into i+1 I / O groups, and each I / O group contains N general-purpose output ports. Correspondingly, the number of the second multiplexer groups is i+1, where i is less than j.

[0121] In some embodiments, the port multiplexing logic module may further include multiple output channel registers 420 and multiple output registers 460.

[0122] In some embodiments, the preset granularity is N, the input / output port group (I / O group) contains N input / output ports, each second multiplexer group contains N second multiplexers, and each EDT channel chain group contains N EDT channel chains.

[0123] Furthermore, Figure 7 The circuit connections are made in a bus manner, with each bus containing a group of N lines.

[0124] In this embodiment, each of the EDT channel chain groups is connected to the plurality of second multiplexer groups through the output channel register, and each of the second multiplexer groups is connected to a group general output port through the output register.

[0125] In this embodiment, the second multiplexer group is used to select one of the multiple EDT channel chain groups and the corresponding target I / O group according to the control command, wherein the output terminals of N EDT channel chains in the target EDT channel chain group are connected to N general-purpose output ports in the target I / O group.

[0126] In some embodiments, each second multiplexer group comprises N second multiplexers. Each second multiplexer has j+1 inputs and one output. The j+1 inputs are each connected to one EDT channel chain in the j+1 EDT channel chain groups, and the one output is connected to a general-purpose output port. The second multiplexer can select one of the j+1 EDT channel chains as the target EDT channel chain and connect it to the corresponding unique general-purpose output port to obtain the test result for the target EDT channel chain.

[0127] In some embodiments, the logic of the scan io reuse module is controlled by the configuration chain in the tap controller. The configuration chain can control the conduction logic of the second multiplexer or the second multiplexer group, thereby realizing dynamic I / O multiplexing allocation.

[0128] In this embodiment, the configure chain in the tap controller is connected to the selection terminal dft_edt_out_sel of each multiplexer, so that only one path from dft_edt_out_channel to dft_edt_out is selected in the multiplexer, thereby realizing the dynamic allocation and time-division multiplexing of the scan I / O input terminal. The bit width of the dft_edt_out_sel signal is related to the I / O granularity N.

[0129] Figure 7 This is a schematic diagram (fourth) of the circuit structure of a port multiplexing logic module according to an embodiment of this application, as shown below. Figure 7 As shown, the port multiplexing logic module may include the following structure:

[0130] Multiple second multiplexer groups 430 and multiple OR operation modules 450.

[0131] In this embodiment, the number of the plurality of second multiplexer groups is the same as the number of the plurality of EDT channel chains.

[0132] In this embodiment, each second multiplexer group includes a set of input terminals and multiple sets of output terminals, and can select one set of input terminals and one set of output terminals under the control of control instructions.

[0133] In some embodiments, according to a preset granularity, the input ports of the port multiplexing logic module are divided into j+1 groups, including dft_edt_out_channel_0 to dft_edt_out_channel_j. Each group of input ports is connected to a set of EDT channel chains, and multiple EDT channel chains are divided into j+1 EDT channel chain groups. The output ports of the port multiplexing logic module are divided into i+1 groups, including dft_edt_out_0 to dft_edt_out_i. Each group of output ports is connected to a set of general-purpose output ports, and multiple general-purpose output ports are divided into i+1 I / O groups. Correspondingly, the number of the second multiplexer groups is j+1, where i is less than j.

[0134] In some embodiments, the port multiplexing logic module may further include multiple output channel registers 420 and multiple output registers 460.

[0135] In this embodiment, each of the EDT channel chain groups is connected to a second multiplexer group through the output channel register, each of the plurality of second multiplexer groups is connected to the plurality of OR operation modules, and each of the OR operation modules is connected to a set of general-purpose output ports through the output register.

[0136] In this embodiment, the second multiplexer group is used to select one of the multiple I / O groups and the corresponding target EDT channel chain group according to the control command, wherein the output terminals of N EDT channel chains in the target EDT channel chain group are connected to N general-purpose output ports in the target I / O group.

[0137] In some embodiments, when the granularity is N, each second multiplexer group contains N second multiplexers. Each second multiplexer has one input and i+1 outputs. The input is connected to one EDT channel chain, and each output is connected to multiple OR operation modules.

[0138] Furthermore, each second multiplexer selects a target output from i+1 outputs under the control of the control command, connects the input to the target output, and then transmits the signal of the target output to the uniquely connected general output port through the OR operation module, thereby obtaining the test result of the EDT channel chain.

[0139] In some embodiments, the logic of the scan io reuse module is controlled by the configuration chain in the tap controller. The configuration chain can control the conduction logic of the second demultiplexer or the second demultiplexer group, thereby realizing dynamic I / O multiplexing.

[0140] In this embodiment, the configure chain in the tap controller is connected to the selection terminal dft_edt_out_sel of each demultiplexer, so that only one path from dft_edt_out_channel to dft_edt_out is selected in the demultiplexer, thereby realizing the dynamic allocation and time-division multiplexing of the scan I / O input terminal. The bit width of the dft_edt_out_sel signal is related to the I / O granularity N.

[0141] In some embodiments, with a granularity of 1, the number of general-purpose input ports is i+1, the number of EDT channel chains is j+1, and without considering the selection end, the number of standard cells N required by the I / O multiplexing logic is... cell It can be represented as:

[0142] N cell= (2(i+1)-1)(j+1).

[0143] In some embodiments, when the granularity is N, assuming the number of general-purpose input ports is N(i+1) and the number of EDT channel chains is N(j+1), the number of I / O groups and the number of EDT channel chain groups remain unchanged. Correspondingly, the number of standard cells N cell The complexity remains the same. With the same internal logic complexity, this application's embodiments allow for the allocation of more I / O resources.

[0144] In some embodiments, when the granularity is N, assuming the number of general-purpose input ports is i+1 and the number of EDT channel chains is j+1, then the corresponding number of I / O groups is (i+1) / N, and the number of EDT channel chain groups is (j+1) / N. In this case, the number of standard units required by the I / O multiplexing logic module is N. cell for:

[0145]

[0146] That is, the number of standard units in the I / O multiplexing logic module will be approximately equal to the square of N. 2 The relationship has decreased.

[0147] In some embodiments, it can be deduced that Figure 5 The number of standard cells N required for the I / O multiplexing logic module in the middle cell for:

[0148]

[0149] Furthermore, Figure 6 , Figure 7 This describes the transmission process from the EDT channel chain output to the general-purpose output port. Similar to the input transmission logic, the output signal is connected to the general-purpose output port through the output channel register, I / O multiplexing logic module, and output register. By configuring the configuration chain of dft_edt_out_sel in the tap controller, which controls the selection terminal of the I / O multiplexing logic module, a certain I / O multiplexing logic can be dynamically selected, thereby realizing the dynamic allocation and time-division multiplexing of the general-purpose output port.

[0150] In an exemplary embodiment, the I / O multiplexing logic modules in the above embodiments can be arbitrarily combined to obtain a complete port multiplexing logic module.

[0151] The port multiplexing logic module in this application is a dynamic scan I / O reallocation technology proposed for scan testing mode. It possesses high-degree-of-freedom grouping capabilities and can effectively solve the key problem of fixed I / O allocation that cannot be reallocated in related technologies. Through this application embodiment, utilizing scan I / O reuse logic, I / O resources can be reallocated at any stage of chip design, even after chip tape-out, according to the optimal module grouping. The entire scan I / O reallocation process demonstrates high flexibility and configurability, playing a crucial role in chip design and testing.

[0152] In some embodiments, the scan test logic module includes multiple scan test modules, which can be divided into multiple test groups based on their attribute parameters. The scan test logic module can then perform tests on different test groups at different times.

[0153] Furthermore, the attribute parameters include, but are not limited to, any of the following parameters or combinations thereof: number of EDT channels, crosstalk paths between scan test modules, test mode, number of test vector patterns, and power consumption. The attribute parameters can be extended and selected according to the grouping strategy of the test modules. For example, in the shortest test time grouping strategy, the number of test vector patterns can be used as the grouping basis, while in the optimal power consumption grouping strategy, power consumption can be used as the grouping basis.

[0154] In one exemplary embodiment, a port multiplexing logic module can be used to achieve highly flexible grouping, realize a grouping strategy with the shortest test time, and save test costs.

[0155] In this embodiment, all modules are grouped for testing during the chip scan test. The optimal grouping strategy is to make the number of test vectors (patterns) of the test modules in each test group similar, that is, the test time of each test module is similar, so as to avoid only one test module being tested for a period of time, which would waste test time.

[0156] In this embodiment, it is assumed that there are 8 test modules to be tested, each test module has 4 EDT channels, and the chip I / O resources are 16, which can support 4 test modules to be tested at the same time. Therefore, the test needs to be divided into two groups.

[0157] Furthermore, Table 1 shows examples of the number of patterns for the eight test modules under different test modes. As shown in Table 1, the optimal grouping strategy can be determined for each test mode. For example, in the "stuck at" mode, modules 0, 1, 2, and 3 are grouped into one group, and modules 4, 5, 6, and 7 are grouped into another group; in the "transition" mode, modules 0, 2, 3, and 4 are grouped into one group, and modules 1, 5, 6, and 7 are grouped into another group.

[0158] Table 1:

[0159]

[0160] In this embodiment, the port multiplexing logic module enables dynamic reallocation of I / O resources, thereby allowing for different grouping of test modules under different test modes. This embodiment also effectively reduces actual testing time and improves testing efficiency.

[0161] In another exemplary embodiment, a high degree of freedom grouping can be achieved through a port multiplexing logic module, thereby realizing a power-optimal grouping strategy.

[0162] In this embodiment, the optimal power consumption grouping strategy during testing refers to avoiding clustering between test modules, which can lead to chip overheating and voltage drop (IR drop), thus causing overkill during testing.

[0163] In this embodiment, when grouping, it is necessary to ensure that the power consumption of each test group is evenly distributed to avoid excessive power consumption in any one group.

[0164] In this embodiment, it is assumed that there are 8 test modules to be tested, each test module has 4 EDT channels, and the chip I / O resources are 16, which can support 4 test modules to be tested at the same time. Therefore, the test needs to be divided into two groups.

[0165] Furthermore, Table 2 shows an example of the power consumption and physical location distribution of the eight test modules. As shown in Table 2, according to the optimal power consumption grouping strategy, the test grouping should be adjusted so that modules 0, 2, 5, and 7 are in one group, and modules 1, 3, 4, and 6 are in another group.

[0166] Table 2:

[0167] Module 4 (2W) Module 5 (1W) Module 6 (1W) Module 7 (1W)

[0168] In this embodiment, the port multiplexing logic module enables dynamic reallocation of I / O resources, thereby allowing for dynamic readjustment of the test module grouping strategy based on power consumption. Through this embodiment, the grouping strategy can be dynamically adjusted according to the actual power consumption distribution, revealing the true chip quality and improving yield.

[0169] In another exemplary embodiment, a port multiplexing logic module can be used to achieve high-degree-of-freedom grouping, thereby enabling full coverage testing of cross-talk paths between test modules.

[0170] In this embodiment, under the scan extest mode, it is assumed that the cross-talk relationships between the test modules are as follows: modules 0, 1, 2, and 3 have cross-talk with each other in pairs; modules 4, 5, 6, and 7 have cross-talk with each other in pairs; modules 0 and 4 have cross-talk; modules 1 and 5 have cross-talk; modules 2 and 6 have cross-talk; and modules 3 and 7 have cross-talk. To fully cover all cross-talk paths, the scanextest test groups should test the following four groups respectively: modules 0, 1, 2, and 3 form the first group; modules 4, 5, 6, and 7 form the second group; modules 0, 4, 1, and 5 form the third group; and modules 2, 6, 3, and 7 form the fourth group.

[0171] In this embodiment, the port multiplexing logic module enables dynamic reallocation of I / O resources, meeting the needs of various module groups and thus achieving full coverage testing of cross-talk paths between test modules. This embodiment covers all test paths, improving test accuracy and facilitating chip selection.

[0172] Embodiments of this application also provide an electronic device that includes the chip from any of the foregoing embodiments.

[0173] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0174] The above description is merely an exemplary embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A chip, characterized in that, The chip includes multiple chip ports, a port multiplexing logic module, and a scan test logic module, wherein: The port multiplexing logic module has multiple sets of first ports and multiple sets of second ports, and the multiple chip ports are divided into multiple groups according to a preset granularity. Each group of chip ports is connected to at least one of the multiple groups of first ports and multiple groups of second ports of the port multiplexing logic module, and the multiple groups of first ports or multiple groups of second ports of the port multiplexing logic module are connected to the scan test logic module. The port multiplexing logic module is used to control the selection of the path between the chip port and the scan test logic module according to the control command in units of the preset granularity; The multiple chip ports are divided into i+1 groups, and the number of port groups of the scanning test logic module is j+1, where i is less than j, and i and j are positive integers; When the chip port is a chip input port, the multiple first ports of the port multiplexing logic module are multiple input ports, and the multiple second ports of the port multiplexing logic module are multiple output ports, each chip port is connected to at least one of the multiple first ports of the port multiplexing logic module, the multiple second ports of the port multiplexing logic module are connected to the scan test logic module, the number of input port groups of the port multiplexing logic module is i+1, and the number of output port groups of the port multiplexing logic module is j+1.

2. The chip according to claim 1, characterized in that, The port multiplexing logic module includes j+1 first multiplexer groups, wherein each first multiplexer group is connected to i+1 input port groups of the port multiplexing logic module, and each first multiplexer group is connected to one output port group of the port multiplexing logic module. The first multiplexer group is used to select one of the i+1 input port groups and the corresponding target output port group according to the control command.

3. The chip according to claim 2, characterized in that, With the preset granularity being N, each input port group contains N input ports, each output port group contains N output ports, and each first multiplexer group contains N first multiplexers.

4. The chip according to claim 1, characterized in that, The port multiplexing logic module includes i+1 first multiplexer groups and j+1 OR operation modules, wherein each first multiplexer group is connected to one input port group of the port multiplexing logic module, each first multiplexer group is connected to the j+1 OR operation modules, and each OR operation module is connected to one output port group of the port multiplexing logic module. The first multiplexer group is used to select one of the j+1 output port groups and the corresponding target input port group according to the control command.

5. The chip according to claim 4, characterized in that, With the preset granularity being N, each input port group contains N input ports, each output port group contains N output ports, and each first multiplexer group contains N first multiplexers.

6. The chip according to claim 1, characterized in that, The multiple chip ports are divided into i+1 groups, and the number of port groups of the scanning test logic module is j+1, where i is less than j, and i and j are positive integers; When the chip port is a chip output port, the multiple sets of second ports of the port multiplexing logic module are multiple sets of output ports, and the multiple sets of first ports of the port multiplexing logic module are multiple sets of input ports, each set of chip ports is connected to at least one set of the multiple sets of second ports of the port multiplexing logic module, the multiple sets of first ports of the port multiplexing logic module are connected to the scan test logic module, the number of input port groups of the port multiplexing logic module is j+1, and the number of output port groups of the port multiplexing logic module is i+1.

7. The chip according to claim 6, characterized in that, The port multiplexing logic module includes i+1 second multiplexer groups, wherein each second multiplexer group is connected to j+1 input port groups of the port multiplexing logic module, and each second multiplexer group is connected to one output port group of the port multiplexing logic module. The second multiplexer group is used to select one of the j+1 input port groups and the corresponding target output port group according to the control command.

8. The chip according to claim 7, characterized in that, With the preset granularity being N, each input port group contains N input ports, each output port group contains N output ports, and each second multiplexer group contains N second multiplexers.

9. The chip according to claim 6, characterized in that, The port multiplexing logic module includes j+1 second multiplexer groups and i+1 OR operation modules, wherein each second multiplexer group is connected to one input port group of the port multiplexing logic module, each second multiplexer group is connected to i+1 OR operation modules, and each OR operation module is connected to one output port group of the port multiplexing logic module. The second multiplexer group is used to select one of the i+1 output port groups and the corresponding target input port group according to the control command.

10. The chip according to claim 9, characterized in that, With the preset granularity being N, each input port group contains N input ports, each output port group contains N output ports, and each second multiplexer group contains N second multiplexers.

11. The chip according to any one of claims 1 to 10, characterized in that, The scanning test logic module includes: multiple embedded deterministic test EDT channel chains, wherein the multiple EDT channel chains are divided into multiple groups according to the preset granularity; The scanning test logic module is used to test multiple EDT channel chains that are connected to the chip port.

12. The chip according to claim 11, characterized in that, The scan test logic module includes multiple scan test modules, wherein each scan test module contains at least one EDT channel chain; The scanning test logic module is used to test each of the multiple test groups at different times, wherein each test group contains at least one EDT channel chain group, and the multiple test groups are allocated according to the attribute parameters of the multiple scanning test modules.

13. The chip according to claim 12, characterized in that, The chip also includes: The controller is used to send the control commands to the port multiplexing logic module.

14. An electronic device, characterized in that, The electronic device includes the chip described in any one of claims 1 to 13.

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