Chip identity generation circuit, chip and electronic device

Abstract

The application relates to the field of electronic technology, in particular to a chip identity generation circuit, a chip and an electronic device. The identity generation circuit comprises an identity sequence generation circuit and a plurality of sub-identity generation circuits. Each sub-identity generation circuit is used for receiving an input signal and outputting a corresponding output signal under the triggering of the input signal. The identity sequence generation circuit is used for receiving the input signal and the output signal corresponding to each sub-identity generation circuit and generating an identity sequence according to the input signal and the output signal. The identity sequence is used for representing the unique identity of a chip. The identity generation circuit of the application has a simple circuit structure, the generated identity sequence is convenient to read, no related burning and reading circuits are needed, the occupation area of the chip is small, and the production cost of the chip is reduced.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a chip identity generation circuit, a chip, and an electronic device. Background Technology

[0002] In order to effectively trace the chip manufacturer information, such as production date, production line, and chip coordinates on the wafer, when a chip malfunctions or fails, a unique identifier is usually assigned to the chip during the chip manufacturing process. This identifier can provide effective clues for analyzing the cause of chip failure or malfunction.

[0003] In related technologies, the main approach involves setting up an eFuse (Electrically Programmable Fuse) in each chip, and then programming the chip's identification information into the eFuse. When a chip fails, the identification information can be retrieved from the chip's eFuse. Typically, the chip's identification information mainly includes its XY coordinates on the wafer. Understandably, when there are many chips on a wafer, multiple eFuses are needed on each chip to record its identification. Due to the complex circuit structure of the eFuse, multiple eFuses on a single chip occupy a large area; furthermore, each chip requires corresponding programming and reading circuits for the eFuse, which also occupies a significant area, thus increasing the chip's manufacturing cost. Summary of the Invention

[0004] This application provides a chip identity generation circuit, a chip, and an electronic device to solve the technical problem of high chip production costs in related technologies.

[0005] In a first aspect, this application provides a chip identity generation circuit for generating chip identity identifiers, the identity identifier generation circuit including an identifier sequence generation circuit and multiple sub-identifier generation circuits;

[0006] Each sub-identifier generation circuit is configured to receive an input signal and output a corresponding output signal upon triggering the input signal; the identifier sequence generation circuit is configured to receive the input signal and output signal corresponding to each sub-identifier generation circuit.

[0007] The identifier sequence generation circuit is also used to generate an identity identifier sequence based on the multiple output signals corresponding to the multiple sub-identifier generation circuits;

[0008] Alternatively, the identifier sequence generation circuit is further configured to generate a deviation value based on the input signal and output signal corresponding to each of the sub-identifier generation circuits, and generate an identity identifier sequence based on multiple deviation values;

[0009] Alternatively, the identifier sequence generation circuit is further configured to obtain the trigger value of the input signal when the output signal corresponding to each of the sub-identifier generation circuits undergoes a state change; and generate an identity identifier sequence based on the trigger values ​​corresponding to the plurality of sub-identifier generation circuits.

[0010] The identity sequence is used to represent the unique identity of a chip.

[0011] In one possible design, the identity generation circuit also includes multiple switching circuits;

[0012] Each of the sub-identifier generation circuits is connected to at least one switching circuit; the switching circuit is used to receive a control signal, the control signal being used to control the switching circuit to be turned on or off, thereby controlling the corresponding sub-identifier generation circuit to be turned on or off.

[0013] In one possible design, the sub-identifier generation circuit is an operational amplifier; the input signal is a reference voltage signal, and the output signal is a clamping voltage signal;

[0014] The operational amplifier is used to receive the input reference voltage signal and clamp the reference voltage signal to output a corresponding clamp voltage signal.

[0015] The identifier sequence generation circuit is used to generate a voltage deviation value based on the clamping voltage signal and reference voltage signal corresponding to each of the operational amplifier circuits, and to generate the identity identifier sequence based on the voltage deviation values ​​corresponding to the multiple operational amplifiers.

[0016] In one possible design, the operational amplifier is a two-stage operational amplifier composed of multiple transistors.

[0017] In one possible design, the operational amplifier includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and a first capacitor;

[0018] The first terminal of the first transistor is connected to the first terminal of the second transistor, the second terminal of the first transistor is connected to the second terminal of the fourth transistor, the control terminal of the first transistor is shorted to the second terminal of the first transistor, and the first terminal of the fourth transistor is connected to the first terminal of the fifth transistor; the control terminal of the first transistor is connected to the control terminal of the second transistor, the second terminal of the second transistor is connected to the second terminal of the fifth transistor, and the control terminal of the fifth transistor is the input terminal of the operational amplifier;

[0019] The first terminal of the third transistor is connected to the first terminal of the second transistor, the control terminal of the third transistor is connected to the second terminal of the third transistor through the first capacitor, the second terminal of the third transistor is connected to the second terminal of the ninth transistor, and the first terminal of the ninth transistor is grounded; the second terminal of the sixth transistor is connected to the first terminal of the third transistor, the control terminal of the sixth transistor is connected to the second terminal of the third transistor, the first terminal of the sixth transistor is connected to the second terminal of the tenth transistor, the first terminal of the tenth transistor is grounded, and the control terminal of the fourth transistor is also connected to the second terminal of the tenth transistor;

[0020] The second terminal of the seventh transistor is used to receive a current signal; the first terminal of the seventh transistor is grounded; the second terminal of the seventh transistor and the control terminal are shorted; the second terminal of the eighth transistor is connected to the first terminal of the fourth transistor; the first terminal of the eighth transistor is grounded.

[0021] The control electrodes of the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor are shorted to each other.

[0022] In one possible design, each of the sub-identifier generation circuits is connected to the first switch circuit and the second switch circuit, respectively.

[0023] The first switching circuit includes an eleventh transistor and a first current source; the second switching circuit includes a twelfth transistor.

[0024] The positive terminal of the first current source is used to connect to the power supply, the negative terminal of the first current source is connected to the first terminal of the eleventh transistor, and the second terminal of the eleventh transistor is connected to the second terminal of the seventh transistor; the first terminal of the twelfth transistor is used to connect to the power supply, and the second terminal of the twelfth transistor is connected to the first terminal of the third transistor.

[0025] The control electrode of the eleventh transistor and the control electrode of the twelfth transistor are both used to receive the first control signal; the first control signal is used to control the eleventh transistor and / or the twelfth transistor to turn on or off, thereby controlling the corresponding operational amplifier to turn on or off.

[0026] In one possible design, the sub-identifier generation circuit includes a thirteenth transistor, a first resistor, a second resistor, and an inverter;

[0027] The first terminal of the thirteenth transistor is connected to the first end of the first resistor, the second end of the first resistor is used to connect to the power supply, the second terminal of the thirteenth transistor is grounded, the first terminal of the thirteenth transistor is connected to the input terminal of the inverter; the control terminal of the thirteenth transistor is used to receive the input signal, and the output terminal of the inverter is used to output the output signal.

[0028] The identifier sequence generation circuit is further configured to obtain the trigger value of the input signal when the output signal of the inverter in each sub-identifier generation circuit flips from low level to high level; and generate the identity identifier sequence according to the trigger values ​​corresponding to the multiple sub-identifier generation circuits.

[0029] In one possible design, the sub-identifier generation circuit is connected to a third switching circuit, which includes a fourteenth transistor.

[0030] The first terminal of the fourteenth transistor is connected to the power supply, the second terminal of the fourteenth transistor is connected to the second terminal of the second resistor, and the control terminal of the fourteenth transistor is used to receive a second control signal. The second control signal is used to control the fourteenth transistor to turn on or off, thereby controlling the corresponding sub-identifier generation circuit to turn on or off.

[0031] Secondly, this application also provides a chip that includes the chip identity generation circuit described above.

[0032] Thirdly, this application also provides an electronic device that includes the chip described above.

[0033] Compared with the eFuse structure in related technologies, the chip identity generation circuit provided in the first aspect above has a simpler circuit structure and the generated identity sequence is easy to read. It does not require related programming and reading circuits, resulting in a smaller chip footprint and reduced chip production costs.

[0034] The beneficial effects provided in the second aspect and its various possible designs can be found in the first aspect and its various possible implementations, and will not be repeated here. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the chip identity generation circuit structure provided in the embodiments of this application;

[0036] Figure 2 This is a schematic diagram of the operational amplifier structure provided in an embodiment of this application;

[0037] Figure 3 This is a schematic diagram of a sub-identifier generation circuit provided in this application. Detailed Implementation

[0038] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c alone can mean: a alone, b alone, c alone, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0039] The terms “center,” “longitudinal,” “lateral,” “up,” “down,” “left,” “right,” “front,” and “rear,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0040] The terms "connected" and "connected" should be interpreted broadly. For example, in circuit structures, "connected" or "connected" can refer not only to physical connections but also to electrical or signal connections. This could be a direct connection (physical connection) or an indirect connection via at least one intermediate component, as long as the circuit is connected. It could also refer to the internal connection between two components. Similarly, a signal connection can refer to a connection via a circuit or a medium, such as radio waves. Those skilled in the art will understand the specific meaning of these terms in this application based on the specific circumstances.

[0041] The transistor in this application is a three-terminal transistor, with its three terminals being a control terminal, a first terminal, and a second terminal. The transistor can be a bipolar transistor (BPT) or a field-effect transistor (FET), etc. For example, when the transistor is a BPT, its control terminal is the base of the BPT, the first terminal can be the collector or emitter of the BPT, and the corresponding second terminal can be the emitter or collector of the BPT; when the transistor is a FET, its control terminal is the gate of the FET, the first terminal can be the drain or source of the FET, and the corresponding second terminal can be the source or drain of the FET.

[0042] To overcome the technical problem in related technologies where the large area required for the eFuse and its associated circuitry used to store chip identification leads to high chip production costs, this application uses random deviation values ​​generated during chip manufacturing as chip identification. Even with identical circuit structures, differences in the manufacturing processes of the components can cause slight variations in circuit performance. For example, multiple circuits with identical structures may have different output signals, different deviations between the input and output signals, or different trigger values ​​for certain circuits when inputting the same signal. These different output values, deviation values, or trigger values ​​can be used to characterize the chip's identification information.

[0043] Based on the above concept, this application provides a chip identification generation circuit. This circuit includes an identification sequence generation circuit and multiple sub-identifier generation circuits. Each sub-identifier generation circuit receives an input signal and outputs a corresponding output signal upon triggering the input signal. The identification sequence generation circuit receives the input and output signals corresponding to each sub-identifier generation circuit and generates an identification sequence based on multiple output signals, multiple deviation values, or trigger values. This identification sequence represents the unique identification of a chip. To avoid non-unique chip identification, multiple output signals, multiple deviation values, or trigger values ​​are used to generate an identification sequence, thus ensuring the uniqueness of the chip identification. Furthermore, the chip identification generation circuit provided in this application has a simple structure, and the generated identification sequence is easy to read, eliminating the need for related programming and reading circuits, resulting in a smaller chip footprint and reduced chip production costs.

[0044] Figure 1 For a schematic diagram of the chip identity generation circuit structure provided in the embodiments of this application, please refer to [link / reference]. Figure 1 As shown, the chip's identity generation circuit includes an identity sequence generation circuit and multiple sub-identity generation circuits. For example, the multiple sub-identity generation circuits are respectively as follows: Figure 1The first sub-identifier generation circuit, the second sub-identifier generation circuit, ... the Nth sub-identifier generation circuit.

[0045] Each sub-identifier generation circuit receives an input signal and outputs a corresponding output signal upon triggering the input signal. The identifier sequence generation circuit receives the input and output signals corresponding to each sub-identifier generation circuit. The identifier sequence generation circuit also generates an identity identifier sequence based on the multiple output signals from the multiple sub-identifier generation circuits. For example, if multiple sub-identifier generation circuits receive the same input signal, the output signals from each sub-identifier generation circuit will differ due to variations in the components themselves. For instance, the identifier sequence generation circuit might generate an identity identifier sequence of a1, a2, a3, a4, a5, and a6 based on the multiple output signals, where a1 is the first sub-identifier included in the output signal of the first sub-identifier generation circuit.

[0046] It can be understood that each identity identifier sequence is unique because each of its sub-identifiers is different and the order of these sub-identifiers is also different. This makes each identity identifier sequence unique and can be used to represent the unique identity of the current chip.

[0047] The signal type for each sub-identifier can be voltage value, current value, resistance value, level signal, etc.

[0048] In some embodiments, the identifier sequence generation circuit is further configured to generate a deviation value based on the input signal and output signal corresponding to each sub-identifier generation circuit, and to generate an identity identifier sequence based on multiple deviation values. For example, the deviation values ​​generated by the input signals and output signals corresponding to multiple sub-identifier generation circuits are d1, d2, ..., dN, respectively, where d1 is the deviation value between the input signal and output signal of the first sub-identifier generation circuit. Then, multiple deviation values ​​can form an identity identifier sequence d1, d2, ..., dN.

[0049] In some embodiments, the identifier sequence generation circuit is further configured to obtain the trigger value of the input signal when the output signal corresponding to each sub-identifier generation circuit undergoes a state change; and generate an identifier sequence based on the trigger values ​​corresponding to multiple sub-identifier generation circuits. For example, for the first sub-identifier generation circuit, when its input signal is 1.211V, the trigger output signal is high-level, so the trigger value of the first sub-identifier generation circuit can be determined as 1.211V. Similarly, the trigger values ​​corresponding to multiple sub-identifier generation circuits can form a set of identifier sequences. Since the random deviations generated during the manufacturing process of the components in each sub-identifier generation circuit result in certain differences in the trigger values ​​of each sub-identifier generation circuit, the identifier sequence formed by multiple trigger values ​​in a certain order is unique and can identify the unique identifier of the chip.

[0050] In some embodiments, the identity generation circuit further includes multiple switching circuits; each sub-identity generation circuit is connected to at least one switching circuit, which is connected in series in the conduction loop of the sub-identity generation circuit. The switching circuit receives a control signal, which controls the switching circuit to turn on or off, thereby controlling the corresponding sub-identity generation circuit to turn on or off. Thus, when the chip is operating normally, the sub-identity generation circuit can be turned off via the switching circuit, meaning there is no need to read the identity identifier generated by the identity generation circuit. This reduces chip power consumption and extends the lifespan of the identity generation circuit.

[0051] In some embodiments, the sub-identifier generation circuit can be an operational amplifier. Specifically, the sub-identifier generation circuit can be an operational amplifier for voltage clamping. In this embodiment, the input signal to the operational amplifier is a reference voltage signal, and the corresponding output signal is a clamping voltage signal. The operational amplifier receives the input reference voltage signal and clamps it to output a corresponding clamping voltage signal. The identifier sequence generation circuit generates a voltage deviation value based on the clamping voltage signal and the reference voltage signal corresponding to each operational amplifier circuit, and generates an identification sequence based on the voltage deviation values ​​corresponding to multiple operational amplifiers.

[0052] It is understandable that operational amplifiers composed of multiple identical components with the same structure will exhibit slight performance differences due to variations in the manufacturing process. Therefore, even if multiple operational amplifiers use the same input reference voltage signal (e.g., multiple operational amplifiers with a 4.500V reference voltage), each amplifier will output different clamping voltage signals (i.e., different clamping voltage values) when clamping the input reference voltage signal due to its different performance characteristics. This results in a slight difference in the voltage deviation between the clamping voltage signal and the reference voltage signal generated by each operational amplifier circuit. These voltage deviation values ​​can form an identification sequence to uniquely identify the chip.

[0053] In some embodiments, the operational amplifier can be a two-stage operational amplifier composed of multiple transistors. Generally, because a two-stage operational amplifier is composed of multiple transistors, each transistor has a certain deviation during the manufacturing process, resulting in a certain difference in deviation due to the combination of multiple transistors.

[0054] Figure 2 For a schematic diagram of the operational amplifier structure provided in the embodiments of this application, please refer to [link / reference]. Figure 2As shown, the operational amplifier 10 includes a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, an eighth transistor Q8, a ninth transistor Q9, a tenth transistor Q10, and a first capacitor C1.

[0055] In this configuration, the first terminal of the first transistor Q1 is connected to the first terminal of the second transistor Q2, the second terminal of the first transistor Q1 is connected to the second terminal of the fourth transistor Q4, the control terminal of the first transistor Q1 is shorted to the second terminal of the first transistor Q1, the first terminal of the fourth transistor Q4 is connected to the first terminal of the fifth transistor Q5, the control terminal of the first transistor Q1 is connected to the control terminal of the second transistor Q2, the second terminal of the second transistor Q2 is connected to the second terminal of the fifth transistor Q5, and the control terminal of the fifth transistor Q5 is the input terminal of the operational amplifier 10. The first terminal of the third transistor Q3 is connected to the first terminal of the second transistor Q2. The control terminal of the third transistor Q3 is connected to the second terminal of the third transistor Q3 through the first capacitor C1. The second terminal of the third transistor Q3 is connected to the second terminal of the ninth transistor Q9. The first terminal of the ninth transistor Q9 is grounded. The second terminal of the sixth transistor Q6 is connected to the first terminal of the third transistor Q3. The control terminal of the sixth transistor Q6 is connected to the second terminal of the third transistor Q3. The first terminal of the sixth transistor Q6 is connected to the second terminal of the tenth transistor Q10. The first terminal of the sixth transistor Q6 is the output terminal of the operational amplifier 10. The first terminal of the tenth transistor Q10 is grounded. The control terminal of the fourth transistor Q4 is also connected to the second terminal of the tenth transistor Q10.

[0056] In this configuration, the second terminal of the seventh transistor Q7 receives a current signal, which drives the operational amplifier to conduct. The first terminal of the seventh transistor Q7 is grounded, and its second terminal and control terminal are shorted. The second terminal of the eighth transistor Q8 is connected to the first terminal of the fourth transistor Q4, and its first terminal is grounded. The control terminals of the seventh transistor Q7, the eighth transistor Q8, the ninth transistor Q9, and the tenth transistor Q10 are all shorted to each other.

[0057] When the operational amplifier 10 is turned on, the reference voltage signal VBG is input from the control electrode of the fifth transistor Q5, and the corresponding clamping voltage signal Vout1 is output from the first electrode of the sixth transistor Q6.

[0058] In this embodiment, each operational amplifier 10 is connected to a first switching circuit 20 and a second switching circuit 21, respectively. The first switching circuit 20 includes an eleventh transistor Q11 and a first current source IA; the second switching circuit 21 includes a twelfth transistor Q12. The positive terminal of the first current source IA is connected to the power supply AVDD, the negative terminal of the first current source IA is connected to the first terminal of the eleventh transistor Q11, and the second terminal of the eleventh transistor Q11 is connected to the second terminal of the seventh transistor Q7. The first terminal of the twelfth transistor Q12 is connected to the power supply AVDD, and the second terminal of the twelfth transistor Q12 is connected to the first terminal of the third transistor Q3.

[0059] The control terminals of the eleventh transistor Q11 and the twelfth transistor Q12 are both used to receive the first control signal EN1. The first control signal EN1 is used to control the eleventh transistor Q11 and the twelfth transistor Q12 to be turned on or off simultaneously, thereby controlling the corresponding operational amplifier 10 to be turned on or off.

[0060] Generally, after chip production is completed, the XY coordinates of the chip on the wafer are obtained, and the chip's identification is read. The chip's identification and its XY coordinates on the wafer are stored accordingly.

[0061] When the chip is operating normally, it is generally unnecessary to read the chip's identification identifier. The operational amplifier 10 can be turned off via the first switching circuit 20 and the second switching circuit 21. This eliminates the need to read the chip's identification identifier generated by the identifier generation circuit, reducing power consumption and extending the lifespan of the identifier generation circuit. When the chip fails, a corresponding control signal is input to activate the first switching circuit 20 and the second switching circuit 21, thereby turning on the operational amplifier 10. The identifier sequence generation circuit then outputs the chip's corresponding identification identifier. Based on this identifier, the chip's XY coordinates on the wafer are then located to trace its relevant information.

[0062] Regarding the operational amplifier 10 of the above embodiment, it is assumed that the random deviation coefficient generated during the manufacturing process of each transistor is A. vt The input pair of operational amplifier 10 has a transistor width of W and a length of L. The influence of the active load on the transistor can be ignored. Therefore, the average voltage deviation of operational amplifier 10 can be expressed as:

[0063]

[0064] Assuming a chip includes n operational amplifiers as described above, reading the chip's identifier yields an identifier sequence, which can be represented as [V]. OS0 VOS1 V OS2 ,…,V OSn ].

[0065] Based on the measurement accuracy, each ±α is divided into a range. The probability that the voltage deviation value of each operational amplifier output falls within the ±α range can be expressed as:

[0066] For a chip containing n operational amplifiers, its identification sequence [V] Os0 V OS1 V OS2 ,…,V OSn The probability that each sub-identifier (i.e., the voltage deviation value of each operational amplifier output) falls within the range of ±α can be expressed as:

[0067]

[0068] Furthermore, assuming a precision of βmV per level, the probability p0 of the voltage deviation value of each operational amplifier output falling within [α, α+β] can be expressed as:

[0069]

[0070] For a chip containing n operational amplifiers, its identification sequence [V] OS0 V OS1 V OS2 ,…,V OSn The probability P1 that each subsequence in the sequence falls within the range [α, α+β] can be expressed as:

[0071]

[0072] Assume the identity sequence [V] in the two chips OS0 V OS1 V OS2 ,…,V OSn If the probability that each sub-identifier in a given set of N chips is the same is M, then the probability P2 that at least two chips have the same identifier sequence can be expressed as:

[0073]

[0074] For example, if a chip includes 8 operational amplifiers, and the average deviation of each operational amplifier is 30mV, and the operational amplifiers are divided into ±2mV increments, then the probability P3 of a single operational amplifier falling within the ±2mV range is:

[0075]

[0076] Since the eight operational amplifiers are independent of each other, the probability that the output deviation of each of the eight operational amplifiers is within ±2mV is 0.0531529. 8 =6.37×10 -11 .

[0077] If we divide the range into 4mV increments, the probability that all the deviation values ​​of the eight operational amplifiers are in the same range and are identical is 2.4374820164 × 10⁻⁶. -10 Assuming there are 12,000 chips on each wafer, the probability that at least two chips on a wafer have the same identification is 1.74%; even if 50 chips are returned due to customer complaints, the probability that two chips have the same identification is 2.986E-07.

[0078] As can be seen, using the chip identity generation circuit provided in this embodiment, the probability that any two chips on a wafer generate the same identity sequence is very low. Therefore, the identity sequence generated by this chip identity generation circuit can represent the unique identity of the chip.

[0079] As can be seen, compared with the circuit structure of setting multiple eFuse in related technologies, the chip identity generation circuit structure provided in this embodiment is simple, and the generated identity sequence is easy to read. It does not require the configuration of related programming and reading circuits, which makes the chip occupy a small area and reduces the chip production cost.

[0080] Figure 3 For a schematic diagram of a sub-identifier generation circuit provided in this application, please refer to [link / reference]. Figure 3 As shown, the sub-identifier generation circuit 31 includes a thirteenth transistor Q13, a first resistor R1, a second resistor R2, and an inverter D1. The first terminal of the thirteenth transistor Q13 is connected to the first end of the first resistor R1, the second end of the first resistor R1 is used to connect to the power supply AVDD, the second terminal of the thirteenth transistor Q13 is grounded, and the first terminal of the thirteenth transistor Q13 is connected to the input terminal of the inverter D1. The control terminal of the thirteenth transistor Q13 is used to receive the input signal Vtest, and the output terminal of the inverter D1 is used to output the output signal Vout2. The identifier sequence generation circuit is also used to obtain the trigger value of the input signal Vtest when the output signal of the inverter D1 in each sub-identifier generation circuit 31 flips from low level to high level; and to generate an identity identifier sequence according to the trigger values ​​corresponding to multiple sub-identifier generation circuits 31.

[0081] Understandably, due to manufacturing variations in the components that make up the sub-identity generation circuit 31, the trigger values ​​for each sub-identity generation circuit 31 to conduct are different. For example, the value of the input signal Vtest when the inverter D1 of each sub-identity generation circuit 31 flips from low to high is recorded as the trigger value, which is the threshold voltage at which the sub-identity generation circuit 31 conducts. The multiple trigger values ​​output by the multiple sub-identity generation circuits 31 form an identity sequence, used to represent the identity of the chip.

[0082] Similarly, after the chip is generated, the identification sequence corresponding to each chip is read first, and the identification sequence of the chip and its corresponding identification are stored. When the chip fails, the identification sequence of the chip can be read, and the identification of the chip can be found according to the identification sequence.

[0083] Understandably, the identification of a chip can generally include the chip's DIE ID, Lot ID, manufacturer information, production date, production line, and other related information.

[0084] In some embodiments, please refer to Figure 3 As shown, the sub-identifier generation circuit 31 is connected to the third switching circuit 30. The third switching circuit 30 includes a fourteenth transistor Q14. The first terminal of the fourteenth transistor Q14 is connected to the power supply AVDD, the second terminal of the fourteenth transistor Q14 is connected to the second terminal of the second resistor R2, and the control terminal of the fourteenth transistor Q14 is used to receive the second control signal EN2. The second control signal EN2 is used to control the conduction or cutoff of the fourteenth transistor Q14, thereby controlling the conduction or cutoff of the corresponding sub-identifier generation circuit 31. Specifically, when the chip is operating normally, by controlling the fourteenth transistor Q14 to turn off, the sub-identifier generation circuit 31 is disconnected, and the control terminal of the thirteenth transistor Q13 is pulled down to ground through the first resistor R1 to reduce device aging.

[0085] Under normal chip operation, the sub-identifier generation circuit 31 can be turned off by the third switch circuit 30 to prevent device aging, extend the working life of the sub-identifier generation circuit 31, and save power consumption.

[0086] Understandably, based on the number of chips on the wafer, the number of sub-identifier generation circuits 31 that need to be set for each chip is determined to ensure that the identity identifier sequence generated by each chip is unique.

[0087] As can be seen, compared with the circuit structure of setting multiple eFuse in related technologies, the sub-identifier generation circuit structure provided in this embodiment is simple, and the generated identity identifier sequence is easy to read. It does not require the configuration of related programming and reading circuits, which makes the chip occupy a small area and reduces the chip production cost.

[0088] In one embodiment, the embodiment also provides a chip, which includes the chip identification recording circuit and related functional circuits as described above. The working process and functional effects of the chip in this embodiment can be referred to the chip identification recording circuit described above, and will not be repeated here.

[0089] In one embodiment, the embodiment also provides an electronic device that includes the chip described above.

[0090] It is understood that in other embodiments, the electronic device may include, in addition to the chip described above, some related hardware such as housing, circuit board, power supply and communication interface, which will not be described in detail here.

[0091] Finally, it should be noted that the above embodiments are merely specific implementations of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip identification generation circuit, used to generate chip identification, characterized in that, The identity generation circuit includes an identity sequence generation circuit and multiple sub-identity generation circuits; The identity generation circuit further includes multiple switching circuits; each sub-identity generation circuit is connected to at least one switching circuit; the switching circuit is used to receive a control signal, which controls the switching circuit to be turned on or off, thereby controlling the corresponding sub-identity generation circuit to be turned on or off; when the chip is working normally, the control signal controls the switching circuit to be turned off, thereby controlling the sub-identity generation circuit to be in a turned-off state; when the chip fails, the control signal controls the switching circuit to be turned on, thereby controlling the sub-identity generation circuit to be in a turned-on state. The sub-identifier generation circuit is an operational amplifier; the input signal is a reference voltage signal, and the output signal is a clamping voltage signal; the operational amplifier is used to receive the input reference voltage signal and perform clamping processing on the reference voltage signal to output a corresponding clamping voltage signal; the identifier sequence generation circuit is used to generate a voltage deviation value based on the clamping voltage signal and the reference voltage signal corresponding to each operational amplifier, and generate an identity identifier sequence based on the voltage deviation values ​​corresponding to multiple operational amplifiers; Alternatively, the identifier sequence generation circuit is further configured to generate an identity identifier sequence based on the multiple clamping voltage signals corresponding to the multiple sub-identifier generation circuits; Alternatively, the identifier sequence generation circuit is further configured to obtain the trigger value of the reference voltage signal when the clamping voltage signal corresponding to each of the sub-identifier generation circuits undergoes a state change; and generate an identity identifier sequence based on the trigger values ​​corresponding to the plurality of sub-identifier generation circuits. The identity sequence is used to represent the unique identity of a chip.

2. The chip identity generation circuit according to claim 1, characterized in that, The operational amplifier is a two-stage operational amplifier composed of multiple transistors.

3. The chip identity generation circuit according to claim 2, characterized in that, The operational amplifier includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, and a first capacitor; The first terminal of the first transistor is connected to the first terminal of the second transistor, the second terminal of the first transistor is connected to the second terminal of the fourth transistor, the control terminal of the first transistor is shorted to the second terminal of the first transistor, and the first terminal of the fourth transistor is connected to the first terminal of the fifth transistor; the control terminal of the first transistor is connected to the control terminal of the second transistor, the second terminal of the second transistor is connected to the second terminal of the fifth transistor, and the control terminal of the fifth transistor is the input terminal of the operational amplifier; The first terminal of the third transistor is connected to the first terminal of the second transistor, the control terminal of the third transistor is connected to the second terminal of the third transistor through the first capacitor, the second terminal of the third transistor is connected to the second terminal of the ninth transistor, and the first terminal of the ninth transistor is grounded; the second terminal of the sixth transistor is connected to the first terminal of the third transistor, the control terminal of the sixth transistor is connected to the second terminal of the third transistor, the first terminal of the sixth transistor is connected to the second terminal of the tenth transistor, the first terminal of the tenth transistor is grounded, and the control terminal of the fourth transistor is also connected to the second terminal of the tenth transistor; The second terminal of the seventh transistor is used to receive a current signal; the first terminal of the seventh transistor is grounded; the second terminal of the seventh transistor and the control terminal are shorted; the second terminal of the eighth transistor is connected to the first terminal of the fourth transistor; the first terminal of the eighth transistor is grounded. The control electrodes of the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor are shorted to each other.

4. The chip identity generation circuit according to claim 3, characterized in that, Each of the sub-identifier generation circuits is connected to the first switch circuit and the second switch circuit respectively; The first switching circuit includes an eleventh transistor and a first current source; the second switching circuit includes a twelfth transistor. The positive terminal of the first current source is used to connect to the power supply, the negative terminal of the first current source is connected to the first terminal of the eleventh transistor, and the second terminal of the eleventh transistor is connected to the second terminal of the seventh transistor; the first terminal of the twelfth transistor is used to connect to the power supply, and the second terminal of the twelfth transistor is connected to the first terminal of the third transistor. The control electrode of the eleventh transistor and the control electrode of the twelfth transistor are both used to receive the first control signal; the first control signal is used to control the eleventh transistor and / or the twelfth transistor to turn on or off, thereby controlling the corresponding operational amplifier to turn on or off.

5. The chip identity generation circuit according to claim 1, characterized in that, The sub-identifier generation circuit includes a thirteenth transistor, a first resistor, a second resistor, and an inverter; The first terminal of the thirteenth transistor is connected to the first end of the first resistor, the second end of the first resistor is used to connect to the power supply, the second terminal of the thirteenth transistor is grounded, the first terminal of the thirteenth transistor is connected to the input terminal of the inverter; the control terminal of the thirteenth transistor is used to receive the input signal, and the output terminal of the inverter is used to output the output signal. The identifier sequence generation circuit is further configured to obtain the trigger value of the input signal when the output signal of the inverter in each sub-identifier generation circuit flips from low level to high level; and generate the identity identifier sequence according to the trigger values ​​corresponding to the multiple sub-identifier generation circuits.

6. The chip identity generation circuit according to claim 5, characterized in that, The sub-identifier generation circuit is connected to the third switching circuit, which includes a fourteenth transistor. The first terminal of the fourteenth transistor is connected to the power supply, the second terminal of the fourteenth transistor is connected to the second terminal of the second resistor, and the control terminal of the fourteenth transistor is used to receive a second control signal. The second control signal is used to control the fourteenth transistor to turn on or off, thereby controlling the corresponding sub-identifier generation circuit to turn on or off.

7. A chip, characterized in that, Includes the chip identity generation circuit as described in any one of claims 1-6.

8. An electronic device, characterized in that, Includes the chip as described in claim 7.

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