A memory scan protection method, system and apparatus

Abstract

The application relates to the technical field of memory protection, in particular to a memory scanning protection method, system and device, which comprises the following steps: saving address information of a plurality of adjacent addresses in response to a scanning operation of a storage module; performing difference value calculation on the address information of the adjacent addresses to obtain difference value information; judging whether the difference value information of the adjacent addresses is consistent to obtain output logic information, wherein if the difference value information is consistent, first logic information is output, and if the difference value information is inconsistent, second logic information is output; performing one addition or zero return on the result based on the first logic information and the second logic information to obtain scanning rule information; comparing the scanning rule information with preset maximum linear reading times of the memory to obtain a comparison result; and judging whether an attack flag instruction of a protection mechanism is triggered according to the comparison result, so that the interference of a malicious circuit on a memory circuit is reduced, and the safety of the memory circuit is improved.

Description

Technical Field

[0001] This application relates to the field of memory protection technology, and in particular to a method, system and apparatus for protecting memory from scanning. Background Technology

[0002] With the rapid development of the digital economy, the security issues of modern electronic information systems have become increasingly prominent. Chips, as their underlying core, have always played an irreplaceable role. Therefore, in certain specific fields, such as financial IC cards, automotive chips, and systems, related chips are subject to significant potential attack risks. Memory, as the carrier of chip programs and critical information, is a crucial component of chip security. Currently, a common design approach is to increase the complexity of encryption algorithms to enhance security, but this method is limited and reactive.

[0003] Throughout a chip's lifecycle, its design, manufacturing, and application require the participation of multiple third-party entities. The assistance of third-party design tools and design vendors may introduce unforeseen risks. For example, third-party IP cores and foundries may introduce hardware malware, or even chip users may crack the programming interface and use implanted or external malicious circuits to scan the chip's internal memory, obtain its complete program, and then decompile it to analyze chip functionality or other critical information. Therefore, proactive attack detection and protection of memory are necessary.

[0004] Currently, chips mainly consist of highly controllable circuits and general-purpose circuits, both of which can perform read and write operations on memory. Highly controllable circuits are custom-designed modules, making them less likely to contain malicious circuits. However, if the general-purpose module is a standard module, attackers have diverse and feasible attack methods. For example, through multiple simulation tests and attacks, and after statistical analysis, or even with the assistance of reverse engineering, attackers can decipher communication and programming protocols to scan the memory. If it is a third-party designed module, because its internal details are not disclosed, the user cannot determine whether it contains insecure circuits, thus the security of the memory cannot be guaranteed. These issues need to be addressed. Summary of the Invention

[0005] To reduce interference from malicious circuits to memory circuits and improve the security of memory circuits, this application provides a method, system, and apparatus for protecting memory from scanning, employing the following technical solution:

[0006] In a first aspect, this application provides a method for protecting a memory from scanning, comprising:

[0007] In response to the scanning operation of the storage module, it saves several adjacent address information;

[0008] The difference between each pair of adjacent address information is calculated to obtain the difference information;

[0009] Determine whether the difference information of several adjacent values ​​is consistent, and obtain the output logic information. If they are consistent, output the first logic information; if they are inconsistent, output the second logic information.

[0010] Based on the first and second logical information, the result is incremented by one or reset to zero to obtain the scanning pattern information;

[0011] The scanning pattern information is compared with the preset maximum number of linear reads of the memory to obtain the comparison result. Based on the comparison result, it is determined whether the attack flag instruction of the protection mechanism is triggered.

[0012] Preferably, when an attack flag instruction is obtained, reset information is obtained, and a reset operation is performed on the pseudo-random number generator according to the reset information. Also, when an attack flag instruction is obtained, pseudo-sequence information is generated by the pseudo-random number generator, and a feedback operation is performed based on the pseudo-sequence information.

[0013] Preferably, when an attack flag instruction is obtained, the count value of the attack flag instruction is compared with the preset maximum attack value to obtain the attack result, and a decision is made on whether to perform a data destruction operation based on the attack result.

[0014] Secondly, this application provides a memory scan protection system, including a processor module, a read / write control module, an encryption module, a storage module, a decryption module, and several general modules, as well as a detection module and a protection module. The detection module includes an address register submodule, which is used to store several adjacent address information in response to the scan operation of the storage module.

[0015] The calculation submodule is used to calculate the difference between each pair of adjacent address information to obtain the difference information;

[0016] The first comparison submodule is used to determine whether the difference information of several adjacent values ​​is consistent, and to obtain output logic information. If they are consistent, the first logic information is output; if they are inconsistent, the second logic information is output.

[0017] The counting register submodule is used to increment or reset the result based on the first logic information and the second logic information to obtain the scanning pattern information;

[0018] The maximum value register submodule is used to store the maximum number of linear reads;

[0019] The second comparison submodule is used to compare the scanning pattern information with the preset maximum number of linear reads of the memory, obtain the comparison result, and determine whether to trigger the attack flag instruction of the protection mechanism based on the comparison result.

[0020] The protection module is used to acquire attack flag instructions and perform false feedback operations and data destruction operations based on the attack flag instructions.

[0021] Preferably, the address register submodule includes three address registers, which are used to store first address information, second address information and third address information respectively. The calculation submodule includes two subtractors, one of which is used to calculate the first address information and the second address information, and the other of which is used to calculate the second address information and the third address information to obtain two difference information that are applied to the first comparison submodule.

[0022] Preferably, the address register submodule includes two address registers, one address register for storing the first address information and the second address information of the first clock cycle, and the other address register for storing the second address information and the third address information of the second clock cycle. The calculation submodule includes a subtractor and two difference registers. The subtractor is used to calculate the address information of the first clock cycle and the second clock cycle respectively, and the two difference information acting on the first comparison submodule are stored in the difference registers respectively.

[0023] Preferably, the protection module includes a false feedback submodule, which is used to obtain reset information when the attack flag instruction of the detection module is obtained, perform a reset operation on the pseudo-random number generator according to the reset information, and generate pseudo-sequence information according to the pseudo-random number generator when the attack flag instruction of the detection module is obtained, and perform a feedback operation according to the pseudo-sequence information.

[0024] Preferred,

[0025] The protection module also includes:

[0026] The data destruction submodule is used to compare the count value of the attack flag command with the preset maximum attack value when an attack flag command is obtained, to obtain the attack result, and to determine whether to perform the data destruction operation based on the attack result.

[0027] Preferably, the address information includes ciphertext address information or plaintext address information.

[0028] Preferably, the second comparison submodule obtains an attack flag instruction when the scanning pattern information is greater than or equal to the maximum number of linear reads.

[0029] Thirdly, this application provides a scan protection device for a memory, including the scan protection system for the memory as described above.

[0030] In summary, compared with the prior art, the beneficial effects of the technical solution provided in this application include at least the following:

[0031] This application comprises a memory circuit system consisting of a processor module, a read / write control module, an encryption module, a storage module, a decryption module, and several general-purpose modules. A detection module is connected to the read / write control module to obtain its address information. This address information is monitored, and if an address jump conforms to a scanning pattern, an attack flag instruction is obtained and sent to the connected protection module. Upon detecting the attack flag instruction, the protection module performs false feedback and data destruction operations, thereby protecting the memory's program or data, reducing interference from malicious circuits, and improving the security of the memory circuit. Attached Figure Description

[0032] Figure 1 This is a schematic flowchart of a memory scan protection method according to an embodiment of this application.

[0033] Figure 2 This is a schematic diagram of a module of a memory scan protection system according to an embodiment of this application.

[0034] Figure 3 This is a schematic diagram of the first module of the detection module described in the embodiments of this application.

[0035] Figure 4 This is a schematic diagram of the second module of the detection module described in the embodiments of this application.

[0036] Figure 5 This is a schematic diagram of the false feedback submodule described in the embodiments of this application.

[0037] Figure 6 This is a schematic diagram of the reset data processing flow of the false feedback submodule described in the embodiments of this application.

[0038] Figure 7 This is a schematic diagram of the data destruction submodule described in the embodiments of this application.

[0039] Figure 8 This is a schematic diagram of the data processing flow of the data destruction submodule described in the embodiments of this application.

[0040] Explanation of reference numerals in the attached figures:

[0041] 1. Processor module; 2. Read / write control module; 3. Encryption module; 4. Storage module; 5. Decryption module; 6. General module; 7. Detection module; 71. Address register submodule; 72. Calculation submodule; 73. First comparison submodule; 74. Count register submodule; 75. Maximum value register submodule; 76. Second comparison submodule; 8. Protection module; 81. False feedback submodule; 82. Data destruction submodule. Detailed Implementation

[0042] The following combination Figures 1-6 The present application will be described in further detail below. The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting.

[0043] Reference Figure 1 The present application relates to a method for protecting a memory from scanning, comprising:

[0044] Step S1: In response to the scanning operation of the storage module, save the address information of several adjacent addresses;

[0045] Step S2: Calculate the difference between each pair of adjacent address information to obtain the difference information;

[0046] Step S3: Determine whether the difference information of several adjacent values ​​is consistent, and obtain the output logic information. If they are consistent, output the first logic information; if they are inconsistent, output the second logic information.

[0047] Step S4: Based on the first logical information and the second logical information, increment or reset the result to zero to obtain the scanning pattern information;

[0048] Step S5: Compare the scanning pattern information with the preset maximum number of linear reads of the memory to obtain the comparison result, and determine whether to trigger the attack flag instruction of the protection mechanism based on the comparison result.

[0049] Specifically, the detection module is connected to the read / write control module to obtain the address information of the read / write control module. The address information is monitored, and when the address jump conforms to the scanning pattern, an attack flag instruction is obtained. The attack flag instruction is sent to the connected protection module. When the protection module detects the attack flag instruction, it performs false feedback and data destruction operations, thereby protecting the program or data of the memory, reducing the interference of malicious circuits on the memory circuit, and improving the security of the memory circuit.

[0050] In one implementation, when an attack flag instruction is obtained, reset information is obtained, and a reset operation is performed on the pseudo-random number generator according to the reset information. Also, when an attack flag instruction is obtained, pseudo-sequence information is generated by the pseudo-random number generator, and a feedback operation is performed based on the pseudo-sequence information.

[0051] In one implementation, when an attack flag instruction is obtained, the count value of the attack flag instruction is compared with a preset maximum attack value to obtain the attack result, and a decision is made on whether to perform a data destruction operation based on the attack result.

[0052] Reference Figure 2The memory scanning protection system disclosed in this application specifically includes a processor module, a read / write control module, an encryption module, a storage module, a decryption module, and several general-purpose modules, and further includes:

[0053] The detection module is used to obtain the address information of the read / write control module, monitor the address information, and obtain the attack flag instruction when the address jump conforms to the scanning pattern.

[0054] The protection module is used to perform false feedback and data destruction operations when it receives an attack flag instruction from the detection module.

[0055] Specifically, this application comprises an integrated circuit system consisting of a processor module, a read / write control module, an encryption module, a storage module, a decryption module, and several general-purpose or special-purpose modules. The processor module is the core of the system, responsible for executing computational tasks and controlling the entire data flow. It receives instructions and data from other modules, such as data from general-purpose and special-purpose modules, and executes corresponding operations based on the data or instructions. The read / write control module manages data read and write operations. It receives read / write requests from the processor module or encrypted data from the encryption module and communicates with the storage module to interact with it. The encryption module protects data security, typically encrypting data before it enters the storage module. It receives data from the processor, read / write control module, or general-purpose and special-purpose modules, encrypts it, and then transmits it to the storage module. The storage module is the primary data storage location. It receives encrypted or unencrypted data, writes it to storage devices such as hard disks or solid-state drives, or reads data from storage devices and transmits it to the decryption module, which then sends it to the general-purpose and special-purpose modules. The decryption module decrypts data after it is read from the storage module. It receives encrypted data transmitted from the storage module, decrypts it, and then transmits the plaintext data to the processor module or general-purpose / dedicated modules. General-purpose and dedicated modules include functional modules such as IP core modules, communication I / O modules, and programming modules. For IP cores, such as publicly available security algorithm calculation modules (designed by third-party companies), these can be purchased and integrated directly. Dedicated modules are those designed in-house for a specific application scenario. For communication I / O modules using publicly available standard protocols, third-party general-purpose modules can be purchased directly. However, for custom protocols, redesign is required, making them dedicated modules. The internal details of third-party general-purpose modules are not publicly available and may contain hardware malware. For standard modules, there are many ways to crack them.

[0056] This application also includes a detection module and a protection module. During the operation of the memory circuit system, this application connects the detection module to the read / write control module to obtain the address information of the read / write control module, monitors the address information, and when the address jump conforms to the scanning pattern, obtains an attack flag instruction. The attack flag instruction is then sent to the connected protection module. If the protection module detects the attack flag instruction, it performs false feedback and data destruction operations, thereby protecting the program or data of the memory, reducing interference from malicious circuits to the memory circuit, and improving the security of the memory circuit.

[0057] As one implementation method, the detection module includes:

[0058] The address register submodule is used to store several adjacent address information;

[0059] The calculation submodule is used to calculate adjacent address information to obtain several difference information;

[0060] The first comparison submodule is used to compare the difference information and obtain the output logic information;

[0061] The counting register submodule is used to increment or reset the count based on the output logic information to obtain the scanning pattern information;

[0062] The maximum value register submodule is used to store the maximum number of linear reads;

[0063] The second comparison submodule is used to compare the scanning pattern information with the maximum number of linear reads to obtain the attack flag instruction used to trigger the protection mechanism.

[0064] Specifically, refer to Figure 3 In this embodiment, the address register submodule is connected to the calculation submodule, which is connected to the first comparison submodule. The first comparison submodule is connected to the counting register submodule, and both the counting register submodule and the maximum value register submodule are connected to the second comparison submodule. Finally, an attack flag instruction is output and sent to the protection module. The address register submodule obtains and saves address information. Figure 3 The A signal represents address information, specifically including ciphertext and plaintext address information. Based on the connection between the address register submodule and the calculation submodule, the address information is sent to the corresponding subtractor in the calculation submodule for calculation. The resulting difference is sent to the first comparison submodule for comparison, yielding the output logic information. The output logic information is typically logic 1 or logic 0. The counting register submodule performs an increment operation if it receives a logic 1; otherwise, it resets to zero. Each execution yields a scan pattern. The second comparison submodule retrieves the maximum linear read count from the maximum value register submodule and compares it with the scan pattern information. If the conditions are met, an attack flag instruction is obtained. Figure 3 The B signal in the signal activates the protection module.

[0065] As one implementation method, the address information includes ciphertext address information or plaintext address information.

[0066] Specifically, this application monitors the encrypted and plaintext addresses of the read memory using a detection module. When an address jump conforms to a scanning pattern, a protection mechanism is triggered, and the detection module processes the encrypted and plaintext address information. Plaintext address information refers to the actual physical or logical address of the data in memory, i.e., the original address without encryption or obfuscation. In the system, the processor and other components use plaintext addresses to directly access data or instructions in memory. Cited address information refers to addresses that have undergone encryption. In systems with high security requirements, data is encrypted and stored in memory. The corresponding storage address also needs to be encrypted to protect data security. Cited addresses differ from plaintext addresses; they are addresses generated using a specific encryption or conversion algorithm.

[0067] In one implementation, the address register submodule includes three address registers, which are used to store first address information, second address information and third address information respectively. The calculation submodule includes two subtractors, one of which is used to calculate the first address information and the second address information, and the other is used to calculate the second address information and the third address information to obtain two difference information that are applied to the first comparison submodule.

[0068] Specifically, refer to Figure 3 In this application embodiment, two identical detection circuit modules are designed. One group monitors the plaintext address to prevent malicious programs and circuits from scanning it, and the other group monitors the ciphertext address to prevent malicious circuits and reverse engineering from assisting in scanning.

[0069] The detection process involves first using three address registers: ADDR1 (first address register), ADDR2 (second address register), and ADDR3 (third address register), to store the plaintext or ciphertext address information of three consecutive memory reads. The first and second address registers are connected to the inputs of the first subtractor, and the second and third address registers are connected to the inputs of the second subtractor, enabling the subtractors to calculate ADDR1-ADDR2 and ADDR2-ADDR3 respectively.

[0070] After the first comparison submodule obtains the difference information between ADDR1-ADDR2 and ADDR2-ADDR3, it performs a difference comparison. The comparator determines whether the two differences are consistent. If they are consistent, it means that ADDR1, ADDR2, and ADDR3 conform to a single scan pattern, and the module outputs a logic 1 or logic 0; otherwise, it outputs a logic 0 or logic 1. Based on the comparator's output, the counter register is incremented by 1 or reset to 0. At this point, the counter value CNT means that the plaintext or ciphertext address has consecutively conformed to the CNT scan pattern.

[0071] In one implementation, the second comparison submodule obtains an attack flag instruction when the scanning pattern information is greater than or equal to the maximum number of linear reads.

[0072] Specifically, in this embodiment, the maximum value register submodule ensures that the number of linear memory reads during normal chip operation will not exceed MAX times. Therefore, during the chip's POR stage, the data MAX is written into the maximum value register, or the data MAX is permanently stored using hardware circuitry. Finally, the second comparison submodule compares CNT and MAX. When CNT ≥ MAX, it indicates that the chip is under attack, generating an attack flag and triggering the chip protection mechanism.

[0073] In one implementation, the address register submodule includes two address registers. One address register stores the first address information and the second address information for the first clock cycle, and the other address register stores the second address information and the third address information for the second clock cycle. The calculation submodule includes a subtractor and two difference registers. The subtractor calculates the address information for the first clock cycle and the second clock cycle respectively, and obtains two difference information acting on the first comparison submodule, which are stored in the difference registers respectively.

[0074] Specifically, refer to Figure 4 The detection module circuit can also be implemented in the manner described in this embodiment. The previous embodiment achieves the same function as this embodiment. In the previous embodiment, the difference between ADDR1 and ADDR2 and the difference between ADDR2 and ADDR3 were calculated simultaneously. If they were consistent, it indicated that the scan pattern was met. In this embodiment, the difference between ADDR1 and ADDR2 is first calculated and stored in difference 1. In the next clock cycle, the value of ADDR2 overwrites ADDR1, and the value of ADDR3 overwrites ADDR2. At the same time, difference 1 is transferred to difference 2. At this time, the new difference 1 is equal to ADDR2 - ADDR3. If difference 1 and difference 2 are consistent, it also indicates that the scan pattern is met.

[0075] As one implementation method, the protection module includes:

[0076] The false feedback submodule is used to obtain reset information when the attack flag instruction from the detection module is obtained, and to perform a reset operation on the pseudo-random number generator according to the reset information. When the attack flag instruction from the detection module is obtained, pseudo-sequence information is generated by the pseudo-random number generator according to the pseudo-random number generator, and a feedback operation is performed according to the pseudo-sequence information.

[0077] Specifically, refer to Figure 5 and Figure 6 This application embodiment considers that emergency measures against attacks typically involve resetting the chip. However, for experienced attackers, the interference or misleading nature of a reset is insufficient to provide protection, and they can often quickly adjust their attack direction. Therefore, this application embodiment designs a scanning attack response module with multi-dimensional interference and misleading analysis. This module first performs a superficially erroneous behavior that matches the attacker's expectations. Then, when the attacker performs multiple scanning attacks on the chip, the data sequence returned by the chip remains unchanged, consistent with the phenomenon of normal memory scanning, guiding the attacker in erroneous directions, such as: the scanning attack was successful.

[0078] Specifically, the attack flag instruction is sent to the false feedback module, which activates the pseudo-random number generator logic. The pseudo-random sequence replaces the ciphertext sequence in the memory, i.e., replaces... Figure 5 The D signal in the output is used to ensure the consistency of the pseudo-random sequence during multiple scan attacks without power loss. The pseudo-random number generator needs to be initialized at the end of the scan attack, and its initial value is a reset or set value.

[0079] The false feedback submodule also includes a circuit to determine the end of the scanning attack. The process for generating the reset or set signal is as follows: attack information is sent to the false feedback module, and the main clock counts the time interval between two memory read signals, specifically by acquiring... Figure 5 The C signal, namely the master clock and memory read signal, is used. Then, the count value is shifted to generate an end reference value, and the result is stored in the reference value register. When the count value is equal to the end reference value, it is considered that the scan attack has ended, and a reset or set signal is generated to initialize the pseudo-random number generator.

[0080] As one implementation, the protection module further includes a data destruction submodule, used to perform data destruction operations upon receiving an attack flag instruction from the detection module.

[0081] Specifically, refer to Figure 7 and Figure 8 The data destruction module's workflow is as follows: the chip powers on, and the attack count value is read, i.e. Figure 7 The E signal in the signal; the generated attack maximum value = base + finite-length random number, where the base determines the minimum value of the interval to which the maximum value belongs, and the random number increases the interference. Figure 7 The F signal is a base number and a random number; the count value is compared with the maximum value. If the count value is less than the maximum value, the chip is undamaged; if the count value is greater than or equal to the maximum value, a memory erase signal is triggered, damaging the chip. A scan attack signal is triggered, incrementing the attack count by 1; the count value is compared with the maximum value. If the count value is less than the maximum value, the chip is undamaged, and the new attack count value is recorded in memory, i.e., output. Figure 7 The G signal; when the count value is greater than or equal to the maximum value, the memory erase signal is triggered, i.e. Figure 7 The H signal caused the chip to be damaged.

[0082] Because the maximum attack value generated each time the chip is powered on is different, the chip destruction time is not unique, which can effectively hide the chip's damage conditions and thus mislead attackers.

[0083] This application provides a memory scan protection device, including the memory scan protection system as described above.

[0084] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the device and product described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0085] In the several embodiments provided in this application, it should be understood that the disclosed methods, systems, apparatus and program products can be implemented in other ways.

[0086] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0087] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A method for protecting a memory from scanning, characterized in that, include: In response to the scanning operation of the storage module, it saves several adjacent address information; The difference between each pair of adjacent address information is calculated to obtain the difference information; Determine whether the difference information of several adjacent values ​​is consistent, and obtain the output logic information. If they are consistent, output the first logic information; if they are inconsistent, output the second logic information. Based on the first and second logical information, the result is incremented by one or reset to zero to obtain the scanning pattern information; The scanning pattern information is compared with the preset maximum linear read count of the memory to obtain the comparison result. Based on the comparison result, it is determined whether the attack flag instruction of the protection mechanism is triggered. Upon receiving an attack flag instruction, reset information is obtained, and a reset operation is performed on the pseudo-random number generator based on the reset information. Furthermore, upon receiving an attack flag instruction, pseudo-sequence information is generated based on the pseudo-random number generator, and a feedback operation is performed based on the pseudo-sequence information.

2. The memory scan protection method according to claim 1, characterized in that, Upon receiving an attack flag command, the attack flag command's count value is compared with a preset maximum attack value to obtain the attack result. Based on the attack result, it is determined whether to perform a data destruction operation.

3. A scan protection system for a memory, comprising a processor module, a read / write control module, an encryption module, a storage module, a decryption module, and several general-purpose modules, characterized in that, It also includes a detection module and a protection module. The detection module includes: The address register submodule is used to respond to the scan operation of the storage module and store several adjacent address information; The calculation submodule is used to calculate the difference between each pair of adjacent address information to obtain the difference information; The first comparison submodule is used to determine whether the difference information of several adjacent values ​​is consistent, and to obtain output logic information. If they are consistent, the first logic information is output; if they are inconsistent, the second logic information is output. The counting register submodule is used to increment or reset the result based on the first logic information and the second logic information to obtain the scanning pattern information; The maximum value register submodule is used to store the maximum number of linear reads; The second comparison submodule is used to compare the scanning pattern information with the preset maximum number of linear reads of the memory, obtain the comparison result, and determine whether to trigger the attack flag instruction of the protection mechanism based on the comparison result. The protection module is used to acquire attack flag instructions and perform false feedback operations and data destruction operations based on the attack flag instructions.

4. The memory scan protection system according to claim 3, characterized in that, The address register submodule includes three address registers, which are used to store first address information, second address information and third address information respectively. The calculation submodule includes two subtractors. One subtractor is used to calculate the first address information and the second address information, and the other subtractor is used to calculate the second address information and the third address information to obtain two difference information that are applied to the first comparison submodule.

5. The memory scan protection system according to claim 3, characterized in that, The address register submodule includes two address registers. One address register is used to store the first address information and the second address information of the first clock cycle, and the other address register is used to store the second address information and the third address information of the second clock cycle. The calculation submodule includes a subtractor and two difference registers. The subtractor is used to calculate the address information of the first clock cycle and the second clock cycle respectively, and the two difference information acting on the first comparison submodule are stored in the difference registers respectively.

6. The memory scan protection system according to claim 3, characterized in that, The protection module includes: The false feedback submodule is used to obtain reset information when the attack flag instruction from the detection module is obtained, and to perform a reset operation on the pseudo-random number generator according to the reset information. When the attack flag instruction from the detection module is obtained, pseudo-sequence information is generated by the pseudo-random number generator according to the pseudo-random number generator, and a feedback operation is performed according to the pseudo-sequence information.

7. The memory scan protection system according to claim 3, characterized in that, The protection module also includes: The data destruction submodule is used to compare the count value of the attack flag command with the preset maximum attack value when an attack flag command is obtained, to obtain the attack result, and to determine whether to perform the data destruction operation based on the attack result.

8. The memory scan protection system according to claim 3, characterized in that, The address information includes encrypted address information or plaintext address information.

9. A scan protection device for a memory, characterized in that, A scan protection system for a memory including any one of claims 3-8.

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