A display panel driving method, display device, and display panel.

Abstract

This application provides a display panel driving method, a display device, and a display panel. The display panel driving method includes: generating a non-uniform width pulse PWM signal when switching from a DC dimming mode to a pulse width modulation (PWM) dimming mode. The non-uniform width pulse PWM signal includes multiple first-type pulses and multiple second-type pulses. Both the first-type pulses and the second-type pulses are first-level signals. The pulse width of the first-type pulses is greater than the pulse width of the second-type pulses, and the pulse width of the first-type pulses is not less than the minimum level width required for scanning or resetting the pixel circuits in the display panel. The non-uniform width pulse PWM signal is then used to scan each row of pixel circuits in the display panel. By including multiple first-type pulses and multiple second-type pulses in the non-uniform width pulse PWM signal, the duty cycle of PWM dimming can be increased in high-frequency PWM situations, reducing flicker during switching between high-frequency PWM dimming and DC dimming.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel driving method, display device and display panel. Background Technology

[0002] Traditional PWM (Pulse Width Modulation) dimming, in OLED (Organic Light Emitting Diode) screens using PMOS (positive channel Metal Oxide Semiconductor) technology, sets all EM (emitting control signals) high-level signals to approximately match the first one. This setup is relatively simple to implement and easy to control. However, with the improvement of high-frequency PWM specifications, and the implementation of new LTPO (Low Temperature Polycrystalline Oxide) solutions (which have a reset in the intermediate holding area and limited EM width), or the reduction in vertical resolution of certain special products, the proportion of high-level EM signals increases, and the duty cycle of PWM dimming decreases accordingly. In contrast, high-brightness DC dimming (which changes screen brightness by increasing or decreasing the power of the screen panel circuitry) has a very small proportion of high-level EM signals and a large proportion of low-level signals. Therefore, the duty cycle of DC dimming is usually very high. (See [link to relevant documentation]). Figure 3 If the duty cycle of high-frequency PWM dimming is too short, the flickering problem will increase when switching between dimming and DC dimming. Summary of the Invention

[0003] The purpose of this application is to provide a display panel driving method, display device, and display panel to reduce flickering during switching between high-frequency PWM dimming and DC dimming. The specific technical solution is as follows:

[0004] In a first aspect, embodiments of this application provide a display panel driving method, the method comprising:

[0005] When switching from DC dimming mode to pulse width modulation (PWM) dimming mode, a non-uniform width pulse PWM signal is generated. The non-uniform width pulse PWM signal includes multiple first-type pulses and multiple second-type pulses. Both the first-type pulses and the second-type pulses are first-level signals. The pulse width of the first-type pulses is greater than the pulse width of the second-type pulses, and the pulse width of the first-type pulses is not less than the minimum level width of the pixel circuit scanning or resetting in the display panel.

[0006] The non-uniform width pulse PWM signal is used to scan the pixel circuits in each row of the display panel.

[0007] In one possible implementation, for each frame of non-uniform width pulse PWM signal, the frame of non-uniform width pulse PWM signal includes at least two sub-timing signals; for each sub-timing signal, the sub-timing signal includes one first type pulse and a plurality of second type pulses.

[0008] In one possible implementation, the pulse width of the first type of pulse is the minimum level width for scanning or resetting the pixel circuit in the display panel, and the pulse width of the second type of pulse is the minimum width required for the timing of the display panel.

[0009] In one possible implementation, the timing of the reset signal, initialization signal, charging signal, and reset compensation signal of the pixel circuit is within the timing of the first type of pulse.

[0010] In one possible implementation, the method further includes:

[0011] The system acquires the number of pulses within each refreshed image frame, the pulse width of the first type of pulse, the pulse width of the second type of pulse, and the timing of the reset signal, initialization signal, charging signal, and reset compensation signal of the pixel circuit.

[0012] Based on the timing of the reset signal, initialization signal, charging signal and reset compensation signal and the pulse width of the first type of pulse, the number and timing of the first type of pulse are determined, wherein the timing of the reset signal, initialization signal, charging signal and reset compensation signal is within the timing of the first type of pulse, and the timing of the first type of pulse is evenly distributed within the time of one image frame.

[0013] Based on the number and timing of the first type of pulses, an image frame is divided into n sub-time signals, where n is the number of the first type of pulses. For each sub-time signal, the sub-time signal includes one first type of pulse and is located at the timing header of the sub-time signal.

[0014] Based on the number of pulses, the number of the first type of pulses, and the pulse width of the second type of pulses, the timing and number of the second type of pulses in each segment of the sub-timing signal are determined to obtain the generation parameters of the PWM signal; wherein, the generation parameters include the timing of the first type of pulses, the timing and number of the second type of pulses in each segment of the sub-timing signal, and the number of segments n of the sub-timing signal;

[0015] The step of generating a non-uniform width pulse PWM signal when switching from DC dimming mode to pulse width modulation (PWM) dimming mode includes:

[0016] When switching from DC dimming mode to pulse width modulation (PWM) dimming mode, a non-uniform width pulse PWM signal is generated according to the aforementioned generation parameters.

[0017] In one possible implementation, after scanning each row of pixel circuits in the display panel using the non-uniform width pulse PWM signal, the method further includes:

[0018] According to a preset scanning cycle, the pulse width of the second type of pulse in the non-equal width pulse PWM signal is increased by a preset width to obtain the current PWM signal;

[0019] The current PWM signal is used to scan the pixel circuits of each row in the display panel;

[0020] Return to execution steps: According to the preset scanning cycle, increase the pulse width of the second type of pulse in the non-uniform width pulse PWM signal, or increase the pulse width of the first type of pulse and the second type of pulse in the non-uniform width pulse PWM signal to obtain the current PWM signal, until the brightness of the scanned image under the current PWM signal is the specified brightness.

[0021] In one possible implementation, the method further includes:

[0022] In PWM dimming mode, under the first brightness scenario, a second non-uniform width pulse PWM signal is generated, wherein the second non-uniform width pulse PWM signal includes multiple first type pulses and multiple second type pulses;

[0023] The second non-uniform width pulse PWM signal is used to scan the pixel circuits in each row of the display panel;

[0024] When switching from the first brightness scene to the second brightness scene, a third non-uniform width pulse PWM signal is generated, wherein the third non-uniform width pulse PWM signal includes multiple first type pulses and multiple second type pulses;

[0025] The third non-uniform width pulse PWM signal is used to scan the pixel circuits in each row of the display panel;

[0026] In the first brightness scenario, the brightness of the scanned image is greater than that of the scanned image in the second brightness scenario; the number of second-type pulses in the second non-uniform width pulse PWM signal is less than the number of second-type pulses in the third non-uniform width pulse PWM signal, and the total width of the second-type pulses in the second non-uniform width pulse PWM signal is greater than the total width of the second-type pulses in the third non-uniform width pulse PWM signal.

[0027] Secondly, embodiments of this application provide a display device, the display device including a display panel and a display driver chip:

[0028] The display panel includes a display module, which includes multiple rows of pixels, and each row of pixels includes multiple pixel circuits.

[0029] The display driver chip is used to: generate a non-uniform width pulse PWM signal when switching from DC dimming mode to pulse width modulation (PWM) dimming mode, wherein the non-uniform width pulse PWM signal includes multiple first-type pulses and multiple second-type pulses, both the first-type pulses and the second-type pulses are first-level signals, the pulse width of the first-type pulses is greater than the pulse width of the second-type pulses, and the pulse width of the first-type pulses is not less than the minimum level width for scanning or resetting the pixel circuits in the display panel; and scan the pixel circuits in each pixel row of the display panel using the non-uniform width pulse PWM signal.

[0030] The display module is used to drive the pixel circuits in each pixel row in response to the scanning of the non-uniform width pulse PWM signal.

[0031] In one possible implementation, for each frame of non-uniform width pulse PWM signal, the frame of non-uniform width pulse PWM signal includes at least two sub-timing signals; for each sub-timing signal, the sub-timing signal includes one first type pulse and a plurality of second type pulses.

[0032] In one possible implementation, the pulse width of the first type of pulse is the minimum level width for scanning or resetting the pixel circuit in the display panel, and the pulse width of the second type of pulse is the minimum width required for the timing of the display panel.

[0033] In one possible implementation, the timing of the reset signal, initialization signal, charging signal, and reset compensation signal of the pixel circuit is within the timing of the first type of pulse.

[0034] In one possible implementation,

[0035] The display driver chip is further configured to acquire the number of pulses within each refreshed image frame, the pulse width of the first type of pulses, the pulse width of the second type of pulses, and the timing of the reset signal, initialization signal, charging signal, and reset compensation signal of the pixel circuit; and to determine the number and timing of the first type of pulses based on the timing of the reset signal, initialization signal, charging signal, and reset compensation signal, and the pulse width of the first type of pulses, wherein the timing of the reset signal, initialization signal, charging signal, and reset compensation signal is within the timing of the first type of pulses, and the timing of the first type of pulses is evenly distributed within the time of one image frame. Based on the number and timing of the first type of pulses, an image frame is divided into n sub-timing signals, where n is the number of the first type of pulses. For each sub-timing signal, the sub-timing signal includes one first type of pulse and is located at the timing header of the sub-timing signal. Based on the number of pulses, the number of the first type of pulses, and the pulse width of the second type of pulses, the timing and number of the second type of pulses in each sub-timing signal are determined to obtain the generation parameters of the PWM signal. The generation parameters include the timing of the first type of pulses, the timing and number of the second type of pulses in each sub-timing signal, and the number of segments n of the sub-timing signal.

[0036] The display driver chip is specifically used to generate a non-uniform width pulse PWM signal according to the generation parameters when switching from DC dimming mode to pulse width modulation (PWM) dimming mode.

[0037] In one possible implementation, the display driver chip is further used for:

[0038] According to a preset scanning cycle, the pulse width of the second type of pulse in the non-uniform width pulse PWM signal is increased by a preset width to obtain the current PWM signal; the current PWM signal is used to scan each row of pixel circuits in the display panel; the execution steps are returned: according to a preset scanning cycle, the pulse width of the second type of pulse in the non-uniform width pulse PWM signal is increased, or the pulse width of the first type of pulse and the second type of pulse in the non-uniform width pulse PWM signal is increased to obtain the current PWM signal, until the brightness of the scanned image under the current PWM signal is the specified brightness.

[0039] In one possible implementation, the display driver chip is further used for:

[0040] In PWM dimming mode, under the first brightness scene, a second non-uniform width pulse PWM signal is generated, wherein the second non-uniform width pulse PWM signal includes multiple first-type pulses and multiple second-type pulses; the second non-uniform width pulse PWM signal is used to scan each row of pixel circuits in the display panel; when switching from the first brightness scene to the second brightness scene, a third non-uniform width pulse PWM signal is generated, wherein the third non-uniform width pulse PWM signal includes multiple first-type pulses and multiple second-type pulses; the third non-uniform width pulse PWM signal is used to scan each row of pixel circuits in the display panel; wherein the brightness of the scanned image under the first brightness scene is greater than the brightness of the scanned image under the second brightness scene; the number of second-type pulses in the second non-uniform width pulse PWM signal is less than the number of second-type pulses in the third non-uniform width pulse PWM signal, and the total width of the second-type pulses in the second non-uniform width pulse PWM signal is greater than the total width of the second-type pulses in the third non-uniform width pulse PWM signal.

[0041] Thirdly, embodiments of this application also provide a display panel, the display panel comprising:

[0042] A driving module and a display module, wherein the display module includes multiple rows of pixels, and each row of pixels includes multiple pixel circuits;

[0043] The driving module is used to: generate a non-uniform width pulse PWM signal when switching from DC dimming mode to pulse width modulation (PWM) dimming mode, wherein the non-uniform width pulse PWM signal includes multiple first-type pulses and multiple second-type pulses, both the first-type pulses and the second-type pulses are first-level signals, the pulse width of the first-type pulses is greater than the pulse width of the second-type pulses, and the pulse width of the first-type pulses is not less than the minimum level width for scanning or resetting the pixel circuits in the display panel; and scan the pixel circuits in each pixel row of the display panel using the non-uniform width pulse PWM signal.

[0044] The display module is used to drive the pixel circuits in each pixel row in response to the scanning of the non-uniform width pulse PWM signal.

[0045] Beneficial effects of the embodiments in this application:

[0046] This application provides a display panel driving method, display device, and display panel. The display panel driving method includes: generating a non-uniform width pulse PWM signal when switching from a DC dimming mode to a pulse width modulation (PWM) dimming mode. The non-uniform width pulse PWM signal includes multiple first-type pulses and multiple second-type pulses. Both the first-type pulses and the second-type pulses are first-level signals. The pulse width of the first-type pulses is greater than the pulse width of the second-type pulses, and the pulse width of the first-type pulses is not less than the minimum level width for scanning or resetting the pixel circuits in the display panel. The non-uniform width pulse PWM signal is used to scan each row of pixel circuits in the display panel. By including multiple first-type pulses and multiple second-type pulses in the non-uniform width pulse PWM signal, the duty cycle of PWM dimming can be increased in the case of high-frequency PWM, reducing flickering during switching between high-frequency PWM dimming and DC dimming.

[0047] Of course, implementing any product or method of this application does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0049] Figure 1 This is a schematic diagram of the 7T1C pixel circuit in related technologies;

[0050] Figure 2a This is a schematic diagram of a display panel scan in related technologies;

[0051] Figure 2b This is a schematic diagram of PWM dimming in related technologies;

[0052] Figure 2c This is a schematic diagram of DC dimming in related technologies;

[0053] Figure 3 This is a timing diagram of PWM dimming and DC dimming in related technologies;

[0054] Figure 4a This is a schematic diagram of a first flowchart of a display panel driving method provided in an embodiment of this application;

[0055] Figure 4b A timing diagram of an EM signal for high-frequency non-uniform-width pulse PWM dimming provided in an embodiment of this application;

[0056] Figure 5 This is a second flowchart illustrating the display panel driving method provided in an embodiment of this application;

[0057] Figure 6a This is a third flowchart illustrating the display panel driving method provided in an embodiment of this application;

[0058] Figure 6b This is a schematic diagram showing the switching between high-frequency PWM dimming and DC dimming.

[0059] Figure 6c Another timing diagram of the EM signal for high-frequency non-uniform-width pulse PWM dimming provided in the embodiments of this application;

[0060] Figure 7 A timing diagram of the scanning signal and reset compensation signal for high-frequency non-uniform-width pulse PWM dimming provided in an embodiment of this application;

[0061] Figure 8a This is a schematic diagram of the fourth process of the display panel driving method provided in the embodiments of this application;

[0062] Figure 8b The timing diagrams for PWM dimming in two different scenarios are shown.

[0063] Figure 9 A schematic diagram of the structure of a display device provided in an embodiment of this application;

[0064] Figure 10 This is a schematic diagram of a first structure of a display panel provided in an embodiment of this application;

[0065] Figure 11 This is a schematic diagram of a second structure of the display panel provided in an embodiment of this application. Detailed Implementation

[0066] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of this application.

[0067] First, a brief description of the display device in the related technology is given. The display device in the related technology includes a display panel and a display driver chip. The display panel includes a display module, and the display module includes multiple rows of pixels, each row of pixels including multiple pixel circuits. The display driver chip is used to: generate an equal-width pulse PWM signal (EM signal) in pulse width modulation dimming mode, and use the equal-width pulse PWM signal to scan the pixel circuits in each row of pixels in the display panel; the display driver chip is also used to: generate an EM signal with a high proportion of low levels in DC dimming mode, and use the EM signal to scan the pixel circuits in each row of pixels in the display panel.

[0068] The following is a brief explanation of PWM dimming in related technologies. Due to the current-driven light-emitting principle and characteristics of OLED (Organic Light Emitting Diode), the current is very small at low brightness and low grayscale, resulting in poor color and brightness uniformity, and serious color shift and mura (a phenomenon caused by uneven brightness in displays). To solve these problems, current OLED screens use PWM dimming at low brightness and DC dimming (changing screen brightness by increasing or decreasing the power of the screen panel circuitry) at high brightness. However, traditional low-frequency PWM dimming may have adverse effects on the eyes after prolonged screen viewing. To address this issue, high-frequency PWM solutions have emerged. Generally, the higher the PWM frequency, the less impact it has on the eyes, making it more eye-friendly. With increasing demands and technological advancements, PWM is evolving towards higher frequencies. However, for higher-frequency PWM dimming, the risk of flickering increases when switching between low-frequency PWM dimming and high-brightness DC dimming, requiring optimization.

[0069] To better illustrate the problems with the relevant technologies, some basic concepts will be briefly introduced below:

[0070] GOA signal: GOA stands for Gate Drive On Array, which is a signal used to control the scanning of the gate. Through timing configuration, the scanning time h of each row of pixels, as well as the duration of the porch (blank area) of each frame of image, VBP (Vertical Back Porch, the back shoulder of the vertical sync signal, indicating the number of invalid rows after the vertical sync signal at the beginning of a frame of image) and VFP (Vertical Front Porch, the front shoulder of the vertical sync signal, indicating the number of invalid rows before the vertical sync signal at the end of a frame of image).

[0071] EM (PWM) signal: This is the signal that controls the OLED to turn on. See [link / reference] Figure 1The diagram shows a 7T1C (7 TFTs, Thin Film Transistors, 1 capacitor) pixel circuit. In this circuit, ELVDD is the positive power supply, ELVSS is the negative power supply, Cst is the storage capacitor, Vdata is the data signal, Scan1, Scan2, and Scan3 are the scan signals, and Vref is the reset signal. For each pixel, after charging is complete, the driving TFT (T3 transistor) remains on. At this time, the OLED's on / off state is controlled by the EM signal. DC dimming typically refers to the EM signal remaining on continuously, while PWM dimming refers to the EM signal switching on and off at a set frequency to modulate the pixel brightness.

[0072] The principle of PWM (EM) dimming: Due to the light-emitting principle of OLED driven by current, the process consistency of TFTs of different pixels cannot be guaranteed when the brightness is low, which will lead to problems such as mura and color shift caused by different pixel brightness. Therefore, OLED basically uses PWM dimming when the brightness is low, that is, maintaining a certain TFT driving voltage (current) and adjusting the OLED brightness by the duty cycle of EM signal, which is the so-called bright-dark-bright-dark ratio.

[0073] The scan time (h) per line of a display panel: When a panel is working, it is usually controlled by a DDIC (Display Driver IC) to drive the panel's related GOA, EM, and TFT timings, completing actions such as reset, initialization, charging, and illumination. The scanning of each pixel row is precisely controlled by hardware timing, and the required length of each line can be generated by setting the internal clock of the IC. This length is called the line scan time (h). For example, for a screen with a resolution of 1200×2800×120Hz, assuming the inter-frame porch areas VFP and VBP total 80 h (the actual length can be flexibly set according to different product requirements), then the approximate length of h is h = 1 / 120 / (2800+80) = 2.894µs.

[0074] In current OLED displays, the percentage of time the EM signal is low is generally defined as the EM duty cycle (EM duty), hereinafter referred to as duty. It's important to note that if the OLED screen uses PMOS technology, a high level EM signal corresponds to the OLED being off, and a low level EM signal corresponds to the OLED being on. If the OLED screen uses NMOS (Negative channel-Metal-Oxide-Semiconductor) technology, a high level EM signal corresponds to the OLED being on, and a low level EM signal corresponds to the OLED being off. Currently, OLED screens typically use PMOS technology. PWM (EM) duty cycle calculation: The duration of the high and low levels of PWM is usually calculated using the number of 'h' values. The duration of each EM signal's black insertion (high level, OLED off) is x*h, and the duration of each EM signal's illuminated area (active level) is y*h. Therefore, x + y = total number of pixel rows + VBP + VFP. The EM duty cycle is calculated as: EM illuminated area duration / total frame duration * 100% = 1 - x*h / (total number of pixel rows + VBP + VFP) * h * 100% = 1 - x / (total number of pixel rows + VBP + VFP) * 100%. Figure 2a , Figure 2b and Figure 2c As shown, for example, for a 1200×2800×120Hz screen, assuming a total of 80 hours for VFP and VBP, the EM lighting duty is approximately 1 - (x / (2800+80))×100%. Therefore, the wider the EM signal black insertion within a frame, the smaller the duty and the dimmer the screen brightness, and vice versa. DC dimming range duty can typically reach over 90%, even over 98%. Due to increasingly higher PWM specifications and the use of LTPO, the PWM dimming range duty is becoming increasingly lower.

[0075] OLED screens typically perform line-by-line scanning (including reset, initialization, charging, and emission). For each row of pixels, reset, initialization, and charging are usually completed during the high level of the first EM signal (when no light is emitted). See also Figure 1 The signals used for reset, initialization, and charging operations require several scan operation signals, such as Scan1, Scan2, and Scan3 (it should be noted that there may be 2, 3, 4, or 5 scan signals, depending on the circuit architecture). This necessitates a relatively wide EM signal width to encompass these scan signals within the time frame. Other EM signals outside the scanning / charging range typically only need to meet the minimum requirements of the panel circuit. For example... Figure 3As shown, EM-1 is the DC EM signal waveform in the high-brightness range, and EM-2 is the PWM EM signal waveform in the low-brightness range. The first EM pulse duration is required to be relatively long. In related technologies, PWM dimming typically sets the high level of all EM signals to be approximately consistent with the first one. This is because during actual duty adjustment, there are certain regular fine adjustments to the width of some EM high levels. Taking 12 pulses (12 pulses) at 120Hz as an example, if one step is adjusted to 4h, this 4h is usually added to the first EM high level, making the first EM high level 4h longer than the others. If 8h is adjusted, it is usually added to the first and seventh EM high levels, making the width of the first and seventh EM high levels slightly wider. The increased EM high level duration is usually distributed as evenly as possible across the 12 pulses in terms of time and scan space. Therefore, the high level of the EM signal is approximately consistent with the first EM high level, with minimal difference and no noticeably wider EM pulses. This setup is relatively simple to implement and easy to control logically. However, with the improvement of high-frequency PWM specifications, such as 2160Hz and 3840Hz, and the implementation of new LTPO schemes (with a reset in the middle holding area and a limited EM width), or the reduction in vertical resolution of certain special products, the duty cycle of PWM dimming decreases accordingly. DC dimming typically has a high duty cycle at high brightness. If the high-frequency PWM dimming duty cycle is too small, the risk of flickering increases when switching between DC and PWM dimming during the dimming process. Alternatively, in certain low-frequency PWM dimming scenarios, the proportion of high-level EM signals is smaller compared to high-frequency PWM dimming. Therefore, the duty cycle of low-frequency PWM dimming is larger than that of high-frequency PWM dimming. When switching between them, the large difference in duty cycle can also cause severe flickering problems.

[0076] For example, see Figure 3 If DC dimming is a 1-pulse PWM and PWM dimming is a 4-pulse PWM, with each PWM black insertion width of 40 hours, the duration of one frame is 2800 + 80 = 2880 hours. Then, the duty cycle of the 4-pulse PWM dimming is 1 - (40 * 4 / 2880) * 100% = 94.4%, and the duty cycle of the DC dimming is 1 - (40 * 1 / 2880) * 100% = 98.6%. The difference between the two is very small, and the flickering during switching is weak. If the PWM dimming becomes 32 pulses (or possibly higher), then the PWM dimming duty cycle becomes 1 - (40 * 32 / 2800) * 100% = 55.6%, while the DC dimming duty cycle remains at 98.6%. In this case, the flickering problem during switching becomes more severe.

[0077] To improve the duty cycle of high-frequency PWM dimming and reduce flickering during switching between high-frequency PWM dimming and DC dimming / low-frequency PWM dimming, this application provides a display panel driving method. (See also...) Figure 4a This includes the following steps:

[0078] Step S401: When switching from DC dimming mode to pulse width modulation (PWM) dimming mode, a non-uniform width pulse PWM signal is generated. The non-uniform width pulse PWM signal includes multiple first-type pulses and multiple second-type pulses. Both the first-type pulses and the second-type pulses are first-level signals. The pulse width of the first-type pulses is greater than the pulse width of the second-type pulses, and the pulse width of the first-type pulses is not less than the minimum level width of the pixel circuit scanning or resetting in the display panel.

[0079] Referring to the description in the aforementioned related technologies, if the OLED screen uses PMOS technology, the first level signal in step S401 is a high-level signal; if the OLED screen uses NMOS technology, the first level signal in step S401 is a low-level signal. Examples and descriptions in subsequent embodiments are based on the OLED screen using PMOS technology, and this will not be further elaborated in subsequent embodiments.

[0080] In one example, see Figure 4b EM-3 is a schematic diagram of the EM signal waveform of low-frequency PWM dimming in related technologies, and EM-4 is a schematic diagram of the EM signal waveform of high-frequency non-equal width pulse PWM dimming provided in the embodiments of this application (taking the OLED screen using PMOS process as an example). Figure 4b In this context, EM-4 can be a 32-pulse high-frequency PWM timing sequence. The first and 17th EM pulses can be Type I pulses, which can be high-level signals. The pulse width of the Type I pulses is not less than the minimum level width for pixel circuit scanning or reset in the display panel. In one example, the minimum level width can be 80h, which can be flexibly set according to the actual display panel product. The other 30 EM pulses can be Type II pulses, which can be high-level signals.

[0081] Step S402: Use the non-uniform width pulse PWM signal to scan the pixel circuits in each row of the display panel.

[0082] In the embodiments of this application, by including multiple first-type pulses and multiple second-type pulses in the non-equal-width pulse PWM signal, the duty cycle of PWM dimming can be improved in the case of high-frequency PWM.

[0083] In one possible implementation, for each frame of non-uniform width pulse PWM signal, the frame of non-uniform width pulse PWM signal includes at least two sub-timing signals; for each sub-timing signal, the sub-timing signal includes one first type pulse and a plurality of second type pulses.

[0084] In one example, see Figure 4b Each frame of non-equal width pulse PWM signal can include two sub-timing signals, and each sub-timing signal can include one first type pulse and 16 second type pulses.

[0085] In one possible implementation, the pulse width of the first type of pulse is the minimum level width for scanning or resetting the pixel circuit in the display panel, and the pulse width of the second type of pulse is the minimum width required for the timing of the display panel.

[0086] In one example, see Figure 4b The pulse width of the first and 17th EM pulses can be 80h, 85h, or 75h, depending on the specific product. The pulse width of the other 30 EM pulses can be 16h, 4h, 8h, etc., also depending on the specific product. It should be noted that the above examples are for the first and second type pulse widths at their minimum (i.e., the brightest state when PWM dimming is applied).

[0087] In one possible implementation, see Figure 5 ,based on Figure 4a The display panel driving method further includes the following steps:

[0088] Step S501: According to the preset scanning period, the pulse width of the second type of pulse in the non-equal width pulse PWM signal is increased by a preset width to obtain the current PWM signal.

[0089] Step S502: Scan each row of pixel circuits in the display panel using the current PWM signal.

[0090] Step S503: Return to step S501: Increase the pulse width of the second type of pulse in the non-equal width pulse PWM signal according to the preset scanning cycle, or increase the pulse width of the first type of pulse and the second type of pulse in the non-equal width pulse PWM signal to obtain the current PWM signal, until the brightness of the scanned image under the current PWM signal is the specified brightness.

[0091] PWM dimming typically operates within the duty cycle. As brightness decreases, the high level of the second type of pulse gradually increases. Generally, at the lowest brightness level, such as 2 nits, the duty cycle drops to around 10%. At this point, all second-type pulses may have the same width as the first type of pulse, such as 1 - 80*32 / 2880 = 16.67%. That is, in the low-brightness range of high-frequency PWM dimming, the first and second types of pulses may reach the same or similar widths. After the first and second types of pulses reach the same or similar widths, the brightness continues to decrease. These two types of pulses can be considered as one type. As brightness is adjusted, the EM width is adjusted in minimum steps (e.g., increasing by 4 hours each time).

[0092] During PWM dimming, as brightness decreases, EM duty decreases accordingly. The widths of Type I and Type II pulses increase according to certain rules, such as in panel (display panel) design, where the duration increases by 4 hours each time. The increased EMs are distributed as evenly as possible across each EM at the duration position. This way, at lower brightness, the widths of Type I and Type II pulses may be the same or approximately the same width; this is not fixed. In one example, as brightness decreases, at a certain state, the widths of both Type I and Type II pulses reach 80 hours. At this point, EM duty = 1 - (80 * 32) / 2880 * 100% = 11.11%. Of course, if the minimum width of Type I pulses is 70 hours or lower, or if the EM pulse number is relatively small, when the widths of Type I and Type II pulses reach the same value, the duty is still high, such as 30%. Then, as brightness decreases, the duty will continue to decrease, meaning the EM width continues to increase in 4-hour steps (intervals). In this case, the widths of Type I and Type II pulses will exceed the originally set 70 hours.

[0093] In one possible implementation, the timing of the reset signal, initialization signal, charging signal, and reset compensation signal of the pixel circuit is within the timing of the first type of pulse.

[0094] In one possible implementation, see Figure 6a ,based on Figure 4a The display panel driving method further includes the following steps:

[0095] Step S601: Obtain the number of pulses in each refreshed image frame, the pulse width of the first type of pulse, the pulse width of the second type of pulse, and the timing of the reset signal, initialization signal, charging signal, and reset compensation signal of the pixel circuit.

[0096] Step S602: Determine the number and timing of the first type of pulses based on the timing of the reset signal, initialization signal, charging signal, and reset compensation signal, and the pulse width of the first type of pulses. The timing of the reset signal, initialization signal, charging signal, and reset compensation signal is within the timing of the first type of pulses, and the timing of the first type of pulses is evenly distributed within the time of one image frame.

[0097] Step S603: According to the number and timing of the first type of pulses, a frame of image is divided into n sub-time signals, where n is the number of the first type of pulses. For each sub-time signal, the sub-time signal includes one first type of pulse and is located at the timing header of the sub-time signal.

[0098] Step S604: Based on the number of pulses, the number of the first type of pulses, and the pulse width of the second type of pulses, determine the timing and number of the second type of pulses in each segment of the sub-timing signal to obtain the generation parameters of the PWM signal; wherein, the generation parameters include the timing of the first type of pulses, the timing and number of the second type of pulses in each segment of the sub-timing signal, and the number of segments n of the sub-timing signal.

[0099] Step S605: When switching from DC dimming mode to pulse width modulation (PWM) dimming mode, a non-uniform width pulse PWM signal is generated according to the generation parameters.

[0100] In one example, based on the description of the calculation method of PWM dimming duty cycle in the aforementioned related technologies, it is still based on... Figure 4bTo illustrate, each frame of the PWM signal can be divided into two sub-timing signals. Each sub-timing signal can include one type-1 pulse and 16 type-2 pulses, with the type-1 pulse located at the beginning of the timing sequence. Therefore, EM-4 can be a 32-pulse high-frequency PWM timing sequence. The high-level widths of the first and seventeenth EM pulses are set to the minimum level width required for pixel circuit scanning, which can be 80h. The high-level widths of the other 30 EM pulses are set to the minimum width required for the display panel timing, which can be 16h. Taking a frame with a total duration of 2900 hours as an example, the duty cycle is 1 - (80*2 / 2900)*100% = 94.5% during high-brightness DC dimming, and 1 - {(80*2+16*30) / 2900}*100% = 77.9% during low-brightness high-frequency PWM dimming. According to the low-brightness high-frequency PWM dimming method described in the aforementioned related technologies, the calculated duty cycle is 1 - {(40*32) / 2900}*100% = 55.9%. It can be seen that the non-uniform pulse PWM signal provided in this application embodiment can improve the lighting duty cycle, reducing the difference between the duty cycle and the high-brightness DC dimming during switching, and can reduce the flickering problem during the switching between high-frequency PWM dimming and DC dimming. A schematic diagram of the high-frequency PWM dimming and DC dimming switching is shown below. Figure 6b As shown, nit, or nit, is the unit of display brightness. Similarly, this can also reduce flickering issues when switching between high-frequency PWM dimming and low-frequency PWM dimming.

[0101] In one example, for Figure 4b The non-uniform width pulse PWM signal shown can also be set to be equally spaced in two segments, that is, each frame of PWM signal is divided into two sub-timing signals. For example, it can be 2 pulses for high brightness DC dimming, and 24, 30, or 36 pulses for low brightness high frequency PWM dimming. The high-level width of the first EM pulse and the high-level width of the (24 / 3)*n+1, (30 / 3)*n+1, and (36 / 3)*n+1 (n=1, 2, 3…) EM pulses can be set to the minimum level width required for pixel scanning, and the high-level width of other EM pulses can be set to the minimum width required for the timing of the display panel. Similarly, it can also be set to 4, 5, 6, etc., according to actual needs. This application does not make specific limitations on this.

[0102] It should be noted that, Figure 4b This is just an illustration. In reality, at different refresh rates, the first type of pulse can also extend with equal periods within the same base frequency of 120Hz. For example, within 120Hz, there are 2 equal-period first type pulses, and within 60Hz, there are 4 equal-period first type pulses. Figure 6c As shown, other refresh rates are similar.

[0103] Setting a non-uniform-width PWM signal can also be well integrated with LTPO scanning and reset compensation, reducing the duty cycle of high-frequency PWM while meeting the timing requirements for reset and compensation in non-scanning regions. For example, some LTPS (Low Temperature Poly-Silicon) or LTPO use 8T1C (8 TFTs, 1 capacitor) pixel circuits. After charging is complete, there will be a pair of T3 transistors (same here) in the hold interval. Figure 1 The reset compensation operation of the 7T1C pixel circuit shown also requires a certain period of EM high level. Using a non-uniform width PWM signal setting allows the reset compensation operation to occur during these wider EM high levels. For example... Figure 7 As shown, the scanning action is completed in the first width and height level EM of each sub-timing, while the reset compensation can be performed in the equally divided width and height level EM of the holding interval.

[0104] In the above embodiments, the non-uniform width pulse PWM signal settings distribute the wider EM pulses at equal intervals in the time domain according to a certain period. This can be well integrated with some OLED operations that require reset and compensation during the hold interval. In addition, the wider EM pulses can also be adjusted to unequal intervals according to actual needs. This allows for the distribution of wide-level EM pulses in different frequency domains, dispersing the frequency domain energy of black bars, which is beneficial for eye protection.

[0105] This application also provides a display panel driving method, see [link to relevant documentation]. Figure 8a This includes the following steps:

[0106] Step S801: In PWM dimming mode, under the first brightness scenario, a second non-uniform width pulse PWM signal is generated, wherein the second non-uniform width pulse PWM signal includes multiple first type pulses and multiple second type pulses;

[0107] Step S802: Use the second non-uniform width pulse PWM signal to scan the pixel circuits in each row of the display panel;

[0108] Step S803: When switching from the first brightness scene to the second brightness scene, a third non-uniform width pulse PWM signal is generated, wherein the third non-uniform width pulse PWM signal includes multiple first type pulses and multiple second type pulses;

[0109] Step S804: Use the third non-uniform width pulse PWM signal to scan the pixel circuits in each row of the display panel;

[0110] In the first brightness scenario, the brightness of the scanned image is greater than that of the scanned image in the second brightness scenario; the number of second-type pulses in the second non-uniform width pulse PWM signal is less than the number of second-type pulses in the third non-uniform width pulse PWM signal, and the total width of the second-type pulses in the second non-uniform width pulse PWM signal is greater than the total width of the second-type pulses in the third non-uniform width pulse PWM signal.

[0111] Non-uniform width EM settings, besides being used for high / low brightness DC and high-frequency PWM switching, can also be applied to different scenarios with different PWM pulse configurations. In one example, special scenario 1 (which could be AOD, i.e., Always On Display) uses 8 pulses, and normal display scenario 2 uses 32 pulses. In this case, both scenario 1 and scenario 2 use non-uniform width EM settings, such as... Figure 8b As shown, this can also effectively reduce the duty difference when switching between the two scenes using PWM dimming, thus reducing switching flicker.

[0112] This application also provides a display device, see [link to relevant documentation] Figure 9 The display device includes a display panel 1 and a display driver chip 2.

[0113] The display panel 1 includes a display module 12, which includes multiple rows of pixel rows 121, and each row of pixel rows 121 includes multiple pixel circuits 1211.

[0114] The display driver chip 2 is used to: generate a non-uniform width pulse PWM signal when switching from DC dimming mode to pulse width modulation (PWM) dimming mode, wherein the non-uniform width pulse PWM signal includes multiple first-type pulses and multiple second-type pulses, both the first-type pulses and the second-type pulses are first-level signals, the pulse width of the first-type pulses is greater than the pulse width of the second-type pulses, and the pulse width of the first-type pulses is not less than the minimum level width for scanning or resetting the pixel circuits in the display panel; and scan the pixel circuits 1211 in each pixel row 121 of the display panel using the non-uniform width pulse PWM signal.

[0115] The specific analysis is the same as above, and will not be repeated here.

[0116] The display module 12 is used to drive the pixel circuits 1211 in each pixel row 121 in response to the scanning of the non-uniform width pulse PWM signal.

[0117] The specific analysis is the same as above, and will not be repeated here.

[0118] The display panel is used to receive the timing of the non-uniform width pulse PWM signal generated by the display driver chip. Through its own driving circuit, it completes the timing scanning and transmission of each row of pixels, realizing the timing control and driving of the non-uniform width pulse.

[0119] In the embodiments of this application, by including multiple first-type pulses and multiple second-type pulses in the non-equal-width pulse PWM signal, the duty cycle of PWM dimming can be improved in the case of high-frequency PWM.

[0120] In one possible implementation, for each frame of non-uniform width pulse PWM signal, the frame of non-uniform width pulse PWM signal includes at least two sub-timing signals; for each sub-timing signal, the sub-timing signal includes one first type pulse and a plurality of second type pulses.

[0121] The specific analysis is the same as above, and will not be repeated here.

[0122] In one possible implementation, the pulse width of the first type of pulse is the minimum level width for scanning or resetting the pixel circuit in the display panel, and the pulse width of the second type of pulse is the minimum width required for the timing of the display panel.

[0123] The specific analysis is the same as above, and will not be repeated here.

[0124] In one possible implementation, the timing of the reset signal, initialization signal, charging signal, and reset compensation signal of the pixel circuit is within the timing of the first type of pulse.

[0125] The specific analysis is the same as above, and will not be repeated here.

[0126] In one possible implementation,

[0127] The display driver chip 2 is further configured to acquire the number of pulses within each refreshed image frame, the pulse width of the first type of pulses, the pulse width of the second type of pulses, and the timing of the reset signal, initialization signal, charging signal, and reset compensation signal of the pixel circuit; and to determine the number and timing of the first type of pulses based on the timing of the reset signal, initialization signal, charging signal, and reset compensation signal, and the pulse width of the first type of pulses, wherein the timing of the reset signal, initialization signal, charging signal, and reset compensation signal is within the timing of the first type of pulses, and the timing of the first type of pulses is uniform within the time of one image frame. Arrangement: Based on the number and timing of the first type of pulses, a frame of image is divided into n sub-timing signals, where n is the number of the first type of pulses. For each sub-timing signal, the sub-timing signal includes one first type of pulse and is located at the timing header of the sub-timing signal. Based on the number of pulses, the number of the first type of pulses, and the pulse width of the second type of pulses, the timing and number of the second type of pulses in each sub-timing signal are determined to obtain the generation parameters of the PWM signal. The generation parameters include the timing of the first type of pulses, the timing and number of the second type of pulses in each sub-timing signal, and the number of segments n of the sub-timing signal.

[0128] The specific analysis is the same as above, and will not be repeated here.

[0129] Examples of settings in the display driver chip are as follows: 1. Set the number of EM Pulses according to the specifications, such as 12Pulse, 16Pulse, 24Pulse, 32Pulse, etc.

[0130] 2. Based on the resolution and porch time, the total PWM timing duration is determined by manually estimating the maximum EM duty, such as 66.67% in the above embodiment, and setting the corresponding parameters; and setting the duty adjustment rules (the minimum number of steps to increase, such as 4h, 8h, etc., evenly distributed in different Pulses), and outputting them to the display panel's own drive circuit.

[0131] 3. Output scan-related signals according to the expected timing, ensuring that the scan-related signals are within the expected EM high level, such as within the first EM high level.

[0132] The display driver chip 2 is specifically used to generate a non-uniform width pulse PWM signal according to the generation parameters when switching from DC dimming mode to pulse width modulation (PWM) dimming mode.

[0133] The specific analysis is the same as above, and will not be repeated here.

[0134] In one possible implementation, the display driver chip 2 is further used for:

[0135] According to a preset scanning cycle, the pulse width of the second type of pulse in the non-uniform width pulse PWM signal is increased by a preset width to obtain the current PWM signal; the current PWM signal is used to scan each row of pixel circuits in the display panel; the execution steps are returned: according to a preset scanning cycle, the pulse width of the second type of pulse in the non-uniform width pulse PWM signal is increased, or the pulse width of the first type of pulse and the second type of pulse in the non-uniform width pulse PWM signal is increased to obtain the current PWM signal, until the brightness of the scanned image under the current PWM signal is the specified brightness.

[0136] The specific analysis is the same as above, and will not be repeated here.

[0137] The display driver chip is used to generate non-uniform width pulse PWM signals and control the pulse width variation rules in the PWM signals caused by corresponding duty changes.

[0138] In one possible implementation, the display driver chip 2 is further used for:

[0139] In PWM dimming mode, under the first brightness scene, a second non-uniform width pulse PWM signal is generated, wherein the second non-uniform width pulse PWM signal includes multiple first-type pulses and multiple second-type pulses; the second non-uniform width pulse PWM signal is used to scan each row of pixel circuits in the display panel; when switching from the first brightness scene to the second brightness scene, a third non-uniform width pulse PWM signal is generated, wherein the third non-uniform width pulse PWM signal includes multiple first-type pulses and multiple second-type pulses; the third non-uniform width pulse PWM signal is used to scan each row of pixel circuits in the display panel; wherein the brightness of the scanned image under the first brightness scene is greater than the brightness of the scanned image under the second brightness scene; the number of second-type pulses in the second non-uniform width pulse PWM signal is less than the number of second-type pulses in the third non-uniform width pulse PWM signal, and the total width of the second-type pulses in the second non-uniform width pulse PWM signal is greater than the total width of the second-type pulses in the third non-uniform width pulse PWM signal.

[0140] The specific analysis is the same as above, and will not be repeated here.

[0141] This application embodiment also provides a display panel 3, see [link] Figure 10 The display panel 3 includes:

[0142] The driving module 31 and the display module 32 are included. The display module 32 includes multiple rows of pixel rows 321, and each row of pixel rows 321 includes multiple pixel circuits 3211.

[0143] The driving module 31 is used to: generate a non-uniform width pulse PWM signal when switching from DC dimming mode to pulse width modulation (PWM) dimming mode, wherein the non-uniform width pulse PWM signal includes multiple first-type pulses and multiple second-type pulses, both the first-type pulses and the second-type pulses are first-level signals, the pulse width of the first-type pulses is greater than the pulse width of the second-type pulses, and the pulse width of the first-type pulses is not less than the minimum level width for scanning or resetting the pixel circuits in the display panel; and scan the pixel circuits 3211 in each pixel row 321 of the display panel using the non-uniform width pulse PWM signal.

[0144] The display module 32 is used to drive the pixel circuits 3211 in each pixel row 321 in response to the scanning of the non-uniform width pulse PWM signal.

[0145] In one possible implementation, see Figure 11 The display panel 3 further includes:

[0146] The drive configuration module 33 is used to acquire the number of pulses in each refreshed image frame, the pulse width of the first type of pulses, the pulse width of the second type of pulses, and the timing of the reset signal, initialization signal, charging signal, and reset compensation signal of the pixel circuit; based on the timing of the reset signal, initialization signal, charging signal, and reset compensation signal, and the pulse width of the first type of pulses, it determines the number and timing of the first type of pulses, wherein the timing of the reset signal, initialization signal, charging signal, and reset compensation signal is within the timing of the first type of pulses, and the timing of the first type of pulses is evenly distributed within the time of one image frame. Based on the number and timing of the first type of pulses, an image frame is divided into n sub-timing signals, where n is the number of the first type of pulses. For each sub-timing signal, the sub-timing signal includes one first type of pulse and is located at the timing header of the sub-timing signal. Based on the number of pulses, the number of the first type of pulses, and the pulse width of the second type of pulses, the timing and number of the second type of pulses in each sub-timing signal are determined to obtain the generation parameters of the PWM signal. The generation parameters include the timing of the first type of pulses, the timing and number of the second type of pulses in each sub-timing signal, and the number of segments n of the sub-timing signal.

[0147] The driving module 31 is specifically used to generate a non-uniform width pulse PWM signal according to the generation parameters when switching from DC dimming mode to pulse width modulation (PWM) dimming mode.

[0148] In one possible implementation, the drive module 31 is further configured to:

[0149] According to a preset scanning cycle, the pulse width of the second type of pulse in the non-uniform width pulse PWM signal is increased by a preset width to obtain the current PWM signal; the current PWM signal is used to scan each row of pixel circuits in the display panel; the execution steps are returned: according to a preset scanning cycle, the pulse width of the second type of pulse in the non-uniform width pulse PWM signal is increased, or the pulse width of the first type of pulse and the second type of pulse in the non-uniform width pulse PWM signal is increased to obtain the current PWM signal, until the brightness of the scanned image under the current PWM signal is the specified brightness.

[0150] In this embodiment, the display panel can generate a constant-width pulse PWM signal through its own driving module, and can set the number of EM pulses and the width of EM pulses in different frames through its own driving configuration module.

[0151] In one possible implementation, the drive module 31 is further configured to:

[0152] In PWM dimming mode, under the first brightness scene, a second non-uniform width pulse PWM signal is generated, wherein the second non-uniform width pulse PWM signal includes multiple first-type pulses and multiple second-type pulses; the second non-uniform width pulse PWM signal is used to scan each row of pixel circuits in the display panel; when switching from the first brightness scene to the second brightness scene, a third non-uniform width pulse PWM signal is generated, wherein the third non-uniform width pulse PWM signal includes multiple first-type pulses and multiple second-type pulses; the third non-uniform width pulse PWM signal is used to scan each row of pixel circuits in the display panel; wherein the brightness of the scanned image under the first brightness scene is greater than the brightness of the scanned image under the second brightness scene; the number of second-type pulses in the second non-uniform width pulse PWM signal is less than the number of second-type pulses in the third non-uniform width pulse PWM signal, and the total width of the second-type pulses in the second non-uniform width pulse PWM signal is greater than the total width of the second-type pulses in the third non-uniform width pulse PWM signal.

[0153] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0154] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0155] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A display panel driving method, characterized in that, The method includes: The system obtains the number of pulses in each refreshed image frame, the pulse width of the first type of pulse, the pulse width of the second type of pulse, and the timing of the reset signal, initialization signal, charging signal, and reset compensation signal of the pixel circuit. Based on the timing of the reset signal, initialization signal, charging signal and reset compensation signal and the pulse width of the first type of pulse, the number and timing of the first type of pulse are determined, wherein the timing of the reset signal, initialization signal, charging signal and reset compensation signal is within the timing of the first type of pulse, and the timing of the first type of pulse is evenly distributed within the time of one image frame. Based on the number and timing of the first type of pulses, an image frame is divided into n sub-time signals, where n is the number of the first type of pulses. For each sub-time signal, the sub-time signal includes one first type of pulse and is located at the timing header of the sub-time signal. Based on the number of pulses, the number of the first type of pulses, and the pulse width of the second type of pulses, the timing and number of the second type of pulses in each segment of the sub-timing signal are determined to obtain the generation parameters of the PWM signal; wherein, the generation parameters include the timing of the first type of pulses, the timing and number of the second type of pulses in each segment of the sub-timing signal, and the number of segments n of the sub-timing signal; When switching from DC dimming mode to pulse width modulation (PWM) dimming mode, a non-uniform width pulse PWM signal is generated according to the generation parameters. The non-uniform width pulse PWM signal includes multiple first-type pulses and multiple second-type pulses. Both the first-type pulses and the second-type pulses are first-level signals. The pulse width of the first-type pulses is greater than the pulse width of the second-type pulses, and the pulse width of the first-type pulses is not less than the minimum level width of the pixel circuit scanning or reset in the display panel. The non-uniform width pulse PWM signal is used to scan the pixel circuits in each row of the display panel.

2. The method according to claim 1, characterized in that, For each frame of non-uniform width pulse PWM signal, the frame of non-uniform width pulse PWM signal includes at least two sub-timing signals; for each sub-timing signal, the sub-timing signal includes one first type pulse and multiple second type pulses.

3. The method according to claim 1, characterized in that, The pulse width of the first type of pulse is the minimum level width for scanning or resetting the pixel circuit in the display panel, and the pulse width of the second type of pulse is the minimum width required for the timing of the display panel.

4. The method according to claim 1, characterized in that, The timing of the reset signal, initialization signal, charging signal, and reset compensation signal of the pixel circuit is within the timing of the first type of pulse.

5. The method according to claim 1, characterized in that, After scanning each row of pixel circuits in the display panel using the non-uniform width pulse PWM signal, the method further includes: According to a preset scanning cycle, the pulse width of the second type of pulse in the non-equal width pulse PWM signal is increased by a preset width to obtain the current PWM signal; The current PWM signal is used to scan the pixel circuits of each row in the display panel; Return to execution steps: According to the preset scanning cycle, increase the pulse width of the second type of pulse in the non-uniform width pulse PWM signal, or increase the pulse width of the first type of pulse and the second type of pulse in the non-uniform width pulse PWM signal to obtain the current PWM signal, until the brightness of the scanned image under the current PWM signal is the specified brightness.

6. The method according to claim 1, characterized in that, The method further includes: In PWM dimming mode, under the first brightness scenario, a second non-uniform width pulse PWM signal is generated, wherein the second non-uniform width pulse PWM signal includes multiple first type pulses and multiple second type pulses; The second non-uniform width pulse PWM signal is used to scan the pixel circuits in each row of the display panel; When switching from the first brightness scene to the second brightness scene, a third non-uniform width pulse PWM signal is generated, wherein the third non-uniform width pulse PWM signal includes multiple first type pulses and multiple second type pulses; The third non-uniform width pulse PWM signal is used to scan the pixel circuits in each row of the display panel; In the first brightness scenario, the brightness of the scanned image is greater than that of the scanned image in the second brightness scenario; the number of second-type pulses in the second non-uniform width pulse PWM signal is less than the number of second-type pulses in the third non-uniform width pulse PWM signal, and the total width of the second-type pulses in the second non-uniform width pulse PWM signal is greater than the total width of the second-type pulses in the third non-uniform width pulse PWM signal.

7. A display device, characterized in that, The display device includes a display panel and a display driver chip: The display panel includes a display module, which includes multiple rows of pixels, and each row of pixels includes multiple pixel circuits. The display driver chip is used to: acquire the number of pulses, the pulse width of the first type of pulse, and the pulse width of the second type of pulse within each refreshed image frame; acquire the timing of the reset signal, initialization signal, charging signal, and reset compensation signal of the pixel circuit; determine the number and timing of the first type of pulse based on the timing of the reset signal, initialization signal, charging signal, and reset compensation signal, and the pulse width of the first type of pulse, wherein the timing of the reset signal, initialization signal, charging signal, and reset compensation signal is within the timing of the first type of pulse, and the timing of the first type of pulse is evenly distributed within the time of one image frame; divide one image frame into n sub-timing signals based on the number and timing of the first type of pulse, where n is the number of the first type of pulse, and for each sub-timing signal, the sub-timing signal includes one first type of pulse and is located at the timing header of the sub-timing signal; based on the number of pulses, the first type of pulse, and the pulse width of the second type of pulse, determine the number and timing of the first type of pulse. The number of first-type pulses and the pulse width of the second-type pulses are used to determine the timing and number of second-type pulses in each segment of the sub-timing signal, thus obtaining the generation parameters of the PWM signal. The generation parameters include the timing of the first-type pulses, the timing and number of the second-type pulses in each segment of the sub-timing signal, and the number of segments n of the sub-timing signal. When switching from DC dimming mode to pulse width modulation (PWM) dimming mode, a non-uniform width pulse PWM signal is generated according to the generation parameters. This non-uniform width pulse PWM signal includes multiple first-type pulses and multiple second-type pulses. Both the first-type pulses and the second-type pulses are first-level signals. The pulse width of the first-type pulses is greater than the pulse width of the second-type pulses, and the pulse width of the first-type pulses is not less than the minimum level width for scanning or resetting the pixel circuits in the display panel. The non-uniform width pulse PWM signal is used to scan the pixel circuits in each pixel row of the display panel. The display module is used to drive the pixel circuits in each pixel row in response to the scanning of the non-uniform width pulse PWM signal.

8. The display device according to claim 7, characterized in that, For each frame of non-uniform width pulse PWM signal, the frame of non-uniform width pulse PWM signal includes at least two sub-timing signals; for each sub-timing signal, the sub-timing signal includes one first type pulse and multiple second type pulses.

9. The display device according to claim 7, characterized in that, The pulse width of the first type of pulse is the minimum level width for scanning or resetting the pixel circuit in the display panel, and the pulse width of the second type of pulse is the minimum width required for the timing of the display panel.

10. The display device according to claim 7, characterized in that, The timing of the reset signal, initialization signal, charging signal, and reset compensation signal of the pixel circuit is within the timing of the first type of pulse.

11. The display device according to claim 7, characterized in that, The display driver chip is also used for: According to a preset scanning cycle, the pulse width of the second type of pulse in the non-uniform width pulse PWM signal is increased by a preset width to obtain the current PWM signal; the current PWM signal is then used to scan the pixel circuits in each row of the display panel. Return to execution steps: According to the preset scanning cycle, increase the pulse width of the second type of pulse in the non-uniform width pulse PWM signal, or increase the pulse width of the first type of pulse and the second type of pulse in the non-uniform width pulse PWM signal to obtain the current PWM signal, until the brightness of the scanned image under the current PWM signal is the specified brightness.

12. The display device according to claim 7, characterized in that, The display driver chip is also used for: In PWM dimming mode, under the first brightness scene, a second non-uniform width pulse PWM signal is generated, wherein the second non-uniform width pulse PWM signal includes multiple first-type pulses and multiple second-type pulses; the second non-uniform width pulse PWM signal is used to scan each row of pixel circuits in the display panel; when switching from the first brightness scene to the second brightness scene, a third non-uniform width pulse PWM signal is generated, wherein the third non-uniform width pulse PWM signal includes multiple first-type pulses and multiple second-type pulses; the third non-uniform width pulse PWM signal is used to scan each row of pixel circuits in the display panel; wherein the brightness of the scanned image under the first brightness scene is greater than the brightness of the scanned image under the second brightness scene; the number of second-type pulses in the second non-uniform width pulse PWM signal is less than the number of second-type pulses in the third non-uniform width pulse PWM signal, and the total width of the second-type pulses in the second non-uniform width pulse PWM signal is greater than the total width of the second-type pulses in the third non-uniform width pulse PWM signal.

13. A display panel, characterized in that, The display panel includes: The system includes a configuration module, a driver module, and a display module. The display module includes multiple rows of pixels, and each row of pixels includes multiple pixel circuits. The drive configuration module is used to: obtain the number of pulses, the pulse width of the first type of pulse, and the pulse width of the second type of pulse within each refreshed image frame; and obtain the timing of the reset signal, initialization signal, charging signal, and reset compensation signal of the pixel circuit; and determine the number and timing of the first type of pulse based on the timing of the reset signal, initialization signal, charging signal, and reset compensation signal, and the pulse width of the first type of pulse, wherein the timing of the reset signal, initialization signal, charging signal, and reset compensation signal is within the timing of the first type of pulse, and the timing of the first type of pulse is evenly distributed within the time of one image frame; Based on the number and timing of the first type of pulses, an image frame is divided into n sub-timing signals, where n is the number of the first type of pulses. For each sub-timing signal, the sub-timing signal includes one first type of pulse and is located at the timing header of the sub-timing signal. Based on the number of pulses, the number of the first type of pulses, and the pulse width of the second type of pulses, the timing and number of the second type of pulses in each sub-timing signal are determined to obtain the generation parameters of the PWM signal. The generation parameters include the timing of the first type of pulses, the timing and number of the second type of pulses in each sub-timing signal, and the number of segments n of the sub-timing signal. The driving module is used to: when switching from DC dimming mode to pulse width modulation (PWM) dimming mode, generate a non-uniform width pulse PWM signal according to the generation parameters, wherein the non-uniform width pulse PWM signal includes multiple first-type pulses and multiple second-type pulses, both the first-type pulses and the second-type pulses are first-level signals, the pulse width of the first-type pulses is greater than the pulse width of the second-type pulses, and the pulse width of the first-type pulses is not less than the minimum level width for scanning or resetting the pixel circuits in the display panel; and scan the pixel circuits in each pixel row of the display panel using the non-uniform width pulse PWM signal. The display module is used to drive the pixel circuits in each pixel row in response to the scanning of the non-uniform width pulse PWM signal.

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