Wafer level packaging method and wafer packaging structure
CN119275116APending Publication Date: 2025-01-07ENOVATE3D (HANGZHOU) TECH DEV CO LTD
Patent Information
- Application Number
- CN202411371245.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-29
- Publication Date
- 2025-01-07
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Figure CN119275116A_ABST
Abstract
The invention relates to a wafer level packaging method and a wafer packaging structure. The wafer level packaging method comprises the steps that a wafer is provided, a chip is arranged on the wafer, and the chip is provided with a functional area; forming a supporting box dam layer on the surface of one side of the wafer; the supporting box dam layer surrounds the functional area to form a closed structure; forming an adhesive box dam layer on the surface of one side of the wafer; the adhesion box dam layer is located on the side face of the side, back to the functional area, of the supporting box dam layer, and the height of the adhesion box dam layer is larger than that of the supporting box dam layer; providing a cover plate, and arranging the cover plate on one side, opposite to the wafer, of the supporting box dam layer; pressing the cover plate and the wafer; the adhesion box dam layer adheres to the side face of the supporting box dam layer and fills a gap between the cover plate and the supporting box dam layer; the cover plate, the supporting box dam layer, the adhesion box dam layer and the wafer form a cavity together. According to the wafer level packaging method provided by the invention, the sealing performance and the stability of the cavity can be improved, pollutants are prevented from being introduced into the cavity, meanwhile, the formation of a cavity with a larger size is facilitated, and the process cost is reduced.
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Citation Information
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