Dual-mirror DBR type vertical cavity surface emitting laser and preparation method thereof

Abstract

The application provides a double medium DBR type vertical cavity surface emitting laser and a preparation method thereof. The double medium DBR type vertical cavity surface emitting laser comprises a conductive heat sink layer, a first metal electrode, a first medium DBR layer, a first transparent conductive layer, a first insulating medium layer, an active structure layer, a second insulating medium layer, a second transparent conductive layer, a second medium DBR layer and a second metal electrode. The application has the advantages of simple process, a plane structure of the overall structure, good heat dissipation function, better restriction on the optical field and the electric field, optimized current injection efficiency, improved output power and conversion efficiency of the laser device, and improved workable current density of the device and increased optical power due to the excellent heat dissipation.

Description

Technical Field

[0001] This invention belongs to the field of vertical cavity surface-emitting lasers, specifically relating to a dual-dielectric DBR type vertical cavity surface-emitting laser and its fabrication method. Background Technology

[0002] Vertical-cavity surface-emitting lasers (VCSELs) possess advantages such as small size, low threshold current, high beam quality, high photoelectric conversion efficiency, and ease of two-dimensional array integration and fabrication. They are increasingly being applied in optical communication, optical interconnection, information storage, display, medical, industrial processing, and military fields, demonstrating broad development prospects. However, traditional oxide-confined VCSEL structures face challenges in device research, including the need for improved technological processes, yield, and reliability. Traditional processes often use oxidation to control the size of the current-confining aperture to achieve single-mode output. This process struggles to precisely control the aperture size, especially in fabricating small current-confining apertures (below 5µm); furthermore, the effectiveness of single-sided current confinement in limiting the electric field needs improvement. On the other hand, the epitaxial growth of distributed Bragg reflectors (DBRs) may also encounter problems such as lattice mismatch between the DBR material and the substrate, small refractive index differences, and poor heat dissipation, which is particularly evident in GaN-based and InP-based devices. Therefore, there is an urgent need to develop a more efficient and easier-to-fabricate and controllable structure to drive the development of VCSELs. Summary of the Invention

[0003] Therefore, the purpose of this invention is to overcome the defects in the prior art and provide a dual-dielectric DBR type vertical cavity surface-emitting laser and its fabrication method.

[0004] Before describing the technical solution of this invention, the terms used herein are defined as follows:

[0005] The term "VCSEL" refers to a vertical cavity surface-emitting laser.

[0006] The term "DBR" refers to: Top and Bottom Distributed Bragg Mirrors.

[0007] The term "n-type semiconductor" refers to an impurity semiconductor in which the concentration of free electrons is much greater than the concentration of holes.

[0008] The term "p-type semiconductor layer" refers to an impurity semiconductor in which the hole concentration is much greater than the free electron concentration.

[0009] The term "ITO" refers to indium tin oxide.

[0010] To achieve the above objectives, a first aspect of the present invention provides a dual-dielectric DBR type vertical-cavity surface-emitting laser, the dual-dielectric DBR type vertical-cavity surface-emitting laser comprising: a conductive heat sink layer, a metal electrode, a dielectric DBR layer, a transparent conductive layer, an insulating dielectric layer, and an active structure layer; wherein,

[0011] The metal electrode includes a first metal electrode and a second metal electrode;

[0012] The dielectric DBR layer includes a first dielectric DBR layer and a second dielectric DBR layer;

[0013] The transparent conductive layer includes a first transparent conductive layer and a second transparent conductive layer; and / or

[0014] The insulating dielectric layer includes a first insulating dielectric layer and a second insulating dielectric layer.

[0015] According to a first aspect of the present invention, a dual-dielectric DBR type vertical-cavity surface-emitting laser comprises, from bottom to top, the following components:

[0016] A conductive heat sink layer with heat dissipation and conductivity;

[0017] First metal electrode;

[0018] A first dielectric DBR layer distributed at intervals from the first metal electrode;

[0019] First transparent conductive layer for current spreading;

[0020] A first insulating dielectric layer, and a first current window is formed in the middle of the first insulating dielectric layer;

[0021] Active structural layer;

[0022] A second insulating dielectric layer is formed in the middle of the second insulating dielectric layer;

[0023] A second transparent conductive layer for current spreading; and

[0024] The second metal electrode has a light-emitting window formed in the middle, and the second metal electrode and the second dielectric DBR layer are distributed alternately between the second metal electrode and the second transparent conductive layer.

[0025] Preferably, a bonding layer is further included between the conductive heat sink layer and the first metal electrode; and / or

[0026] Preferably, the active structure layer comprises, from top to bottom, the following:

[0027] p-type semiconductor layer;

[0028] Active layer; and

[0029] n-type semiconductor layer.

[0030] According to a first aspect of the present invention, a dual-dielectric DBR type vertical cavity surface-emitting laser is provided, wherein the first dielectric DBR layer, the second dielectric DBR layer, the first transparent conductive layer, and the second transparent conductive layer form an optical confinement layer;

[0031] The first transparent conductive layer, the second transparent conductive layer, the first insulating dielectric layer, and the second insulating dielectric layer form a current limiting layer;

[0032] The materials of the first metal electrode and the second metal electrode are selected from one or more of the following: gold, aluminum, nickel, titanium, zinc, platinum, silver, copper, chromium, germanium, palladium, cobalt, tungsten, preferably selected from one or more of the following: gold, titanium, nickel, aluminum, silver, chromium, platinum, more preferably selected from one or more of the following: gold, titanium, nickel, platinum;

[0033] The materials of the first dielectric DBR layer and the second dielectric DBR layer are selected from one or more of the following: silicon oxide, silicon nitride, nickel oxide, aluminum oxide, aluminum nitride, niobium oxide, titanium oxide, and hafnium oxide;

[0034] The materials of the first transparent conductive layer and the second transparent conductive layer are selected from one or more of the following: ITO, zinc oxide, silicon carbide, graphene, conductive polymer, thin-layer metal, preferably selected from one or more of the following: ITO, zinc oxide, silicon carbide, graphene, silver, aluminum, copper, gold, and more preferably: ITO or zinc oxide;

[0035] The materials of the first insulating dielectric layer and the second insulating dielectric layer are selected from one or more of the following: silicon nitride, silicon oxide, silicon oxynitride, nickel oxide, aluminum oxide, aluminum nitride, and boron nitride in a single layer or stack, preferably selected from one or more of the following: silicon nitride, silicon oxide, aluminum oxide, and more preferably silicon nitride or silicon oxide;

[0036] The active layer material is selected from one or more of the following: silicon, germanium, gallium nitride, gallium arsenide, indium phosphide, silicon carbide, germanium silicide / silicon quantum well, indium gallium nitride / gallium nitride quantum well, indium gallium arsenide / gallium arsenide quantum well, aluminum gallium arsenide / gallium arsenide quantum well, indium gallium arsenide / aluminum gallium arsenide quantum well, silicon quantum dot, germanium quantum dot, gallium nitride quantum dot, gallium arsenide quantum dot, indium phosphide quantum dot, germanium silicide quantum dot, indium gallium nitride quantum dot, indium gallium arsenide quantum dot, aluminum gallium arsenide quantum dot, indium gallium arsenide quantum dot, preferredly selected from one or more of the following: germanium silicide / silicon quantum well, indium gallium nitride / gallium nitride quantum well, indium gallium arsenide / gallium arsenide quantum well, aluminum gallium arsenide / gallium arsenide quantum well, indium gallium arsenide / aluminum gallium arsenide quantum well; and / or

[0037] The conductive heat sink layer is selected from one or more of the following: single metal substrate, alloy substrate, ceramic substrate; the material of the single metal substrate is preferably selected from one or more of the following: gold, copper, aluminum, silver; the material of the alloy substrate is preferably selected from one or more of the following: molybdenum copper, tungsten copper, chromium copper; and / or the material of the ceramic substrate is preferably selected from one or more of the following: aluminum nitride, diamond, silicon carbide;

[0038] Preferably, the reflectivity of the first dielectric DBR layer is greater than 99%, and the reflectivity of the second dielectric DBR layer is greater than 98% and less than the reflectivity of the first DBR.

[0039] Preferably, the materials of the first dielectric DBR layer and the second dielectric DBR layer are a dielectric material pair; more preferably, the refractive index difference of the dielectric material pair is not less than 0.1.

[0040] Preferably, the resistivity of the materials of the first and second transparent conductive layers is less than 0.05 Ω·cm, and the transmittance for the laser emission center wavelength is greater than 70%; and / or

[0041] Preferably, the thermal conductivity of the ceramic substrate is greater than 300 W / (m·K).

[0042] A second aspect of the present invention provides a method for fabricating the dual-dielectric DBR type vertical-cavity surface-emitting laser described in the first aspect, the method comprising the following steps:

[0043] (1) Prepare an initial active structure layer comprising a p-type semiconductor layer, an active layer, and an n-type semiconductor layer;

[0044] (2) On the p-type semiconductor layer of the initial active structure layer prepared in step (1), a first insulating dielectric layer, a first transparent conductive layer, a first dielectric DBR layer and a first metal electrode are sequentially prepared.

[0045] (3) A conductive heat sink layer is prepared on the first metal electrode prepared in step (2), exposing the n-type semiconductor layer of the active structure layer; and

[0046] (4) On the n-type semiconductor layer exposed in step (3), a second insulating dielectric layer, a second transparent conductive layer, a second dielectric DBR layer, and a second metal electrode are sequentially prepared to obtain the dual dielectric DBR type vertical cavity surface emission laser.

[0047] According to a second aspect of the method of the present invention, step (1) further includes the following step:

[0048] (a) Selecting a wafer substrate; and

[0049] (b) A buffer layer, a selection stop layer, an n-type semiconductor layer, an active layer and a p-type semiconductor layer are sequentially grown on the wafer substrate in step (a) to obtain the initial active structure layer;

[0050] Preferably, in step (a), the wafer substrate is selected from one or more of the following: gallium arsenide, silicon, germanium, gallium nitride, indium phosphide, silicon carbide, and sapphire; more preferably, it is selected from one or more of the following: gallium arsenide, silicon, gallium nitride, and indium phosphide; and / or

[0051] Preferably, in step (b), the growth method is epitaxial growth, more preferably selected from one or more of the following: organometallic chemical vapor deposition, molecular beam epitaxy, vapor phase epitaxy, liquid phase epitaxy, and even more preferably organometallic chemical vapor deposition and / or molecular beam epitaxy.

[0052] According to the method of the second aspect of the present invention, in step (2):

[0053] The method for preparing the first insulating dielectric layer is selected from one or more of the following: atomic layer deposition, sputtering, chemical vapor deposition, physical vapor deposition, and ion beam evaporation;

[0054] The preparation method of the first transparent conductive layer is selected from one or more of the following: sputtering, evaporation, ion plating, wet coating, sol-gel method, high-temperature pyrolysis spraying, chemical vapor deposition, and high-temperature pyrolysis spraying;

[0055] The first metal electrode is prepared by deposition.

[0056] Before preparing the first transparent conductive layer, the method further includes: preparing a first pattern on the first insulating dielectric layer, using the first pattern as a mask to etch or corrode the first insulating dielectric layer down to the p-type semiconductor layer to form a first current window;

[0057] Before fabricating the first metal electrode, the method further includes: fabricating a second pattern on the first dielectric DBR layer; using the second pattern as a mask, etching or corroding the first dielectric DBR layer down to the first transparent conductive layer to form a first electrode hole; and / or

[0058] The first metal electrode covers the first dielectric DBR layer and the first transparent conductive layer at the bottom of the first electrode hole.

[0059] According to the method of the second aspect of the present invention, in step (4):

[0060] The method for preparing the second insulating dielectric layer is selected from one or more of the following: atomic layer deposition, sputtering, chemical vapor deposition, physical vapor deposition, and ion beam evaporation;

[0061] The preparation method of the second transparent conductive layer is selected from one or more of the following: sputtering, evaporation, ion plating, wet coating, sol-gel method, high-temperature pyrolysis spraying, chemical vapor deposition, and high-temperature pyrolysis spraying;

[0062] The second metal electrode is prepared by deposition.

[0063] Before preparing the second transparent conductive layer, the method further includes: preparing a third pattern on the second insulating dielectric layer, using the third pattern as a mask to etch or corrode the second insulating dielectric layer to an n-type semiconductor layer to form a second current window;

[0064] Before fabricating the second metal electrode, the method further includes: fabricating a fourth pattern on the second dielectric DBR layer; using the fourth pattern as a mask, etching or corroding the second dielectric DBR layer down to the second transparent conductive layer to form a second electrode hole; and / or

[0065] A fifth pattern is prepared on the second metal electrode. Using the fifth pattern as a mask, the second metal electrode is deposited. The second metal electrode covers the second dielectric DBR layer and the first transparent conductive layer at the bottom of the second electrode hole, and a light-emitting window is formed in the middle of the second dielectric DBR layer.

[0066] According to the method of the second aspect of the present invention, wherein,

[0067] In step (2), the first insulating dielectric layer is prepared by: directly preparing it on a p-type semiconductor layer or by preparing it as a buried layer; and / or

[0068] In step (4), the second insulating dielectric layer is prepared by either directly preparing it on an n-type semiconductor layer or by preparing it as a buried layer.

[0069] Preferably, the method for preparing the buried layer of the first insulating dielectric layer is as follows: etching the p-type semiconductor layer followed by preparing the first insulating dielectric layer; and / or

[0070] Preferably, the method for preparing the buried layer of the second insulating dielectric layer is as follows: etching the n-type semiconductor layer and then preparing the second insulating dielectric layer.

[0071] According to the method of the second aspect of the present invention, step (3) further includes:

[0072] (c) A bonding layer is prepared on the first metal electrode;

[0073] (d) Bond the bonding layer prepared in step (c) onto the conductive heat sink to obtain a bonding structure; and

[0074] (e) Remove the wafer substrate, buffer layer and selection stop layer of the bonding structure obtained in step (d) to expose the surface of the n-type semiconductor layer of the active structure layer;

[0075] Preferably, in step (c), the material of the bonding layer is selected from one or more of the following: gold-tin, indium, copper-tin, gold-silicon, silver, and curing adhesive;

[0076] Preferably, in step (d), the bonding method is selected from one or more of the following: metal diffusion bonding, metal eutectic bonding, low-temperature direct bonding, and plasma-assisted bonding;

[0077] Preferably, in step (e), the removal method of the wafer substrate and the buffer layer is selected from one or more of the following: substrate thinning method, chemical mechanical polishing method, wet etching method, dry etching method, laser lift-off method, more preferably wet etching method or laser lift-off method; the removal method of the selected stop layer is wet etching or dry etching.

[0078] According to the method of the second aspect of the present invention, step (3) further includes:

[0079] (f) Electroplating a thick metal layer onto the first metal electrode to obtain a conductive heat sink layer; and

[0080] (g) Remove the wafer substrate, buffer layer, and selection stop layer of the initial active structure layer prepared in step (1) to expose the surface of the n-type semiconductor layer of the active structure layer.

[0081] Preferably, in step (f), the metal being electroplated is selected from one or more of the following: copper, gold, chromium, nickel, zinc, silver, titanium, more preferably copper or chromium; and / or

[0082] Preferably, in step (g), the removal method of the wafer substrate and the buffer layer is selected from one or more of the following: substrate thinning method, chemical mechanical polishing method, wet etching method, dry etching method, laser lift-off method, more preferably wet etching method or laser lift-off method; the removal method of the selected stop layer is wet etching or dry etching.

[0083] Traditional oxide-confined VCSELs typically employ epitaxial fabrication of upper and lower dielectric barrier layers (DBRs) to control the optical field, followed by an oxidation process to control the current-confining aperture size, i.e., the electric field. In this invention, photolithography is used instead of the traditional oxidation process, avoiding the problem of inaccurate current aperture confinement. Simultaneously, a dual-dielectric DBR layer plus a transparent conductive layer replaces the traditional epitaxial DBR layer, achieving current spread and better optical field confinement.

[0084] This invention provides a dual-dielectric DBR type vertical cavity surface-emitting laser and its fabrication method, avoiding the shortcomings of traditional VCSEL fabrication processes.

[0085] The overall structure of the dual-dielectric DBR type vertical cavity surface-emitting laser is arranged sequentially from bottom to top as follows:

[0086] Conductive heat sink:

[0087] First metal electrode;

[0088] A first metal electrode and a first dielectric DBR layer are spaced apart;

[0089] First transparent conductive layer;

[0090] A first insulating dielectric layer, and a first current window is formed in the middle of the first insulating dielectric layer;

[0091] p-type semiconductor layer;

[0092] Active layer;

[0093] n-type semiconductor layer;

[0094] A second insulating dielectric layer is formed in the middle of the second insulating dielectric layer;

[0095] Second transparent conductive layer

[0096] A second metal electrode and a second DBR layer are spaced apart;

[0097] A second metal electrode is provided, and a light-emitting window is formed in the middle of the second metal electrode.

[0098] The structural features of the dual-dielectric DBR type vertical cavity surface-emitting laser are as follows:

[0099] Optical confinement layer: consists of two dielectric DBR layers and two transparent conductive layers;

[0100] Current limiting layer: It consists of two transparent conductive layers and two insulating dielectric layers. The transparent conductive layers play a role in current expansion and prevent current accumulation.

[0101] Heat dissipation: A conductive heat sink layer that combines good heat dissipation and conductivity.

[0102] The fabrication method of the dual-dielectric DBR type vertical cavity surface-emitting laser includes, but is not limited to, a method of bonding a conductive heat sink and a direct insulating medium, a method of electroplating a conductive heat sink and a direct insulating medium, and a method of bonding a conductive heat sink and a buried insulating medium. Among these,

[0103] The method for bonding the conductive heat sink and the direct insulating medium includes the following steps:

[0104] 1. Provide a wafer substrate required for the growth process; preferably, the wafer substrate is selected from one or more of the following: gallium arsenide, silicon, germanium, gallium nitride, indium phosphide, silicon carbide, and sapphire;

[0105] 2. A buffer layer, a selected stop layer, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer are sequentially epitaxially grown on the wafer; preferably, the epitaxial growth method is selected from metal-organic chemical vapor deposition and / or molecular beam epitaxy;

[0106] 3. A first insulating dielectric layer is prepared on a p-type semiconductor. Preferably, the preparation method of the first insulating dielectric layer is selected from one or more of the following: atomic layer deposition, sputtering, chemical vapor deposition, physical vapor deposition, and ion beam evaporation.

[0107] 4. A first pattern is prepared on the first insulating dielectric layer. Using the first pattern as a mask, the first insulating dielectric layer is etched down to the p-type semiconductor layer using etching / etching techniques to form a first current window.

[0108] 5. Prepare a first transparent conductive layer on the first insulating dielectric layer; preferably, the preparation method of the first transparent conductive layer is selected from one or more of the following: sputtering, evaporation, ion plating, wet coating, sol-gel method, high-temperature pyrolysis spraying, chemical vapor deposition, and high-temperature pyrolysis spraying.

[0109] 6. Prepare a first dielectric DBR layer on the first transparent conductive layer;

[0110] 7. Prepare a second pattern on the first dielectric DBR layer. Using the second pattern as a mask, etch the first dielectric DBR layer down to the first transparent conductive layer using etching / etching techniques to form the first electrode hole.

[0111] 8. Deposit a first metal electrode, which covers the first dielectric DBR layer and the first transparent conductive layer at the bottom of the first electrode hole;

[0112] 9. Prepare a bonding layer on the first metal electrode;

[0113] 10. The wafer prepared in step (11) is bonded to the conductive heat sink layer through a bonding layer;

[0114] 11. Remove the wafer substrate and buffer layer using substrate removal technology;

[0115] 12. Remove the selective stop layer using wet etching or dry etching techniques to expose the surface of the n-type semiconductor layer;

[0116] 13. A second insulating dielectric layer is prepared on an n-type semiconductor layer. Preferably, the preparation method of the second insulating dielectric layer is selected from one or more of the following: atomic layer deposition, sputtering, chemical vapor deposition, physical vapor deposition, and ion beam evaporation.

[0117] 14. Prepare a third pattern on the second insulating dielectric layer. Using the third pattern as a mask, etch the second insulating dielectric layer down to the n-type semiconductor layer using etching / etching techniques to form a second current window.

[0118] 15. Prepare a second transparent conductive layer on the second insulating dielectric layer; preferably, the preparation method of the first transparent conductive layer is selected from one or more of the following: sputtering, evaporation, ion plating, wet coating, sol-gel method, high-temperature pyrolysis spraying, chemical vapor deposition, and high-temperature pyrolysis spraying.

[0119] 16. Prepare a second DBR layer on the second transparent conductive layer;

[0120] 17. Prepare a fourth pattern on the second DBR layer. Using the fourth pattern as a mask, use etching / etching technology to etch the second DBR layer down to the second transparent conductive layer to form the second electrode hole.

[0121] 18. A fifth pattern is prepared on the second metal electrode. Using the fifth pattern as a mask, a second metal electrode is deposited. The metal electrode covers the second DBR layer and the first transparent conductive layer at the bottom of the second electrode hole, and a light-emitting window is formed in the middle of the second DBR layer.

[0122] The second method of electroplating conductive heat sink and direct insulating medium replaces the bonded conductive heat sink in the first method with an electroplated metal conductive heat sink.

[0123] The third method of bonding the conductive thermal deposited layer and the buried insulating medium is to replace the direct deposition of the insulating medium layer in the first method with a buried insulating medium layer.

[0124] The key point of the technical solution of this invention lies in the overall structure, specifically:

[0125] 1. By precisely controlling the current limiting aperture size through photolithography, the current is precisely limited, effectively avoiding the impact of the oxidation process on the current limiting window in the original VCSEL route.

[0126] 2. By using a dual-dielectric DBR to replace the traditional epitaxial DBR technology route, the pressure of epitaxy (InP, GaN-based) can be alleviated, while a resonant cavity with higher reflectivity can be formed to achieve better confinement of the light field.

[0127] 3. The addition of a transparent conductive layer enables good current expansion and avoids current blockage.

[0128] The dual-dielectric DBR type vertical-cavity surface-emitting laser of the present invention, and its fabrication method, may have, but are not limited to, the following beneficial effects:

[0129] 1. By using photolithography on the insulating dielectric layer to replace the wet oxidation process of the current limiting layer in the traditional VCSEL process, the aperture size can be precisely controlled to form a current limiting window of controllable size.

[0130] 2. By using dielectric DBR to replace the traditional epitaxial DBR technology route, the pressure of epitaxy (InP, GaN-based) can be alleviated. At the same time, only thinner DBR layer pairs are needed to form a resonant cavity with higher reflectivity, thus achieving better confinement of the optical field.

[0131] 3. By fabricating transparent conductive layers on n-type and p-type semiconductors respectively, good current spread can be achieved, avoiding the reduction in efficiency and shortening of device life caused by current blockage.

[0132] 4. By transferring the epitaxial structure onto a conductive heat sink layer with good conductivity and heat dissipation, the original substrate is removed, thereby improving the heat dissipation and optoelectronic performance of the device. Attached Figure Description

[0133] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings, wherein:

[0134] Figure 1 A flowchart illustrating the fabrication method of the dual-dielectric DBR type vertical cavity surface-emitting laser of the present invention in Example 1 is shown.

[0135] Figure 2 A flowchart illustrating the fabrication method of the dual-dielectric DBR type vertical cavity surface-emitting laser of the present invention in Example 2 is shown.

[0136] Figure 3 A flowchart illustrating the fabrication method of the dual-dielectric DBR type vertical cavity surface-emitting laser of the present invention in Example 3 is shown.

[0137] Figure 4 A schematic diagram of the initial active structure layer of the dual-dielectric DBR type vertical cavity surface-emitting laser of the present invention is shown.

[0138] Figure 5 A schematic diagram of the structure of the dual-dielectric DBR type vertical cavity surface-emitting laser of the present invention in Embodiment 1 is shown.

[0139] Figure 6 A schematic diagram of the structure of the dual-dielectric DBR type vertical cavity surface-emitting laser of the present invention in Embodiment 2 is shown.

[0140] Figure 7 A schematic diagram of the structure of the dual-dielectric DBR type vertical cavity surface-emitting laser of the present invention in Embodiment 3 is shown.

[0141] Explanation of reference numerals in the attached figures:

[0142] 1. Substrate wafer; 2. Buffer layer; 3. Selection stop layer; 4. n-type semiconductor layer; 5. Active layer; 6. p-type semiconductor layer; 7. First insulating dielectric layer; 8. First current window; 9. First transparent conductive layer; 10. First dielectric DBR layer; 11. First electrode hole; 12. First metal electrode; 13. Bonding layer; 14. Conductive heat sink layer; 15. Second insulating dielectric layer; 16. Second current window; 17. Second transparent conductive layer; 18. Second dielectric DBR layer; 19. First electrode hole; 20. Second metal electrode; 21. Light emission window. Detailed Implementation

[0143] The present invention will be further illustrated below with specific embodiments. However, it should be understood that these embodiments are merely for more detailed and specific illustration and should not be construed as limiting the present invention in any way.

[0144] This section provides a general description of the materials and testing methods used in the experiments of this invention. While many of the materials and methods of operation used to achieve the objectives of this invention are well known in the art, the invention is still described in as much detail as possible herein. It will be apparent to those skilled in the art that, unless otherwise stated in the context, the materials and methods of operation used in this invention are well known in the art.

[0145] Example 1

[0146] This embodiment illustrates the fabrication method of the dual-dielectric DBR type vertical cavity surface-emitting laser of the present invention.

[0147] This embodiment employs a bonded conductive heat-absorbing layer and a direct insulating dielectric method to fabricate a dual-dielectric DBR-type vertical-cavity surface-emitting laser. The following describes the process in conjunction with... Figure 1 The preparation method of the bonded conductive heat sink and the direct insulating dielectric is further explained. The specific method includes the following steps:

[0148] 1. Provide a wafer substrate required for the growth process; the wafer substrate is selected from one or more of the following: gallium arsenide, silicon, germanium, gallium nitride, indium phosphide, silicon carbide, sapphire, and gallium arsenide is selected as the wafer substrate in this embodiment.

[0149] 2. A buffer layer 2, a selective stop layer 3, an n-type semiconductor layer 4, an active layer 5, and a p-type semiconductor layer 6 are sequentially epitaxially grown on the wafer; the epitaxial growth method is selected from metal-organic chemical vapor deposition and / or molecular beam epitaxy; in this embodiment, the method used is metal-organic chemical vapor deposition, the active layer material is gallium arsenide-based material, and the center wavelength of the emission is about 940nm.

[0150] 3. A first insulating dielectric layer 7 is fabricated on a p-type semiconductor. The fabrication method of the first insulating dielectric layer is selected from one or more of the following: atomic layer deposition, sputtering, chemical vapor deposition, physical vapor deposition, and ion beam evaporation; in this embodiment, atomic layer deposition is used. The material of the first insulating dielectric layer is selected from one or more of the following: a single layer or stack of silicon nitride, silicon oxide, silicon oxynitride, nickel oxide, aluminum oxide, aluminum nitride, and boron nitride; in this embodiment, 20nm silicon oxide is used.

[0151] 4. A first pattern is prepared on the first insulating dielectric layer 7. Using the first pattern as a mask, in this embodiment, the first insulating dielectric layer is dry etched to the p-type semiconductor layer to form a first current window 8. The shape of the first current window is a circle with a diameter of 10 μm.

[0152] 5. A first transparent conductive layer 9 is prepared on the first insulating dielectric layer 7; the preparation method of the first transparent conductive layer is selected from one or more of the following: sputtering, evaporation, ion plating, wet coating, sol-gel method, high-temperature pyrolysis spraying, chemical vapor deposition, and high-temperature pyrolysis spraying; in this embodiment, electron beam evaporation is selected as the method; the material of the first transparent conductive layer selected in this embodiment is 30nm ITO, with a resistivity of 0.001Ω·cm and a transmittance of 98.5% for the center wavelength of the GaAs-based laser.

[0153] 6. A first dielectric DBR layer 10 is prepared on the first transparent conductive layer 9. In this embodiment, the first dielectric DBR layer material is a periodic silicon oxide / niobium oxide material pair, which has a reflectivity of 99.99% for the center wavelength of the laser.

[0154] 7. A second pattern is prepared on the first dielectric DBR layer 10. Using the second pattern as a mask, in this embodiment, the first electrode hole 11 is formed by etching the first dielectric DBR layer to the first transparent conductive layer. The electrode hole is a ring with a width of 5 μm and an inner radius of about 50 μm.

[0155] 8. Deposit a first metal electrode 12, which covers the first dielectric DBR layer 10 and the first transparent conductive layer at the bottom of the first electrode hole 11. In this embodiment, the metal electrode material is 20 / 100nm titanium / gold.

[0156] 9. A bonding layer 13 is prepared on the first metal electrode. The material of the bonding layer is selected from one or more of the following: gold-tin, indium, copper-tin, gold-silicon, silver, and curing adhesive. In this embodiment, the bonding layer material is 100nm / 20nm gold / tin.

[0157] 10. The bonding layer prepared in step (9) is bonded to the conductive heat sink layer 14 by a bonding method; the bonding method is selected from one or more of the following: metal diffusion bonding, metal eutectic bonding, low temperature direct bonding, plasma-assisted bonding; the bonding method selected in this embodiment is metal eutectic bonding, and the temperature is 350℃; the conductive heat sink layer selected in this embodiment is a molybdenum copper substrate with a thermal expansion coefficient close to that of gallium arsenide material.

[0158] 11. Remove the wafer substrate 1 and buffer layer 2 using substrate removal technology;

[0159] 12. Remove the selective stop layer 3 using wet etching or dry etching techniques to expose the n-type semiconductor layer surface 4; in this embodiment, wet etching technique is used.

[0160] 13. A second insulating dielectric layer 15 is prepared on the n-type semiconductor layer. The preparation method of the second insulating dielectric layer is selected from one or more of the following: atomic layer deposition, sputtering, chemical vapor deposition, physical vapor deposition, ion beam evaporation; in this embodiment, atomic layer deposition is selected. The material of the second insulating dielectric layer is selected from one or more of the following: single layer or stack of silicon nitride, silicon oxide, silicon oxynitride, nickel oxide, aluminum oxide, aluminum nitride, and boron nitride; in this embodiment, 20nm silicon oxide is selected.

[0161] 14. A third pattern is prepared on the second insulating dielectric layer 15. Using the third pattern as a mask, in this embodiment, a second current window 16 is formed by etching the second insulating dielectric layer 15 to the n-type semiconductor layer. The shape of the second current window is a circle with a diameter of 10 μm.

[0162] 15. A second transparent conductive layer 17 is prepared on the second insulating dielectric layer; the preparation method of the second transparent conductive layer is selected from one or more of the following: sputtering, evaporation, ion plating, wet coating, sol-gel method, high-temperature pyrolysis spraying, chemical vapor deposition, and high-temperature pyrolysis spraying; in this embodiment, electron beam evaporation is selected; the first transparent conductive layer material selected in this embodiment is 30nm ITO with a resistivity of 0.001Ω·cm and a transmittance of 98.5% to the center wavelength of the GaAs-based laser.

[0163] 16. Prepare a second DBR layer 18 on the second transparent conductive layer; the second dielectric DBR layer material selected in this embodiment is a periodic silicon oxide / niobium oxide material pair with a reflectivity of 99.95%.

[0164] 17. A fourth pattern is fabricated on the second DBR layer. Using the fourth pattern as a mask, in this embodiment, the second electrode hole 19 is formed by etching the second DBR layer to the second transparent conductive layer 18. The electrode hole is a ring with a width of 5 μm and an inner radius of about 70 μm.

[0165] 18. A fifth pattern is fabricated on the second metal electrode. Using the fifth pattern as a mask, a second metal electrode 20 is deposited. This metal electrode covers the second DBR layer 18 and the second transparent conductive layer at the bottom of the second electrode aperture 19, and a light-emitting window 21 is formed in the middle of the second DBR layer. In this embodiment, the second metal electrode is nickel / gold / germanium / nickel / gold with a thickness of 20 / 50 / 25 / 20 / 200 nm, and the light-emitting window is a circle with a radius of 25 μm.

[0166] Example 2

[0167] This embodiment illustrates the fabrication method of the dual-dielectric DBR type vertical cavity surface-emitting laser of the present invention.

[0168] This embodiment uses an electroplated conductive heat deposition layer and a direct insulating dielectric method to fabricate a dual-dielectric DBR type vertical-cavity surface-emitting laser. The following describes the process in conjunction with... Figure 2 The preparation method of the electroplated conductive heat sink layer and the direct insulating medium is further explained. The specific method includes the following steps:

[0169] 1. Provide a wafer substrate required for the growth process; the wafer substrate is selected from one or more of the following: gallium arsenide, silicon, germanium, gallium nitride, indium phosphide, silicon carbide, sapphire, and in this embodiment, sapphire is selected as the wafer substrate.

[0170] 2. A buffer layer 2, a selective stop layer 3, an n-type semiconductor layer 4, an active layer 5, and a p-type semiconductor layer 6 are sequentially epitaxially grown on the wafer; the epitaxial growth method is selected from metal-organic chemical vapor deposition and / or molecular beam epitaxy; in this embodiment, the method used is metal-organic chemical vapor deposition, the active layer material is gallium nitride-based material, and the center wavelength emitted by the active layer is about 450nm.

[0171] 3. A first insulating dielectric layer 7 is fabricated on a p-type semiconductor. The fabrication method of the first insulating dielectric layer is selected from one or more of the following: atomic layer deposition, sputtering, chemical vapor deposition, physical vapor deposition, ion beam evaporation; in this embodiment, magnetron sputtering is used. The material of the first insulating dielectric layer is selected from one or more of the following: single layer or stack of silicon nitride, silicon oxide, silicon oxynitride, nickel oxide, aluminum oxide, aluminum nitride, and boron nitride; in this embodiment, 40nm silicon nitride is used.

[0172] 4. A first pattern is prepared on the first insulating dielectric layer 7. Using the first pattern as a mask, in this embodiment, the first insulating dielectric layer is dry etched to the p-type semiconductor layer to form a first current window 8. The shape of the first current window is a circle with a diameter of 20 μm.

[0173] 5. A first transparent conductive layer 9 is prepared on the first insulating dielectric layer 7; the preparation method of the first transparent conductive layer is selected from one or more of the following: sputtering, evaporation, ion plating, wet coating, sol-gel method, high-temperature pyrolysis spraying, chemical vapor deposition, and high-temperature pyrolysis spraying; in this embodiment, the method used is metal magnetron sputtering; the material of the first transparent conductive layer selected in this embodiment is 2nm / 2nm platinum / gold with a resistivity of ~1×10⁻⁶. -5 The transmittance to the center wavelength of the laser is approximately 80% (Ω·cm), and the transparent conductive layer 9 is designed at the valley of the standing wave in the resonant cavity to reduce absorption.

[0174] 6. A first dielectric DBR layer 10 is prepared on the first transparent conductive layer 9; in this embodiment, the first dielectric DBR layer material is a periodic silicon oxide / zirconia material pair with a reflectivity of 99.9%.

[0175] 7. A second pattern is prepared on the first dielectric DBR layer 10. Using the second pattern as a mask, in this embodiment, the first electrode hole 11 is formed by etching the first dielectric DBR layer to the first transparent conductive layer. The electrode hole is a ring with a width of 8 μm and an inner radius of about 80 μm.

[0176] 8. Deposit a first metal electrode 12, which covers the first dielectric DBR layer 10 and the first transparent conductive layer at the bottom of the first electrode hole 11. In this embodiment, the metal electrode material selected is 20 / 100 / 30 / 50nm titanium / aluminum / nickel / gold.

[0177] 9. A 100µm thick metal layer is electroplated on the surface of the first metal electrode to form a conductive heat sink layer 14; the electroplating metal material selected in this embodiment is copper.

[0178] 10. Remove the wafer substrate 1 and buffer layer 2 using substrate removal technology; the substrate removal technology selected in this embodiment is the laser lift-off method.

[0179] 11. Remove the selective stop layer 3 using wet etching or dry etching techniques to expose the n-type semiconductor layer surface 4; in this embodiment, the dry etching technique is used.

[0180] 12. A second insulating dielectric layer 15 is fabricated on the n-type semiconductor layer. The fabrication method of the second insulating dielectric layer is selected from one or more of the following: atomic layer deposition, sputtering, chemical vapor deposition, physical vapor deposition, ion beam evaporation; in this embodiment, chemical vapor deposition is used. The material of the second insulating dielectric layer is selected from one or more of the following: single layer or stack of silicon nitride, silicon oxide, silicon oxynitride, nickel oxide, aluminum oxide, aluminum nitride, and boron nitride; in this embodiment, 40nm silicon nitride is used.

[0181] 13. A third pattern is prepared on the second insulating dielectric layer 15. Using the third pattern as a mask, in this embodiment, a second current window 16 is formed by etching the second insulating dielectric layer 15 to the n-type semiconductor layer. The shape of the second current window is a circle with a diameter of 20 μm.

[0182] 14. A second transparent conductive layer 17 is prepared on the second insulating dielectric layer; the preparation method of the second transparent conductive layer is selected from one or more of the following: sputtering, evaporation, ion plating, wet coating, sol-gel method, high-temperature pyrolysis spraying, chemical vapor deposition, and high-temperature pyrolysis spraying; in this embodiment, the method used is metal magnetron sputtering; the material of the second transparent conductive layer selected in this embodiment is 2nm / 2nm platinum / gold with a resistivity of ~1×10⁻⁶. -5 The transmittance to the center wavelength of the laser is approximately 80% (Ω·cm), and the transparent conductive layer 17 is designed at the valley of the standing wave in the resonant cavity to reduce absorption.

[0183] 15. Prepare a second DBR layer 18 on the second transparent conductive layer; the second dielectric DBR layer material selected in this embodiment is a periodic silicon oxide / zirconia material pair with a reflectivity of 99.8%.

[0184] 16. A fourth pattern is fabricated on the second DBR layer. Using the fourth pattern as a mask, in this embodiment, the second electrode hole 19 is formed by etching the second DBR layer to the second transparent conductive layer. The electrode hole is a ring with a width of 8 μm and an inner radius of about 100 μm.

[0185] 17. A fifth pattern is prepared on the second metal electrode. Using the fifth pattern as a mask, a second metal electrode 20 is deposited. The metal electrode covers the second DBR layer 18 and the second transparent conductive layer at the bottom of the second electrode hole 19, and a light-emitting window 21 is formed in the middle of the second DBR layer. In this embodiment, the second metal electrode is nickel / gold with a thickness of 20 / 200nm, and the light-emitting window is a circle with a radius of 50um.

[0186] Example 3

[0187] This embodiment illustrates the fabrication method of the dual-dielectric DBR type vertical cavity surface-emitting laser of the present invention.

[0188] This embodiment employs a method of bonding a conductive thermally deposited layer and a buried insulating dielectric layer to fabricate a dual-dielectric DBR-type vertical-cavity surface-emitting laser. The following describes the process in conjunction with... Figure 3 The preparation method of the bonded conductive heat sink and the direct insulating dielectric is further explained. The specific method includes the following steps:

[0189] 1. Provide a wafer substrate required for the growth process; the wafer substrate is selected from one or more of the following: silicon, gallium arsenide, germanium, gallium nitride, indium phosphide, silicon carbide, sapphire, and indium phosphide is selected as the wafer substrate in this embodiment.

[0190] 2. A buffer layer 2, a selective stop layer 3, an n-type semiconductor layer 4, an active layer 5, and a p-type semiconductor layer 6 are sequentially epitaxially grown on the wafer; the epitaxial growth method is selected from metal-organic chemical vapor deposition and / or molecular beam epitaxy; in this embodiment, the method used is molecular beam epitaxy, the active layer material is indium phosphide-based material, and the center wavelength emitted by the active layer is about 1550nm.

[0191] 3. A first pattern is fabricated on a p-type semiconductor. Using the first pattern as a mask, in this embodiment, the p-type semiconductor layer is etched to approximately 30 nm using a dry etching method.

[0192] 4. A first insulating dielectric layer 7 is fabricated on a p-type semiconductor. The fabrication method of the first insulating dielectric layer is selected from one or more of the following: atomic layer deposition, sputtering, chemical vapor deposition, physical vapor deposition, ion beam evaporation; in this embodiment, magnetron sputtering is used. The material of the first insulating dielectric layer is selected from one or more of the following: single layer or stack of silicon nitride, silicon oxide, silicon oxynitride, nickel oxide, aluminum oxide, aluminum nitride, and boron nitride; in this embodiment, 30nm silicon oxide is used.

[0193] 5. Using the first pattern as a mask, remove the first insulating dielectric layer on the first pattern down to the P-type semiconductor to form a first current window 8. The shape of the first current window is a circle with a diameter of 8 μm.

[0194] 6. A first transparent conductive layer 9 is prepared on the first insulating dielectric layer 7; the preparation method of the first transparent conductive layer is selected from one or more of the following: sputtering, evaporation, ion plating, wet coating, sol-gel method, high-temperature pyrolysis spraying, chemical vapor deposition, and high-temperature pyrolysis spraying; in this embodiment, the method used is dielectric magnetron sputtering; the material of the first transparent conductive layer selected in this embodiment is 30nm SiC, with a resistivity of 0.01Ω·cm and a transmittance of 98% for the center wavelength of the laser.

[0195] 7. A first dielectric DBR layer 10 is prepared on the first transparent conductive layer 9; in this embodiment, the first dielectric DBR layer material is a periodic silicon oxide / titanium oxide material pair with a reflectivity of 99.95%.

[0196] 8. A second pattern is prepared on the first dielectric DBR layer 10. Using the second pattern as a mask, in this embodiment, the first electrode hole 11 is formed by etching the first dielectric DBR layer to the first transparent conductive layer. The electrode hole is a ring with a width of 6 μm and an inner radius of about 40 μm.

[0197] 9. Deposit a first metal electrode 12, which covers the first dielectric DBR layer 10 and the first transparent conductive layer at the bottom of the first electrode hole 11. In this embodiment, the metal electrode material is 20 / 50nm titanium / gold.

[0198] 10. A bonding layer 13 is prepared on the first metal electrode. The material of the bonding layer is selected from one or more of the following: gold-tin, indium, copper-tin, gold-silicon, silver, and curing adhesive. In this embodiment, the bonding layer material is 200nm / 50nm copper-tin.

[0199] 11. The wafer bonding layer prepared in step (10) is bonded to the conductive heat sink layer 14 by a bonding layer bonding method; the bonding method is selected from one or more of the following: metal diffusion bonding, metal eutectic bonding, low temperature direct bonding, plasma-assisted bonding; the bonding method selected in this embodiment is metal diffusion bonding, and the temperature is 20°C; the conductive heat sink layer selected in this embodiment is silicon carbide.

[0200] 12. Remove the wafer substrate 1 and buffer layer 2 using substrate removal technology; the substrate removal technology selected in this embodiment is wet etching technology.

[0201] 13. Remove the selective stop layer 3 using wet etching or dry etching techniques to expose the n-type semiconductor layer surface 4; in this embodiment, wet etching technique is used.

[0202] 14. A third pattern is fabricated on the n-type semiconductor. Using the third pattern as a mask, the n-type semiconductor layer is etched to approximately 30 nm using a dry etching process in this embodiment.

[0203] 15. A second insulating dielectric layer 15 is prepared on the n-type semiconductor layer. The preparation method of the second insulating dielectric layer is selected from one or more of the following: atomic layer deposition, sputtering, chemical vapor deposition, physical vapor deposition, ion beam evaporation; in this embodiment, magnetron sputtering is selected. The material of the second insulating dielectric layer is selected from one or more of the following: single layer or stack of silicon nitride, silicon oxide, silicon oxynitride, nickel oxide, aluminum oxide, aluminum nitride, and boron nitride; in this embodiment, 30nm silicon oxide is selected.

[0204] 16. Using the third pattern as a mask, remove the second insulating dielectric layer on the third pattern to the n-type semiconductor to form a second current window 16. The shape of the second current window is a circle with a diameter of 8 μm.

[0205] 17. A second transparent conductive layer 17 is prepared on the second insulating dielectric layer; the preparation method of the second transparent conductive layer is selected from one or more of the following: sputtering, evaporation, ion plating, wet coating, sol-gel method, high-temperature pyrolysis spraying, chemical vapor deposition, and high-temperature pyrolysis spraying; in this embodiment, the method used is dielectric magnetron sputtering; the first transparent conductive layer material selected in this embodiment is 30nm SiC, with a resistivity of 0.01Ω·cm and a transmittance of 98% for the center wavelength of the laser.

[0206] 18. A second DBR layer 18 is prepared on the second transparent conductive layer; in this embodiment, the material of the second dielectric DBR layer is a periodic silicon oxide / titanium oxide material pair with a reflectivity of 99.9%.

[0207] 19. A fourth pattern is prepared on the second DBR layer. Using the fourth pattern as a mask, in this embodiment, the second electrode hole 19 is formed by etching the second DBR layer to the second transparent conductive layer. The electrode hole is a ring with a width of 6 μm and an inner radius of about 60 μm.

[0208] 20. A fifth pattern is prepared on the second metal electrode. Using the fifth pattern as a mask, a second metal electrode 20 is deposited. The metal electrode covers the second DBR layer 18 and the second transparent conductive layer at the bottom of the second electrode hole 19, and a light-emitting window 21 is formed in the middle of the second DBR layer. In this embodiment, the second metal electrode is nickel / gold with a thickness of 20 / 200nm, and the light-emitting window is a circle with a radius of 20um.

[0209] Comparative Example

[0210] This comparative example is used to compare the differences and effects of the dielectric DBR type vertical cavity surface-emitting laser of this application with lasers in the prior art.

[0211] 1. Comparative Example 1 – Top and Bottom Epitaxial Conductive DBR

[0212] The overall structure is arranged from bottom to top as follows:

[0213] Substrate required for epitaxy;

[0214] n-metal electrode;

[0215] n-DBR;

[0216] Active layer;

[0217] Insulation limiting layer (current limiting window);

[0218] p-DBR;

[0219] p-metal electrode;

[0220] Structural characteristics: The overall structure is epitaxially prepared. Specifically:

[0221] Optical confinement layer: The upper and lower conductive DBRs (require epitaxy, which requires high lattice matching of materials; and because the refractive indices of the materials are relatively similar, a thicker DBR is often required to achieve the required reflectivity. A typical semiconductor film is generally composed of 20-30 pairs of thin films).

[0222] Current-limiting layer: The intermediate interlayer is oxidized from the sidewall to limit the pore size (not precise);

[0223] Heat dissipation: The substrate used for epitaxy itself (the substrate material has poor thermal conductivity, which affects heat dissipation).

[0224] 2. Comparative Example 2 – Single-sided Dielectric DBR

[0225] The overall structure is arranged from bottom to top as follows:

[0226] Substrate required for epitaxy;

[0227] n-metal electrode;

[0228] n-DBR;

[0229] Active layer;

[0230] Insulating dielectric layer (current limiting window);

[0231] Medium DBR;

[0232] p-metal electrode;

[0233] Structural features: The overall structure is fabricated using epitaxy and subsequent mesa processes. Specifically:

[0234] Optical confinement layer: lower n-type conductive DBR and upper dielectric DBR (n-DBR requires epitaxy, which requires high lattice matching of materials, and because the refractive index of materials is small, a thicker DBR is often required to achieve the reflectivity requirement. A typical semiconductor film is generally composed of 20-30 pairs of thin films).

[0235] Current limiting layer: Etched insulating dielectric layer (one-sided current limiting, limited limiting effect);

[0236] Heat dissipation: The substrate used for epitaxy itself (the substrate material has poor thermal conductivity, which affects heat dissipation).

[0237] 3. Comparative Example 3 – Conductive Substrate + Porous Conductive DBR

[0238] The overall structure is arranged from bottom to top as follows:

[0239] Conductive substrate;

[0240] p-metal electrode;

[0241] Medium DBR;

[0242] Transparent conductive layer;

[0243] Active layer;

[0244] Porous conductive DBR;

[0245] Insulating dielectric layer (current limiting window);

[0246] n-Electrical metal electrode.

[0247] Structural features: The laser is transferred to a conductive heat dissipation substrate, and the resonant function is achieved by a porous conductive DBR. Specifically:

[0248] Optical confinement layer: lower dielectric DBR and upper n-type porous conductive DBR (n-porous conductive DBR requires epitaxy and then electrochemical etching, which is a complex process; and the refractive index of the material needs to be controlled by the size of the air pores, so the etching uniformity needs to be precisely controlled to obtain the same refractive index of the spacer layer, and the precision control of the preparation process is required to be high).

[0249] Current limiting layer: Etched insulating dielectric layer (one-sided current limiting, limited limiting effect);

[0250] Heat dissipation: conductive substrate.

[0251] 4. The dielectric DBR type vertical cavity surface-emitting laser of this application

[0252] The overall structure of the dual-dielectric DBR type vertical cavity surface-emitting laser is arranged sequentially from bottom to top as follows:

[0253] A conductive heat sink layer with heat dissipation and conductivity;

[0254] First metal electrode;

[0255] A first dielectric DBR layer distributed at intervals from the first metal electrode;

[0256] First transparent conductive layer for current spreading;

[0257] A first insulating dielectric layer, and a first current window is formed in the middle of the first insulating dielectric layer;

[0258] Active structural layer;

[0259] A second insulating dielectric layer is formed in the middle of the second insulating dielectric layer;

[0260] A second transparent conductive layer for current spreading; and

[0261] The second metal electrode has a light-emitting window formed in the middle, and the second metal electrode and the second dielectric DBR layer are distributed alternately between the second metal electrode and the second transparent conductive layer.

[0262] The structural features of the dual-dielectric DBR type vertical cavity surface-emitting laser are as follows:

[0263] Optical confinement layer: Consists of two dielectric DBR layers and two transparent conductive layers;

[0264] Current limiting layer: It consists of two transparent conductive layers and two insulating dielectric layers. The transparent conductive layers play a role in current expansion and prevent current accumulation.

[0265] Heat dissipation: A conductive heat sink layer that combines good heat dissipation and conductivity.

[0266] As shown in the comparative examples above, this invention provides a dual-dielectric DBR type vertical-cavity surface-emitting laser and its fabrication method. By replacing the traditional epitaxial DBR technology route with a dual-dielectric DBR plus a transparent conductive layer, the pressure of epitaxy (especially on InP and GaN-based lasers) is alleviated, while a resonant cavity with higher reflectivity can be formed to achieve better confinement of the optical field. Simultaneously, two symmetrical insulating dielectric layers are set above and below the active structure layer, and the current-limiting aperture size is precisely controlled through photolithography to improve current confinement, optimize current injection efficiency, and effectively avoid the impact of oxidation processes on the current-limiting window in the original VCSEL route. The introduction of the transparent conductive layer effectively achieves current expansion to a certain extent, avoiding the heat generation and efficiency reduction caused by current blockage. Replacing the original substrate with a conductive heat sink layer achieves good heat dissipation while creating a vertically continuous conductive channel in the overall device, resulting in higher current injection efficiency and improved output power and conversion efficiency. This invention has a simple process, a planar structure, good optical and electrical confinement, and good heat dissipation, which can increase the working current density and optical power of the device.

[0267] Although the invention has been described to a certain extent, it is apparent that appropriate variations can be made to the various conditions without departing from the spirit and scope of the invention. It is understood that the invention is not limited to the described embodiments, but falls within the scope of the claims, which include equivalent substitutions for each of the elements.

Claims

1. A dual-dielectric DBR type vertical-cavity surface-emitting laser, characterized in that, The dual-dielectric DBR type vertical cavity surface-emitting laser comprises, from bottom to top, the following: A conductive heat sink layer with heat dissipation and conductivity; First metal electrode; A first dielectric DBR layer distributed at intervals from the first metal electrode; First transparent conductive layer for current spreading; A first insulating dielectric layer, and a first current window is formed in the middle of the first insulating dielectric layer; Active structural layer; A second insulating dielectric layer is formed, and a second current window is formed in the middle of the second insulating dielectric layer; A second transparent conductive layer for current spreading; and The second metal electrode has a light-emitting window formed in the middle, and the second metal electrode and the second dielectric DBR layer are distributed alternately between the second metal electrode and the second transparent conductive layer. Furthermore, the active structure layer comprises, from bottom to top, the following: p-type semiconductor layer; Active layer; and n-type semiconductor layer; Meanwhile, the reflectivity of the first dielectric DBR layer is greater than 99%, and the reflectivity of the second dielectric DBR layer is greater than 98% and less than the reflectivity of the first dielectric DBR. The first dielectric DBR layer and the second dielectric DBR layer are made of dielectric material pairs; the refractive index difference of the dielectric material pairs is not less than 0.1; the resistivity of the first transparent conductive layer and the second transparent conductive layer is less than 0.05 Ω·cm, and the transmittance for the laser emission center wavelength is greater than 70%.

2. The dual-dielectric DBR type vertical-cavity surface-emitting laser according to claim 1, characterized in that, A bonding layer is also included between the conductive heat sink layer and the first metal electrode.

3. The dual-dielectric DBR type vertical-cavity surface-emitting laser according to claim 1, characterized in that: The first dielectric DBR layer, the second dielectric DBR layer, the first transparent conductive layer, and the second transparent conductive layer form an optical confinement layer; The first transparent conductive layer, the second transparent conductive layer, the first insulating dielectric layer, and the second insulating dielectric layer form a current limiting layer; The materials of the first metal electrode and the second metal electrode are selected from one or more of the following: gold, aluminum, nickel, titanium, zinc, platinum, silver, copper, chromium, germanium, palladium, cobalt, and tungsten; The materials of the first dielectric DBR layer and the second dielectric DBR layer are selected from one or more of the following: silicon oxide, silicon nitride, nickel oxide, aluminum oxide, aluminum nitride, niobium oxide, titanium oxide, and hafnium oxide; The materials of the first transparent conductive layer and the second transparent conductive layer are selected from one or more of the following: ITO, zinc oxide, silicon carbide, graphene, conductive polymer, and thin-layer metal; The materials of the first insulating dielectric layer and the second insulating dielectric layer are selected from one or more of the following: silicon nitride, silicon oxide, silicon oxynitride, nickel oxide, aluminum oxide, aluminum nitride, and boron nitride in single or multilayer form; The active layer is made of one or more of the following materials: silicon, germanium, gallium nitride, gallium arsenide, indium phosphide, silicon carbide, germanium silicide / silicon quantum well, indium gallium nitride / gallium nitride quantum well, indium gallium arsenide / gallium arsenide quantum well, aluminum gallium arsenide / gallium arsenide quantum well, indium gallium arsenide / aluminum gallium arsenide quantum well, silicon quantum dot, germanium quantum dot, gallium nitride quantum dot, gallium arsenide quantum dot, indium phosphide quantum dot, germanium silicide quantum dot, indium gallium nitride quantum dot, indium gallium arsenide quantum dot, aluminum gallium arsenide quantum dot, indium gallium arsenide quantum dot; and / or The conductive heat sink layer is selected from one or more of the following: single metal substrate, alloy substrate, and ceramic substrate.

4. The dual-dielectric DBR type vertical-cavity surface-emitting laser according to claim 3, characterized in that: The materials of the first metal electrode and the second metal electrode are selected from one or more of the following: gold, titanium, nickel, aluminum, silver, chromium, and platinum; The materials of the first transparent conductive layer and the second transparent conductive layer are selected from one or more of the following: ITO, zinc oxide, silicon carbide, graphene, silver, aluminum, copper, and gold; The materials of the first insulating dielectric layer and the second insulating dielectric layer are selected from one or more of the following: silicon nitride, silicon oxide, and aluminum oxide; The active layer is made of one or more of the following materials: germanium silicide / silicon quantum well, indium gallium nitride / gallium nitride quantum well, indium gallium arsenide / gallium arsenide quantum well, aluminum gallium arsenide / gallium arsenide quantum well, indium gallium arsenide / aluminum gallium arsenide quantum well; and / or The material of the single metal substrate is selected from one or more of the following: gold, copper, aluminum, silver; the material of the alloy substrate is selected from one or more of the following: molybdenum copper, tungsten copper, chromium copper; and / or the material of the ceramic substrate is selected from one or more of the following: aluminum nitride, diamond, silicon carbide.

5. The dual-dielectric DBR type vertical-cavity surface-emitting laser according to claim 4, characterized in that: The materials of the first metal electrode and the second metal electrode are selected from one or more of the following: gold, titanium, nickel, and platinum; The materials of the first transparent conductive layer and the second transparent conductive layer are: ITO or zinc oxide; The materials of the first insulating dielectric layer and the second insulating dielectric layer are silicon nitride or silicon oxide; The active layer is made of one or more of the following materials: indium gallium nitride / gallium nitride quantum well, indium gallium arsenide / gallium arsenide quantum well, aluminum gallium arsenide / gallium arsenide quantum well, indium gallium arsenide / aluminum gallium arsenide quantum well; and / or The thermal conductivity of the ceramic substrate is greater than 300 W / (m·K).

6. A method for preparing a dual-dielectric DBR type vertical-cavity surface-emitting laser according to any one of claims 1 to 5, characterized in that, The method includes the following steps: (1) Prepare an initial active structure layer comprising a p-type semiconductor layer, an active layer, and an n-type semiconductor layer; (2) On the p-type semiconductor layer of the initial active structure layer prepared in step (1), a first insulating dielectric layer, a first transparent conductive layer, a first dielectric DBR layer and a first metal electrode are sequentially prepared; (3) A conductive heat sink layer is prepared on the first metal electrode prepared in step (2), exposing the n-type semiconductor layer of the active structure layer; and (4) A second insulating dielectric layer, a second transparent conductive layer, a second dielectric DBR layer, and a second metal electrode are sequentially prepared on the n-type semiconductor layer exposed in step (3) to obtain the dual dielectric DBR type vertical cavity surface emission laser.

7. The method according to claim 6, characterized in that, Step (1) also includes the following steps: (a) Selection of wafer substrate; and (b) A buffer layer, a selection stop layer, an n-type semiconductor layer, an active layer and a p-type semiconductor layer are grown sequentially on the wafer substrate of step (a) to obtain the initial active structure layer.

8. The method according to claim 7, characterized in that, In step (1): In step (a), the wafer substrate is selected from one or more of the following: gallium arsenide, silicon, germanium, gallium nitride, indium phosphide, silicon carbide, sapphire; and / or In step (b), the growth method is epitaxial growth.

9. The method according to claim 8, characterized in that, In step (1): In step (a), the wafer substrate is selected from one or more of the following: gallium arsenide, silicon, gallium nitride, indium phosphide; and / or In step (b), the epitaxial growth is selected from one or more of the following: organometallic chemical vapor deposition, molecular beam epitaxy, vapor phase epitaxy, and liquid phase epitaxy.

10. The method according to claim 9, characterized in that, In step (b), the epitaxial growth is metal-organic chemical vapor deposition and / or molecular beam epitaxy.

11. The method according to any one of claims 6 to 10, characterized in that, In step (2): The method for preparing the first insulating dielectric layer is selected from one or more of the following: atomic layer deposition, sputtering, chemical vapor deposition, physical vapor deposition, and ion beam evaporation; The preparation method of the first transparent conductive layer is selected from one or more of the following: sputtering, evaporation, ion plating, wet coating, sol-gel method, high-temperature pyrolysis spraying, chemical vapor deposition, and high-temperature pyrolysis spraying; The first metal electrode is prepared by deposition. Before preparing the first transparent conductive layer, the method further includes: preparing a first pattern on the first insulating dielectric layer, using the first pattern as a mask to etch or corrode the first insulating dielectric layer down to the p-type semiconductor layer to form a first current window; Before fabricating the first metal electrode, the method further includes: fabricating a second pattern on the first dielectric DBR layer; using the second pattern as a mask, etching or corroding the first dielectric DBR layer down to the first transparent conductive layer to form a first electrode hole; and / or The first metal electrode covers the first dielectric DBR layer and the first transparent conductive layer at the bottom of the first electrode hole.

12. The method according to any one of claims 6 to 10, characterized in that, In step (4): The method for preparing the second insulating dielectric layer is selected from one or more of the following: atomic layer deposition, sputtering, chemical vapor deposition, physical vapor deposition, and ion beam evaporation; The preparation method of the second transparent conductive layer is selected from one or more of the following: sputtering, evaporation, ion plating, wet coating, sol-gel method, high-temperature pyrolysis spraying, chemical vapor deposition, and high-temperature pyrolysis spraying; The second metal electrode is prepared by deposition. Before preparing the second transparent conductive layer, the method further includes: preparing a third pattern on the second insulating dielectric layer, using the third pattern as a mask to etch or corrode the second insulating dielectric layer to an n-type semiconductor layer to form a second current window; Before fabricating the second metal electrode, the method further includes: fabricating a fourth pattern on the second dielectric DBR layer; using the fourth pattern as a mask, etching or corroding the second dielectric DBR layer down to the second transparent conductive layer to form a second electrode hole; and / or A fifth pattern is fabricated on the second dielectric DBR layer. Using the fifth pattern as a mask, the second metal electrode is deposited. The second metal electrode covers the second dielectric DBR layer and the second transparent conductive layer at the bottom of the second electrode hole, and a light-emitting window is formed in the middle of the second dielectric DBR layer.

13. The method according to any one of claims 6 to 10, characterized in that: In step (2), the first insulating dielectric layer is prepared by: directly preparing it on a p-type semiconductor layer or by preparing it as a buried layer; and / or In step (4), the second insulating dielectric layer is prepared by either directly preparing it on an n-type semiconductor layer or by preparing it as a buried layer.

14. The method according to claim 13, characterized in that: The method for preparing the buried layer of the first insulating dielectric layer is as follows: etching the p-type semiconductor layer and then preparing the first insulating dielectric layer; and / or The method for preparing the buried layer of the second insulating dielectric layer is as follows: after etching the n-type semiconductor layer, the second insulating dielectric layer is prepared.

15. The method according to any one of claims 6 to 10, characterized in that, Step (3) also includes: (c) A bonding layer is prepared on the first metal electrode; (d) The bonding layer prepared in step (c) is bonded to the conductive heat sink to obtain a bonding structure; and (e) Remove the wafer substrate, buffer layer and selection stop layer of the bonding structure obtained in step (d) to expose the surface of the n-type semiconductor layer of the active structure layer.

16. The method according to claim 15, characterized in that: In step (c), the material of the bonding layer is selected from one or more of the following: gold-tin, indium, copper-tin, gold-silicon, silver, and curing adhesive; In step (d), the bonding method is selected from one or more of the following: metal diffusion bonding, metal eutectic bonding, low-temperature direct bonding, and plasma-assisted bonding; and / or In step (e), the removal method for the wafer substrate and the buffer layer is selected from one or more of the following: substrate thinning method, chemical mechanical polishing method, wet etching method, dry etching method, and laser lift-off method.

17. The method according to claim 16, characterized in that, In step (e), the removal method for the wafer substrate and the buffer layer is a wet etching method or a laser lift-off method; the removal method for the selected stop layer is a wet etching method or a dry etching method.

18. The method according to any one of claims 6 to 10, characterized in that, Step (3) also includes: (f) Electroplating a thick metal layer onto the first metal electrode to obtain a conductive heat-absorbing layer; and (g) Remove the wafer substrate, buffer layer and selection stop layer of the initial active structure layer prepared in step (1) to expose the surface of the n-type semiconductor layer of the active structure layer.

19. The method according to claim 18, characterized in that: In step (f), the metal used for electroplating is selected from one or more of the following: copper, gold, chromium, nickel, zinc, silver, titanium; and / or In step (g), the removal method for the wafer substrate and the buffer layer is selected from one or more of the following: substrate thinning method, chemical mechanical polishing method, wet etching method, dry etching method, and laser lift-off method.

20. The method according to claim 19, characterized in that: In step (f), the metal being electroplated is: copper or chromium; and / or In step (g), the removal method for the wafer substrate and the buffer layer is a wet etching method or a laser lift-off method; the removal method for the selected stop layer is a wet etching method or a dry etching method.

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