Ldpc decoder, decoding method, and electronic device

Abstract

The application provides an LDPC decoder, a decoding method and an electronic device. The method obtains channel messages of a code word and an index value, and cyclically shifts the channel messages based on the index value. First feedback information is generated, the first feedback information being feedback information from a variable node to a check node. Second feedback information is generated according to the first feedback information, the second feedback information being compressed feedback information from the check node to the variable node. Third feedback information is generated, the third feedback information being updated channel messages, and a decoding result is generated according to the third feedback information. A parity check is performed on the decoding result to output a parity check result, and if the parity check result is low, the decoding result is output. The method can adapt to changes in multiple code rates and code lengths by using different decoding configurations, simplifies the decoding process, and is compatible with different applications, thereby solving the problem of low flexibility of an LDPC decoder.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to an LDPC decoder, decoding method, and electronic device. Background Technology

[0002] 5G NR (New Radio) is one of the standards for mobile communication networks. Wi-Fi provides high-density wireless connectivity within a local area network. Both 5G NR and Wi-Fi aim to provide higher data transmission rates for electronic devices. Furthermore, to support Ultra Reliable Low Latency Communication (URLLC), eMBB, and massive machine-type communication (mMTC) scenarios, 5G NR requires channel coding and error correction technologies to complete data transmission and error correction in a short time.

[0003] Channel coding is used to protect data integrity in the presence of noise and interference. In 5G NR, two main channel coding schemes are employed. LDPC (Low-Density Parity-Check) achieves efficient error correction through a sparse parity-check matrix, achieving near-Shannon limit performance at a relatively low signal-to-noise ratio (SNR). LDPC decoders are optimized for a single communication standard, enabling high performance in a single application scenario.

[0004] However, LDPC decoders only support specific block sizes and code rates. When the scenario changes, such as changes in code length or code rate, they cannot be used in the new scenario. Furthermore, some LDPC decoders can support some 5G NR code rates but are not compatible with LDPC decoding in Wi-Fi mode and cannot support decoding of multi-rate LDPC codes. Therefore, LDPC decoders cannot adapt to application scenarios such as 5G NR and Wi-Fi, resulting in low flexibility. Summary of the Invention

[0005] This application provides an LDPC decoder, decoding method, and electronic device to solve the problem of low flexibility in LDPC decoders.

[0006] In a first aspect, this application provides an LDPC decoder, comprising:

[0007] The first storage unit is used to receive and buffer the input channel messages;

[0008] The first shift unit is used to receive the index value and cyclically shift the channel message based on the index value;

[0009] The processing unit includes a variable node processing module and a check node processing module. The variable node processing module is used to generate first feedback information based on the output of the first shift unit. The first feedback information is feedback information from the variable node to the check node.

[0010] The inspection node processing module is used to generate second feedback information based on the first feedback information. The second feedback information is feedback information from the inspection node to the variable node, and is compressed feedback information.

[0011] The channel message update module is used to generate third feedback information, which is the updated channel message;

[0012] A parity check unit is used to generate a decoding result based on the third feedback information, and to perform parity check on the decoding result to output a parity check result. If the parity check result is low, the decoding result is output.

[0013] In some feasible embodiments, it also includes:

[0014] A multiplexer, connected to the variable node processing module, is used to receive the first feedback information;

[0015] If the multiplexer receives the first feedback information, it outputs the first feedback information to the first storage unit;

[0016] If the multiplexer does not receive the first feedback information, it outputs the channel message to the first storage unit.

[0017] In some feasible embodiments, it also includes:

[0018] The second storage unit is used to store the second feedback information;

[0019] The first decompression unit is used to decompress the second feedback information and input the decompressed second feedback information into the variable node processing module.

[0020] The variable node processing module is also used to output variable node information based on the decompressed second feedback information, wherein the bit width of the variable node information is different from that of the first feedback information.

[0021] In some feasible embodiments, it also includes:

[0022] The second decompression unit is used to decompress the second feedback information and input the decompressed second feedback information into the channel message update module so as to generate a decoding result through the channel message update module;

[0023] The second shift unit is used to shift the updated channel message and transmit the shifted channel message to the multiplexer.

[0024] In some feasible embodiments, the check node processing module is further configured to obtain a first value, a second value, and a first value index based on the first feedback information, wherein the first value is the smallest first feedback information among the variable nodes, the second value is the smallest first feedback information other than the first value, and the bit width of the first value index is the maximum row weight bit width, wherein the row weight is the number of valid elements in a row of the check matrix;

[0025] Based on the first feedback information, the sign bit is determined, and the bit width of the sign bit is the maximum row overlap value;

[0026] The inspection node processing module is further configured to perform an XOR operation between the first feedback information and the sign bit to output the second feedback information.

[0027] Secondly, this application provides a decoding method, including:

[0028] Obtain the channel message and index value of the variable node, and cyclically shift the channel message based on the index value;

[0029] Generate first feedback information, which is feedback information from the variable node to the inspection node;

[0030] Based on the first feedback information, a second feedback information is generated, which is a compressed feedback information from the inspection node to the variable node.

[0031] Generate a third feedback message, which is the updated channel message;

[0032] Generate decoding results based on the third feedback information;

[0033] Perform parity checking on the decoding result and output the parity check result;

[0034] If the parity check result is low, output the decoding result.

[0035] In some feasible embodiments, before obtaining the channel message and index value of the variable node, the following steps are included:

[0036] Obtain the reset signal;

[0037] In response to the reset signal being pulled low, a reset operation is performed until the reset is completed. Then, the reset signal is pulled high to generate configuration information, which includes a boost factor and a control word.

[0038] After generating decoding information based on the configuration information, the reset signal is pulled low, and the first storage unit is cleared.

[0039] In some feasible embodiments, obtaining the channel message and index value of the variable node includes:

[0040] When the first storage unit receives and buffers the input channel message, it pulls up the input information valid signal and transmits the channel message to the first shift unit.

[0041] In some feasible embodiments, the method further includes:

[0042] When the channel message update module generates the decoding result, the enable signal is pulled high;

[0043] When the parity check result output by the parity check unit is low, the valid signal for output information is pulled high.

[0044] Thirdly, this application provides an electronic device, comprising:

[0045] Memory, used to store programs;

[0046] A processor for executing the program, specifically for implementing the decoding method described in any one of the second aspects.

[0047] As can be seen from the above technical solutions, this application provides an LDPC decoder, decoding method, and electronic device. The method acquires the channel message and index value of a variable node, and cyclically shifts the channel message based on the index value; then generates first feedback information, which is feedback information from the variable node to the check node; based on the first feedback information, generates second feedback information, which is compressed feedback information from the check node to the variable node; generates third feedback information, which is the updated channel message; generates a decoding result based on the third feedback information; performs parity checking on the decoding result to output a parity check result; if the parity check result is low, the decoding result is output. This method, by acquiring the channel message and index value of the variable node, can adapt to changes in multiple code rates and code lengths, simplifies the decoding process, and is compatible with different applications, thus solving the problem of low flexibility in LDPC decoders. Attached Figure Description

[0048] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1This is a schematic diagram of the LDPC decoder provided in the embodiments of this application;

[0050] Figure 2 This is a schematic diagram of the hardware output of the LDPC decoder provided in an embodiment of this application;

[0051] Figure 3 This is a schematic diagram of a WIFI verification matrix provided in an embodiment of this application;

[0052] Figure 4 A schematic diagram of the first compressed C2V message provided in an embodiment of this application;

[0053] Figure 5 A schematic diagram of a second-compressed C2V message provided in an embodiment of this application;

[0054] Figure 6 A flowchart illustrating the output decoding results provided in an embodiment of this application;

[0055] Figure 7 This is a schematic diagram of the index flow provided in the embodiments of this application;

[0056] Figure 8 This is a flowchart illustrating the decoding method provided in an embodiment of this application. Detailed Implementation

[0057] The embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described below do not represent all embodiments consistent with this application. They are merely examples of systems and methods consistent with some aspects of this application as detailed in the claims.

[0058] An LDPC decoder is a device or algorithm used to decode LDPC codes, recovering the original transmitted data as accurately as possible from a noisy received signal. In a single application scenario, LDPC decoders are specifically optimized for a particular data block size (Lift Size, Zc) and code rate, thus achieving high performance. These decoders employ fixed hardware architectures and algorithms, fine-tuned to maximize performance advantages. However, they can only operate under specific conditions; once the scenario changes, such as changes in code length or code rate, the existing decoder cannot adapt to the new requirements.

[0059] Because the hardware architecture and algorithms of LDPC decoders are customized for specific application scenarios, they cannot flexibly adapt to new bitrates and data block sizes. For example, if a decoder is designed to process data blocks of a specific length, its performance may degrade or even fail to function properly when the block length changes. Similarly, if a decoder is designed for a specific bitrate, it will be unable to effectively process new data when the bitrate changes.

[0060] Furthermore, different communication standards have different requirements; for example, 5G NR and Wi-Fi differ in block size, bit rate, and other aspects. Therefore, a separate decoder must be designed for each standard. This not only increases costs but also makes the manufacturing process more complex.

[0061] Some LDPC decoders can support some code rates in 5G NR, but due to the significant differences between 5G NR and Wi-Fi in terms of block size, code rate, etc., these decoders often struggle to support both. To support multi-code-rate LDPC decoding, decoders need greater flexibility and configurability, requiring more complex hardware and software designs. Therefore, while some decoders can support some code rates in 5G NR, they may not be fully compatible with LDPC decoding in Wi-Fi mode, nor can they support all possible code rate combinations. In summary, the reason LDPC decoders perform well in a single application scenario is that they are optimized for specific conditions, but this also results in low flexibility.

[0062] To address the low flexibility of LDPC, see [link / reference]. Figure 1 , Figure 2 This application provides an LDPC decoder in some embodiments, including: a first storage unit, a first shift unit, a processing unit, a channel message update module, and a parity check unit. The decoder can simultaneously support different code lengths and code rates in both 5G NR and WIFI scenarios.

[0063] The first storage unit, which can be one or more memory regions, such as RAM, ROM, or other types of storage media, is used to receive and buffer the input channel message (ch_llr). In the LDPC decoding process, the channel message is represented in the form of a log-likelihood ratio (LLR), which is the log ratio of the probability that the received bit of the channel message is 0 or 1. The LLR value is input into the first storage unit as the channel message for subsequent iterative decoding processes.

[0064] The first shift unit is a barrel shifter, used to receive index values ​​and cyclically shift the channel messages based on these index values. At the input of the LDPC decoder, these code blocks are processed as input data. The code blocks (i.e., the received encoded data blocks) are first converted into channel messages (LLR values). These LLR values, serving as the starting point of the decoding process, are stored in the first storage unit and subsequently shifted by the barrel shifter. The code blocks are LDPC-encoded data blocks received from the channel. These data blocks are encoded before transmission to increase redundancy, enabling error detection and correction at the receiving end.

[0065] By shifting channel messages using a barrel shifter, the decoding process can be made more efficient and flexible. This allows the decoder to appropriately rearrange and preprocess the received data according to the structure and characteristics of the LDPC code, thereby improving decoding performance.

[0066] The processing unit includes a variable node processing module and an inspection node processing module.

[0067] The variable node processing module generates first feedback information (v2c) based on the output of the first shift unit. This first feedback information is the feedback information from the variable node to the check node. Here, the variable node represents either the encoded bit or the information bit. During the decoding process, each variable node collects information from its neighboring check nodes and updates its own state based on this information. The variable node processing module implements the variable node update algorithm, such as a variant of the product-sum algorithm (SPA) or the minimum-sum algorithm (MSA).

[0068] The update formula for the first feedback information v2c is as follows:

[0069] v2c = app - c2v old ;

[0070] In the first iteration, app (A Posteriori Probability) is initialized to ch_llr (channel llr, channel probability), c2v old It is initialized to 0. It outputs v2c messages (9 bits) and variable node messages (10 bits). The v2c messages are passed to the check node processing module, and the variable node messages are passed to the first storage unit for storage.

[0071] The check node processing module generates second feedback information (C2V) based on the first feedback information. The second feedback information is compressed feedback from the check node to the variable node. For example, the check node processing module handles calculations related to the check node, receives messages from the variable node, and generates new messages based on these messages, sending them to the variable node.

[0072] In some embodiments, the check node processing module obtains a first value min1, a second value min2, and a first value index min1_idx based on the first feedback information. The first value is the smallest first feedback information among the variable nodes, and the second value is the smallest first feedback information other than the first value. Based on the input first feedback information, the check node processing module determines a sign bit sign_reg, the width of which is the maximum row overlap value. The check node processing module is also used to perform an XOR operation on the first feedback information and the sign bit to output the second feedback information.

[0073] The first-value index has a bit width equal to the maximum row-weight bit width, which is 5 bits. The first-value index is the index of the effective codeword for each layer, ranging from 0 to `row_degree` to 1. `sign_reg` is the sign bit of the effective codeword for each layer, with a bit width of `row_degree`. For compatibility reasons, the maximum `row_degree` is 22, where Z = 27 and R = 5 / 6 in the WIFI protocol table F-1. Figure 3 As shown, min1_idx has a bit width of 5 bits, and sign_reg has a bit width of 22 bits, meaning the maximum row weight is 22 bits.

[0074] The update of the second feedback information is based on a simplified form of the Min-Sum algorithm, an LDPC decoding algorithm that decodes by comparing and selecting the minimum value. The Min-Sum algorithm improves hardware friendliness and reduces computational complexity. The formula for updating the second feedback information is as follows:

[0075]

[0076] Among them, V c Let V be the set of all variable nodes connected to the current check node c, and let V be the specific variable node currently being considered. c \v represents the set V c The set obtained after removing element V is the set of all variable nodes connected to the current verification node c, excluding V. v′ This refers to the message from variable node v′ to check node c (i.e., v2c).

[0077] In other words, the verification node updates its own state based on the messages received from the variable nodes and sends the updated state back to the corresponding variable nodes. This is an iterative process. In each iteration, the verification node recalculates its own state based on the latest message received until it reaches a stable state or the maximum number of iterations is reached. In this embodiment, the maximum number of iterations is 63.

[0078] See Figure 4 , Figure 5 After secondary compression, that is, XORing each bit in Xor and sign_reg, the c2v message (43 bits) is output while satisfying compatibility.

[0079] Since the C2V message has already been compressed in the check node processing module, in some embodiments, the decoder further includes a second storage unit and a first decompression unit for storing and decompressing the C2V message compression. The second storage unit stores the second feedback information, and like the first storage unit, it can be one or more memory regions. The first decompression unit decompresses the second feedback information and inputs the decompressed second feedback information to the variable node processing module. The first decompression unit may contain dedicated hardware logic, such as logic blocks in an FPGA or software algorithms, for executing the decompression algorithm. The first decompression unit restores the compressed C2V message to a 9-bit C2V message.

[0080] The variable node processing module is also used to output variable node information based on the decompressed second feedback information, and then perform variable node update operations based on the variable node information, such as calculating new LLR values ​​and updating the node status. The bit width of the variable node information differs from that of the first feedback information; the first feedback information has a bit width of 9 bits, while the variable node information has a bit width of 10 bits.

[0081] For example, during the decoding process, the verification node processing module generates and compresses the second feedback information and stores it in the second storage unit. When a variable node needs to be updated, the first decompression unit reads the compressed second feedback information from the second storage unit and decompresses it. The decompressed second feedback information is input to the variable node processing module, which performs an update operation based on this information and other possible inputs, such as the first feedback information. The variable node processing module outputs the updated variable node information, which is used for subsequent decoding iterations or the final decoding decision.

[0082] Through the second storage unit and the first decompression unit, the decoder can process the compressed feedback information, reducing storage and transmission costs. Simultaneously, the variable node processing module can handle information of varying widths, enhancing the decoder's adaptability.

[0083] The channel message update module is used to generate the third feedback information, which is the updated channel message. The third feedback information is the result of summing the first and second feedback information. The generation of the third feedback information is shown in the following formula:

[0084] app new =v2c+c2v new ;

[0085] Among them, v2c is the first feedback information, and c2v new This is the second feedback message.

[0086] join Figure 6 The parity check unit generates the decoding result based on the third feedback information and performs parity check on the decoding result (S301) to output the parity check result. The parity check unit may include check logic to verify the correctness of the decoding result. If the parity check result is low, the decoding result is output (S302), and the iteration stops. If the parity check result is high, decoding continues (S302). If the decoding reaches the maximum number of iterations without meeting the check condition, decoding stops, and the current decoding result is output.

[0087] In some embodiments, the system further includes: a multiplexer connected to a variable node processing module, configured to receive first feedback information; if the multiplexer receives the first feedback information, it outputs the first feedback information to a first storage unit; if the multiplexer does not receive the first feedback information, it outputs a channel message to the first storage unit.

[0088] A multiplexer is a digital circuit that allows selection of one signal from multiple input signals and transmission to a single output line. It is controlled by a selection signal that determines which input signal is selected. A multiplexer includes multiple input ports, one or more selection ports, and one output port. In this embodiment, multiple input signals from different sources (e.g., a variable node processing module or other inputs) are received, and one of them is selected for output based on a control signal.

[0089] For example, if the variable node processing module generates first feedback information based on the shifted channel message, the multiplexer receives the first feedback information and outputs it to the first storage unit. If the multiplexer does not receive the first feedback information, it outputs the channel message to the first storage unit.

[0090] In some embodiments, the decoder further includes a second decompression unit and a second shift unit. The second decompression unit is used to decompress the second feedback information and input the decompressed second feedback information to the channel message update module to generate third feedback information through the channel message update module, wherein the third feedback information is the updated channel message. The second shift unit is used to shift the updated channel message and transmit the shifted channel message to the multiplexer.

[0091] Similar to the first decompression unit, the second decompression unit may contain dedicated hardware logic, such as logic blocks or software algorithms in an FPGA, for executing the decompression algorithm. The second decompression unit processes the compressed data, receives the compressed second feedback information, and restores it to its original format using the decompression algorithm. In other words, after the verification node processing module generates the compressed second feedback information, it sends it to both the second storage unit and the second decompression unit.

[0092] After the channel message update module generates the third feedback information, it is sent to the second shift unit. The second shift unit, similar to the first shift unit, can be a barrel shifter. The second shift unit shifts the decoding result, and the shifted third feedback information is transmitted to the multiplexer. Understandably, the multiplexer can also output the third feedback information as an input to the first storage unit, depending on requirements.

[0093] See Figure 7 The first shift unit acquires an index value, idx, which is an integer indicating the position of the code block within the entire code frame. For example, if idx = 0, it indicates that the codeword is the first code block in the entire code frame. It's important to note that idx starts counting from 0, and idx > 0. This index value is provided by an external controller to manage the decoder's behavior.

[0094] In some embodiments, the control information required for decoding can also be generated by a decoding state machine.

[0095] The proposed LDPC decoder features a highly flexible hardware architecture, allowing it to adapt to various application scenarios without requiring hardware redesign. During use, switching to different scenarios is as simple as configuring the scenario control word, lift_size, and maximum iteration count. Furthermore, within the existing framework, new application scenarios can be supported by redesigning the configuration information memory and the mapping relationship between the control word and memory within the hardware itself, without requiring a complete redesign of other parts of the decoder.

[0096] See Figure 8 This application provides a decoding method, including:

[0097] S100: Obtain the channel message and index value of the variable node, and cyclically shift the channel message based on the index value.

[0098] In some embodiments, before acquiring channel messages, a reset (rst_n) signal is acquired first; then, in response to the reset signal being pulled low, a reset operation is performed until the reset is completed, the reset signal is pulled high, configuration information is generated, the configuration information includes a lift factor (lift_size) and a control word (mode), where lift_size determines the size and structure of the parity check matrix, and mode contains other configuration information, such as the selected parity check matrix information; after generating decoding information based on the configuration information, the reset signal is pulled low, and the first memory unit is cleared.

[0099] The control word is a 6-bit binary number used to specify the scenario and BaseGraph (BG) configuration. The two highest bits (the most significant and second-highest bits) define the selected scenario, and the four lowest bits (the remaining four bits) define the specific background configuration. The two highest bits: 00 indicates 5G NR BaseGraph 1; 01 indicates 5G NR BaseGraph 2; 10 indicates WiFi BaseGraph. The four lowest bits are used to further differentiate the specific background configuration for each scenario. For example, in a 5G NR scenario, there can be multiple different BaseGraph configurations, such as radix-2, radix-3, etc. Similarly, different configurations can be used in a WiFi scenario.

[0100] This mode control word allows the decoder to select the appropriate configuration based on different application scenarios and requirements. For example, when the Mode value is 000000, it indicates that the first configuration in 5G NR BaseGraph 1 has been selected; when the Mode value is 000001, it indicates that the second configuration in 5G NR BaseGraph 1 has been selected. Mode provides sufficient flexibility, allowing the decoder to switch to different operating modes and configurations as needed to adapt to different wireless environments and technical requirements.

[0101] For example, before acquiring channel messages, configuration information such as control words and boosting factors containing scene information is sent to the decoder. The decoder will configure the decoding information accordingly and initialize or reset the state inside the decoder in order to prepare for the new iterative decoding process.

[0102] During decoding initialization, five initial addresses are obtained: COL_IDX_MEMORY (column index memory), SHIFTER_NUBER_MEMORY (shift factor memory), ROW_DEGREE_MEMORY (row weight memory), H_SHIFTER_MEMORY (parity check matrix shift factor memory), and H_MATRIX_MEMORY (parity check matrix valid element memory). During the decoding process, the information required for decoding is read sequentially starting from the initial addresses, and the process returns to the initial addresses after one iteration.

[0103] The column index memory (COL_IDX_MEMORY) stores the index information for each column of the parity check matrix (H matrix). These indexes indicate which variable nodes are associated with a specific parity check node. During decoding, based on this index information, the decoder can determine which variable nodes need to participate in the calculation of the current parity check node.

[0104] The shift factor memory (SHIFTER_NUMBER_MEMORY) stores the shift factors associated with each parity check node. These shift factors indicate how many bits need to be cyclically shifted during message passing. During iterative decoding, the decoder can correctly cyclically shift the message according to these numbers to fit the structure of the parity check matrix.

[0105] The row-weight memory (ROW_DEGREE_MEMORY) stores the number of valid blocks in each row of the parity check matrix. The number of valid blocks indicates how many variable nodes that row is associated with. During decoding, based on this row-weight information, the decoder can determine how many messages each parity check node needs to process.

[0106] The parity check matrix shift factor memory (H_SHIFTER_MEMORY) stores shifter information associated with the parity check matrix. This information typically includes the number of shifts required for each row or column. During iterative decoding, the decoder uses this shift information to correctly adjust cyclic shifts in message passing.

[0107] The H_MATRIX_MEMORY memory is used to store the complete valid elements of the parity-check matrix (H matrix). The parity-check matrix defines the connection relationships between variable nodes and parity nodes. During decoding, based on the parity-check matrix, the decoder can determine which variable nodes are connected to which parity nodes, thus enabling correct message passing and updates.

[0108] The decoding configuration memory (ROM) retrieves five initial addresses from the ROM during decoding initialization. These addresses point to the starting locations of the five memory types mentioned above. During decoding, the required information is read sequentially from these initial addresses. After one iteration, the process returns to the initial addresses to start the next iteration.

[0109] Next, the channel message is acquired. Before the first storage unit receives and buffers the input channel message, the configuration enable (initial_en) signal is pulled high. initial_en is a control signal used to indicate whether the configuration information is valid. After the configuration information is input, the initial_en signal is pulled low. After the configuration information is input, the decoder is ready to receive the data to be decoded.

[0110] Input the data to be decoded by pulling the input_valid signal high. input_valid is a control signal used to indicate whether the data to be decoded is valid, representing the data about to be input. Input ch_llr, which is the maximum likelihood probability of the channel to be decoded. One code block is input per cycle, and each code block contains 384 maximum likelihood probabilities. When lift_size is less than 384, the high-order bits are padded with 0. That is, if lift_size is less than 384, the lift factor is insufficient to cover 384 bits, so the high-order bits are padded with 0 to meet the requirements of the parity-check matrix.

[0111] S200: Generate the first feedback information.

[0112] The first feedback information is the feedback information from the variable node to the check node. It can be understood that the process of generating the first feedback information can be referred to the process of generating the first feedback information in the variable node processing module of the LDPC decoder in the above embodiment, and will not be described in detail here.

[0113] S300: Generate second feedback information based on the first feedback information.

[0114] The second feedback information is compressed feedback information from the check node to the variable node. It is understood that the process of generating the second feedback information can be found in the process of the check node processing module generating the second feedback information in the LDPC decoder of the above embodiment, and will not be elaborated here.

[0115] S400: Generate third feedback information.

[0116] The third feedback information is the result of summing the first and second feedback information. It is understood that the process of generating the third feedback information can be found in the process of the channel message update module generating the third feedback information in the LDPC decoder of the above embodiment, and will not be elaborated here.

[0117] S500: Generates decoding results based on the third feedback information, performs parity checking on the decoding results, and outputs the parity check results.

[0118] S600: If the parity check result is low, output the decoding result.

[0119] Output the parity check result (parity_code_check). If parity_code_check is low, it means that the decoding meets the check condition and the iteration stops; otherwise, continue decoding.

[0120] In some embodiments, an external enable signal (output_en) is pulled high; when the output_en signal is pulled high and decoding is complete, the output_valid signal is pulled high. The output_valid signal indicates whether the output data is valid, and the decoded data is output at the same time. 128 bits are output per cycle, that is, a part of the decoding result is output each time.

[0121] It is understood that the decoding process can be referred to the LDPC decoder process in the above embodiment, and will not be repeated here.

[0122] This application also provides an electronic device, including:

[0123] Memory, used to store programs;

[0124] A processor for executing the program, specifically for implementing the decoding method.

[0125] The electronic device can be a server or terminal device that other electronic devices can log in to and access. The electronic device can include at least one memory and at least one processor. The processor can execute multiple computer instructions stored in the memory to implement the steps of the information processing method proposed in the above-described embodiments. The implementation process can be referred to the description of the corresponding method embodiments above, and will not be described in detail here.

[0126] In this embodiment, the memory may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device or other volatile solid-state storage device. The processor may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an off-the-shelf programmable gate array (FPGA), or other programmable logic devices. This application does not limit the structure and model of the above-mentioned memory and processor, and can flexibly adjust them according to actual needs.

[0127] As can be seen from the above technical solutions, this application provides an LDPC decoder, a decoding method, and an electronic device. The method acquires the channel message and index value of a variable node, and cyclically shifts the channel message based on the index value; then generates first feedback information, which is feedback information from the variable node to the check node; based on the first feedback information, generates second feedback information, which is compressed feedback information from the check node to the variable node; generates third feedback information, which is the result of accumulating the first and second feedback information; performs parity checking on the decoding result to output a parity check result; if the parity check result is low, the decoding result is output. The method can adapt to changes in multiple code rates and code lengths by using different decoding configurations, simplifies the decoding process, and is compatible with different applications, thus solving the problem of low flexibility in LDPC decoders.

[0128] Similar parts between the embodiments provided in this application can be referred to mutually. The specific implementation methods provided above are only a few examples under the overall concept of this application and do not constitute a limitation on the scope of protection of this application. For those skilled in the art, any other implementation methods extended from the solution of this application without creative effort shall fall within the scope of protection of this application.

Claims

1. An LDPC decoder, characterized in that, include: The first storage unit is used to receive and buffer the input channel messages; The first shift unit is used to receive the index value and cyclically shift the channel message based on the index value; The processing unit includes a variable node processing module and a check node processing module. The variable node processing module is used to generate first feedback information based on the output of the first shift unit. The first feedback information is feedback information from the variable node to the check node. The inspection node processing module is used to generate second feedback information based on the first feedback information. The second feedback information is feedback information from the inspection node to the variable node, and is compressed feedback information. The check node processing module is further configured to obtain a first value, a second value, and a first value index based on the first feedback information. The first value is the smallest first feedback information among the variable nodes, the second value is the smallest first feedback information other than the first value, and the bit width of the first value index is the maximum row weight bit width. The row weight is the number of valid elements in a row of the check matrix. Based on the first feedback information, the sign bit is determined, and the bit width of the sign bit is the maximum row overlap value; The inspection node processing module is also used to perform an XOR operation between the first feedback information and the sign bit to output the second feedback information; The channel message update module is used to generate third feedback information, which is the updated channel message and is the result of accumulating the first feedback information and the second feedback information. A parity check unit is used to generate a decoding result based on the third feedback information, and to perform parity check on the decoding result to output a parity check result. If the parity check result is low, the decoding result is output.

2. The LDPC decoder according to claim 1, characterized in that, Also includes: A multiplexer, connected to the variable node processing module, is used to receive the first feedback information; If the multiplexer receives the first feedback information, it outputs the first feedback information to the first storage unit; If the multiplexer does not receive the first feedback information, it outputs the channel message to the first storage unit.

3. The LDPC decoder according to claim 2, characterized in that, Also includes: The second storage unit is used to store the second feedback information; The first decompression unit is used to decompress the second feedback information and input the decompressed second feedback information into the variable node processing module. The variable node processing module is also used to output variable node information based on the decompressed second feedback information, wherein the bit width of the variable node information is different from that of the first feedback information.

4. The LDPC decoder according to claim 3, characterized in that, Also includes: The second decompression unit is used to decompress the second feedback information and input the decompressed second feedback information into the channel message update module so as to generate a decoding result through the channel message update module; The second shift unit is used to shift the updated channel message and transmit the shifted channel message to the multiplexer.

5. A decoding method, characterized in that, Applied to the LDPC decoder according to any one of claims 1-4, comprising: Obtain the channel message and index value of the variable node, and cyclically shift the channel message based on the index value; Generate first feedback information, which is feedback information from the variable node to the inspection node; Based on the first feedback information, a second feedback information is generated, which is a compressed feedback information from the inspection node to the variable node. Based on the first feedback information, obtain the first value, the second value, and the index of the first value. The first value is the smallest first feedback information among the variable nodes, the second value is the smallest first feedback information other than the first value, and the bit width of the first value index is the maximum row weight bit width. The row weight is the number of valid elements in the row of the check matrix. Based on the first feedback information, the sign bit is determined, and the bit width of the sign bit is the maximum row overlap value; The inspection node processing module is also used to perform an XOR operation between the first feedback information and the sign bit to output the second feedback information; Generate third feedback information, which is an updated channel message, and the third feedback information is the result of accumulating the first feedback information and the second feedback information; Generate decoding results based on the third feedback information; Perform parity checking on the decoding result and output the parity check result; If the parity check result is low, output the decoding result.

6. The decoding method according to claim 5, characterized in that, Before obtaining the channel message and index value of the variable node, the following steps are included: Obtain the reset signal; In response to the reset signal being pulled low, a reset operation is performed until the reset is completed. Then, the reset signal is pulled high to generate configuration information, which includes a boost factor and a control word. After generating decoding information based on the configuration information, the reset signal is pulled low, and the first storage unit is cleared.

7. The decoding method according to claim 6, characterized in that, The acquisition of the channel message and index value of the variable node includes: When the first storage unit receives a valid input information signal and buffers the input channel message, it transmits the channel message to the first shift unit.

8. The decoding method according to claim 7, characterized in that, The method further includes: When the channel message update module generates the third feedback information, the enable signal is pulled high. When the parity check result output by the parity check unit is low, the valid signal for output information is pulled high.

9. An electronic device, characterized in that, include: Memory, used to store programs; A processor for executing the program, specifically for implementing the decoding method according to any one of claims 5-8.

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