Pixel and display device having same

Abstract

A pixel and a display device including the same are provided. The pixels include a first sub-pixel and a second sub-pixel. The first sub-pixel includes a first light emitting element, a first transistor configured to drive the first light emitting element, a second transistor configured to apply a data voltage to the first transistor in response to a first write gate signal, and a fifth transistor configured to apply a power supply voltage to the first transistor in response to an emission signal. The second sub-pixel includes a second light emitting element having a viewing angle different from that of the first light emitting element, a sixth transistor configured to drive the second light emitting element, a seventh transistor configured to apply a data voltage to the sixth transistor in response to a second write gate signal different from the first write gate signal; and a tenth transistor configured to apply a power supply voltage to the sixth transistor in response to an emission signal.

Description

Technical Field

[0001] Embodiments of the inventive concept relate to a display device. More particularly, embodiments of the inventive concept relate to a pixel and a display device including the pixel. Background Art

[0002] The display device may include a display panel and a panel driver for driving the display panel. The display panel may include a plurality of gate lines, a plurality of data lines, a plurality of emission lines and a plurality of pixels. The panel driver may include a gate driver configured to provide a gate signal to the gate line, a data driver configured to provide a data voltage to the data line, an emission driver configured to provide an emission signal to the emission line, and a drive controller configured to control the gate driver, the data driver and the emission driver.

[0003] A display device that supports a public mode and a private mode has recently been developed. The display device may include public mode pixels for the public mode and private mode pixels for the private mode. The image during the private mode can be viewed by authorized viewers, but is more difficult to be viewed by unauthorized viewers. The image during the public mode can be viewed by all viewers. However, since the areas of the public mode pixels and the private mode pixels are fixed, there may be a situation where unauthorized viewers can view the image during the private mode. In addition, due to the presence of both the public mode pixels and the private mode pixels, brightness degradation may occur. Summary of the invention

[0004] At least one embodiment of the inventive concept provides a pixel of a display panel in which a public mode area and a private mode area are dynamically set according to image data.

[0005] At least one embodiment of the inventive concept also provides a display device including a pixel.

[0006] In an embodiment according to the concept of the present invention, a pixel includes a first sub-pixel and a second sub-pixel. The first sub-pixel includes a first light-emitting element, a first transistor configured to apply a first drive current to the first light-emitting element, a second transistor configured to apply a data voltage to the first transistor in response to a first write gate signal, and a fifth transistor configured to apply a first power supply voltage to the first transistor in response to an emission signal. The second sub-pixel includes a second light-emitting element having a viewing angle different from that of the first light-emitting element, a sixth transistor configured to apply a second drive current to the second light-emitting element, a seventh transistor configured to apply a data voltage to the sixth transistor in response to a second write gate signal different from the first write gate signal, and a tenth transistor configured to apply a first power supply voltage to the sixth transistor in response to an emission signal.

[0007] In an embodiment, the first sub-pixel may be a private mode sub-pixel having a first viewing angle, and the second sub-pixel may be a public mode sub-pixel having a second viewing angle wider than the first viewing angle.

[0008] In an embodiment, in an odd-numbered frame period, the second transistor may be turned off, and the seventh transistor may be turned on.

[0009] In an embodiment, in an even-numbered frame period, the second transistor may be turned on, and the seventh transistor may be turned off.

[0010] In an embodiment, the first sub-pixel may include: a first transistor including a first control electrode connected to the first node, a second control electrode connected to the third node, a first electrode connected to the second node, and a second electrode connected to the third node; a second transistor including a control electrode configured to receive a first write gate signal, a first electrode configured to receive a data voltage, and a second electrode connected to the first node; a third transistor including a control electrode configured to receive a control gate signal, a first electrode configured to receive a reference voltage, and a second electrode connected to the first node; a fourth transistor including a control electrode configured to receive an initialization gate signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to the third node; a first storage capacitor including a first electrode connected to the third node and a second electrode connected to the first node; a first holding capacitor including a first electrode configured to receive a first power supply voltage and a second electrode connected to the third node; and a first light-emitting element, and the second sub-pixel may include: a sixth transistor including a control electrode connected to the fourth a first control electrode of a node, a second control electrode connected to a sixth node, a first electrode connected to a fifth node, and a second electrode connected to the sixth node; a seventh transistor, including a control electrode configured to receive a second write gate signal, a first electrode configured to receive a data voltage, and a second electrode connected to the fourth node; an eighth transistor, including a control electrode configured to receive a control gate signal, a first electrode configured to receive a reference voltage, and a second electrode connected to the fourth node; a ninth transistor, including a control electrode configured to receive an initialization gate signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to the sixth node; a tenth transistor, including a control electrode configured to receive an emission signal, a first electrode configured to receive a first power supply voltage, and a second electrode connected to the fifth node; a second storage capacitor, including a first electrode connected to the sixth node, and a second electrode connected to the fourth node; a second holding capacitor, including a first electrode configured to receive a first power supply voltage, and a second electrode connected to the sixth node; and a second light-emitting element.

[0011] In an embodiment, the odd frame period of the pixel may include: an odd frame initialization period, in which the emission signal has a non-valid level, the control gate signal has a valid level, the initialization gate signal has a valid level, the first write gate signal has a non-valid level, and the second write gate signal has a non-valid level; an odd frame compensation period, in which the emission signal has a valid level, the control gate signal has a valid level, the initialization gate signal has a non-valid level, the first write gate signal has a non-valid level, and the second write gate signal has a non-valid level; an odd frame write period, in which the emission signal has a non-valid level, the control gate signal has a non-valid level, the initialization gate signal has a non-valid level, the first write gate signal has a non-valid level, and the second write gate signal has a valid level; and an odd frame emission period, in which the emission signal has a valid level, the control gate signal has a non-valid level, the initialization gate signal has a non-valid level, the first write gate signal has a non-valid level, and the second write gate signal has a non-valid level. flat; and the even frame period of the pixel may include: an even frame initialization period, in which the emission signal has a non-valid level, the control gate signal has a valid level, the initialization gate signal has a valid level, the first write gate signal has a non-valid level, and the second write gate signal has a non-valid level; an even frame compensation period, in which the emission signal has a valid level, the control gate signal has a valid level, the initialization gate signal has a non-valid level, the first write gate signal has a non-valid level, and the second write gate signal has a non-valid level; an even frame write period, in which the emission signal has a non-valid level, the control gate signal has a non-valid level, the initialization gate signal has a non-valid level, the first write gate signal has a valid level, and the second write gate signal has a non-valid level; and an even frame emission period, in which the emission signal has a valid level, the control gate signal has a non-valid level, the initialization gate signal has a non-valid level, the first write gate signal has a non-valid level, and the second write gate signal has a non-valid level.

[0012] In an embodiment conceived according to the present invention, a display device includes a display panel, a data driver, a gate driver, an emission driver, and a drive controller. The display panel includes a first sub-pixel and a second sub-pixel having a viewing angle different from that of the first sub-pixel. The data driver is configured to apply a data voltage and a reference voltage to the display panel. The gate driver is configured to apply a control gate signal, an initialization gate signal, a first write gate signal, and a second write gate signal to the display panel. The emission driver is configured to apply an emission signal to the display panel. The drive controller is configured to control the data driver, the gate driver, and the emission driver. The first sub-pixel and the second sub-pixel are configured to receive the same emission signal in the emission signal.

[0013] In an embodiment, the first sub-pixel may be a private mode sub-pixel having a first viewing angle, and wherein the second sub-pixel may be a public mode sub-pixel having a second viewing angle wider than the first viewing angle.

[0014] In an embodiment, a data write operation may not be performed on the first sub-pixel in an odd-numbered frame write period of an odd-numbered frame cycle, and a data write operation may not be performed on the second sub-pixel in an odd-numbered frame write period.

[0015] In an embodiment, in an odd frame emission period of an odd frame cycle, the first subpixel may emit light based on previous even frame data, and the second subpixel may emit light based on current odd frame data.

[0016] In an embodiment, the initialization operation may not be performed on the first subpixel in an odd frame initialization period of an odd frame cycle, and the compensation operation may not be performed on the first subpixel in an odd frame compensation period of an odd frame cycle.

[0017] In an embodiment, in an odd-numbered frame emission period of an odd-numbered frame cycle, the first subpixel may not emit light, and the second subpixel may emit light based on current odd-numbered frame data.

[0018] In an embodiment, the data write operation may not be performed on the second sub-pixel in an even frame write period of an even frame cycle, and the data write operation may be performed on the first sub-pixel in an even frame write period of an even frame cycle.

[0019] In an embodiment, in an even frame emission period of an even frame cycle, the second subpixel may emit light based on previous odd frame data, and the first subpixel may emit light based on current even frame data.

[0020] In an embodiment, an initialization operation may be performed on the second subpixel in an even-numbered frame initialization period of an even-numbered frame cycle, and a compensation operation may be performed on the second subpixel in an even-numbered frame compensation period.

[0021] In an embodiment, in an even frame emission period of an even frame period, the second subpixel may not emit light, and the first subpixel may emit light based on current even frame data of the even frame period.

[0022] In an embodiment, the display device may operate in a private mode or a public mode, and when in the private mode, the data writing operation may not be performed on the second sub-pixel in a frame period.

[0023] In an embodiment, the data driver may apply a first data voltage and a first reference voltage to the first subpixel, and the data driver may apply a second data voltage different from the first data voltage and a second reference voltage different from the first reference voltage to the second subpixel.

[0024] In an embodiment, a first subpixel may include a first light-emitting element, a first transistor configured to apply a first driving current to the first light-emitting element, a second transistor configured to apply a data voltage to the first transistor in response to a first write gate signal, and a fifth transistor configured to apply a first power supply voltage to the first transistor in response to an emission signal, and a second subpixel includes a second light-emitting element having a viewing angle different from that of the first light-emitting element, a sixth transistor configured to apply a second driving current to the second light-emitting element, a seventh transistor configured to apply a data voltage to the sixth transistor in response to a second write gate signal different from the first write gate signal, and a tenth transistor configured to apply the first power supply voltage to the sixth transistor in response to the emission signal.

[0025] In an embodiment, the first sub-pixel may include: a first transistor including a first control electrode connected to the first node, a second control electrode connected to the third node, a first electrode connected to the second node, and a second electrode connected to the third node; a second transistor including a control electrode configured to receive a first write gate signal, a first electrode configured to receive a data voltage, and a second electrode connected to the first node; a third transistor including a control electrode configured to receive a control gate signal, a first electrode configured to receive a reference voltage, and a second electrode connected to the first node; a fourth transistor including a control electrode configured to receive an initialization gate signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to the third node; a first storage capacitor including a first electrode connected to the third node and a second electrode connected to the first node; a first holding capacitor including a first electrode configured to receive a first power supply voltage and a second electrode connected to the third node; and a first light-emitting element, and the second sub-pixel may include: a sixth transistor including a control electrode connected to the fourth a first control electrode of a node, a second control electrode connected to a sixth node, a first electrode connected to a fifth node, and a second electrode connected to the sixth node; a seventh transistor, including a control electrode configured to receive a second write gate signal, a first electrode configured to receive a data voltage, and a second electrode connected to the fourth node; an eighth transistor, including a control electrode configured to receive a control gate signal, a first electrode configured to receive a reference voltage, and a second electrode connected to the fourth node; a ninth transistor, including a control electrode configured to receive an initialization gate signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to the sixth node; a tenth transistor, including a control electrode configured to receive an emission signal, a first electrode configured to receive a first power supply voltage, and a second electrode connected to the fifth node; a second storage capacitor, including a first electrode connected to the sixth node, and a second electrode connected to the fourth node; a second holding capacitor, including a first electrode configured to receive a first power supply voltage, and a second electrode connected to the sixth node; and a second light-emitting element.

[0026] As described above, a pixel or a pixel circuit according to an embodiment may include a first sub-pixel and a second sub-pixel, and different write gate signals may be applied to the first sub-pixel and the second sub-pixel, so that each of the sub-pixels may be a public mode sub-pixel or a private mode sub-pixel. Since the write gate signal may be applied to the sub-pixel according to the image data and the same emission signal may be applied to the sub-pixel, the public mode area and the private mode area may be arbitrarily set in the display panel of the display device. Therefore, the position of displaying the public mode area and the private mode area in the display panel of the display device may be dynamically changed according to the image data.

[0027] In an embodiment according to the concept of the present invention, a display device includes a display panel, a gate driver and an emission driver. The display panel includes a plurality of pixels, wherein each of the plurality of pixels includes a first sub-pixel and a second sub-pixel. The gate driver is configured to generate a first write gate signal and a second write gate signal different from the first write gate signal. The emission driver is configured to apply a plurality of emission signals to the display panel. The first sub-pixel includes a first light-emitting element having a first viewing angle, a first drive transistor configured to apply a first drive current to the first light-emitting element, a first data write transistor configured to apply a data voltage to the first drive transistor in response to the first write gate signal, and a first emission control transistor configured to apply a power supply voltage to the first drive transistor in response to a first emission signal among the emission signals. The second sub-pixel includes a second light-emitting element having a second viewing angle different from the first viewing angle, a second drive transistor configured to apply a second drive current to the second light-emitting element, a second data write transistor configured to apply a data voltage to the second drive transistor in response to the second write gate signal, and an emission control transistor configured to apply a power supply voltage to the second drive transistor in response to the first emission signal.

[0028] Furthermore, since the common mode sub-pixel and the private mode sub-pixel can emit light throughout the entire frame period, luminance degradation can be prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other features of the present inventive concept will become more apparent by describing detailed embodiments of the present inventive concept with reference to the accompanying drawings, in which: Figure 1 is a block diagram illustrating a display device according to an embodiment of the inventive concept; Figure 2 It is shown Figure 1 a circuit diagram of a pixel circuit of a pixel of a display device; Figure 3 is shown applied to Figure 2 A timing diagram of an example of an input signal of a pixel circuit; Figure 4 is a block diagram illustrating a display device according to an embodiment of the inventive concept; Figure 5 It is shown Figure 4 a circuit diagram of a pixel circuit of a pixel of a display device; Figure 6 is shown applied to Figure 5 A timing diagram of an example of an input signal of a pixel circuit; Figure 7 is a block diagram illustrating a display device according to an embodiment of the inventive concept; Figure 8FIG. 1 is a diagram showing an embodiment according to the present invention. Figure 7 a circuit diagram of a pixel circuit of a pixel of a display device; Fig. 9 is a block diagram illustrating an electronic device according to an embodiment of the inventive concept; and Fig.10 It is shown Fig. 9 FIG. 1 is a diagram of an example in which the electronic device is implemented as a smart phone. DETAILED DESCRIPTION

[0030] Hereinafter, the inventive concept will be described in more detail with reference to the accompanying drawings.

[0031] Figure 1 is a block diagram illustrating a display device 101 according to an embodiment of the inventive concept.

[0032] Reference Figure 1 , the display device 101 may include a display panel 100 and a display panel driver (e.g., a panel driver circuit). The display panel driver may include a drive controller 200 (e.g., a control circuit), a gate driver 300 (e.g., a first driver circuit), a gamma reference voltage generator 400, a data driver 500 (e.g., a second driver circuit), and an emission driver 600 (e.g., a third driver circuit).

[0033] The display panel 100 may include a display portion configured to display an image and a peripheral portion adjacent to the display portion.

[0034] The display panel 100 may include a plurality of gate lines GIL, GRL, GW1L, GW2L, a plurality of data lines DL, a plurality of emission lines EL, and a plurality of pixels PX electrically connected to the gate lines GIL, GRL, GW1L, GW2L and the data lines DL, respectively. The gate lines GIL, GRL, GW1L, GW2L may extend in a first direction D1, the data lines DL may extend in a second direction D2 crossing the first direction D1, and the emission lines EL may extend in the first direction D1.

[0035] The driving controller 200 may receive input image data IMG and an input control signal CONT from an external device. For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a main clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0036] The driving controller 200 may generate a gate control signal CONT1 , a data control signal CONT2 , a gamma control signal CONT3 , an emission control signal CONT4 , and a data signal DATA based on input image data IMG and an input control signal CONT.

[0037] The driving controller 200 may generate a gate control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT to output the generated gate control signal CONT1 to the gate driver 300. The gate control signal CONT1 may include a vertical start signal and a gate clock signal.

[0038] The driving controller 200 may generate a data control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT to output the generated data control signal CONT2 to the data driver 500. The data control signal CONT2 may include a horizontal start signal and a load signal.

[0039] The driving controller 200 may generate a data signal DATA based on the input image data IMG. The driving controller 200 may output the data signal DATA to the data driver 500.

[0040] The driving controller 200 may generate a gamma control signal CONT3 for controlling the operation of the gamma reference voltage generator 400 based on the input control signal CONT to output the generated gamma control signal CONT3 to the gamma reference voltage generator 400 .

[0041] The driving controller 200 may generate an emission control signal CONT4 for controlling the operation of the emission driver 600 based on the input control signal CONT to output the generated emission control signal CONT4 to the emission driver 600 .

[0042] The gate driver 300 may generate gate signals GI, GR, GW1, GW2 for driving the gate lines GIL, GRL, GW1L, GW2L in response to the gate control signal CONT1 received from the driving controller 200. The gate driver 300 may output the gate signals GI, GR, GW1, GW2 to the gate lines GIL, GRL, GW1L, GW2L. For example, the gate driver 300 may sequentially output the gate signals GI, GR, GW1, GW2 to the gate lines GIL, GRL, GW1L, GW2L. The gate signals GI, GR, GW1, GW2 may include an initialization gate signal GI, a control gate signal GR, a first write gate signal GW1, and a second write gate signal GW2.

[0043] For example, the gate driver 300 may be installed in the peripheral area of ​​the display panel 100. For example, the gate driver 300 may be integrated in the peripheral area of ​​the display panel 100.

[0044] The gamma reference voltage generator 400 may generate the gamma reference voltage VGREF in response to the gamma control signal CONT3 received from the driving controller 200. The gamma reference voltage generator 400 may provide the gamma reference voltage VGREF to the data driver 500.

[0045] In an embodiment, the gamma reference voltage generator 400 may be provided in the driving controller 200 or in the data driver 500 .

[0046] The data driver 500 may receive the data control signal CONT2 and the data signal DATA from the driving controller 200, and receive the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 may convert the data signal DATA into an analog data voltage VDATA by using the gamma reference voltage VGREF. The data driver 500 may output the data voltage VDATA to the data line DL. The data voltage VDATA may include the reference voltage VREF.

[0047] For example, the data driver 500 may be installed in the peripheral area of ​​the display panel 100. For example, the data driver 500 may be integrated in the peripheral area of ​​the display panel 100.

[0048] The emission driver 600 may generate an emission signal EM for driving the emission line EL in response to the emission control signal CONT4 received from the driving controller 200. The emission driver 600 may output the emission signal EM to the emission line EL.

[0049] For example, the emission driver 600 may be integrated in the peripheral area of ​​the display panel 100. For example, the emission driver 600 may be installed in the peripheral area of ​​the display panel 100.

[0050] although Figure 1 100 and the emission driver 600 are provided on the second side of the display panel 100 opposite to the first side, but the embodiments of the present inventive concept are not limited thereto. For example, the gate driver 300 and the emission driver 600 may be provided on the same side of the display panel 100. For example, the gate driver 300 and the emission driver 600 may be integrated in the peripheral area of ​​the display panel 100 on the same side of the display area of ​​the display panel 100. The gate driver 300 and the emission driver 600 may be formed integrally with each other. For example, the gate driver 300 and the emission driver 600 may be implemented using a single circuit.

[0051] Figure 2 It is shown Figure 1 1 is a circuit diagram of a pixel circuit 111 of a pixel PX of a display device 101.

[0052] Reference Figure 1 and Figure 2 In this embodiment, the pixel circuit 111 includes a first sub-pixel SPX1A and a second sub-pixel SPX2A.

[0053] The first subpixel SPX1A may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a first storage capacitor CST1, a first holding capacitor CHOLD1 and a first light emitting element EE1. In an embodiment, the first transistor T1 has a double gate structure.

[0054] The first transistor T1 may generate a first driving current based on a voltage of the first node N1. For example, the first transistor T1 may be referred to as a driving transistor or a first driving transistor. The first transistor T1 may include a first control electrode connected to the first node N1, a second control electrode connected to the third node N3, a first electrode connected to the second node N2, and a second electrode connected to the third node N3.

[0055] The second transistor T2 may apply the data voltage VDATA to the first node N1 in response to the first write gate signal GW1. For example, the second transistor T2 may be referred to as a data write transistor or a first data write transistor. The second transistor T2 may include a control electrode (e.g., a gate) configured to receive the first write gate signal GW1, a first electrode configured to receive the data voltage VDATA, and a second electrode connected to the first node N1. For example, an operation in which the data voltage VDATA is applied to the first node N1 via the second transistor T2 may be referred to as a data write operation or a first data write operation.

[0056] The third transistor T3 may apply a reference voltage VREF to the first node N1 in response to the control gate signal GR. For example, the third transistor T3 may be referred to as a reference voltage writing transistor. The third transistor T3 may include a control electrode configured to receive the control gate signal GR, a first electrode configured to receive the reference voltage VREF, and a second electrode connected to the first node N1.

[0057] The fourth transistor T4 may apply the initialization voltage VINT to the third node N3 in response to the initialization gate signal GI. For example, the fourth transistor T4 may be referred to as an initialization transistor or a light emitting element initialization transistor. The fourth transistor T4 may include a control electrode configured to receive the initialization gate signal GI, a first electrode configured to receive the initialization voltage VINT, and a second electrode connected to the third node N3.

[0058] The fifth transistor T5 may apply a first power supply voltage ELVDD (e.g., a high power supply voltage) to the second node N2 in response to the emission signal EM. For example, the fifth transistor T5 may be referred to as an emission control transistor or a first emission control transistor. The fifth transistor T5 may include a control electrode configured to receive the emission signal EM, a first electrode configured to receive the first power supply voltage ELVDD, and a second electrode connected to the second node N2.

[0059] The first storage capacitor CST1 may apply the data voltage VDATA to the third node N3. The first storage capacitor CST1 may include a first electrode connected to the third node N3 and a second electrode connected to the first node N1.

[0060] The first holding capacitor CHOLD1 may apply the compensation data voltage to the third node N3. The first holding capacitor CHOLD1 may include a first electrode configured to receive the first power voltage ELVDD and a second electrode connected to the third node N3.

[0061] The first light emitting element EE1 may emit light based on the driving current generated by the first transistor T1. In an embodiment, the first light emitting element EE1 may be an organic light emitting diode (OLED), but is not limited thereto. In other embodiments, the first light emitting element EE1 may be a nano light emitting diode (NED), a quantum dot (QD) light emitting diode, a micro light emitting diode, an inorganic light emitting diode, or any other suitable light emitting device. The first light emitting element EE1 may include a first electrode (e.g., an anode) connected to a third node N3 and a second electrode (e.g., a cathode) configured to receive a second power supply voltage ELVSS (e.g., a low power supply voltage).

[0062] The second subpixel SPX2A may include a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a second storage capacitor CST2, a second holding capacitor CHOLD2 and a second light emitting element EE2. In an embodiment, the sixth transistor T6 has a double gate structure.

[0063] The sixth transistor T6 may generate a second drive current based on the voltage of the fourth node N4. For example, the sixth transistor T6 may be referred to as a drive transistor or a second drive transistor. The sixth transistor T6 may include a first control electrode connected to the fourth node N4, a second control electrode connected to the sixth node N6, a first electrode connected to the fifth node N5, and a second electrode connected to the sixth node N6.

[0064] The seventh transistor T7 may apply the data voltage VDATA to the fourth node N4 in response to the second write gate signal GW2. For example, the seventh transistor T7 may be referred to as a data write transistor or a second data write transistor. The seventh transistor T7 may include a control electrode configured to receive the second write gate signal GW2, a first electrode configured to receive the data voltage VDATA, and a second electrode connected to the fourth node N4. For example, an operation in which the data voltage VDATA is applied to the fourth node N4 via the seventh transistor T7 may be referred to as a data write operation or a second data write operation.

[0065] The eighth transistor T8 may apply the reference voltage VREF to the fourth node N4 in response to the control gate signal GR. For example, the eighth transistor T8 may be referred to as a reference voltage writing transistor. The eighth transistor T8 may include a control electrode configured to receive the control gate signal GR, a first electrode configured to receive the reference voltage VREF, and a second electrode connected to the fourth node N4.

[0066] The ninth transistor T9 may apply the initialization voltage VINT to the sixth node N6 in response to the initialization gate signal GI. For example, the ninth transistor T9 may be referred to as an initialization transistor or a light emitting element initialization transistor. The ninth transistor T9 may include a control electrode configured to receive the initialization gate signal GI, a first electrode configured to receive the initialization voltage VINT, and a second electrode connected to the sixth node N6.

[0067] The tenth transistor T10 may apply a first power supply voltage ELVDD (e.g., a high power supply voltage) to the fifth node N5 in response to the emission signal EM. For example, the tenth transistor T10 may be referred to as an emission control transistor or a second emission control transistor. The tenth transistor T10 may include a control electrode configured to receive the emission signal EM, a first electrode configured to receive the first power supply voltage ELVDD, and a second electrode connected to the fifth node N5.

[0068] The second storage capacitor CST2 may apply the data voltage VDATA to the sixth node N6. The second storage capacitor CST2 may include a first electrode connected to the sixth node N6 and a second electrode connected to the fourth node N4.

[0069] The second holding capacitor CHOLD2 may apply the compensation data voltage to the sixth node N6. The second holding capacitor CHOLD2 may include a first electrode configured to receive the first power voltage ELVDD and a second electrode connected to the sixth node N6.

[0070] The second light emitting element EE2 may emit light based on the driving current generated by the sixth transistor T6. In an embodiment, the second light emitting element EE2 is an organic light emitting diode (OLED), but is not limited thereto. In other embodiments, the second light emitting element EE2 may be a nano light emitting diode (NED), a quantum dot (QD) light emitting diode, a micro light emitting diode, an inorganic light emitting diode, or any other suitable light emitting device. The second light emitting element EE2 may include a first electrode (e.g., an anode) connected to the sixth node N6 and a second electrode (e.g., a cathode) configured to receive a second power supply voltage ELVSS (e.g., a low power supply voltage).

[0071] Thus, the first sub-pixel SPX1A may have a 5T2C structure including five transistors T1, T2, T3, T4, T5 and two capacitors CST1, CHOLD1. The second sub-pixel SPX2A may have a 5T2C structure including five transistors T6, T7, T8, T9, T10 and two capacitors CST2, CHOLD2. However, the inventive concept is not limited to sub-pixels having such a number of transistors and capacitors. In addition, the inventive concept is not limited to Figure 2 The transistor type shown in .

[0072] Although the first sub-pixel SPX1A and the second sub-pixel SPX2A Figure 2 Although shown as being vertically disposed, the inventive concept is not limited to such an arrangement of the first subpixel SPX1A and the second subpixel SPX2A. For example, the first subpixel SPX1A and the second subpixel SPX2A may be horizontally disposed.

[0073] In an embodiment, the viewing angle of the second light emitting element EE2 is different from the viewing angle of the first light emitting element EE1. For example, the viewing angle of the first light emitting element EE1 (e.g., the first viewing angle) may be wider than the viewing angle of the second light emitting element EE2 (e.g., the second viewing angle). For example, the viewing angle of the first light emitting element EE1 (e.g., the first viewing angle) may be narrower than the viewing angle of the second light emitting element EE2 (e.g., the second viewing angle). For example, a viewer outside a given viewing angle of a given sub-pixel may have difficulty perceiving an image of the given sub-pixel.

[0074] One of the first subpixel SPX1A and the second subpixel SPX2A may be a public mode subpixel, and the other may be a private mode subpixel. Although the pixel PX is shown as including two subpixels, the inventive concept is not limited thereto. In an embodiment, when the viewing angle (e.g., the second viewing angle) of the second light emitting element EE2 is wider than the viewing angle (e.g., the first viewing angle) of the first light emitting element EE1, the first subpixel SPX1A is referred to as a private mode subpixel, and the second subpixel SPX2A is referred to as a public mode subpixel.

[0075] In an embodiment, the first sub-pixel SPX1A and the second sub-pixel SPX2A have the same structure and operation except that the applied write gate signal and the viewing angle of the light-emitting element are different. In an embodiment, the emission signal EM applied to the first sub-pixel SPX1A and the second sub-pixel SPX2A is the same. Therefore, a private mode area or a public mode area can be locally formed in any part of the display panel 100 of the display device 101. In addition, the size of the private mode area and the public mode area can be dynamically adjusted as needed. For example, if the image of the image data needs to be displayed in a private mode area of ​​an area located at a specific position and having a specific size, the size and position of the private mode area can be constructed by activating a corresponding number of private mode sub-pixels.

[0076] Figure 3 is shown applied to Figure 2 1 is a timing diagram of an example of an input signal to the pixel circuit 111.

[0077] Reference Figure 3 , the pixel circuit 111 of the pixel can be driven during multiple odd frame periods FP1A, FP3A and multiple even frame periods FP2A, FP4A.

[0078] Each of the odd frame periods FP1A, FP3A may include an odd frame initialization hold period TPO1A, an odd frame initialization period TPO2A, an odd frame compensation hold period TPO3A, an odd frame compensation period TPO4A, an odd frame write hold period TPO5A, an odd frame write period TPO6A, an odd frame emission hold period TPO7A and an odd frame emission period TPO8A.

[0079] Reference Figure 3, in the odd-numbered frame initialization holding period TPO1A, the emission signal EM may have a non-effective level (e.g., a first logic level), the control gate signal GR may be changed from the non-effective level to an effective level (e.g., a second logic level different from the first logic level), the initialization gate signal GI may have a non-effective level, the first write gate signal GW1 may have a non-effective level, and the second write gate signal GW2 may have a non-effective level. The pixel circuit 111 may include an N-type transistor. Therefore, the effective levels of the initialization gate signal GI, the control gate signal GR, the first write gate signal GW1, and the second write gate signal GW2 may be a high level. In addition, the non-effective levels of the initialization gate signal GI, the control gate signal GR, the first write gate signal GW1, and the second write gate signal GW2 may be a low level lower than a high level. In another embodiment, when the pixel circuit 111 includes a P-type transistor, the effective levels of the initialization gate signal GI, the control gate signal GR, the first write gate signal GW1, and the second write gate signal GW2 may be a low level. Furthermore, when the pixel circuit 111 includes a P-type transistor, the inactive levels of the initialization gate signal GI, the control gate signal GR, the first write gate signal GW1, and the second write gate signal GW2 may be high levels.

[0080] When the emission signal EM has a non-effective level in the odd frame initialization holding period TPO1A, the fifth transistor T5 and the tenth transistor T10 may be turned off. When the first write gate signal GW1 and the second write gate signal GW2 have a non-effective level in the odd frame initialization holding period TPO1A, the second transistor T2 and the seventh transistor T7 may be turned off. In addition, when the control gate signal GR changes to an effective level in the odd frame initialization holding period TPO1A, the third transistor T3 and the eighth transistor T8 may be turned on. Therefore, the reference voltage VREF may be applied to the first node N1 and the fourth node N4. For example, the voltage of the first node N1 and the voltage of the fourth node N4 may be the reference voltage VREF.

[0081] In the odd frame initialization period TPO2A, the emission signal EM may have a non-active level, the control gate signal GR may have an active level, the initialization gate signal GI may have an active level, the first write gate signal GW1 may have a non-active level, and the second write gate signal GW2 may have a non-active level.

[0082] When the initialization gate signal GI has an effective level in the odd frame initialization period TPO2A, the fourth transistor T4 and the ninth transistor T9 may be turned on. Therefore, the initialization voltage VINT may be applied to the third node N3 and the sixth node N6. For example, the voltage of the third node N3 and the voltage of the sixth node N6 may be the initialization voltage VINT. For example, the operation in which the initialization voltage VINT is applied to the third node N3 may be referred to as an initialization operation or a light emitting element initialization operation. For example, the operation in which the initialization voltage VINT is applied to the sixth node N6 may be referred to as an initialization operation or a light emitting element initialization operation.

[0083] In the odd frame compensation holding period TPO3A, the emission signal EM may have a non-valid level, the control gate signal GR may have a valid level, the initialization gate signal GI may have a non-valid level, the first write gate signal GW1 may have a non-valid level, and the second write gate signal GW2 may have a non-valid level.

[0084] In the odd frame compensation holding period TP03A, ​​the fourth transistor T4 and the ninth transistor T9 may be turned off. Therefore, the voltage of the first node N1 may maintain the reference voltage VREF. In addition, the voltage of the fourth node N4 may maintain the reference voltage VREF. In addition, the voltage of the third node N3 may maintain the initialization voltage VINT. In addition, the voltage of the sixth node N6 may maintain the initialization voltage VINT.

[0085] In the odd frame compensation period TPO4A, the emission signal EM may have an active level, the control gate signal GR may have an active level, the initialization gate signal GI may have an inactive level, the first write gate signal GW1 may have an inactive level, and the second write gate signal GW2 may have an inactive level.

[0086] Since the emission signal EM may have an effective level in the odd frame compensation period TPO4A, the first transistor T1, the fifth transistor T5, the sixth transistor T6, and the tenth transistor T10 may be turned on. Therefore, the voltage of the third node N3 may be a first compensation voltage. For example, the first compensation voltage may be a value obtained by subtracting the threshold voltage (VTH1) of the first transistor T1 from the voltage of the first control electrode of the first transistor T1. For example, the first compensation voltage may be a value of VREF-VTH1. In addition, the voltage of the sixth node N6 may be a second compensation voltage. For example, the second compensation voltage may be a value obtained by subtracting the threshold voltage (VTH6) of the sixth transistor T6 from the voltage of the first control electrode of the sixth transistor T6. For example, the second compensation voltage may be a value of VREF-VTH6. For example, an operation in which the third node N3 has a first compensation voltage in response to the first transistor T1 and the fifth transistor T5 may be referred to as a compensation operation or a first compensation operation. For example, an operation in which the sixth node N6 has a second compensation voltage in response to the sixth transistor T6 and the tenth transistor T10 may be referred to as a compensation operation or a second compensation operation.

[0087] In the odd frame write hold period TPO5A, the emission signal EM may have a non-valid level, the control gate signal GR may change from a valid level to a non-valid level, the initialization gate signal GI may have a non-valid level, the first write gate signal GW1 may have a non-valid level, and the second write gate signal GW2 may have a non-valid level.

[0088] When the emission signal EM has a non-active level in the odd frame write holding period TP05A, the fifth transistor T5 and the tenth transistor T10 may be turned off. When the control gate signal GR changes from an active level to a non-active level, the third transistor T3 and the eighth transistor T8 may be turned off.

[0089] In the odd frame write period TPO6A, the emission signal EM may have a non-active level, the control gate signal GR may have a non-active level, the initialization gate signal GI may have a non-active level, the first write gate signal GW1 may have a non-active level, and the second write gate signal GW2 may have a valid level.

[0090] When the first write gate signal GW1 has a non-active level in the odd-numbered frame write period TPO6A, the second transistor T2 may be turned off. Therefore, the voltage of the first node N1 and the voltage of the third node N3 may be maintained.

[0091] Since the second write gate signal GW2 may have an effective level in the odd frame write period TPO6A, the seventh transistor T7 may be turned on. Therefore, the data voltage VDATA may be applied to the fourth node N4. For example, the voltage of the fourth node N4 may be the data voltage VDATA. In addition, due to the bootstrapping of the second storage capacitor CST2, the voltage of the sixth node N6 may be the final write voltage of the odd frame. For example, the final write voltage of the odd frame may be VREF-VTH6+(CST2C / (CST2C+CHOLD2C))*(VDATA-VREF). In this case, CST2C refers to the capacitance of the second storage capacitor CST2, and CHOLD2C refers to the capacitance of the second holding capacitor CHOLD2. For example, the final write voltage of the odd frame may be referred to as the odd frame data.

[0092] In the odd frame emission holding period TPO7A, the emission signal EM may have a non-active level, the control gate signal GR may have a non-active level, the initialization gate signal GI may have a non-active level, the first write gate signal GW1 may have a non-active level, and the second write gate signal GW2 may have a non-active level.

[0093] When the first and second write gate signals GW1 and GW2 have inactive levels in the odd frame emission holding period TPO7A, voltages of the first, third, fourth and sixth nodes N1, N3, N4 and N6 may be maintained.

[0094] In the odd frame emission period TPO8A, the emission signal EM may have an effective level, the control gate signal GR may have an ineffective level, the initialization gate signal GI may have an ineffective level, the first write gate signal GW1 may have an ineffective level, and the second write gate signal GW2 may have an ineffective level.

[0095] The emission signal EM may have an effective level in the odd frame emission period TPO8A. The second control electrode of the first transistor T1 may have a voltage of the third node N3. For example, the voltage of the third node N3 may be VREF-VTH1. Therefore, the first transistor T1 may be turned off. Therefore, the first subpixel SPX1A should not emit light in the odd frame emission period TPO8A.

[0096] When the emission signal EM has an effective level in the odd frame emission period TPO8A, the tenth transistor T10 can be turned on. The second control electrode of the sixth transistor T6 can have the voltage of the sixth node N6. For example, the voltage of the sixth node N6 can be the final write voltage of the odd frame. Therefore, the sixth transistor T6 can apply the second drive current to the second light emitting element EE2 based on the final write voltage of the odd frame. Therefore, the second light emitting element EE2 can emit light. For example, the second sub-pixel SPX2A can emit light based on the current odd frame data.

[0097] Each of the even frame periods FP2A, FP4A may include an even frame initialization hold period TPE1A, an even frame initialization period TPE2A, an even frame compensation hold period TPE3A, an even frame compensation period TPE4A, an even frame write hold period TPE5A, an even frame write period TPE6A, an even frame transmission hold period TPE7A and an even frame transmission period TPE8A.

[0098] Reference Figure 3 , in the even frame initialization holding period TPE1A, the emission signal EM may have a non-active level, the control gate signal GR may be changed from the non-active level to the active level, the initialization gate signal GI may have a non-active level, the first write gate signal GW1 may have a non-active level, and the second write gate signal GW2 may have a non-active level.

[0099] When the emission signal EM has a non-effective level in the even frame initialization holding period TPE1A, the fifth transistor T5 and the tenth transistor T10 may be turned off. When the first write gate signal GW1 and the second write gate signal GW2 have a non-effective level in the even frame initialization holding period TPE1A, the second transistor T2 and the seventh transistor T7 may be turned off. In addition, when the control gate signal GR changes to an effective level in the even frame initialization holding period TPE1A, the third transistor T3 and the eighth transistor T8 may be turned on. Therefore, the reference voltage VREF may be applied to the first node N1 and the fourth node N4. For example, the voltage of the first node N1 and the voltage of the fourth node N4 may be the reference voltage VREF.

[0100] In the even frame initialization period TPE2A, the emission signal EM may have an inactive level, the control gate signal GR may have an active level, the initialization gate signal GI may have an active level, the first write gate signal GW1 may have an inactive level, and the second write gate signal GW2 may have an inactive level.

[0101] When the initialization gate signal GI has an active level in the even frame initialization period TPE2A, the fourth transistor T4 and the ninth transistor T9 may be turned on. Therefore, the initialization voltage VINT may be applied to the third node N3 and the sixth node N6. For example, the voltage of the third node N3 and the voltage of the sixth node N6 may be the initialization voltage VINT.

[0102] In the even frame compensation holding period TPE3A, the emission signal EM may have a non-active level, the control gate signal GR may have a valid level, the initialization gate signal GI may have a non-active level, the first write gate signal GW1 may have a non-active level, and the second write gate signal GW2 may have a non-active level.

[0103] In the even frame compensation holding period TPE3A, the fourth transistor T4 and the ninth transistor T9 may be turned off. Therefore, the voltage of the first node N1 may maintain the reference voltage VREF. In addition, the voltage of the fourth node N4 may maintain the reference voltage VREF. In addition, the voltage of the third node N3 may maintain the initialization voltage VINT. In addition, the voltage of the sixth node N6 may maintain the initialization voltage VINT.

[0104] In the even frame compensation period TPE4A, the emission signal EM may have an active level, the control gate signal GR may have an active level, the initialization gate signal GI may have an inactive level, the first write gate signal GW1 may have an inactive level, and the second write gate signal GW2 may have an inactive level.

[0105] When the emission signal EM has an active level in the even frame compensation period TPE4A, the fifth transistor T5 and the tenth transistor T10 may be turned on. Therefore, the voltage of the third node N3 may be the first compensation voltage. In addition, the voltage of the sixth node N6 may be the second compensation voltage.

[0106] In the even frame write hold period TPE5A, the emission signal EM may have a non-active level, the control gate signal GR may change from a valid level to a non-active level, the initialization gate signal GI may have a non-active level, the first write gate signal GW1 may have a non-active level, and the second write gate signal GW2 may have a non-active level.

[0107] When the emission signal EM has a non-active level in the even frame write holding period TPE5A, the fifth transistor T5 and the tenth transistor T10 may be turned off. In addition, when the control gate signal GR changes from an active level to a non-active level, the third transistor T3 and the eighth transistor T8 may be turned off.

[0108] In the even frame write period TPE6A, the emission signal EM may have an inactive level, the control gate signal GR may have an inactive level, the initialization gate signal GI may have an inactive level, the first write gate signal GW1 may have an active level, and the second write gate signal GW2 may have an inactive level.

[0109] When the first write gate signal GW1 has an effective level in the even frame write period TPE6A, the second transistor T2 can be turned on. Therefore, the data voltage VDATA can be applied to the first node N1. For example, the voltage of the first node N1 can be the data voltage VDATA. In addition, due to the bootstrap of the first storage capacitor CST1, the voltage of the third node N3 can be the even frame final write voltage. For example, the even frame final write voltage can be VREF-VTH1+(CST1C / (CST1C+CHOLD1C))*(VDATA-VREF). In this case, CST1C refers to the capacitance of the first storage capacitor CST1, and CHOLD1C refers to the capacitance of the first holding capacitor CHOLD1. For example, the even frame final write voltage can be referred to as the even frame data.

[0110] When the second write gate signal GW2 has a non-active level in the even frame write period TPE6A, the seventh transistor T7 may be turned off. Therefore, the voltage of the fourth node N4 may be maintained. In addition, the voltage of the sixth node N6 may be maintained.

[0111] In the even frame emission holding period TPE7A, the emission signal EM may have an inactive level, the control gate signal GR may have an inactive level, the initialization gate signal GI may have an inactive level, the first write gate signal GW1 may have an inactive level, and the second write gate signal GW2 may have an inactive level.

[0112] When the first and second write gate signals GW1 and GW2 have inactive levels in the even frame emission maintaining period TPE7A, voltages of the first, third, fourth and sixth nodes N1, N3, N4 and N6 may be maintained.

[0113] In the even frame emission period TPE8A, the emission signal EM may have an effective level, the control gate signal GR may have an ineffective level, the initialization gate signal GI may have an ineffective level, the first write gate signal GW1 may have an ineffective level, and the second write gate signal GW2 may have an ineffective level.

[0114] The emission signal EM may have an effective level in the even frame emission period TPE8A. Therefore, the fifth transistor T5 may be turned on. The second control electrode of the first transistor T1 may have a voltage of the third node N3. For example, the voltage of the third node N3 may be an even frame final write voltage. Therefore, the first transistor T1 may apply a first drive current to the first light emitting element EE1 based on the even frame final write voltage. Therefore, the first light emitting element EE1 may emit light. For example, the first sub-pixel SPX1A may emit light based on the current even frame data.

[0115] The emission signal EM may have an effective level in the even frame emission period TPE8A. The second control electrode of the sixth transistor T6 may have a voltage of the sixth node N6. For example, the voltage of the sixth node N6 may be VREF-VTH6. Therefore, the sixth transistor T6 may be turned off. Therefore, the second subpixel SPX2A should not emit light in the even frame emission period TPE8A.

[0116] Reference Figure 2 and Figure 3 In this embodiment, the first sub-pixel SPX1A includes a first light-emitting element EE1, and the second sub-pixel SPX2A includes a second light-emitting element EE2. In an embodiment, a first viewing angle of the first light-emitting element EE1 and a second viewing angle of the second light-emitting element EE2 are different from each other. Therefore, one of the first sub-pixel SPX1A and the second sub-pixel SPX2A may be a private mode sub-pixel, and the remaining one may be a public mode sub-pixel. In an embodiment, the emission signal EM applied to the first sub-pixel SPX1A and the second sub-pixel SPX2A is the same. Therefore, the public mode area and the private mode area may be arbitrarily set in a portion of the display panel 100. The first write gate signal GW1 may be applied to the first sub-pixel SPX1A, and the second write gate signal GW2 may be applied to the second sub-pixel SPX2A. In an embodiment, the timing of the first write gate signal GW1 and the timing of the second write gate signal GW2 are different from each other. Therefore, the public mode area and the private mode area may be distinguished according to the image data.

[0117] In an embodiment, the display device 101 can operate in a public mode or a private mode. When the display device 101 operates in the public mode, Figure 3 The signal may be applied to the pixel circuit 111. When the display device 101 operates in the private mode, the second write gate signal GW2 may be maintained at an inactive level during the frame period. Therefore, the second data write operation should not be performed. In addition, the second sub-pixel SPX2A (eg, a public mode sub-pixel) should not emit light.

[0118] Figure 4is a block diagram illustrating a display device 102 according to an embodiment of the inventive concept.

[0119] Reference Figure 4 In addition to the initialization gate signal GI including the first initialization gate signal GI1 and the second initialization gate signal GI2, the control gate signal GR including the first control gate signal GR1 and the second control gate signal GR2, the first initialization gate signal GI1 and the first control gate signal GR1 can be applied to the first sub-pixel SPX1B, and the second initialization gate signal GI2 and the second control gate signal GR2 can be applied to the second sub-pixel SPX2B, the display device 102 according to this embodiment is respectively Figure 1 Therefore, the same reference numerals will be used to refer to the same elements, and any repeated explanation regarding the above elements will be omitted.

[0120] Figure 5 is a diagram showing a method according to an embodiment of the present invention. Figure 4 1 is a circuit diagram of a pixel circuit 112 of a pixel PX of a display device 102.

[0121] Reference Figure 5 , the pixel circuit 112 may include a first sub-pixel SPX1B and a second sub-pixel SPX2B.

[0122] Reference Figure 5 , except that the first control gate signal GR1 is applied to the control node of the third transistor T3, the first initialization gate signal GI1 is applied to the control node of the fourth transistor T4, the second control gate signal GR2 is applied to the control node of the eighth transistor T8, and the second initialization gate signal GI2 is applied to the control node of the ninth transistor T9, the pixel circuit 112 according to this embodiment is respectively connected to Figure 2 Therefore, the same reference numerals will be used to refer to the same elements, and any repeated explanation regarding the above elements will be omitted.

[0123] Figure 6 is shown applied to Figure 5 1 is a timing diagram of an example of an input signal to the pixel circuit 112.

[0124] Reference Figure 6 , the pixel circuit 112 is driven during a plurality of odd frame periods FP1B, FP3B and a plurality of even frame periods FP2B, FP4B.

[0125] Each of the odd frame periods FP1B, FP3B may include an odd frame initialization hold period TPO1B, an odd frame initialization period TPO2B, an odd frame compensation hold period TPO3B, an odd frame compensation period TPO4B, an odd frame write hold period TPO5B, an odd frame write period TPO6B, an odd frame emission hold period TPO7B and an odd frame emission period TPO8B.

[0126] Reference Figure 6 , in the odd-numbered frame initialization holding period TPO1B, the emission signal EM may have a non-effective level, the first control gate signal GR1 may have a non-effective level, the first initialization gate signal GI1 may have a non-effective level, the first write gate signal GW1 may have a non-effective level, the second control gate signal GR2 may be changed from the non-effective level to the effective level, the second initialization gate signal GI2 may have a non-effective level, and the second write gate signal GW2 may have a non-effective level. The pixel circuit 112 may include an N-type transistor. Therefore, the effective level of the first initialization gate signal GI1, the second initialization gate signal GI2, the first control gate signal GR1, the second control gate signal GR2, the first write gate signal GW1, and the second write gate signal GW2 may be a high level. In addition, the non-effective level of the first initialization gate signal GI1, the second initialization gate signal GI2, the first control gate signal GR1, the second control gate signal GR2, the first write gate signal GW1, and the second write gate signal GW2 may be a low level lower than a high level. In another embodiment, when the pixel circuit 112 includes a P-type transistor, the effective level of the first initialization gate signal GI1, the second initialization gate signal GI2, the first control gate signal GR1, the second control gate signal GR2, the first write gate signal GW1, and the second write gate signal GW2 may be a low level. In addition, when the pixel circuit 112 includes a P-type transistor, the ineffective level of the first initialization gate signal GI1, the second initialization gate signal GI2, the first control gate signal GR1, the second control gate signal GR2, the first write gate signal GW1, and the second write gate signal GW2 may be a high level.

[0127] When the emission signal EM has a non-effective level in the odd frame initialization holding period TPO1B, the fifth transistor T5 and the tenth transistor T10 may be turned off. When the first write gate signal GW1 and the second write gate signal GW2 have a non-effective level in the odd frame initialization holding period TPO1B, the second transistor T2 and the seventh transistor T7 may be turned off. In addition, when the second control gate signal GR2 changes to an effective level in the odd frame initialization holding period TPO1B, the eighth transistor T8 may be turned on. Therefore, the reference voltage VREF may be applied to the fourth node N4. For example, the voltage of the fourth node N4 may be the reference voltage VREF.

[0128] When the first control gate signal GR1 and the first initialization gate signal GI1 are maintained at the inactive level in the odd frame initialization holding period TPO1B, the voltage of the first node N1 and the voltage of the third node N3 may have the voltage of the previous frame (e.g., the voltage of the previous even frame). For example, the voltage of the first node N1 may be the data voltage VDATA of the previous even frame, and the voltage of the third node N3 may be the even frame final write voltage of the previous even frame. For example, the even frame final write voltage of the previous even frame may be VREF-VTH1+(CST1C / (CST1C+CHOLD1C))*(VDATA-VREF).

[0129] In the odd frame initialization period TPO2B, the emission signal EM may have a non-valid level, the first control gate signal GR1 may have a non-valid level, the first initialization gate signal GI1 may have a non-valid level, the first write gate signal GW1 may have a non-valid level, the second control gate signal GR2 may have a valid level, the second initialization gate signal GI2 may have a valid level, and the second write gate signal GW2 may have a non-valid level.

[0130] When the second initialization gate signal GI2 has an active level in the odd frame initialization period TPO2B, the ninth transistor T9 may be turned on. Therefore, the initialization voltage VINT may be applied to the sixth node N6. For example, the voltage of the sixth node N6 may be the initialization voltage VINT.

[0131] When the first control gate signal GR1 and the first initialization gate signal GI1 are maintained at the inactive level in the odd frame initialization period TPO2B, the voltage of the first node N1 and the voltage of the third node N3 may have the voltage of the previous frame (e.g., the voltage of the previous even frame). For example, the voltage of the first node N1 may be the data voltage VDATA of the previous even frame, and the voltage of the third node N3 may be the even frame final write voltage of the previous even frame. For example, the even frame final write voltage of the previous even frame may be VREF-VTH1+(CST1C / (CST1C+CHOLD1C))*(VDATA-VREF).

[0132] In the odd frame compensation holding period TPO3B, the emission signal EM may have a non-valid level, the first control gate signal GR1 may have a non-valid level, the first initialization gate signal GI1 may have a non-valid level, the first write gate signal GW1 may have a non-valid level, the second control gate signal GR2 may have a valid level, the second initialization gate signal GI2 may have a non-valid level, and the second write gate signal GW2 may have a non-valid level.

[0133] In the odd frame compensation holding period TP03B, the ninth transistor T9 may be turned off. Therefore, the voltage of the fourth node N4 may maintain the reference voltage VREF. In addition, the voltage of the sixth node N6 may maintain the initialization voltage VINT.

[0134] When the first control gate signal GR1 and the first initialization gate signal GI1 are maintained at the inactive level in the odd frame compensation holding period TP03B, the voltage of the first node N1 and the voltage of the third node N3 may have the voltage of the previous frame (e.g., the voltage of the previous even frame). For example, the voltage of the first node N1 may be the data voltage VDATA of the previous even frame, and the voltage of the third node N3 may be the even frame final write voltage of the previous even frame. For example, the even frame final write voltage of the previous even frame may be VREF-VTH1+(CST1C / (CST1C+CHOLD1C))*(VDATA-VREF).

[0135] In the odd frame compensation period TPO4B, the emission signal EM may have a valid level, the first control gate signal GR1 may have a non-valid level, the first initialization gate signal GI1 may have a non-valid level, the first write gate signal GW1 may have a non-valid level, the second control gate signal GR2 may have a valid level, the second initialization gate signal GI2 may have a non-valid level, and the second write gate signal GW2 may have a non-valid level.

[0136] When the emission signal EM has an effective level in the odd frame compensation period TPO4B, the tenth transistor T10 may be turned on. Therefore, the voltage of the sixth node N6 may be a second compensation voltage. For example, the second compensation voltage may be a value obtained by subtracting a threshold voltage (VTH6) of the sixth transistor T6 from a voltage of the first control electrode of the sixth transistor T6. For example, the second compensation voltage may be a value of VREF-VTH6.

[0137] When the emission signal EM has an effective level in the odd frame compensation period TPO4B, the fifth transistor T5 may be turned on. The second control electrode of the first transistor T1 may have a voltage of the third node N3. Therefore, the first transistor T1 may apply a first drive current to the first light emitting element EE1 based on the even frame final write voltage. Therefore, the first light emitting element EE1 may emit light.

[0138] In the odd frame write hold period TPO5B, the emission signal EM may have a non-valid level, the first control gate signal GR1 may have a non-valid level, the first initialization gate signal GI1 may have a non-valid level, the first write gate signal GW1 may have a non-valid level, the second control gate signal GR2 may change from a valid level to a non-valid level, the second initialization gate signal GI2 may have a non-valid level, and the second write gate signal GW2 may have a non-valid level.

[0139] When the emission signal EM has a non-active level in the odd frame write holding period TPO5B, the fifth transistor T5 may be turned off. In addition, when the second control gate signal GR2 changes from an active level to a non-active level, the eighth transistor T8 may be turned off.

[0140] When the first control gate signal GR1 and the first initialization gate signal GI1 are maintained at the inactive level in the odd frame write holding period TPO5B, the voltage of the first node N1 and the voltage of the third node N3 may have the voltage of the previous frame (e.g., the voltage of the previous even frame). For example, the voltage of the first node N1 may be the data voltage VDATA of the previous even frame, and the voltage of the third node N3 may be the even frame final write voltage of the previous even frame. For example, the even frame final write voltage of the previous even frame may be VREF-VTH1+(CST1C / (CST1C+CHOLD1C))*(VDATA-VREF).

[0141] In the odd frame write period TPO6B, the emission signal EM may have a non-valid level, the first control gate signal GR1 may have a non-valid level, the first initialization gate signal GI1 may have a non-valid level, the first write gate signal GW1 may have a non-valid level, the second control gate signal GR2 may have a non-valid level, the second initialization gate signal GI2 may have a non-valid level, and the second write gate signal GW2 may have a valid level.

[0142] When the second write gate signal GW2 has an effective level in the odd frame write period TPO6B, the seventh transistor T7 can be turned on. Therefore, the data voltage VDATA can be applied to the fourth node N4. For example, the voltage of the fourth node N4 can be the data voltage VDATA. In addition, due to the bootstrap of the second storage capacitor CST2, the voltage of the sixth node N6 can be the odd frame final write voltage. For example, the odd frame final write voltage can be VREF-VTH6+(CST2C / (CST2C+CHOLD2C))*(VDATA-VREF).

[0143] When the first write gate signal GW1 has an inactive level in the odd frame write period TPO6B, the second transistor T2 may be turned off. Therefore, the voltage of the first node N1 and the voltage of the third node N3 may be maintained. For example, the voltage of the third node N3 may be the final write voltage of the even frame of the previous even frame. For example, the final write voltage of the even frame of the previous even frame may be VREF-VTH1+(CST1C / (CST1C+CHOLD1C))*(VDATA-VREF).

[0144] In the odd frame emission holding period TPO7B, the emission signal EM may have a non-valid level, the first control gate signal GR1 may have a non-valid level, the first initialization gate signal GI1 may have a non-valid level, the first write gate signal GW1 may have a non-valid level, the second control gate signal GR2 may have a non-valid level, the second initialization gate signal GI2 may have a non-valid level, and the second write gate signal GW2 may have a non-valid level.

[0145] When the first and second write gate signals GW1 and GW2 have inactive levels in the odd frame emission holding period TPO7B, voltages of the first, third, fourth and sixth nodes N1, N3, N4 and N6 may be maintained.

[0146] In the odd frame emission period TPO8B, the emission signal EM may have a valid level, the first control gate signal GR1 may have a non-valid level, the first initialization gate signal GI1 may have a non-valid level, the first write gate signal GW1 may have a non-valid level, the second control gate signal GR2 may have a non-valid level, the second initialization gate signal GI2 may have a non-valid level, and the second write gate signal GW2 may have a non-valid level.

[0147] When the emission signal EM has an effective level in the odd frame emission period TPO8B, the tenth transistor T10 may be turned on. The second control electrode of the sixth transistor T6 may have a voltage of the sixth node N6. For example, the voltage of the sixth node N6 may be an odd frame final write voltage. Therefore, the sixth transistor T6 may apply a second drive current to the second light emitting element EE2 based on the odd frame final write voltage. Therefore, the second light emitting element EE2 may emit light.

[0148] The emission signal EM may have an effective level in the odd frame emission period TPO8B. Therefore, the fifth transistor T5 may be turned on. The second control electrode of the first transistor T1 may have a voltage of the third node N3. For example, the voltage of the third node N3 may be an even frame final write voltage. Therefore, the first transistor T1 may apply a first drive current to the first light emitting element EE1 based on the even frame final write voltage. Therefore, the first light emitting element EE1 may emit light.

[0149] Each of the even frame periods FP2B, FP4B may include an even frame initialization hold period TPE1B, an even frame initialization period TPE2B, an even frame compensation hold period TPE3B, an even frame compensation period TPE4B, an even frame write hold period TPE5B, an even frame write period TPE6B, an even frame transmission hold period TPE7B and an even frame transmission period TPE8B.

[0150] In the even frame initialization holding period TPE1B, the emission signal EM may have a non-valid level, the first control gate signal GR1 may be changed from the non-valid level to the valid level, the first initialization gate signal GI1 may have a non-valid level, the first write gate signal GW1 may have a non-valid level, the second control gate signal GR2 may have a non-valid level, the second initialization gate signal GI2 may have a non-valid level, and the second write gate signal GW2 may have a non-valid level.

[0151] When the emission signal EM has a non-effective level in the even frame initialization holding period TPE1B, the fifth transistor T5 and the tenth transistor T10 may be turned off. When the first write gate signal GW1 and the second write gate signal GW2 have a non-effective level in the even frame initialization holding period TPE1B, the second transistor T2 and the seventh transistor T7 may be turned off. In addition, when the first control gate signal GR1 changes to an effective level in the even frame initialization holding period TPO1B, the third transistor T3 may be turned on. Therefore, the reference voltage VREF may be applied to the first node N1. For example, the voltage of the first node N1 may be the reference voltage VREF.

[0152] When the second control gate signal GR2 and the second initialization gate signal GI2 are maintained at the inactive level in the even frame initialization holding period TPE1B, the voltage of the fourth node N4 and the voltage of the sixth node N6 may have the voltage of the previous frame (e.g., the voltage of the previous odd frame). For example, the voltage of the fourth node N4 may be the data voltage VDATA of the previous odd frame, and the voltage of the sixth node N6 may be the final write voltage of the odd frame of the previous odd frame. For example, the final write voltage of the odd frame of the previous odd frame may be VREF-VTH6+(CST2C / (CST2C+CHOLD2C))*(VDATA-VREF).

[0153] In the even frame initialization period TPE2B, the emission signal EM may have a non-valid level, the first control gate signal GR1 may have a valid level, the first initialization gate signal GI1 may have a valid level, the first write gate signal GW1 may have a non-valid level, the second control gate signal GR2 may have a non-valid level, the second initialization gate signal GI2 may have a non-valid level, and the second write gate signal GW2 may have a non-valid level.

[0154] When the first initialization gate signal GI1 has an active level in the even frame initialization period TPE2B, the fourth transistor T4 may be turned on. Therefore, the initialization voltage VINT may be applied to the third node N3. For example, the voltage of the third node N3 may be the initialization voltage VINT.

[0155] When the second control gate signal GR2 and the second initialization gate signal GI2 are maintained at the inactive level in the even frame initialization period TPE2B, the voltage of the fourth node N4 and the voltage of the sixth node N6 may have the voltage of the previous frame (e.g., the voltage of the previous odd frame). For example, the voltage of the fourth node N4 may be the data voltage VDATA of the previous odd frame, and the voltage of the sixth node N6 may be the final write voltage of the odd frame of the previous odd frame. For example, the final write voltage of the odd frame of the previous odd frame may be VREF-VTH6+(CST2C / (CST2C+CHOLD2C))*(VDATA-VREF).

[0156] In the even frame compensation holding period TPE3B, the emission signal EM may have a non-valid level, the first control gate signal GR1 may have a valid level, the first initialization gate signal GI1 may have a non-valid level, the first write gate signal GW1 may have a non-valid level, the second control gate signal GR2 may have a non-valid level, the second initialization gate signal GI2 may have a non-valid level, and the second write gate signal GW2 may have a non-valid level.

[0157] In the even frame compensation holding period TPE3B, the fourth transistor T4 may be turned off. Therefore, the voltage of the first node N1 may maintain the reference voltage VREF. In addition, the voltage of the third node N3 may maintain the initialization voltage VINT.

[0158] When the second control gate signal GR2 and the second initialization gate signal GI2 are maintained at the inactive level in the even frame compensation holding period TPE3B, the voltage of the fourth node N4 and the voltage of the sixth node N6 may have the voltage of the previous frame (e.g., the voltage of the previous odd frame). For example, the voltage of the fourth node N4 may be the data voltage VDATA of the previous odd frame, and the voltage of the sixth node N6 may be the final write voltage of the odd frame of the previous odd frame. For example, the final write voltage of the odd frame of the previous odd frame may be VREF-VTH6+(CST2C / (CST2C+CHOLD2C))*(VDATA-VREF).

[0159] In the even frame compensation period TPE4B, the emission signal EM may have a valid level, the first control gate signal GR1 may have a valid level, the first initialization gate signal GI1 may have a non-valid level, the first write gate signal GW1 may have a non-valid level, the second control gate signal GR2 may have a non-valid level, the second initialization gate signal GI2 may have a non-valid level, and the second write gate signal GW2 may have a non-valid level.

[0160] When the emission signal EM has an effective level in the even frame compensation period TPE4B, the fifth transistor T5 may be turned on. Therefore, the voltage of the third node N3 may be a first compensation voltage. For example, the first compensation voltage may be a value obtained by subtracting a threshold voltage (VTH1) of the first transistor T1 from a voltage of the first control electrode of the first transistor T1. For example, the first compensation voltage may be a value of VREF-VTH1.

[0161] When the emission signal EM has an effective level in the even frame compensation period TPE4B, the tenth transistor T10 may be turned on. The second control electrode of the sixth transistor T6 may have the voltage of the sixth node N6. Therefore, the sixth transistor T6 may apply the second driving current to the second light emitting element EE2 based on the odd frame final write voltage. Therefore, the second light emitting element EE2 may emit light.

[0162] In the even frame write hold period TPE5B, the emission signal EM may have a non-valid level, the first control gate signal GR1 may change from a valid level to a non-valid level, the first initialization gate signal GI1 may have a non-valid level, the first write gate signal GW1 may have a non-valid level, the second control gate signal GR2 may have a non-valid level, the second initialization gate signal GI2 may have a non-valid level, and the second write gate signal GW2 may have a non-valid level.

[0163] When the emission signal EM has a non-active level in the even frame write holding period TPE5B, the fifth transistor T5 may be turned off. In addition, when the first control gate signal GR1 changes from an active level to a non-active level, the third transistor T3 may be turned off.

[0164] When the emission signal EM has a non-effective level in the even frame write holding period TPE5B, the tenth transistor T10 may be turned off. In addition, when the second control gate signal GR2 and the second initialization gate signal GI2 are maintained at a non-effective level in the even frame write holding period TPE5B, the voltage of the fourth node N4 and the voltage of the sixth node N6 may have a voltage of a previous frame (e.g., a voltage of a previous odd frame). For example, the voltage of the fourth node N4 may be the data voltage VDATA of the previous odd frame, and the voltage of the sixth node N6 may be the final write voltage of the odd frame of the previous odd frame. For example, the final write voltage of the odd frame of the previous odd frame may be VREF-VTH6+(CST2C / (CST2C+CHOLD2C))*(VDATA-VREF).

[0165] In the even frame write period TPE6B, the emission signal EM may have a non-valid level, the first control gate signal GR1 may have a non-valid level, the first initialization gate signal GI1 may have a non-valid level, the first write gate signal GW1 may have a valid level, the second control gate signal GR2 may have a non-valid level, the second initialization gate signal GI2 may have a non-valid level, and the second write gate signal GW2 may have a non-valid level.

[0166] When the first write gate signal GW1 has an effective level in the even frame write period TPE6B, the second transistor T2 may be turned on. Therefore, the data voltage VDATA may be applied to the first node N1. For example, the voltage of the first node N1 may be the data voltage VDATA. In addition, due to the bootstrap of the first storage capacitor CST1, the voltage of the third node N3 may be the even frame final write voltage. For example, the even frame final write voltage may be VREF-VTH1+(CST1C / (CST1C+CHOLD1C))*(VDATA-VREF).

[0167] When the second write gate signal GW2 has an inactive level in the even frame write period TPE6B, the seventh transistor T7 may be turned off. Therefore, the voltage of the fourth node N4 and the voltage of the sixth node N6 may be maintained. For example, the voltage of the sixth node N6 may be the final write voltage of the odd frame of the previous odd frame. For example, the final write voltage of the odd frame of the previous odd frame may be VREF-VTH6+(CST2C / (CST2C+CHOLD2C))*(VDATA-VREF).

[0168] In the even frame emission holding period TPE7B, the emission signal EM may have a non-valid level, the first control gate signal GR1 may have a non-valid level, the first initialization gate signal GI1 may have a non-valid level, the first write gate signal GW1 may have a non-valid level, the second control gate signal GR2 may have a non-valid level, the second initialization gate signal GI2 may have a non-valid level, and the second write gate signal GW2 may have a non-valid level.

[0169] When the first and second write gate signals GW1 and GW2 have inactive levels in the even frame emission maintaining period TPE7B, voltages of the first, third, fourth and sixth nodes N1, N3, N4 and N6 may be maintained.

[0170] In the even frame emission period TPE8B, the emission signal EM may have a valid level, the first control gate signal GR1 may have a non-valid level, the first initialization gate signal GI1 may have a non-valid level, the first write gate signal GW1 may have a non-valid level, the second control gate signal GR2 may have a non-valid level, the second initialization gate signal GI2 may have a non-valid level, and the second write gate signal GW2 may have a non-valid level.

[0171] When the emission signal EM has an effective level in the even frame emission period TPE8B, the fifth transistor T5 may be turned on. The second control electrode of the first transistor T1 may have a voltage of the third node N3. For example, the voltage of the third node N3 may be an even frame final write voltage. Therefore, the first transistor T1 may apply a first drive current to the first light emitting element EE1 based on the even frame final write voltage. Therefore, the first light emitting element EE1 may emit light. For example, the first sub-pixel SPX1A may emit light based on the current even frame data.

[0172] The emission signal EM may have an effective level in the even frame emission period TPE8B. Therefore, the tenth transistor T10 may be turned on. The second control electrode of the sixth transistor T6 may have a voltage of the sixth node N6. For example, the voltage of the sixth node N6 may be an odd frame final write voltage. Therefore, the sixth transistor T6 may apply a second drive current to the second light emitting element EE2 based on the odd frame final write voltage. Therefore, the second light emitting element EE2 may emit light.

[0173] Reference Figure 4 and Figure 5 In this embodiment, the first sub-pixel SPX1B includes a first light-emitting element EE1, and the second sub-pixel SPX2B includes a second light-emitting element EE2. In the embodiment, a first viewing angle of the first light-emitting element EE1 and a second viewing angle of the second light-emitting element EE2 are different from each other. Therefore, one of the first sub-pixel SPX1B and the second sub-pixel SPX2B may be a private mode sub-pixel, and the remaining one may be a public mode sub-pixel.

[0174] In an embodiment, the emission signal EM applied to the first sub-pixel SPX1B and the second sub-pixel SPX2B is the same. Therefore, the public mode area and the private mode area can be arbitrarily set in various areas of the display panel 100. For example, instead of using fixed areas of the display panel 100 as the public mode area and the private mode area, these areas can be dynamically configured to various sizes and positions. The first write gate signal GW1 can be applied to the first sub-pixel SPX1B, and the second write gate signal GW2 can be applied to the second sub-pixel SPX2B. In addition, in an embodiment, the timing of the first write gate signal GW1 and the timing of the second write gate signal GW2 are different from each other. Therefore, the public mode area and the private mode area can be distinguished from each other according to the image data. In addition, the second sub-pixel SPX2B can emit light based on the final write voltage of the odd frame in the even frame compensation period TPE4B and the even frame emission period TPE8B. In addition, the first sub-pixel SPX1B can emit light based on the final write voltage of the even frame in the odd frame compensation period TPO4B and the odd frame emission period TPO8B. The display device 102 in which the public mode and the private mode are separated can be operated using time-division driving with the emission time reduced to 50%. However, at least one embodiment of the inventive concept can emit light by maintaining the value of the previous frame. Therefore, the brightness control of the pixel circuit 112 can be improved.

[0175] In an embodiment, the display device 102 operates in a public mode or a private mode. When the display device 102 operates in the public mode, Figure 6 The signal may be applied to the pixel circuit 112. In an embodiment, when the display device 102 operates in the private mode, the second write gate signal GW2 is maintained at an inactive level during the frame period. Therefore, the second data write operation should not be performed. In addition, the second sub-pixel SPX2B (eg, the public mode sub-pixel) should not emit light.

[0176] Figure 7 is a block diagram illustrating a display device 103 according to an embodiment of the inventive concept. Figure 8 It is shown Figure 7 1 is a circuit diagram of a pixel circuit 113 of a pixel PX of a display device 103.

[0177] Reference Figure 7 and Figure 8, the pixel circuit 113 may include a first sub-pixel SPX1C and a second sub-pixel SPX2C. In addition to the data driver 500 applying the first data voltage OVDATA (e.g., odd frame data voltage) and the first reference voltage OVREF (e.g., odd frame reference voltage) to the second sub-pixel SPX2C and the data driver 500 applying the second data voltage EVDATA (e.g., even frame data voltage) and the second reference voltage EVREF (e.g., even frame reference voltage) to the first sub-pixel SPX1C, the display device 103 according to this embodiment is respectively connected to Figure 4 Therefore, the same reference numerals will be used to refer to the same elements, and any repeated explanations regarding the above elements will be omitted.

[0178] Reference Figure 7 and Figure 8 , except that the first electrode of the second transistor T2 is applied with the second data voltage EVDATA, the first electrode of the third transistor T3 is applied with the second reference voltage EVREF, the first electrode of the seventh transistor T7 is applied with the first data voltage OVDATA, and the first electrode of the eighth transistor T8 is applied with the first reference voltage OVREF, the pixel circuit 113 according to this embodiment is respectively connected to Figure 5 The pixel circuit 112 of FIG. 1 is substantially the same as that of FIG. 1 . Therefore, the same reference numerals will be used to refer to the same elements, and any repeated explanation about the above elements will be omitted. In an embodiment, the first data voltage OVDATA and the first reference voltage OVREF are applied during the odd frame period, and the second data voltage EVDATA and the second reference voltage EVREF are applied during the even frame period. In an embodiment, the first reference voltage OVREF is different from the second reference voltage EVREF.

[0179] Reference Figure 7 and Figure 8 , the data driver 500 applies the first data voltage OVDATA, the first reference voltage OVREF, the second data voltage EVDATA, and the second reference voltage EVREF to the pixel circuit 113. Therefore, more optimized brightness control of the pixel circuit 113 can be achieved.

[0180] Fig. 9 is a block diagram illustrating an electronic device 1000 according to an embodiment of the inventive concept. Fig.10 It is shown Fig. 9 FIG. 1 is a diagram of an example in which the electronic device 1000 is implemented as a smart phone.

[0181] Reference Fig. 9 and Fig.10, the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. Here, the display device 1060 may be Figure 1 , Figure 4 or Figure 7 In addition, the electronic device 1000 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like.

[0182] According to an embodiment, Fig.10 As shown in , the electronic device 1000 can be implemented as a smart phone. However, the electronic device 1000 is not limited thereto. For example, the electronic device 1000 can be implemented as a cellular phone, a video phone, a smart tablet, a smart watch, a tablet personal computer (PC), a car navigation system, a computer monitor, a laptop computer, and a head mounted display (HMD) device, etc.

[0183] The processor 1010 may perform various computing functions or various tasks. The processor 1010 may be a microprocessor, a central processing unit (CPU), an application processor (AP), etc. The processor 1010 may be coupled to other components via an address bus, a control bus, a data bus, etc. In addition, the processor 1010 may be coupled to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0184] The processor 1010 can output the input image data IMG and the input control signal CONT to Figure 1 , Figure 4 or Figure 7 A drive controller 200 is provided.

[0185] The memory device 1020 may store data used for the operation of the electronic device 1000. For example, the memory device 1020 may include at least one nonvolatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, and a ferroelectric random access memory (FRAM) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, and a mobile DRAM device, etc.).

[0186] The storage device 1030 may include a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I / O device 1040 may include an input device (such as a keyboard, a keypad, a mouse device, a touch pad, and a touch screen, etc.) and an output device (such as a printer and a speaker, etc.). In some embodiments, a display device 1060 may be included in the I / O device 1040. The power supply 1050 may provide power for the operation of the electronic device 1000. The display device 1060 may be coupled to other components via a bus or other communication link.

[0187] According to at least one embodiment, a pixel may include a first sub-pixel and a second sub-pixel that receive different write gate signals, so that each of the sub-pixels can be a public mode sub-pixel or a private mode sub-pixel. Since the write gate signal can be applied to the sub-pixel according to the image data and the same emission signal can be applied to the sub-pixel, the public mode area and the private mode area can be arbitrarily set in each area of ​​the display panel of the display device. Therefore, the position of displaying the public mode area and the private mode area in the display panel of the display device can be dynamically changed according to the image data.

[0188] The foregoing is an illustration of the inventive concept and should not be construed as limiting it. Although some embodiments of the inventive concept have been described, it will be readily appreciated by those skilled in the art that many modifications may be made in the embodiments without substantially departing from the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims.

Claims

1. A pixel, comprising: a first subpixel including a first light emitting element, a first transistor configured to apply a first driving current to the first light emitting element, a second transistor configured to apply a data voltage to the first transistor in response to a first write gate signal, and a fifth transistor configured to apply a first power supply voltage to the first transistor in response to an emission signal; as well as A second subpixel includes a second light-emitting element having a viewing angle different from that of the first light-emitting element, a sixth transistor configured to apply a second drive current to the second light-emitting element, a seventh transistor configured to apply the data voltage to the sixth transistor in response to a second write gate signal different from the first write gate signal, and a tenth transistor configured to apply the first power supply voltage to the sixth transistor in response to the emission signal.

2. The pixel according to claim 1, wherein: The first sub-pixel is a privacy mode sub-pixel having a first viewing angle, and The second sub-pixel is a common mode sub-pixel having a second viewing angle wider than the first viewing angle.

3. The pixel according to claim 1, wherein: In an odd-numbered frame period, the second transistor is turned off, and the seventh transistor is turned on.

4. The pixel according to claim 1, wherein: In an even-numbered frame period, the second transistor is turned on, and the seventh transistor is turned off.

5. The pixel according to claim 1, wherein: The first sub-pixel comprises: The first transistor includes a first control electrode connected to the first node, a second control electrode connected to the third node, a first electrode connected to the second node, and a second electrode connected to the third node; the second transistor including a control electrode configured to receive the first write gate signal, a first electrode configured to receive the data voltage, and a second electrode connected to the first node; a third transistor including a control electrode configured to receive a control gate signal, a first electrode configured to receive a reference voltage, and a second electrode connected to the first node; a fourth transistor including a control electrode configured to receive an initialization gate signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to the third node; a first storage capacitor including a first electrode connected to the third node and a second electrode connected to the first node; a first holding capacitor including a first electrode configured to receive the first power supply voltage and a second electrode connected to the third node; and the first light emitting element, and Wherein, the second sub-pixel includes: The sixth transistor includes a first control electrode connected to the fourth node, a second control electrode connected to the sixth node, a first electrode connected to the fifth node, and a second electrode connected to the sixth node; the seventh transistor including a control electrode configured to receive the second write gate signal, a first electrode configured to receive the data voltage, and a second electrode connected to the fourth node; an eighth transistor including a control electrode configured to receive the control gate signal, a first electrode configured to receive the reference voltage, and a second electrode connected to the fourth node; a ninth transistor including a control electrode configured to receive the initialization gate signal, a first electrode configured to receive the initialization voltage, and a second electrode connected to the sixth node; a tenth transistor including a control electrode configured to receive the transmission signal, a first electrode configured to receive the first power supply voltage, and a second electrode connected to the fifth node; a second storage capacitor including a first electrode connected to the sixth node and a second electrode connected to the fourth node; a second holding capacitor including a first electrode configured to receive the first power supply voltage and a second electrode connected to the sixth node; and The second light emitting element.

6. The pixel according to claim 5, wherein: The odd frame period of the pixel includes: an odd-numbered frame initialization period, in which the emission signal has a non-active level, the control gate signal has a valid level, the initialization gate signal has a valid level, the first write gate signal has a non-active level, and the second write gate signal has a non-active level; an odd-numbered frame compensation period, in which the emission signal has an effective level, the control gate signal has an effective level, the initialization gate signal has an ineffective level, the first write gate signal has an ineffective level, and the second write gate signal has an ineffective level; an odd-numbered frame writing period, in which the emission signal has a non-active level, the control gate signal has a non-active level, the initialization gate signal has a non-active level, the first writing gate signal has a non-active level, and the second writing gate signal has a valid level; and an odd-numbered frame emission period, in which the emission signal has an effective level, the control gate signal has an ineffective level, the initialization gate signal has an ineffective level, the first write gate signal has an ineffective level, and the second write gate signal has an ineffective level, and Wherein, the even frame period of the pixel includes: an even-numbered frame initialization period, in which the emission signal has a non-active level, the control gate signal has a valid level, the initialization gate signal has a valid level, the first write gate signal has a non-active level, and the second write gate signal has a non-active level; an even frame compensation period, in which the emission signal has an effective level, the control gate signal has an effective level, the initialization gate signal has an ineffective level, the first write gate signal has an ineffective level, and the second write gate signal has an ineffective level; an even-numbered frame writing period, in which the emission signal has a non-active level, the control gate signal has a non-active level, the initialization gate signal has a non-active level, the first writing gate signal has a valid level, and the second writing gate signal has a non-active level; and An even frame emission period, in which the emission signal has a valid level, the control gate signal has a non-valid level, the initialization gate signal has a non-valid level, the first write gate signal has a non-valid level, and the second write gate signal has a non-valid level.

7. A display device, comprising: A display panel comprising a first sub-pixel and a second sub-pixel having a viewing angle different from that of the first sub-pixel; a data driver configured to apply a data voltage and a reference voltage to the display panel; a gate driver configured to apply a control gate signal, an initialization gate signal, a first write gate signal, and a second write gate signal to the display panel; an emission driver configured to apply an emission signal to the display panel; as well as a driving controller configured to control the data driver, the gate driver, and the emission driver, The first sub-pixel and the second sub-pixel are configured to receive the same emission signal among the emission signals.

8. The display device according to claim 7, wherein: The first sub-pixel is a privacy mode sub-pixel having a first viewing angle, and The second sub-pixel is a common mode sub-pixel having a second viewing angle wider than the first viewing angle.

9. The display device according to claim 7, in, The data writing operation is not performed on the first sub-pixel in an odd-numbered frame writing period of an odd-numbered frame cycle, and the data writing operation is performed on the second sub-pixel in the odd-numbered frame writing period.

10. The display device according to claim 9, wherein: In an odd-numbered frame emission period of the odd-numbered frame cycle, the first sub-pixel emits light based on previous even-numbered frame data, and the second sub-pixel emits light based on current odd-numbered frame data.

11. The display device according to claim 9, in, performing an initialization operation on the first sub-pixel in an odd-numbered frame initialization period of the odd-numbered frame cycle, and Wherein, a compensation operation is performed on the first sub-pixel in an odd frame compensation period of the odd frame cycle.

12. The display device according to claim 11, wherein: In an odd-numbered frame emission period of the odd-numbered frame cycle, the first sub-pixel does not emit light, and the second sub-pixel emits light based on current odd-numbered frame data.

13. The display device according to claim 11, in, The data writing operation is not performed on the second sub-pixel in an even frame writing period of an even frame cycle, and the data writing operation is performed on the first sub-pixel in the even frame writing period of the even frame cycle.

14. The display device according to claim 13, wherein: In an even frame emission period of the even frame cycle, the second sub-pixel emits light based on previous odd frame data, and the first sub-pixel emits light based on current even frame data.

15. The display device according to claim 13, in, performing an initialization operation on the second sub-pixel in an even-numbered frame initialization period of the even-numbered frame cycle, and Wherein, a compensation operation is performed on the second sub-pixel in an even frame compensation period of the even frame cycle.

16. The display device according to claim 15, wherein: In an even frame emission period of the even frame cycle, the second sub-pixel does not emit light, and the first sub-pixel emits light based on current even frame data.

17. The display device according to claim 7, wherein: The display device operates in a private mode or a public mode, and Wherein, in the private mode, no data writing operation is performed on the second sub-pixel in a frame period.

18. The display device according to claim 7, wherein: The data driver applies a first data voltage and a first reference voltage to the first subpixel, and the data driver applies a second data voltage different from the first data voltage and a second reference voltage different from the first reference voltage to the second subpixel.

19. The display device according to claim 7, wherein: The first subpixel includes a first light emitting element, a first transistor configured to apply a first driving current to the first light emitting element, a second transistor configured to apply a data voltage to the first transistor in response to a first write gate signal, and a fifth transistor configured to apply a first power supply voltage to the first transistor in response to an emission signal, The second sub-pixel includes a second light-emitting element having a viewing angle different from that of the first light-emitting element, a sixth transistor configured to apply a second driving current to the second light-emitting element, a seventh transistor configured to apply the data voltage to the sixth transistor in response to a second write gate signal different from the first write gate signal, and a tenth transistor configured to apply the first power supply voltage to the sixth transistor in response to the emission signal.

20. The display device according to claim 19, wherein The first sub-pixel comprises: The first transistor includes a first control electrode connected to the first node, a second control electrode connected to the third node, a first electrode connected to the second node, and a second electrode connected to the third node; the second transistor including a control electrode configured to receive the first write gate signal, a first electrode configured to receive the data voltage, and a second electrode connected to the first node; a third transistor including a control electrode configured to receive a control gate signal, a first electrode configured to receive a reference voltage, and a second electrode connected to the first node; a fourth transistor including a control electrode configured to receive an initialization gate signal, a first electrode configured to receive an initialization voltage, and a second electrode connected to the third node; a first storage capacitor including a first electrode connected to the third node and a second electrode connected to the first node; a first holding capacitor including a first electrode configured to receive the first power supply voltage and a second electrode connected to the third node; and the first light emitting element, and Wherein, the second sub-pixel includes: The sixth transistor includes a first control electrode connected to the fourth node, a second control electrode connected to the sixth node, a first electrode connected to the fifth node, and a second electrode connected to the sixth node; the seventh transistor including a control electrode configured to receive the second write gate signal, a first electrode configured to receive the data voltage, and a second electrode connected to the fourth node; an eighth transistor including a control electrode configured to receive the control gate signal, a first electrode configured to receive the reference voltage, and a second electrode connected to the fourth node; a ninth transistor including a control electrode configured to receive the initialization gate signal, a first electrode configured to receive the initialization voltage, and a second electrode connected to the sixth node; a tenth transistor including a control electrode configured to receive the transmission signal, a first electrode configured to receive the first power supply voltage, and a second electrode connected to the fifth node; a second storage capacitor including a first electrode connected to the sixth node and a second electrode connected to the fourth node; a second holding capacitor including a first electrode configured to receive the first power supply voltage and a second electrode connected to the sixth node; and The second light emitting element.

21. A display device, comprising: A display panel comprising a plurality of pixels, wherein each pixel of the plurality of pixels comprises a first sub-pixel and a second sub-pixel; a gate driver configured to generate a first write gate signal and a second write gate signal different from the first write gate signal; and an emission driver configured to apply a plurality of emission signals to the display panel, wherein the first subpixel includes a first light emitting element having a first viewing angle, a first driving transistor configured to apply a first driving current to the first light emitting element, a first data writing transistor configured to apply a data voltage to the first driving transistor in response to the first writing gate signal, and a first emission control transistor configured to apply a power supply voltage to the first driving transistor in response to a first emission signal among the emission signals, and Among them, the second sub-pixel includes a second light-emitting element having a second viewing angle different from the first viewing angle, a second driving transistor configured to apply a second driving current to the second light-emitting element, a second data write transistor configured to apply the data voltage to the second driving transistor in response to the second write gate signal, and an emission control transistor configured to apply the power supply voltage to the second driving transistor in response to the first emission signal.

Images