Level shift driving circuit and driving method

Abstract

Embodiments of the present application relate to a level conversion driving circuit and a driving method. The circuit comprises a main board, a display panel and a target level conversion module, the target level conversion module containing at least one level converter; one end of the level converter in the target level conversion module is connected to the main board; the other end of the level converter in the target level conversion module is connected to the display panel; different types of level converters are selected according to the odd-even timing requirements of the display panel or the 2line mode mode, so as to achieve the purpose of flexible driving display of the display panel for special timing requirements. Thus, the timing support of various requirements of the display screen can be realized, flexible display is achieved, and the technical effect of improving the driving refresh rate of the display screen is achieved.

Description

Technical Field

[0001] This application relates to the technical field of level conversion control in the display driving process, and particularly to a level conversion driving circuit and driving method. Background Technology

[0002] In TV display panel driving, the level shifter IC is a crucial component. In a full-featured TCON board (with TCON IC), the level shifter IC works with the TCON IC to complete the GOA (Gate on Array, where the scanning circuitry is integrated on the glass, unlike the earlier Gate COF architecture) driving timing for the display. This includes the start scan signal STV, the horizontal scan clock signal CK, the GOA drive circuit direction control input signals LC1 / LC2, and partial screen reset signals such as STV0 or Reset. In a TCON-less board, the system-on-a-chip (SOC) (with TCON functionality integrated into the SOC) works with the level shifter IC to generate the GOA drive signals required by the display. Besides receiving control signals or input signals from the SOC or TCON IC, the level shifter IC requires a PMIC (Power Microcontroller) such as VGH / VGL / DVDD3V3) to ensure proper operation. Under normal power supply, the level shifter IC is controlled by the inputs from the SOC or TCON IC and, combined with its internal logic, generates the driving timing required for a specific screen.

[0003] Early level shifter ICs had relatively simple functions, mostly consisting of single-input, single-output logic, which was entirely determined by the TCON IC or SOC. However, for more complex GOA timing patterns, dual-input, multi-output level shifter ICs may not be able to meet the requirements.

[0004] In recent years, display panels have been developing towards high refresh rate local control and other technologies. HSR (High Refresh Rate Boosting) panels (which increase the refresh rate through external driving, sacrificing some resolution) have emerged in large numbers. Simultaneously, to reduce panel costs, dual-gate designs are being implemented on top of HSR panels, achieving a reduction of half the COF (Copy-on-Flight) driving. The most significant problem encountered by panels with these characteristics is image quality, and the most crucial factor affecting image quality is charging time. Improving charging time requires various special GOA (Getting Over-Ahead) timing sequences. These special GOA timing sequences are difficult to drive using the widely used binary-mode multi-output level shifter ICs. Summary of the Invention

[0005] In view of this, in order to solve the technical problem that the timing requirements of the display panel for odd and even number timing or specific HSR mode cannot be met, the embodiments of this application provide a level conversion driving circuit and driving method.

[0006] In a first aspect, embodiments of this application provide a level conversion driving circuit, including: The motherboard, the display panel, and the target level conversion module, wherein the target level conversion module contains at least one level converter; The motherboard is connected to one end of the level converter in the target level conversion module; The other end of the level converter in the target level conversion module is connected to the display panel; The motherboard is used to input control signals and timing signals to the target level conversion module; The target level conversion module is used to receive the control signal and the timing signal input from the motherboard and then generate a drive signal; The display panel is used to drive the liquid crystal display after receiving the drive signal input from the target level conversion module.

[0007] In one possible implementation, the target level conversion module includes at least one one-input-one-output level converter; The one-in-one-out level converter includes n signal input terminals and n signal output terminals, and one input terminal of the one-in-one-out level converter corresponds to one output terminal, where n is a positive integer greater than or equal to 1; Each input terminal of the one-in-one-out level converter is connected to one of the n output terminals of the motherboard, and each output terminal of the one-in-one-out level converter is connected to one of the n input terminals of the display panel. The input-output level converter is used to receive the first control signal and the first timing signal input from the motherboard and then generate the first drive signal. The input-output level converter is also used to input a first drive signal to the display panel.

[0008] In one possible implementation, the target level conversion module includes at least one multiple-input multiple-output level converter, wherein the number of input ports of each multiple-input multiple-output level converter is not exactly the same, and the number of output ports of each multiple-input multiple-output level converter is not exactly the same; The multiple input terminals of each of the multiple input-multiple output level converters are respectively connected to the multiple output terminals of the motherboard, and the multiple output terminals of each of the multiple input-multiple output level converters are respectively connected to the multiple input terminals of the display panel; The multiple-input multiple-output level converter is used to receive the second timing signal and the second control signal input from the motherboard and then generate the second drive signal. The multiple-input multiple-output level converter is also used to input the second drive signal to the display panel.

[0009] In one possible implementation, the target level conversion module includes at least one single-input single-output level converter and at least one multiple-input multiple-output level converter, wherein the single-input single-output level converter and the multiple-input multiple-output level converter are of different types; The multiple input terminals of the one-in-one-out level converter are connected to the multiple output terminals of the motherboard, and the multiple output terminals of the one-in-one-out level converter are connected to the multiple input terminals of the display panel. Each of the multiple input terminals of the multiple input-multiple output level converter is connected to multiple output terminals of the motherboard, and each of the multiple output terminals of the multiple input-multiple output level converter is connected to multiple input terminals of the display panel. There is no cross connection between the input terminals and output terminals of any two level converters.

[0010] In one possible implementation, the one-in-one-out level converter is a 6-in-6-out level converter; The six input signal terminals of the 6-input 6-output level converter are respectively connected to the six output terminals of the motherboard, and the six output terminals of the 6-input 6-output level converter are respectively connected to the six input terminals of the display panel. Alternatively, the one-in-one-out level converter may be an eight-in-eight-out level converter; The eight input signal terminals of the 8-input 8-output level converter are respectively connected to the eight output terminals of the motherboard, and the eight output terminals of the 8-input 8-output level converter are respectively connected to the eight input terminals of the display panel. Alternatively, the one-in-one-out level converter can be a 10-in-10-out level converter; The 10 input signal terminals of the 10-input 10-output level converter are respectively connected to the 10 output terminals of the motherboard, and the 10 output terminals of the 10-input 10-output level converter are respectively connected to the 10 input terminals of the display panel. Alternatively, the one-in-one-out level converter can be a 12-in-12-out level converter; The 12 input signal terminals of the 12-input 12-output level converter are respectively connected to the 12 output terminals of the motherboard, and the 12 output terminals of the 12-input 12-output level converter are respectively connected to the 12 input terminals of the display panel. Alternatively, the one-in-one-out level converter can be a 16-in-16-out level converter; The 16 input signal terminals of the 16-input 16-output level converter are respectively connected to the 16 output terminals of the motherboard, and the 16 output terminals of the 16-input 16-output level converter are respectively connected to the 16 input terminals of the display panel.

[0011] In one possible implementation, the multiple-input multiple-output level converter is a 2-input 12-output level converter; The two input terminals of the 2-input 12-output level converter are respectively connected to the two output terminals of the motherboard, and the 12 output terminals of the 2-input 12-output level converter are respectively connected to the 12 input terminals of the display panel. Alternatively, the multiple-input multiple-output level converter is a 2-input 10-output level converter; The two input terminals of the 2-input 10-output level converter are respectively connected to the two output terminals of the motherboard, and the ten output terminals of the 2-input 10-output level converter are respectively connected to the ten input terminals of the display panel. Alternatively, the multiple-input multiple-output level converter is a 2-input 8-output level converter; The two input terminals of the 2-input 8-output level converter are respectively connected to the two output terminals of the motherboard, and the eight output terminals of the 2-input 8-output level converter are respectively connected to the eight input terminals of the display panel. Alternatively, the multiple-input multiple-output level converter is a 2-input 6-output level converter; The two input terminals of the 2-input 6-output level converter are respectively connected to the two output terminals of the motherboard, and the six output terminals of the 2-input 6-output level converter are respectively connected to the six input terminals of the display panel.

[0012] In a second aspect, embodiments of this application provide a level conversion driving method, applied to a general level conversion driving circuit as described in any of the first aspects, comprising: Obtain the target timing requirements of the display panel and determine the target mode of the display panel corresponding to the target timing requirements, wherein the target mode characterizes the display panel's display parity or multilinearity; The target model corresponding to the level conversion module is determined according to the target mode, and the target model represents the application product type of the level converter in the level conversion module; A level conversion driving circuit is constructed based on the target model to drive the display panel to display the image.

[0013] In one possible implementation, determining the target mode of the display panel corresponding to the target timing requirement includes: When the target timing requirements include driving requirements for an odd number of timings, the target category of the display panel is determined to be an odd-number mode; or, When the target timing requirements include an even number of timing drive requirements, the target category of the display panel is determined to be an even-number mode; or, When the target timing requirement includes the driving requirement of the threshold output timing signal, the target category of the display panel is determined to be super-resolution mode, and the threshold output timing signal represents the number of output signals as a preset maximum number of outputs; or, When the target timing requirements include the driving requirements of an odd number of timing signals and threshold output timing signals, the target mode of the display panel is determined to be an odd super-resolution mode. or, When the target timing requirements include an even number of timing signals and a threshold output timing signal driving requirement, the target mode of the display panel is determined to be an even number super-resolution mode.

[0014] In one possible implementation, determining the target model corresponding to the level conversion module based on the target mode includes: When the target mode is an odd number mode, the target model of the level conversion module is determined to be a single-input single-output level converter, or a single-input single-output level converter and at least one multi-input multi-output level converter. When the target mode is an even number mode, the target model of the level conversion module is determined to be one single-input single-output level converter and / or at least one multi-input multi-output level converter; When the target mode is super-resolution mode, the target model of the level conversion module is determined to be at least one multiple-input multiple-output level converter, or, one single-input single-output level converter and at least one multiple-input multiple-output level converter. When the target mode is an odd super-resolution mode, the target model of the level conversion module is determined to be one single-input single-output level converter and at least one multi-input multi-output level converter; When the target mode is an even-number super-resolution mode, the target model of the level conversion module is determined to be at least one multi-input multi-output level converter, or one single-input single-output level converter and at least one multi-input multi-output level converter.

[0015] In one possible implementation, the construction of the level shifting driver circuit based on the target model includes: When the target model is a single input-output level converter and at least one multiple input-multiple output level converter, the single input-output level converter is configured with an odd number of input terminals and an odd number of output terminals; The output terminal of each of the multiple input multiple output level converters is connected to the input terminal of the display panel according to a preset rule to construct a level conversion drive circuit; or, When the target model is at least one multiple-input multiple-output level converter, the output terminal of each multiple-input multiple-output level converter is connected to the input terminal of the display panel according to a preset rule to construct a level conversion drive circuit; or, When the target model is a single input-output level converter, the output terminal of each input-output level converter is connected to the input terminal of the display panel according to a preset rule to construct a level conversion drive circuit.

[0016] The level conversion driving circuit provided in this application embodiment comprises a motherboard, a display panel, and a target level conversion module. The target level conversion module includes at least one level converter. The motherboard is connected to one end of the level converter in the target level conversion module; the other end of the level converter in the target level conversion module is connected to the display panel. The motherboard is used to input control signals and timing signals to the target level conversion module. The target level conversion module is used to receive the control signals and timing signals input from the motherboard and then generate a driving signal. The display panel is used to receive the driving signal input from the target level conversion module and then drive the liquid crystal display. Different types of level converters are selected according to the display panel's odd / even timing requirements or super-resolution mode, achieving flexible driving display for specific timing requirements. This solution can achieve timing support for various display needs, resulting in flexible display and improved display refresh rate. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0020] Figure 1a This is a timing diagram of a level conversion driving display circuit provided in the prior art; Figure 1b A schematic diagram of a level conversion driving display circuit provided in the prior art; Figure 1c This is a timing diagram for another level-conversion driving display circuit provided in the prior art; Figure 1d A schematic diagram of another level conversion driving display circuit provided in the prior art; Figure 2 This is a schematic diagram of a level conversion driving circuit provided in Embodiment 1 of this application; Figure 3 This is a schematic diagram of a level conversion driving circuit provided in Embodiment 2 of this application; Figure 4 This is a schematic diagram of another level conversion driving circuit provided in Embodiment 2 of this application; Figure 5a A timing diagram of a level conversion driving circuit provided in Embodiment 3 of this application; Figure 5b This is a schematic diagram of a level conversion driving circuit provided in Embodiment 3 of this application; Figure 5c This is a schematic diagram of another level conversion driving circuit provided in Embodiment 3 of this application; Figure 6a A timing diagram of a level conversion driving circuit provided in Embodiment 4 of this application; Figure 6b This is a schematic diagram of a level conversion driving circuit provided in Embodiment 4 of this application; Figure 6c This is a schematic diagram of another level conversion driving circuit provided in Embodiment 4 of this application; Figure 7 This is a schematic diagram of a level conversion driving circuit provided in Embodiment 5 of this application; Figure 8 A timing diagram of another level conversion driving circuit provided in Embodiment 5 of this application; Figure 9a A timing diagram of a level conversion driving circuit provided in Embodiment Six of this application; Figure 9b This is a schematic diagram of a level conversion driving circuit provided in Embodiment Six of this application; Figure 9c This is a schematic diagram of another level conversion driving circuit provided in Embodiment Six of this application; Figure 9dThis is a schematic diagram of another level conversion driving circuit provided in Embodiment Six of this application; Figure 9e This is a schematic diagram of another level conversion driving circuit provided in Embodiment Six of this application; Figure 10 This is a flowchart illustrating a level conversion driving method provided in Embodiment Six of this application; Figure 11 This is a flowchart illustrating another level conversion driving method provided in Embodiment 7 of this application. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] The terms "comprising" and "having" in the embodiments of this application are used to indicate an open-ended inclusion, meaning that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms "first" and "second," etc., are used only as labels and are not intended to limit the number of objects. Furthermore, the different elements and areas in the drawings are only schematic, therefore this application is not limited to the dimensions or distances shown in the drawings.

[0023] Level shifting is used when two devices need to communicate but cannot be directly connected due to different voltage specifications. In this case, level shifting is required.

[0024] HSR mode stands for Hardware Super Resolution, a hardware super-resolution technology. This technology achieves differential display through timing adjustments. In each frame, only the odd-numbered or even-numbered rows of pixels are rendered, while the remaining row is displayed by fusing information from adjacent rows. While this method allows for higher refresh rates, HSR technology represents a significant improvement over DLG technology. It doesn't simply display one line of data; instead, it combines information from two adjacent rows, thus enhancing image clarity and smoothness to a certain extent.

[0025] like Figure 1aFigure 1 shows a timing diagram of a level shifting drive display circuit provided in the prior art. The level shifter logic, with one input and one output, is only responsible for boosting the input waveform; other logic is determined by the TCON IC or SOC. Theoretically, the output waveform of this level shifter IC can be arbitrarily shifted, allowing for flexible output from the TCON IC or SOC, and ultimately, flexible control over the timing of the signal to the display screen. Figure 1b This is a schematic diagram of a level conversion driving display circuit provided in the prior art. Figure 1b yes Figure 1a A schematic diagram showing the hardware connections between the TCON IC or SOC corresponding to the timing sequence, the level shifter IC, and the display panel. Figure 1b The connection relationship can realize 6 inputs and 6 outputs level conversion control.

[0026] Currently, level shifter ICs commonly use 2-input multi-output or 4-input multi-output, such as... Figure 1c This is a timing diagram for another level-shifting drive display circuit provided in the prior art. Figure 1d This is a schematic diagram of another level conversion driving display circuit provided in the prior art. Figure 1d for Figure 1c The corresponding timing hardware connection diagram. Figure 1cThis is the simplest 2-input, 6-output level shifter IC input / output logic. When the rising edge of CPV1 arrives, the output CLK is high; when the rising edge of CPV2 arrives, the output CLK is falling. Other logic is also possible, such as outputting the rising edge of CLK when the falling edge of CPV1 arrives, and the falling edge of CLK when the falling edge of CPV2 arrives. Alternatively, the output timing of CLK can be controlled by the rising and falling edges of a single CPV. However, regardless of the method, the 2-input, 6-output control logic follows certain patterns. For example, the output CLK is staggered by a specific number of rows. The SOC or TCON IC can control the period of CPV1 / CPV2 or the timing of the first waveform output to achieve the required timing for the screen. Simultaneously, the level shifter IC also pulls a square wave with a low level of 0V and a high level of 3.3V into a square wave with a low level of VGL and a high level of VGH. Only when the high level is VGH and the low level is VGL can the TFT switches on the display panel be turned on and off. The 2-input, 3-output level shifter IC also reserves a 2-line mode, which can be enabled by setting the corresponding 2-line mode through registers. This 2-line mode is the simplest, i.e., CLK1=CLK2, CLK3=CLK4, CLK5=CLK6, etc., but in practical applications, it may not always meet the requirements.

[0027] With the development of TV panels, especially the rapid development of gaming TVs, HSR panels have emerged in large numbers to meet people's entertainment needs such as watching movies and playing games. Meanwhile, to reduce costs, dual-gate technology has been gradually adopted in HSR panels. This technology can reduce COF by half, achieving significant cost reduction. While saving COF, dual-gate panels double the number of gates, thus halving the charging time, but this also presents a significant challenge to image quality. To improve image quality, improvements have been made to the GOA timing, resulting in GOA timing for HSR panels based on the dual-gate architecture. Multi-line mode has become an important strategy for improving the display effect of dual-gate architecture HSR panels, but in terms of implementation, a 2-input 12-output levelshifter IC cannot display the timing logic of 2-line mode.

[0028] To address the aforementioned issues, this solution proposes a level conversion driver circuit. By analyzing the different timing requirements of the display panel, a general-purpose one-input-one-output level converter or a multi-input-multi-output level converter is selected as the level conversion module for the display driver, thereby achieving specific timing requirements and using general-purpose timing control logic to meet flexible and diverse timing needs.

[0029] To facilitate understanding of the embodiments of this application, the following will provide further explanation and description with reference to the accompanying drawings and specific embodiments. These embodiments do not constitute a limitation on the embodiments of this application.

[0030] Example 1 Figure 2 This is a schematic diagram of a level conversion driving circuit provided in Embodiment 1 of this application. Figure 2 The provided diagram shows the structure of the level shifting drive circuit, which includes: The motherboard 10, the display panel 20, and the target level conversion module 30 contain at least one level converter 301.

[0031] The motherboard 10 is connected to one end of the level converter 301 in the target level conversion module 30.

[0032] The other end of the level converter 301 in the target level conversion module 30 is connected to the display panel 20.

[0033] The motherboard 10 is used to input control signals and timing signals to the target level conversion module 30.

[0034] The target level conversion module 30 is used to receive control signals and timing signals input from the motherboard 10 and then generate drive signals.

[0035] The display panel 20 is used to drive the LCD screen display after receiving the drive signal input from the target level conversion module 30.

[0036] according to Figure 2 The provided diagram illustrates the selection of different types of level converters based on the timing requirements of the display panel. For complex timing requirements, such as a display panel in 2-line mode HSR mode, a level converter with 12 clock signals CK is required. A general-purpose level converter is used to meet the panel requirements for complex timing, while simplifying the function of the level converter by having it only handle level boosting. Multiple general-purpose level converters are used to handle situations where the number of clock signals CK exceeds the maximum output of the current level converter. This allows the highly versatile level converter to drive the display panel after level boosting.

[0037] The level conversion driving circuit provided in this application embodiment comprises a motherboard, a display panel, and a target level conversion module. The target level conversion module includes at least one level converter. One end of the level converter in the target level conversion module is connected to the motherboard; the other end of the level converter in the target level conversion module is connected to the display panel. The motherboard is used to input control signals and timing signals to the target level conversion module. The target level conversion module generates a driving signal after receiving the control signals and timing signals from the motherboard. The display panel receives the driving signal from the target level conversion module and drives the liquid crystal display. Different types of level converters are selected according to the display panel's odd / even timing requirements or HSR mode, achieving flexible driving display for specific timing requirements. This solution can support various timing needs of the display screen, achieving flexible display and improving the display screen's drive refresh rate.

[0038] Example 2 Figure 3 This is a schematic diagram of a level conversion drive circuit provided in Embodiment 2 of this application. Figure 3 This is based on the previous embodiment. Figure 3 The provided diagram shows the structure of the level shifting drive circuit, which includes: The motherboard 10, the display panel 20, and the target level conversion module 30 contain at least one level converter 301.

[0039] according to Figure 3 The provided diagram shows that the target level conversion module 30 in the level conversion drive circuit includes at least one one-in-one-out level converter 3011.

[0040] The one-in-one-out level converter 3011 has n signal input terminals and n signal output terminals, and one input terminal of the one-in-one-out level converter 3011 corresponds to one output terminal, where n is a positive integer greater than or equal to 1.

[0041] Each input terminal of the one-in-one-out level converter 3011 is connected to one of the n output terminals of the motherboard 10, and each output terminal of the one-in-one-out level converter 3011 is connected to one of the n input terminals of the display panel 20.

[0042] The input-output level converter 3011 is used to receive the first control signal and the first timing signal input from the motherboard 10 and then generate the first drive signal.

[0043] The input-output level converter 3011 is also used to input the first drive signal to the display panel 20.

[0044] according to Figure 3The provided diagram illustrates the selection of different types of level converters based on the timing requirements of the display panel. For complex timing requirements, such as a display panel in even-numbered 2-line mode HSR mode, a level converter with 12 clock signals CK is required. A one-in-one-out level converter 3011 is used to meet the panel requirements for complex timing, while simplifying the function of the level converter. The one-in-one-out level converter 3011 is only responsible for level boosting. Furthermore, multiple one-in-one-out level converters 3011 are used to handle situations where the number of clock signals CK exceeds the maximum output number of the current level converter. This utilizes a versatile level converter to achieve the goal of driving the display panel after level boosting, improving the flexibility of level converter adjustment.

[0045] according to Figure 3 The provided diagram shows that the 3011 level converter in the level conversion drive circuit is a 6-input, 6-output level converter.

[0046] The six input signal terminals of the 6-input 6-output level converter are respectively connected to the six output terminals of the main board 10, and the six output terminals of the 6-input 6-output level converter are respectively connected to the six input terminals of the display panel 20.

[0047] Alternatively, the 3011 one-in-one-out level converter can be an eight-in-eight-out level converter.

[0048] The eight input signal terminals of the 8-in-8-out level converter are connected to the eight output terminals of the motherboard 10, and the eight output terminals of the 8-in-8-out level converter are connected to the eight input terminals of the display panel 20.

[0049] Alternatively, the 3011 one-in-one-out level converter can be a 10-in-10-out level converter.

[0050] The 10 input signal terminals of the 10-in-10-out level converter are respectively connected to the 10 output terminals of the motherboard 10, and the 10 output terminals of the 10-in-10-out level converter are respectively connected to the 10 input terminals of the display panel 20.

[0051] Alternatively, the 3011 one-in-one-out level converter can be a 12-in-12-out level converter.

[0052] The 12 input signal terminals of the 12-input 12-output level converter are respectively connected to the 12 output terminals of the motherboard 10, and the 12 output terminals of the 12-input 12-output level converter are respectively connected to the 12 input terminals of the display panel 20.

[0053] Alternatively, the 3011 one-in-one-out level converter can be a 16-in-16-out level converter.

[0054] The 16 input signal terminals of the 16-in-16-out level converter are respectively connected to the 16 output terminals of the motherboard 10, and the 16 output terminals of the 16-in-16-out level converter are respectively connected to the 16 input terminals of the display panel 20.

[0055] according to Figure 3 The provided diagram illustrates how, when the display panel has specific timing requirements, multiple one-in-one-out level shifters 3011 can be combined to meet the clock signal CK requirements. Alternatively, any one or more of the following level shifter ICs—6in6out, 8in8out, 10in10out, 12in12out, and 16in16out—can be used to construct a level conversion module. By arbitrarily combining multiple one-in-one-out level shifters 3011, the specific timing requirements of the display panel can be met, achieving the versatility and flexibility of the level shifter.

[0056] Furthermore, Figure 4 This is a schematic diagram of another level conversion driving circuit provided in Embodiment 2 of this application. Figure 4 This is based on the first embodiment. Figure 4 The provided diagram shows the structure of the level shifting drive circuit, which includes: The motherboard 10, the display panel 20, and the target level conversion module 30 contain at least one level converter 301.

[0057] according to Figure 4 The provided diagram shows that the target level conversion module 30 in the level conversion drive circuit includes at least one multiple-input multiple-output level converter 3012, each multiple-input multiple-output level converter 3012 having a different number of input ports and a different number of output ports.

[0058] The multiple input terminals of each multiple input multiple output level converter 3012 are respectively connected to the multiple output terminals of the motherboard 10, and the multiple output terminals of each multiple input multiple output level converter 3012 are respectively connected to the multiple input terminals of the display panel 20.

[0059] The multiple-input multiple-output level converter 3012 is used to receive the second timing signal and the second control signal input from the motherboard 10 and generate the second drive signal.

[0060] The multiple-input multiple-output level converter 3012 is also used to input a second drive signal to the display panel 20.

[0061] according to Figure 4The provided diagram illustrates the selection of different types of level converters based on the timing requirements of the display panel. For complex timing requirements, such as a display panel in even-numbered 2-line mode HSR mode, a level converter with 12 clock signals CK is required. In this case, a multi-input multi-output level converter 3012 is selected to meet the panel requirements for complex timing. Simultaneously, the function of the level converter is simplified; the multi-input multi-output level converter 3012 only handles the level boosting function. Furthermore, multiple multi-input multi-output level converters 3012 are used to handle situations where the number of clock signals CK exceeds the maximum output number of the current level converter. This utilizes a versatile level converter to achieve the goal of driving the display panel after level boosting, improving the flexibility of level converter adjustment.

[0062] according to Figure 4 The provided diagram shows that the multi-input multi-output level converter 3012 in the level conversion drive circuit is a 2-input 12-output level converter.

[0063] The two input terminals of the 2-input 12-output level converter are connected to the two output terminals of the motherboard 10, and the twelve output terminals of the 2-input 12-output level converter are connected to the twelve input terminals of the display panel 20, respectively.

[0064] Alternatively, the 3012 is a 2-input, 10-output level converter.

[0065] The two input terminals of the 2-input 10-output level converter are connected to the two output terminals of the motherboard 10, and the ten output terminals of the 2-input 10-output level converter are connected to the ten input terminals of the display panel 20.

[0066] Alternatively, the 3012 is a 2-input, 8-output level converter.

[0067] The two input terminals of the 2-input 8-output level converter are connected to the two output terminals of the motherboard 10, and the eight output terminals of the 2-input 8-output level converter are connected to the eight input terminals of the display panel 20, respectively.

[0068] Alternatively, the 3012 is a 2-input, 6-output level converter.

[0069] The two input terminals of the 2-input 6-output level converter are connected to the two output terminals of the motherboard 10, and the six output terminals of the 2-input 6-output level converter are connected to the six input terminals of the display panel 20, respectively.

[0070] according to Figure 4The provided diagram illustrates the use of multiple multiple-input multiple-output (MIMO) level shifters to address the specific timing requirements of display panels. Utilizing the parity of these shifters, the needs of multiple clock signals (CK) or super-resolution HSR mode are met. By selecting the same or different types of MIMO from 2-in-12-out, 2-in-10-out, 2-in-8-out, and 2-in-6-out level shifter ICs, logic control for 2-line / 3-line HSR modes under multiple clock signals (CK) is achieved. This demonstrates the flexibility and versatility of general-purpose level shifters, providing a stable signal for subsequent display panel driving.

[0071] Example 3 To further demonstrate the versatility of using a one-input-one-output level converter, Figure 5a This is a timing diagram of a level conversion driving circuit provided in Embodiment 3 of this application. Figure 5a The provided diagram uses multiple input-output level converters to achieve the driving display requirements of special timing.

[0072] like Figure 5a The display panel shown is in 2-line mode with even-numbered CK timing requirements. During the GOA driver scan, two rows are periodically enabled (i.e., CK1=CK2, CK3=CK4, CK5=CK6, CK7=CK8, CK9=CK10, CK11=CK12, etc.) to achieve even-numbered outputs. Switching from the normal one-line mode to 2-line mode is achieved by adjusting the internal registers of the level shifter IC. Level shifter ICs with 2 inputs and 12 outputs and 2-line mode are extremely rare; therefore, using two level shifter ICs to meet the driver requirements is considered, for example... Figure 5b This is a schematic diagram of a level conversion driving circuit provided in Embodiment 3 of this application. Figure 5c This is a schematic diagram of another level conversion driving circuit provided in Embodiment 3 of this application. Figure 5bWhen using two level shifter ICs, one input and one output, for driving, the clock signal CK output is at least 6CK output, but can also be 8CK output or 10CK output, etc. If it is 8CK or 10CK output channels, then depending on the display requirements, each level shifter IC can NC-disable 2 or 4 CK output channels and NC-disable 2 or 4 CK inputs.

[0073] Figure 5c When using two 2-input, 3-output level shifter ICs for driving, the minimum CK output is 6CK outputs, but it can also be 8CK outputs or 10CK outputs, etc. If there are 8CK or 10CK output channels, then depending on the display requirements, each level shifter IC can disable 2 or 4 CK output channels. Alternatively, a single 2-input, 12-output or 12-input, 12-output level shifter IC can be used for driving.

[0074] Example 4 Furthermore, to illustrate the logic analysis process of multiple multiple-input multiple-output level converters in odd-numbered mode, Figure 6a This is a timing diagram of a level conversion driving circuit provided in Embodiment 4 of this application. Figure 6a This refers to the timing requirements of a 12CK 2-line mode display panel corresponding to odd-numbered clock signals. Specifically, the clock signals CK must satisfy CK1=CK3, CK2=CK4, CK5=CK7, CK6=CK8, CK9=CK11, CK10=CK12, etc. In this mode, if two 2-input multi-output level shifter ICs are used, they need to enable the odd-numbered 2-line mode when switching to HSR mode. Furthermore, special hardware connections are required. For example, one 2-input multi-output level shifter IC outputs odd-numbered CK signals (i.e., the CK output channels CK1 / CK3 / CK5 / CK7 / CK9 / CK11 of the level shifter IC are connected to the corresponding odd-numbered clock signal CK input of the display panel), while the output channel of the other 2-input multi-output level shifter IC is connected to the even-numbered clock signal CK. That is, the CK output channels corresponding to CK2 / CK4 / CK6 / CK8 / CK10 / CK12 of the 2-input multi-output level shifter IC are connected to the corresponding even-numbered clock signal CK input of the display panel. The specific hardware connection is as follows: Figure 6b and Figure 6c As shown, especially Figure 6c As shown. Figure 6b This is a schematic diagram of a level conversion drive circuit provided in Embodiment 4 of this application. Figure 6c This is a schematic diagram of another level conversion drive circuit provided in Embodiment 4 of this application. Additionally, a motherboard SOC or TCON IC is required to perform corresponding level converter logic control to adjust to the specific timing required by the display screen.

[0075] Example 5 Figure 7 This is a schematic diagram of a level conversion drive circuit provided in Embodiment 5 of this application. Figure 7 This is based on the previous embodiment. Figure 7 The provided diagram shows the structure of the level shifting drive circuit, which includes: The motherboard 10, the display panel 20, and the target level conversion module 30 contain at least one level converter 301.

[0076] according to Figure 7 The provided diagram shows that the target level conversion module 30 in the level conversion drive circuit includes at least one single-input single-output level converter 3011 and at least one multiple-input multiple-output level converter 3012, wherein the single-input single-output level converter 3011 and the multiple-input multiple-output level converter 3012 are of different types.

[0077] The multiple input terminals of the one-in-one-out level converter 3011 are connected to the multiple output terminals of the motherboard 10, and the multiple output terminals of the one-in-one-out level converter 3011 are connected to the multiple input terminals of the display panel 20.

[0078] Each input terminal of a multiple input-multiple output level converter 3012 is connected to multiple output terminals of the motherboard 10, and each output terminal of a multiple input-multiple output level converter 3012 is connected to multiple input terminals of the display panel 20. There is no cross connection between the input terminals and output terminals of any two level converters 301.

[0079] according to Figure 7The provided diagram illustrates how, to address the specific timing requirements of a display panel, multiple one-in-one-out and multiple multiple-in-multiple-out level shifters are employed. By utilizing the parity timing settings of these level shifters, the requirements for multiple clock signals (CK) or HSR mode can be met. By selecting the same or different types of multiple-in-multiple-out level shifters from 2-in-12-out, 2-in-10-out, 2-in-8-out, and 2-in-6-out ICs, as well as one or more one-in-one-out level shifters from 6-in-6-out and 8-in-8-out ICs, logic control for the 2-line / 3-line HSR mode under multiple clock signals (CK) is achieved. This demonstrates the flexibility and versatility of using general-purpose level shifters, providing a stable signal for the subsequent display panel drive.

[0080] In one possible example scenario, Figure 8 This is a timing diagram of another level conversion driving circuit provided in Embodiment 5 of this application. According to... Figure 8 This demonstrates the timing diagram for the 12CK input channel and corresponding 12CK output channel under the 12CK timing requirements in 3-line mode. The timing requirements of 3-line mode can be achieved by using two 6-input / 6-output level converters or multiple MIMO level converters, further improving the flexibility of level converter application.

[0081] Example 6 Figure 9a This is a timing diagram of a level conversion drive circuit provided in Embodiment Six of this application. Figure 9a Analysis of the timing requirements for the provided display panel reveals that the motherboard SOC or TCON IC requires 15 clock signal inputs. Furthermore, the display panel demands an odd number of CK timings, necessitating the use of a one-in-one-out level shifter. To accommodate the 12 timing input signals, a 12-in-12-out level shifter IC or a 16-in-16-out level shifter IC can be selected. Based on the above analysis, we can conclude... Figure 9b and Figure 9c To meet the needs. Among them, Figure 9b This is a schematic diagram of a level conversion drive circuit provided in Embodiment Six of this application. Figure 9c This is a schematic diagram of another level conversion driving circuit provided in Embodiment Six of this application. According to... Figure 9bThe provided diagram utilizes two 8-in-8-out Levelshifter ICs. By NC-disconnecting one pin from each of the input and output terminals of one of the Levelshifter ICs, a timing requirement of 15CK odd-numbers can be achieved. Alternatively, based on... Figure 9c The provided diagram shows that the problem of 15ck odd-number timing requirements can also be solved using a single 16in16out Level shifter IC. By using multiple one-in-one-out Level shifter ICs, a universal Level shifter IC can be used to raise the level. The internal timing logic control is implemented through the motherboard SOC or TCON IC, which improves the flexibility of the display panel driver.

[0082] Furthermore, based on using a one-in-one-out level converter to achieve timing control under odd-number conditions, and further to reduce the number of pin outputs on the motherboard SOC or TCON IC, other options can be selected such as... Figure 9d and Figure 9e The provided illustration. Among them, Figure 9d This is a schematic diagram of another level conversion driving circuit provided in Embodiment Six of this application. Figure 9e This is a schematic diagram of another level shifting drive circuit provided in Embodiment Six of this application. When addressing the driving timing requirements of odd-numbered CK display panels, a one-in-one-out (multiple-in-multiple-out) level shifter IC, or a one-in-one-out (multiple-in-multiple-out) level shifter IC combined with a two-in-multiple-out or four-in-multiple-out level shifter IC, needs to be considered to meet the driving requirements. From the perspective of cost saving and integration space optimization, Figure 9d By selecting one 4-in-4-out Level Shifter IC and one 2-in-12-out Level Shifter IC, and by NC-removing one pin from both the input and output of the 4-in-4-out Level Shifter IC, three odd-numbered control pins and three clock signal outputs are achieved. The 2-in-12-out Level Shifter IC further reduces the number of input pins, significantly saving space and production costs. It also improves the flexibility of using the level shifter in driving display panels. Similarly, refer to... Figure 9eThe provided diagram shows the use of any two of the following: one 4-in-4-out Level shifter IC and two 2-in-6-out Level shifter ICs, or two 2-in-8-out Level shifter ICs, or two 2-in-10-out Level shifter ICs. The 4-in-4-out Level shifter IC is used to achieve an odd number of three control signal inputs and an odd number of three clock signal outputs. The two 2-in-multiple-out Level shifter ICs are used to achieve a smaller number of input signals, with each Level shifter IC outputting six clock signals CK, thereby meeting the special timing requirements and driving the display panel.

[0083] Example 7 Figure 10 This is a flowchart illustrating a level conversion driving method provided in Embodiment Six of this application. It is applied to a level conversion driving circuit. According to... Figure 10 The provided diagram illustrates the specific steps of the level conversion driving method, including: S1001. Obtain the target timing requirements of the display panel and determine the target mode of the display panel corresponding to the target timing requirements.

[0084] This application analyzes the different timing requirements of display panels and, while meeting these requirements, selects a general-purpose level converter to achieve level conversion. Depending on the needs, a single-input-single-output or multi-input-multi-output level converter can be used, with timing logic control performed by a TCON IC or motherboard SOC. The level converter only performs voltage boost drive control, improving the flexibility of the level converter's application.

[0085] The target mode mentioned here represents the odd / even or multi-linearity of the display panel. It can be understood as a special type of requirement determined by factors such as the number of control signals in the target timing and the mapping relationship between clock signals and control signals. The driving mode of the panel is determined according to different analysis categories, such as 2-line mode, super-resolution HSR mode, odd clock signal mode, even clock signal mode, etc.

[0086] Furthermore, the timing requirements of the display panel are first obtained, and the characteristics of the timing requirements are analyzed to determine whether the timing requirements correspond to a multi-clock signal mode, an odd-even output signal mode, or a multi-line mode, etc. Based on the different categories of timing obtained from the analysis, the rated driving mode of the display panel is determined. For example, when the target category is 2-line mode, the driving mode of the display panel is determined to be the super-resolution HSR mode, which provides a reference for the next step of selecting the model of the level converter.

[0087] S1002. Determine the target model of the level conversion module according to the target mode.

[0088] The target model mentioned here can be understood as representing the application product type of the level converter in the level conversion module, and the different categories of level converters corresponding to different numbers of input and output terminals of the selected level converter.

[0089] Furthermore, different models of level converters are selected depending on the target mode. A one-input-one-output level converter is used in odd-numbered modes, while a multi-input-multi-output level converter is used in 2-line mode or even-numbered modes.

[0090] S1003. Construct a level conversion drive circuit based on the target model to drive the display panel to display the image.

[0091] Furthermore, after determining the model of the level converter, one or more level converters are used to connect the motherboard and the display panel to build a level conversion drive circuit. Through timing control, the clock signal of the control signal output by the motherboard SOC or TCON IC is used to boost the level by using the level converter. The square wave with a low level of 0V and a high level of 3.3V is boosted to a square wave with a low level of VGL and a high level of VGH. Only when the high level is VGH and the low level is VGL can the TFT switch of the display panel be turned on and off, so that the display panel drives the display screen.

[0092] This application provides a level conversion driving method. By analyzing the timing requirements of the display panel, the selected model and number of level converters are obtained, and then the level conversion function of the level converters is used to flexibly drive the display screen.

[0093] Example 8 Figure 11 This is a flowchart illustrating another level conversion driving method provided in Embodiment 7 of this application. Figure 11 This is based on the previous embodiment. Figure 11 The provided diagram illustrates the specific steps of the level conversion driving method, including: S1101. Obtain the target timing requirements for the display panel.

[0094] S1102. When the target timing requirements include driving requirements for an odd number of timings, determine the target category of the display panel as odd mode.

[0095] S1103. When the target timing requirements include an even number of timing drive requirements, determine the target category of the display panel as an even-number mode.

[0096] S1104. When the target timing requirements include the driving requirements of the threshold output timing signal, the target category of the display panel is determined to be super-resolution mode.

[0097] S1105. When the target timing requirements include the driving requirements of an odd number of timing signals and threshold output timing signals, the target mode of the display panel is determined to be the odd super-resolution mode.

[0098] S1106. When the target timing requirements include an even number of timing signals and the driving requirements of threshold output timing signals, the target mode of the display panel is determined to be an even number of super-resolution modes.

[0099] The threshold output timing signal mentioned here represents the number of output signals as a preset maximum number of outputs. It can be set to 12 output timing signals, 14 output timing signals, 16 output timing signals, or more output timing signals. The threshold output timing signal represents the maximum number of output signals of the current level converter.

[0100] Furthermore, after obtaining the target timing requirements of the display panel, and analyzing the target timing requirements, it is determined whether the timing requirements are an odd number of timing signals, an even number of timing signals, or a driving requirement that exceeds the limit on the number of output clock signals. Based on the limiting factors, the corresponding mode of the display panel is determined, providing a reference for selecting a suitable level converter in the next step.

[0101] S1107. When the target mode is an odd number mode, the target model of the level conversion module is determined to be a single input-output level converter, or a single input-output level converter and at least one multi-input multi-output level converter.

[0102] S1108. When the target mode is an even-numbered mode, the target model of the level conversion module is determined to be one single-input single-output level converter and / or at least one multi-input multi-output level converter.

[0103] S1109. When the target mode is super-resolution mode, the target model of the level conversion module is determined to be at least one multi-input multi-output level converter, or one single-input single-output level converter and at least one multi-input multi-output level converter.

[0104] S1110. When the target mode is odd super-resolution mode, the target model of the level conversion module is determined to be one single-input single-output level converter and at least one multi-input multi-output level converter.

[0105] S1111 When the target mode is an even super-resolution mode, the target model of the level conversion module is determined to be at least one multi-input multi-output level converter, or, one single-input single-output level converter and at least one multi-input multi-output level converter.

[0106] Furthermore, after selecting the display panel mode, the corresponding level converter model is selected. When the target mode is odd mode or odd super-resolution HSR mode, to achieve an odd number of clock signals, one single-input single-output level converter and at least one multi-input multi-output level converter can be selected. Given the requirement of achieving odd mode, to address cost considerations, one or more single-input single-output level converters can also achieve the requirement of an odd number of timing outputs. When the target mode is even mode or even super-resolution HSR mode, to achieve display driving in even environments, while saving production costs, the target model of the level conversion module should be at least one multi-input multi-output level converter. Alternatively, for versatility, a combination of a single-input single-output level converter and at least one multi-input multi-output level converter can also be used to achieve the special timing requirements of the display panel.

[0107] S1112. When the target model is a single-input-single-output level converter and at least one multi-input-multi-output level converter, the single-input-single-output level converter is configured with an odd number of input terminals and an odd number of output terminals.

[0108] S1113. Connect the output of each multiple-input multiple-output level converter to the input of the display panel according to a preset rule to construct a level conversion drive circuit.

[0109] S1114. When the target model is at least one multi-input multi-output level converter, the output terminal of each multi-input multi-output level converter is connected to the input terminal of the display panel according to a preset rule to construct a level conversion drive circuit.

[0110] S1115. When the target model is a single input-output level converter, the output terminal of each input-output level converter is connected to the input terminal of the display panel according to a preset rule to construct a level conversion drive circuit.

[0111] Furthermore, by using the selected level converter pairing method to connect the motherboard and the display panel, the corresponding odd clock signal output, even clock signal output, or multiple clock signal output can be achieved to enable the display panel to drive the screen display.

[0112] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above description is only a specific embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A level conversion driving circuit, characterized in that, include: The motherboard, the display panel, and the target level conversion module, wherein the target level conversion module contains at least one level converter; The motherboard is connected to one end of the level converter in the target level conversion module; The other end of the level converter in the target level conversion module is connected to the display panel; The motherboard is used to input control signals and timing signals to the target level conversion module; The target level conversion module is used to receive the control signal and the timing signal input from the motherboard and then generate a drive signal; The display panel is used to drive the liquid crystal display after receiving the drive signal input by the target level conversion module; The target level conversion module includes at least one single-input single-output level converter and at least one multi-input multi-output level converter, wherein the single-input single-output level converter and the multi-input multi-output level converter are of different types; The multiple input terminals of the one-in-one-out level converter are connected to the multiple output terminals of the motherboard, and the multiple output terminals of the one-in-one-out level converter are connected to the multiple input terminals of the display panel. Each of the multiple input terminals of the multiple input-multiple output level converter is connected to multiple output terminals of the motherboard, and each of the multiple output terminals of the multiple input-multiple output level converter is connected to multiple input terminals of the display panel. There is no cross connection between the input terminals and output terminals of any two level converters.

2. The circuit according to claim 1, characterized in that, The target level conversion module includes at least one one-input-one-output level converter; The one-in-one-out level converter includes n signal input terminals and n signal output terminals, and one input terminal of the one-in-one-out level converter corresponds to one output terminal, where n is a positive integer greater than or equal to 1; Each input terminal of the one-in-one-out level converter is connected to one of the n output terminals of the motherboard, and each output terminal of the one-in-one-out level converter is connected to one of the n input terminals of the display panel. The input-output level converter is used to receive the first control signal and the first timing signal input from the motherboard and then generate the first drive signal. The input-output level converter is also used to input a first drive signal to the display panel.

3. The circuit according to claim 1, characterized in that, The target level conversion module includes at least one multiple-input multiple-output level converter, wherein the number of input ports of each multiple-input multiple-output level converter is not exactly the same, and the number of output ports of each multiple-input multiple-output level converter is not exactly the same; The multiple input terminals of each of the multiple input-multiple output level converters are respectively connected to the multiple output terminals of the motherboard, and the multiple output terminals of each of the multiple input-multiple output level converters are respectively connected to the multiple input terminals of the display panel; The multiple-input multiple-output level converter is used to receive the second timing signal and the second control signal input from the motherboard and then generate the second drive signal. The multiple-input multiple-output level converter is also used to input the second drive signal to the display panel.

4. The circuit according to claim 2, characterized in that, The one-input-one-output level converter is a six-input-six-output level converter; The six input signal terminals of the 6-input 6-output level converter are respectively connected to the six output terminals of the motherboard, and the six output terminals of the 6-input 6-output level converter are respectively connected to the six input terminals of the display panel. Alternatively, the one-in-one-out level converter may be an eight-in-eight-out level converter; The eight input signal terminals of the 8-input 8-output level converter are respectively connected to the eight output terminals of the motherboard, and the eight output terminals of the 8-input 8-output level converter are respectively connected to the eight input terminals of the display panel. Alternatively, the one-in-one-out level converter can be a 10-in-10-out level converter; The 10 input signal terminals of the 10-input 10-output level converter are respectively connected to the 10 output terminals of the motherboard, and the 10 output terminals of the 10-input 10-output level converter are respectively connected to the 10 input terminals of the display panel. Alternatively, the one-in-one-out level converter can be a 12-in-12-out level converter; The 12 input signal terminals of the 12-input 12-output level converter are respectively connected to the 12 output terminals of the motherboard, and the 12 output terminals of the 12-input 12-output level converter are respectively connected to the 12 input terminals of the display panel. Alternatively, the one-in-one-out level converter can be a 16-in-16-out level converter; The 16 input signal terminals of the 16-input 16-output level converter are respectively connected to the 16 output terminals of the motherboard, and the 16 output terminals of the 16-input 16-output level converter are respectively connected to the 16 input terminals of the display panel.

5. The circuit according to claim 3, characterized in that, The multi-input multi-output level converter is a 2-input 12-output level converter; The two input terminals of the 2-input 12-output level converter are respectively connected to the two output terminals of the motherboard, and the 12 output terminals of the 2-input 12-output level converter are respectively connected to the 12 input terminals of the display panel. Alternatively, the multiple-input multiple-output level converter is a 2-input 10-output level converter; The two input terminals of the 2-input 10-output level converter are respectively connected to the two output terminals of the motherboard, and the ten output terminals of the 2-input 10-output level converter are respectively connected to the ten input terminals of the display panel. Alternatively, the multiple-input multiple-output level converter is a 2-input 8-output level converter; The two input terminals of the 2-input 8-output level converter are respectively connected to the two output terminals of the motherboard, and the eight output terminals of the 2-input 8-output level converter are respectively connected to the eight input terminals of the display panel. Alternatively, the multiple-input multiple-output level converter is a 2-input 6-output level converter; The two input terminals of the 2-input 6-output level converter are respectively connected to the two output terminals of the motherboard, and the six output terminals of the 2-input 6-output level converter are respectively connected to the six input terminals of the display panel.

6. A level conversion driving method, applied to the level conversion driving circuit as described in any one of claims 1-5, characterized in that, include: Obtain the target timing requirements of the display panel and determine the target mode of the display panel corresponding to the target timing requirements, wherein the target mode characterizes the display panel's display parity or multilinearity; The target model corresponding to the level conversion module is determined according to the target mode, and the target model represents the application product type of the level converter in the level conversion module; A level conversion driving circuit is constructed based on the target model to drive the display panel to display the image.

7. The method according to claim 6, characterized in that, Determining the target mode of the display panel corresponding to the target timing requirement includes: When the target timing requirements include driving requirements for an odd number of timings, the target category of the display panel is determined to be an odd-number mode; or, When the target timing requirements include an even number of timing drive requirements, the target category of the display panel is determined to be an even-number mode; or, When the target timing requirement includes the driving requirement of the threshold output timing signal, the target category of the display panel is determined to be super-resolution mode, and the threshold output timing signal represents the number of output signals as a preset maximum number of outputs; or, When the target timing requirements include the driving requirements of an odd number of timing signals and threshold output timing signals, the target mode of the display panel is determined to be an odd super-resolution mode. or, When the target timing requirements include an even number of timing signals and a threshold output timing signal driving requirement, the target mode of the display panel is determined to be an even number super-resolution mode.

8. The method according to claim 7, characterized in that, The step of determining the target model corresponding to the level conversion module based on the target mode includes: When the target mode is an odd number mode, the target model of the level conversion module is determined to be a single-input single-output level converter, or a single-input single-output level converter and at least one multi-input multi-output level converter. When the target mode is an even number mode, the target model of the level conversion module is determined to be one single-input single-output level converter and / or at least one multi-input multi-output level converter; When the target mode is super-resolution mode, the target model of the level conversion module is determined to be at least one multiple-input multiple-output level converter, or, one single-input single-output level converter and at least one multiple-input multiple-output level converter. When the target mode is an odd super-resolution mode, the target model of the level conversion module is determined to be one single-input single-output level converter and at least one multi-input multi-output level converter; When the target mode is an even-number super-resolution mode, the target model of the level conversion module is determined to be at least one multi-input multi-output level converter, or one single-input single-output level converter and at least one multi-input multi-output level converter.

9. The method according to claim 8, characterized in that, The level conversion driver circuit constructed based on the target model includes: When the target model is a single input-output level converter and at least one multiple input-multiple output level converter, the single input-output level converter is configured with an odd number of input terminals and an odd number of output terminals; The output terminal of each of the multiple input multiple output level converters is connected to the input terminal of the display panel according to a preset rule to construct a level conversion drive circuit; or, When the target model is at least one multiple-input multiple-output level converter, the output terminal of each multiple-input multiple-output level converter is connected to the input terminal of the display panel according to a preset rule to construct a level conversion drive circuit; or, When the target model is a single input-output level converter, the output terminal of each input-output level converter is connected to the input terminal of the display panel according to a preset rule to construct a level conversion drive circuit.

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