Semiconductor structure and its fabrication method, laser cutting method, semiconductor unit

Abstract

This disclosure provides a semiconductor structure and its fabrication method, a laser cutting method, and a semiconductor unit. The semiconductor structure includes a substrate with multiple dicing channels that divide the substrate into multiple chip regions. At least some of the dicing channels have at least one air gap. By providing air gaps within the substrate corresponding to the dicing channel positions, this disclosure effectively reduces the mechanical strength of the dicing channels, facilitates the separation of adjacent chip regions during wafer expansion, prevents damage to the chip regions from external forces during wafer expansion, reduces the dicing channel size, allows for the fabrication of more chip regions on the substrate, and improves the effective utilization rate of the substrate.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method, a laser cutting method, and a semiconductor unit. Background Technology

[0002] In semiconductor manufacturing, after integrated circuits are formed on a wafer, the wafer needs to be diced into several individual dies. These dies are then individually packaged or stacked to form individual chips. With the continuous improvement of device integration and dicing technology, laser stealth dicing (SD) has gradually become the mainstream technology.

[0003] However, laser stealth cutting technology still has unavoidable precision limitations, preventing further reduction in the size of the cutting kerf. Furthermore, during the enlargement process in laser stealth cutting, the damaged area is relatively large, easily leading to damage to the bare wafer. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a semiconductor structure and its fabrication method, a laser cutting method, and a semiconductor unit.

[0006] A first aspect of this disclosure provides a semiconductor structure, the semiconductor structure including a substrate, the substrate having a plurality of dicing channels, the plurality of dicing channels dividing the substrate into a plurality of chip regions;

[0007] At least a portion of the cutting channel is provided with at least one air gap.

[0008] In some embodiments, the cutting channel is provided with a structural layer, and the air gap is disposed in the structural layer.

[0009] In some embodiments, the structural layer includes multiple conductive layers spaced apart, and at least a portion of the conductive layers forms the air gap.

[0010] In some embodiments, the structural layer is provided with a device structure, and the air gap is disposed in the device structure.

[0011] In some embodiments, the structural layer is provided with a device structure, and the air gap is provided in the dicing channels on both sides of the device structure near the chip region.

[0012] In some embodiments, the cutting channel is provided with a structural layer, and the air gap is provided in the substrate below the structural layer.

[0013] In some embodiments, the air gap is provided in both the structural layer and the substrate below the structural layer, and the air gap in the structural layer is provided correspondingly to the air gap in the substrate.

[0014] In some embodiments, a cross section perpendicular to the extension direction of the cutting channel is set as a preset cross section;

[0015] The projection pattern of the air gap in the structural layer onto the preset cross section is spindle-shaped, and / or the projection pattern of the air gap in the substrate onto the preset cross section is funnel-shaped.

[0016] In some embodiments, the plurality of air gaps are discretely arranged in the cutting channel, or the plurality of air gaps are connected in the cutting channel to form a groove.

[0017] In some embodiments, the air gap is disposed on both sides of the dicing channel near the chip region.

[0018] A second aspect of this disclosure provides a method for fabricating a semiconductor structure, the method comprising:

[0019] Provide a base;

[0020] At least one air gap is formed in at least a portion of the dicing channels of the substrate, wherein the plurality of dicing channels divide the substrate into a plurality of chip regions.

[0021] In some embodiments, the manufacturing method includes:

[0022] A structural layer is formed on the cutting channel;

[0023] The air gap is formed in the structural layer.

[0024] In some embodiments, forming the air gap in the structural layer includes:

[0025] A device structure is formed on the aforementioned structural layer;

[0026] The air gap is formed in the device structure.

[0027] In some embodiments, forming the air gap in the structural layer includes:

[0028] A device structure is formed on the aforementioned structural layer;

[0029] The air gap is formed in the dicing channels on both sides of the device structure near the chip area.

[0030] In some embodiments, the manufacturing method further includes:

[0031] The air gap is formed in the substrate;

[0032] The structural layer is formed above the air gap.

[0033] A third aspect of this disclosure provides a laser cutting method, comprising: cutting a semiconductor structure provided in the first aspect of this disclosure with a laser to obtain a chip.

[0034] In some embodiments, the laser cutting method includes:

[0035] The semiconductor structure is cut using a first laser beam along two mutually parallel first cutting paths;

[0036] The first cutting trajectory is located in the cutting channel and is located near the chip area of ​​the semiconductor structure.

[0037] In some embodiments, the laser cutting method includes:

[0038] The semiconductor structure is cut in a single pass using a second laser beam along a second cutting trajectory.

[0039] The second cutting trajectory is located in the middle of the cutting path.

[0040] A fourth aspect of this disclosure provides a semiconductor unit comprising a chip obtained by a laser cutting method according to a third aspect of this disclosure.

[0041] In the semiconductor structure, fabrication method, laser cutting method, and semiconductor unit disclosed herein, an air gap is provided inside the substrate corresponding to the cutting track position. The air gap can effectively reduce the mechanical strength of the cutting track, facilitate the separation of adjacent chip areas during wafer expansion, prevent external forces from damaging the chip area during wafer expansion, reduce the cutting track size, facilitate the setting of more chip areas on the substrate, and improve the effective utilization rate of the substrate.

[0042] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood. Attached Figure Description

[0043] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0044] Figure 1 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment.

[0045] Figure 2 This is illustrated according to an exemplary embodiment. Figure 1 A partial schematic diagram of region A in the middle.

[0046] Figure 3 This is illustrated according to an exemplary embodiment. Figure 2 A cross-sectional view along the BB direction.

[0047] Figure 4 This is illustrated according to another exemplary embodiment. Figure 2 A cross-sectional view along the BB direction.

[0048] Figure 5 This is illustrated according to an exemplary embodiment. Figure 2 A cross-sectional view along the CC direction.

[0049] Figure 6 This is illustrated according to another exemplary embodiment. Figure 2 A cross-sectional view along the CC direction.

[0050] Figure 7 This is illustrated according to another exemplary embodiment. Figure 2 A cross-sectional view along the BB direction.

[0051] Figure 8 This is illustrated according to another exemplary embodiment. Figure 2 A cross-sectional view along the BB direction.

[0052] Figure 9 This is illustrated according to another exemplary embodiment. Figure 2 A cross-sectional view along the BB direction.

[0053] Figure 10 This is illustrated according to another exemplary embodiment. Figure 2 A cross-sectional view along the BB direction.

[0054] Figure 11 This is illustrated according to another exemplary embodiment. Figure 2 A cross-sectional view along the BB direction.

[0055] Figure 12 This is illustrated according to another exemplary embodiment. Figure 2 A cross-sectional view along the BB direction.

[0056] Figure 13 This is illustrated according to another exemplary embodiment. Figure 2 A cross-sectional view along the BB direction.

[0057] Figure 14 This is a schematic diagram illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment.

[0058] Figure 15 This is a schematic diagram illustrating the formation of structural layers during the fabrication process of a semiconductor structure according to an exemplary embodiment.

[0059] Figure 16 This is a schematic diagram illustrating the formation of a partition during the fabrication process of a semiconductor structure according to an exemplary embodiment.

[0060] Figure 17 This is a schematic diagram illustrating the formation of an air gap during the fabrication process of a semiconductor structure according to an exemplary embodiment.

[0061] Figure 18 This is illustrated according to an exemplary embodiment. Figure 1 A partial schematic diagram showing two first cutting trajectories set in region A.

[0062] Figure 19 This is illustrated according to an exemplary embodiment. Figure 18 A cross-sectional view along the DD direction.

[0063] Figure 20 This is illustrated according to an exemplary embodiment. Figure 1 A partial schematic diagram of setting the second cutting trajectory in region A.

[0064] Figure 21 This is illustrated according to an exemplary embodiment. Figure 20 A cross-sectional view along the EE direction.

[0065] Figure 22 This is illustrated according to another exemplary embodiment. Figure 20 A cross-sectional view along the EE direction.

[0066] Figure label:

[0067] 100. Semiconductor structure; 101. Substrate; 102. First dicing track; 103. Second dicing track; 10. Die track; 20. Chip area; 21. Detection pin; 30. Air gap; 31. First air gap; 32. Second air gap; 40. Structural layer; 41. Conductive layer; 42. Insulating area; 43. Conductive plug; 44. Device structure; 50. Partition. Detailed Implementation

[0068] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0069] In related technologies, to test the performance of dies in a wafer (e.g., wafer acceptance test), detection pins are set on the dicing trace to check whether each process segment meets the standards. Typically, placing the detection pins on the dicing trace occupies the trace area, resulting in an excessively large dicing trace area, which in turn reduces the area on the wafer that can be used to house the chip.

[0070] To reduce the area of ​​the dicing channels and form more dies on the wafer, detection pins are placed at the edges of the dies to avoid them occupying the dicing channel area. Meanwhile, during wafer expansion, to minimize damage to the dicing channel area and adjacent chip areas, the more precise Stealth Dicing (SD) process has become mainstream. SD involves focusing a laser inside the wafer, irradiating the internal material to form a modified layer, and then separating multiple dies formed on the wafer through dicing or film expansion. This process can be applied to the fabrication of thin or ultra-thin chips for MEMS (Micro-Electro-Mechanical Systems), memory, and logic devices.

[0071] When using laser stealth dicing to cut wafers, the laser intensity must be high to ensure a larger area of ​​the modified layer, which is beneficial for wafer expansion. Simultaneously, the laser spot diameter must be small to prevent the laser spot from deviating from the cutting path due to laser precision issues, thus avoiding impact on the bare die (i.e., the chip area).

[0072] However, when actually employing laser stealth dicing, controlling the movement of a small-diameter laser spot makes it difficult to precisely position the laser spot on the preset cutting trajectory. Laser spots deviating from the cutting trajectory can easily damage the die during wafer expansion because they are further away from the modified layer. To reduce this damage, an offset must be allowed within the dicing kerf. This requires a wider dicing kerf as the working area of ​​the laser spot, resulting in a dicing kerf larger than the actual laser spot size. However, this reduces the number of chip areas that can be placed on the wafer, lowering the wafer's effective utilization rate.

[0073] In view of this, the present disclosure provides a semiconductor structure including a substrate with multiple dicing channels dividing the substrate into multiple chip regions; at least some of the dicing channels have at least one air gap. By providing air gaps within the substrate corresponding to the dicing channel positions, the present disclosure reduces the mechanical strength of the dicing channels, facilitates the separation of adjacent chip regions during wafer expansion, prevents damage to the chip regions from external forces during wafer expansion, helps reduce the dicing channel size, allows for the placement of more chip regions on the substrate, and improves the effective utilization rate of the substrate.

[0074] In exemplary embodiments of this disclosure, such as Figure 1 , Figure 2 and Figure 3 As shown, this disclosure provides a semiconductor structure 100, which can be a wafer or a semi-finished product in the wafer fabrication process. The semiconductor structure 100 includes a substrate 101, which has multiple dicing channels 10 that divide the substrate 101 into multiple chip regions 20. Among these, the multiple dicing channels 10 include those along a first direction (e.g., along a first direction). Figure 1 Multiple first cutting channels extending in the lateral direction shown in the figure and along the second direction (e.g., the first cutting channel extending in the lateral direction shown in the figure) and along the second direction (e.g., the second cutting channel extending in the lateral direction shown in the figure) Figure 1 Multiple second cutting channels (shown in the vertical direction) extend from each other, multiple first cutting channels are parallel to each other, multiple second cutting channels are parallel to each other, there is an angle between the first direction and the second direction, and the first cutting channels and the second cutting channels intersect each other, dividing the substrate 101 into multiple chip regions 20.

[0075] In one example, the first direction and the second direction are perpendicular to each other, and multiple cut lines 10 divide the substrate 101 into multiple chip regions 20 arranged in an array. (See reference...) Figure 1 As shown, Figure 1 The horizontal direction shown is the first direction. Figure 1 The vertical direction shown is the second direction.

[0076] The substrate 101 serves as a carrier for forming several chip regions 20. The substrate 101 can be a circular plate-like structure with a certain thickness. It can be formed from materials such as silicon (Si), germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or other materials such as gallium arsenide and other III-V group compounds. The substrate 101 is used to form a wafer. After determining the positions of the dicing channels 10 and the chip regions 20 on the substrate 101, the chip regions 20 are arranged in an array of rows and columns on the substrate 101. According to the layout of different functional areas, circuit structures can be correspondingly set inside the substrate 101 at the positions of the dicing channels 10 and the chip regions 20. For example, circuit structures (not shown in the figure) can be set inside the chip regions 20. Adjacent chip regions 20 are separated by dicing channels 10. Since the chip regions 20 are arrayed on the substrate 101, and the dicing channels 10 are intersecting on the substrate 101, the chip regions 20 on the substrate 10 can be divided along the dicing channels 10 during the subsequent dicing process to obtain several independent die-shaped chips 20. In some embodiments, since the dicing channel 10 refers to the area used for dicing, the dicing channel 10 may not have a circuit structure, or it may have circuitry for testing. This circuitry can be discarded after testing. Therefore, even if the dicing channel 10 is diced after testing, damage to the circuitry will not affect the functionality and reliability of the chip regions 20.

[0077] In this embodiment, during the subsequent wafer dicing process formed on the substrate 101, laser irradiation is used at the location corresponding to the dicing 10 for dicing. During the laser stealth dicing process on the semiconductor structure 100, the cutting laser penetrates the material on the surface of the dicing 10 and focuses in the substrate 101 at the location corresponding to the dicing 10, modifying the material inside the substrate 101 at the location corresponding to the dicing 10 and forming cracks. These cracks can propagate towards the top and bottom surfaces of the substrate 101. As the cutting laser moves along the extension direction of the dicing 10, multiple cracks are also arranged along the extension direction of the dicing 10, thereby forming a modified layer (not shown in the figure) in the substrate 101 at the location corresponding to the dicing 10. Further, a wafer expander is used to apply opposite external forces to the chip regions 20 on both sides of the dicing 10 after laser irradiation, causing adjacent chip regions 20 to break apart with the modified layer at the location corresponding to the dicing 10 as the starting point for separation, thus forming two independent chip regions 20.

[0078] refer to Figure 2 and Figure 3 As shown, Figure 2 yes Figure 1 A magnified view of a portion of region A in the middle. Figure 3 yes Figure 2 A cross-sectional view along the BB direction. An air gap 30 is provided in the substrate 101. The air gap 30 can be formed by incompletely filling the grooves or openings after etching the area of ​​the cutting channel 10. The air gap 30 is provided inside the substrate 101 at positions corresponding to the cutting channels 10. For example, the air gap 30 can be provided at positions corresponding to some of the cutting channels 10 in the substrate 101, or it can be provided at positions corresponding to all the cutting channels 10 in the substrate 101.

[0079] In some embodiments, an air gap 30 may be provided in the base 101 corresponding to the position of each of the several cutting channels 10, or an air gap 30 may be provided in the base 101 corresponding to the position of each of the entire cutting channels 10.

[0080] In other embodiments, two or more air gaps 30 may be provided in the base 101 corresponding to each position of several cutting channels 10, or two or more air gaps 30 may be provided in the base 101 corresponding to each position of all cutting channels 10.

[0081] This disclosure does not impose any restrictions on the number or shape of the air gaps 30 in each cutting path 10, as long as they are set in the substrate 101 and located in the area where the cutting path 10 is located. For example, they can be set in the circuit structure area or the non-circuit structure area in the cutting path 10. Because the air gaps 30 are set in the cutting path 10, the mechanical strength of the cutting path 10 area is reduced, and a better cutting effect can be obtained using a lower laser intensity when using laser cutting.

[0082] Because an air gap 30 is provided in the cutting channel 10, it is equivalent to pre-processing the fracture position of the substrate 101 during the wafer expansion process in the cutting channel 10, which has reduced the structural strength at the cutting channel 10 to a certain extent. A better cutting effect can be achieved using a lower intensity laser. Simultaneously, with the reduction in laser intensity, the laser spot does not need to be too small to focus energy. Therefore, a cutting laser with a larger spot diameter can be used to cut the cutting channel 10, increasing the cutting speed. Furthermore, since the laser spot is directly enlarged, the probability of deviating from the cutting trajectory is smaller, reducing the accuracy requirement for the laser spot positioning movement. Thus, there is no need to reserve a cutting channel distance to avoid laser spot deviation, allowing for a narrower cutting channel 10 size. This facilitates the placement of more chip regions 20 on the substrate 101, improving the effective utilization rate of the substrate 101. Furthermore, because the fracture position of the chip region 20 during the wafer expansion process is precise, the size of the remaining cutting channel 10 on the chip region 20 after cutting is consistent. This reduces the subsequent processing steps for the bare die formed from the chip region 20, reducing the size of the packaged chip after packaging the bare die formed from the chip region 20.

[0083] Furthermore, an air gap 30 is provided in the substrate 101 corresponding to the cutting track 10 to facilitate the expansion and separation of two adjacent chip regions 20 during subsequent cutting processes, preventing damage to the chip regions 20 from external forces during expansion. When there are precision errors in the laser stealth cutting process, for example, when the cutting laser deviates from the cutting trajectory and approaches the chip region 20, the presence of air gaps 30 at positions corresponding to some or all of the cutting tracks 10 ensures that the material fracture point during the expansion of the chip region 20 is located at the air gap 30. This reduces the damage to the chip region 20 caused by material fracture during expansion, thereby mitigating the impact of precision errors. Therefore, it is beneficial to reduce the size of the cutting track 10, facilitating the placement of more chip regions 20 on the substrate 101 and improving the effective utilization rate of the substrate 101.

[0084] In some possible implementations, refer to Figure 2 and Figure 4 As shown, air gaps 30 are positioned on both sides of the dicing channel 10 near the chip region 20. That is, two parallel rows of air gaps 30 can be positioned within the dicing channel 10 along its extension direction, bringing the air gaps 30 closer to the chip regions 20 on either side of the dicing channel 10. When the cutting laser forms a modified layer in the dicing channel 10, each row of air gaps 30 forms a cutting trajectory for the laser to cut. The laser can irradiate between the two rows of air gaps 30 in the dicing channel 10, or two lasers can simultaneously irradiate the locations of the two rows of air gaps 30. When expanding the chip region 20, adjacent chip regions 20 can be separated based on their adjacent row of air gaps 30 as the starting point for separation. This results in less residual material from the dicing channel 10 at the edges of the separated chip regions 20, reducing subsequent processing of the bare wafers formed from the chip regions 20 and facilitating the miniaturization of the packaged chip after packaging.

[0085] In some possible implementations, such as Figure 2 , Figure 5 and Figure 6 As shown, each cutting channel 10 is provided with multiple air gaps 30. Along the extension direction of the cutting channel 10, the multiple air gaps 30 are independent of each other and discretely distributed in the cutting channel 10, or the multiple air gaps 30 are interconnected to form a groove.

[0086] In the multiple dicing channels 10 provided on the substrate 101, at least one dicing channel 10 or each dicing channel 10 is provided with multiple air gaps 30, so that when the cutting laser moves along the extension direction of the dicing channel 10 and forms a modified layer inside the dicing channel 10, the multiple air gaps 30 can reduce the mechanical strength of the dicing channel 10, thereby assisting the chip area 20 on both sides of the dicing channel 10 to expand, reducing the damage to the chip area 20 during the expansion process, and improving production efficiency.

[0087] In some embodiments, combined with Figure 2 and Figure 5 As shown, Figure 5 yes Figure 2 In the cross-sectional view along the CC direction, multiple air gaps 30 are independently and discretely distributed along the extension direction of the cutting channel 10, which reduces the mechanical strength of the area along the extension direction of the cutting channel 10. The multiple air gaps 30 can locate the fracture position when the chip area 20 is expanded, so as to reduce the impact of the material fracture of the cutting channel 10 on the chip area 20 during the expansion process on both sides of the chip area 20.

[0088] In other embodiments, combined with Figure 2 and Figure 6 As shown, Figure 6 yes Figure 2 In a cross-sectional view along the CC direction, along the extension direction of the cutting channel 10, multiple air gaps 30 are interconnected in the cutting channel 10 to form a groove. Exemplarily, the multiple air gaps 30 are interconnected, meaning that the multiple air gaps 30 have the same shape and are connected, i.e. Figure 6 The groove shape shown can also be multiple air gaps 30 independently arranged, with a connecting channel between adjacent air gaps 30 to allow the multiple air gaps 30 to communicate with each other. The multiple air gaps 30 are interconnected along the extension direction of the dicing track 10 to form a groove, so as to further reduce the mechanical strength of the dicing track 10 and further reduce the damage to the chip area 20 during the wafer expansion process.

[0089] In one exemplary embodiment, reference Figure 2 , Figures 7 to 9 As shown, the cutting channel 10 is provided with a structural layer 40, and the air gap 30 is provided in the structural layer 40.

[0090] Since the semiconductor structure 100 has multiple chip regions 20, after the wafer is formed by fabricating the substrate 101, the multiple chip regions 20 need to be tested to determine the yield of the bare dies formed from the multiple chip regions 20 in the semiconductor structure 100, identify and mark the qualified and unqualified bare dies, so as to facilitate the packaging of qualified bare dies after dicing. A structural layer 40 is provided at the position corresponding to the dicing track 10. The structural layer 40 may include a conductive layer 41 disposed inside the substrate 101 and an insulating region 42 in the dicing track 10 area, and may also include a device structure 44. The structural layer 40 is provided inside the substrate 101 at the position corresponding to the dicing track 10 so that when testing the multiple chip regions 20 on the substrate 101, the test excitation signal given to the chip regions 20 by the external circuit can be transmitted through the conductive layer 41 in the structural layer 40 to complete the testing of the bare dies formed from the chip regions 20. The insulating region 42 can be formed using insulating materials such as silicon dioxide or silicon nitride, so that when multiple chip regions 20 in the semiconductor structure 100 are tested simultaneously, adjacent chip regions 20 are insulated from each other, ensuring the accuracy of the test.

[0091] refer to Figure 7 As shown, in the structural layer 40, the air gap 30 can be disposed within the structural layer 40. Exemplarily, the air gap 30 can be disposed in the insulating region 42 (not shown), or in the conductive layer 41, or simultaneously in the insulating region 42 and the conductive layer 41 (not shown), or in the device structure 44 (see reference). Figure 10 (This will be explained in detail later). It should be noted that when the air gap 30 is set in the conductive layer 41 of the structural layer 40, the position of the air gap 30 should not disconnect the electrical signal path of the structural layer 40 corresponding to the chip area 20. In other words, even if the structural layer 40 corresponding to the chip area 20 is equipped with an air gap 30, it is necessary to ensure that the conductive layer 41 in the structural layer 40 has its normal function of transmitting electrical signals.

[0092] In one exemplary embodiment, reference Figure 2 , Figure 8 and Figure 9As shown, the structural layer 40 includes multiple layers of spaced conductive layers 41. Since the test device for testing the chip region 20 is located inside the substrate 101, and the surface of the chip region 20 can be provided with detection pins 21 for contacting probes that apply test electrical excitation signals to external circuits, the structural layer 40 includes multiple layers of spaced conductive layers 41. The spaced conductive layers 41 can be electrically connected through conductive plugs 43, so that there is an electrical connection between the device structure 44 located at two different positions in the thickness direction of the substrate 101 and the detection pins 21. That is, the detection pins 21 on the chip region 20 transmit the received electrical excitation signals to the device structure 44 through the conductive layers 41 and the conductive plugs 43 to test the corresponding chip region 20.

[0093] For example, the detection pin 21 can be a pad or bump disposed on the surface of the chip region 20. The detection pin 21 is used to contact a probe that applies a test electrical excitation signal to an external circuit, so that the chip region 20 can receive the test electrical excitation signal. The conductive layer 41 can be a metal layer formed of copper, and an insulating region 42 is disposed between two adjacent conductive layers 41. Adjacent conductive layers 41 are electrically connected by conductive plugs 43, which penetrate the insulating region 42 between two adjacent conductive layers 41 in the thickness direction of the substrate 101. For example, the multilayer spaced conductive layers 41 can be formed using a damascus process.

[0094] Air gaps 30 are provided in at least a portion of the conductive layers 41, meaning that air gaps 30 can be provided in one or more conductive layers 41. Based on the position of the electrical connection between the conductive layer 41 and the device structure 44 in each structural layer 40 corresponding to the chip region 20, air gaps 30 can be provided in as many conductive layers 41 as possible, provided that the conductive layers 41 satisfy the electrical connection between the detection pin 21 of the chip region 20 and the device structure 44.

[0095] In some embodiments, reference Figure 8 As shown, for example, when the structural layer 40 includes three spaced-apart conductive layers 41, due to Figure 8 The device structure 44 corresponding to the chip area 20 on the left is located on the right side, which is farther away from the chip area 20. In order to ensure that the detection pin 21 is electrically connected to the device structure 44, an air gap 30 can be set in two of the three conductive layers 41 to assist in the subsequent expansion of the chip area 20.

[0096] In some embodiments, reference Figure 9As shown, for example, when the structure layer 40 includes three spaced conductive layers 41, and the device structure 44 corresponding to each chip region 20 is located close to each other, air gaps 30 can be provided in all conductive layers 41 corresponding to the position of the cutting channel 10 without affecting the electrical connection between the detection pin 21 and the device structure 44, so as to assist in the subsequent wafer expansion of the chip region 20.

[0097] It should be noted that, to improve testing efficiency, multiple chip regions 20 can be tested simultaneously. To ensure testing accuracy, each chip region 20 and its corresponding structural layer 40 are mutually insulated during the testing process. Therefore, refer to... Figure 9 Each chip region 20 is provided with a corresponding structural layer 40, and the structural layers 40 corresponding to two adjacent chip regions 20 are insulated. For example, the device structure 44 in each structural layer 40 can be disposed in an insulating material. In actual manufacturing processes, in order to improve production efficiency, when forming the structural layer 40, two structural layers 40 corresponding to two adjacent chip regions 20 can be formed simultaneously, and the two structural layers 40 are in a connected state; then, all the conductive layers 41 in the structural layer 40 at the corresponding position of the dicing 10 are etched, thereby setting the air gap 30 in the conductive layer 41. That is to say, the air gap 30 is set in all the conductive layers 41, which can make the conductive layers 41 that were originally in a connected state split into two at the corresponding position of the dicing 10, so that the structural layers 40 corresponding to two adjacent chip regions 20 are insulated.

[0098] In some possible implementations, refer to Figures 8 to 10 As shown, the structural layer 40 is provided with a device structure 44, which is used to test the chip region 20. The device structure 44 contains test circuitry. For example, since the dicing channel 10 is cut only after all chip regions 20 on the substrate 101 have been tested, the bare dies formed from the cut individual chip regions 20 do not need to undergo further testing through the device structure 44. Therefore, the device structure 44 can be disposed within the structural layer 40 of the dicing channel 10. In other words, after the chip regions 20 on the substrate 101 are cut and separated, the device structure 44 can be discarded.

[0099] refer to Figure 10As shown, when the air gap 30 is disposed in the structural layer 40, the air gap 30 can be disposed alone in the device structure 44 (not shown in the figure). In some embodiments, the air gap 30 can also be disposed simultaneously in the conductive layer 41 and the device structure 44. Exemplarily, the air gap 30 can be disposed in a position in the device structure 44 where no effective device is disposed, so as to avoid affecting the normal function of the device structure 44. Disposing of the air gap 30 in the device structure 44 further reduces the mechanical strength of the area corresponding to the dicing track 10, which is beneficial for expanding the chip area 20.

[0100] In some possible implementations, refer to Figure 2 and Figure 12 As shown, when the structural layer 40 is provided with a device structure 44, and the device structure 44 is located in the middle of the dicing channel 10 and has a certain distance from the two adjacent chip regions 20, air gaps 30 can be provided in the dicing channels 10 near the chip regions 20 on both sides of the device structure 44. The air gaps 30 can be provided in the conductive layers 41 on both sides of the device structure 44, or in the substrates 101 on both sides of the device structure 44, or simultaneously in both the conductive layers 41 and the substrates 101 on both sides of the device structure 44. The air gap in the conductive layers 41 on both sides of the device structure 44 is designated as the first air gap 31, and the air gap in the substrates 101 on both sides of the device structure 44 is designated as the second air gap 32. The positions of the first air gap 31 and the second air gap 32 are correspondingly arranged to reduce the mechanical strength at the location where the air gaps 30 are provided in the dicing channel 10.

[0101] By setting air gaps 30 in the dicing channels 10 near the chip regions 20 on both sides of the device structure 44, the mechanical strength of the dicing channels 10 is reduced, while the distance between the air gaps 30 and the chip regions 20 on both sides of the dicing channels 10 is made closer. When the cutting laser forms a modified layer in the dicing channels 10, each row of gaps 30 forms a cutting trajectory that the cutting laser can cut. The cutting laser can irradiate the area between two rows of gaps 30 in the dicing channels 10, i.e., the area corresponding to the device structure 44, or two cutting lasers can be set to irradiate the location of two rows of gaps 30 simultaneously. When expanding the chip regions 20, two adjacent chip regions 20 can be separated based on their adjacent row of gaps 30 as the starting point for separation. This results in less material remaining in the dicing channels 10 at the edge of the separated chip regions 20, reducing the need for subsequent processing of the bare dies formed from the chip regions 20, which is beneficial for the miniaturization of the packaged chips after the bare dies are packaged.

[0102] In one exemplary embodiment, reference Figure 2 and Figure 11 As shown, the cutting channel 10 is provided with a structural layer 40, and an air gap is provided in the base 101 below the structural layer 40.

[0103] The structural layer 40 may include a conductive layer 41 disposed inside the substrate 101 and an insulating region 42 in the dicing 10 region, and may also include a device structure 44. The structural layer 40 is disposed inside the substrate 101 at the location corresponding to the dicing 10 so that when testing multiple chip regions 20 on the substrate 101, the test excitation signal given to the chip region 20 by the external circuit can be transmitted through the conductive layer 41 in the structural layer 40 to complete the testing of the bare die formed by the chip region 20.

[0104] In this embodiment, an air gap may not be provided in the structural layer 40, but rather in the substrate 101 below the structural layer 40. This air gap in the substrate 101 below the structural layer 40 serves as a second air gap 32. The second air gap 32 can be located in the substrate 101 on the side of the device structure 44 away from the conductive layer 41, thereby reducing the mechanical strength of the dicing track 10. Reducing the laser intensity during the dicing process increases the laser spot diameter, lowers the accuracy requirement for laser spot positioning, and reduces the impact of spot positioning errors on chip area 20 damage. This allows for a narrower dicing track 10, facilitating the placement of more chip areas 20 on the substrate 101 and improving the effective utilization rate of the substrate 101.

[0105] For example, one or more second air gaps 32 may be provided in the substrate 101 along the extension direction of the cutting channel 10 where the second air gap 32 is located. When multiple second air gaps 32 are provided in the cutting channel 10, the multiple second air gaps 32 may be independent of each other and discretely distributed in the cutting channel 10, or the multiple second air gaps 32 may be interconnected. During the fabrication process, before forming the structural layer 40, the substrate 101 may be etched to form an opening, and the filling process may be controlled in the subsequent filling process to incompletely fill the opening to form the second air gap 32.

[0106] In some embodiments, the second air gap 32 in the substrate 101 can be configured as a through groove extending along the extension direction of the dicing channel 10. Compared to the second air gap 32 being configured as independent and discretely distributed grooves, the second air gap 32 being a through groove extending along the extension direction of the dicing channel 10 can reduce the mechanical strength of the material of the dicing channel 10 along the extension direction of the dicing channel 10. The second air gap 32 can locate the fracture position during wafer expansion of the chip region 20, so as to further reduce the damage to the chip region 20 caused by the fracture of the dicing channel 10 material during the wafer expansion process.

[0107] It is understandable that the second air gap 32 can be set in the middle area of ​​the cutting channel 10 (e.g., Figure 11 As shown), it can also be disposed on both sides near the chip area 20 (not shown in the figure), the cross section of the second air gap 32 in the direction perpendicular to the extension of the cutting channel 10 (i.e. Figure 11The shape on the cross section shown can be circular, elliptical, spindle-shaped, funnel-shaped, etc. This embodiment does not limit the way the second air gap 32 is set.

[0108] In some possible implementations, refer to Figure 12 and Figure 13 As shown, air gaps 30 are provided in both the structural layer 40 and the substrate 101 below the structural layer 40. The first air gap 31 in the structural layer 40 and the second air gap 32 in the substrate 101 are provided in a corresponding manner. This reduces the mechanical strength at the locations where the first air gap 31 and the second air gap 32 are provided in the cutting path 10, thereby reducing the laser intensity required during the cutting process. This can increase the laser spot diameter, reduce the laser spot positioning accuracy requirements, and reduce the impact of spot positioning errors on chip area 20.

[0109] In some possible implementations, refer to Figure 2 , Figure 11 and Figure 12 As shown, the cross section perpendicular to the extension direction of the cutting channel 10 is set as the preset cross section. In one example, the projection pattern of the first air gap 31 in the structural layer 40 on the preset cross section is spindle-shaped; in another example, the projection pattern of the second air gap 32 in the base 101 on the preset cross section is funnel-shaped. Of course, it can be understood that different air gaps in the structural layer 40 can adopt the same shape or different shapes.

[0110] In this embodiment, the preset cross-section is a cross-section extending along the thickness direction of the substrate 101 and perpendicular to the extension direction of the cutting channel 10 where the air gap 30 is located. That is, for the cutting channel 10 extending in the horizontal direction, Figure 2 The cross-section shown in the BB direction is the preset cross-section. Since the cracks formed by the cutting laser inside the cutting path 10 propagate towards the top and bottom surfaces of the substrate 101, the projection pattern of the first air gap 31 on the preset cross-section is spindle-shaped, as shown in the reference section. Figure 11 and Figure 13 As shown, the spindle shape is a shape that is pointed at both ends and wide in the middle, so that the wider position in the middle of the first air gap 31 can be used as the starting point for the separation of two adjacent chip regions 20, so as to facilitate the expansion of the chip region 20 and reduce the damage to the chip region 20 caused by material breakage during the expansion process.

[0111] For example, the projection pattern of the second air gap 32 on a preset cross section is set to be funnel-shaped, as shown in the reference. Figure 11 and Figure 13As shown, the funnel shape can be a shape that is wide at the top and narrow at the bottom, or it can be an inverted cone shape. The second air gap 32 is funnel-shaped, which allows the wider part of the second air gap 32 to be close to the middle position of the substrate 101 on the preset cross section, so as to approach the crack formed inside the cutting track 10 by the cutting laser, so that the second air gap 32 can assist the chip area 20 in expanding.

[0112] In one exemplary embodiment, this disclosure also provides a method for fabricating a semiconductor structure, the method being used to fabricate the semiconductor structure provided in the above embodiments of this disclosure, with reference to... Figure 14 As shown, the method for fabricating a semiconductor structure includes the following steps:

[0113] Step S100: Provide a substrate;

[0114] Step S200: At least one air gap is formed in at least a portion of the dicing channels of the substrate, wherein the multiple dicing channels divide the substrate into multiple chip regions.

[0115] In step S100, refer to Figure 1 As shown, substrate 101 is used to fabricate a wafer. Substrate 101 can be a circular plate-like structure with a certain thickness. Substrate 101 can be formed from materials such as silicon (Si), germanium (Ge), silicon-germanium (GeSi), and silicon carbide (SiC), or from materials such as silicon-on-insulator (SOI) and germanium-on-insulator (GOI), or from other materials such as gallium arsenide and other III-V group compounds. In step S200, reference... Figures 1 to 3 As shown, based on the IC design layout, the functional areas of the wafer formed on the substrate 101 are determined. Multiple dicing channels 10 are defined in the substrate 101. The multiple dicing channels 10 divide the substrate 101 into rectangular block spaces that are distributed in an array and are defined as chip areas 20, so that circuit structures can be set in different functional areas in the subsequent photolithography process.

[0116] During the wafer fabrication process on substrate 101, since the wafer includes multiple chip regions 20, each chip region 20 corresponds to a subsequent die formation. The IC design layout can be formed on the chip region 20 through photolithography, and the design layout corresponding to the dicing track 10 can be formed on the dicing track 10 through photolithography. After the pattern corresponding to the dicing track 10 is formed, etching is performed at the locations where air gaps 30 are set in some or all of the dicing tracks 10. By controlling subsequent filling processes, such as utilizing material properties or controlling process parameters, the filling material is made to incompletely fill the locations where air gaps 30 are set, thereby forming air gaps 30. For example, after the pattern of the chip region 20 is formed, ions are doped in the corresponding areas. By implanting impurities into the silicon structure, local conductivity is controlled to fabricate transistors and form electronic components such as diodes. After the transistors, diodes, and other electronic components are fabricated, a metal interconnect process is performed to connect the transistors in the circuit structure within the chip region 20 to form the chip region.

[0117] Air gaps 30 are provided in at least a portion of the dicing channels 10 on the substrate 101 to reduce the mechanical strength of the corresponding positions of the dicing channels 10. This facilitates the separation of two adjacent chip regions 20 during subsequent dicing processes, preventing damage to the chip regions 20 from external forces during wafer expansion. Furthermore, when there are precision errors in the dicing process, such as when the cutting laser deviates from the dicing trajectory and approaches the chip region 20, the presence of air gaps 30 at the corresponding positions of some or all of the dicing channels 10 ensures that the material fracture point of the chip region 20 during wafer expansion is located at the location of the air gaps 30. This reduces the damage to the chip region 20 caused by material fracture during wafer expansion, thereby reducing the impact of precision errors. Therefore, it is beneficial to reduce the size of the dicing channels 10, making it easier to set more chip regions 20 on the substrate 101 and improving the effective utilization rate of the substrate 101.

[0118] In one exemplary embodiment, the method for fabricating a semiconductor structure further includes the following steps:

[0119] Step S101: Form a structural layer on the cutting path;

[0120] Step S102: Form an air gap in the structural layer.

[0121] In step S101, refer to Figure 15As shown, based on the design layout corresponding to the dicing 10, the layout corresponding to the structural layer 40 is formed by photolithography at the position of the dicing 10 defined on the substrate 101. The structural layer 40 may include conductive layers 41 and insulating regions 42 that separate multiple conductive layers 41. After forming the photolithography pattern, etching is performed at the positions where conductive layers 41 need to be formed to form openings. The openings are filled with conductive materials such as copper, aluminum, or tungsten to form conductive layers 41. For example, after each conductive layer 41 is formed, insulating material is deposited on the surface of the conductive layer 41 to form insulating regions 42 that separate multiple conductive layers 41. Subsequently, the insulating regions 42 are partially etched to form vias, and metal is filled into the vias to form conductive plugs 43 that connect adjacent conductive layers 41. For example, the structural layer 40 including multiple conductive layers 41 and conductive plugs 43 connecting multiple conductive layers 41 can be formed using a damascus process.

[0122] Combination Figure 9 and Figure 15 As shown, since the structure layer 40 is used to test the corresponding chip area 20, in order to ensure that each chip area 20 is tested independently during the testing process, each structure layer 40 is only connected to the detection pin 21 of a certain chip area 20, and the structure layers 40 corresponding to different chip areas 20 are isolated.

[0123] In step S102, combined Figure 9 and Figure 16 As shown, since each structural layer 40 connects only to the detection pin 21 of a specific chip region 20, that is, for each chip region 20, a corresponding structural layer 40 is provided. (Reference) Figure 16 As shown, at the position corresponding to the cutting path 10, the structural layer 40 is etched to form a partition 50. The partition 50 can be an opening that penetrates multiple conductive layers 41. The partition 50 divides the structural layer 40 formed in step S101 into two independent structural layers 40. That is, the etched 50 makes the structural layers 40 corresponding to each chip region 20 mutually insulated, so that each structural layer 40 is electrically connected to the detection pin 21 of its corresponding chip region 20, thereby realizing the simultaneous testing of multiple chip regions 20 before the semiconductor structure 100 is cut.

[0124] Combination Figure 16 and Figure 17As shown, an insulating dielectric layer is formed in the partition 50. This can be achieved using methods such as chemical vapor deposition or plasma vapor deposition. During the formation of the insulating dielectric layer, by adjusting the material used or the process parameters, incomplete filling occurs at the partition 50 corresponding to each conductive layer 41, creating air gaps 30 in each conductive layer 41, thereby forming air gaps 30 in the structural layer 40. Exemplarily, the projection pattern of the cross-section of the air gap 30 extending along the thickness direction of the substrate 101 and perpendicular to the extension direction of the cutting path 10 where the air gap 30 is located is spindle-shaped.

[0125] In some possible implementations, step S102, forming an air gap in the structural layer, includes:

[0126] Step S1021: Form the device structure in the structural layer;

[0127] Step S1022: Form an air gap in the device structure.

[0128] In step S1021, refer to Figure 15 As shown, the position of the cut track 10 is defined on the substrate, and the position of the device structure 44 is determined based on the position of the cut track 10. Based on the transistors and electrical connectors set in the circuit pattern corresponding to the device structure 44, the corresponding test circuit is formed on the circuit pattern using processes such as ion doping and metal interconnection to form the device structure 44.

[0129] In step S1022, refer to Figure 10 As shown, the locations in device structure 44 where no effective devices are located are determined, and these locations are etched to form openings or through-holes. These openings or through-holes are then filled with insulating material. During the filling process, by adjusting the ratio of the insulating material or adjusting the process parameters, incomplete filling is achieved at these openings or through-holes, thus creating an air gap 30 in device structure 44.

[0130] In some possible implementations, step S102, forming an air gap in the structural layer, includes:

[0131] Step S1023: Form the device structure in the structural layer;

[0132] Step S1024: Form an air gap in the dicing channels near the chip area on both sides of the device structure.

[0133] In this embodiment, step S1023 is similar to or the same as step S1021 in the above embodiment, and will not be described in detail here.

[0134] In step S1024, refer to Figure 12 As shown, when the device structure 44 is located in the middle of the dicing channel 10 and the device structure 44 is a certain distance from the two adjacent chip regions 20, after the device structure 44 is formed, air gaps 30 can be formed in the dicing channels 10 near the chip regions 20 on both sides of the device structure 44. The air gaps 30 can be disposed in the conductive layers 41 on both sides of the device structure 44, or they can be disposed in the substrates 101 on both sides of the device structure 44. The air gaps disposed in the conductive layers 41 on both sides of the device structure 44 are used as the first air gaps 31. The method for forming the first air gaps 31 can be the same as or similar to the method shown in step S102, and will not be described in detail here.

[0135] The air gaps in the substrates 101 on both sides of the device structure 44 are used as the second air gaps 32. When forming the second air gaps 32, the material of the substrates 101 on both sides of the device structure 44 can be etched to form two openings based on the distance between the device structure 44 and the two adjacent chip regions 20. The two openings correspond to the positions of the first air gaps 31 in the thickness direction of the substrates 101. Then, the openings on both sides of the device structure 44 are filled with insulating material. When filling the insulating material, by adjusting the ratio of the insulating material or adjusting the process parameters when filling the insulating material, the two openings are partially filled, so as to form the second air gaps 32 in the dicing channels 10 near the chip regions 20 on both sides of the device structure 44.

[0136] In some possible implementations, the method for fabricating the semiconductor structure further includes the following steps:

[0137] Step S201: Form an air gap in the substrate;

[0138] Step S202: Form a structural layer above the air gap.

[0139] In this embodiment, reference Figure 13 As shown, the air gap formed in the substrate 101 serves as the second air gap 32. Before forming the structural layer 40, the substrate 101 is etched in the region corresponding to the etch path 10. The etching can be performed using wet etching or dry etching to form a trench. For example, the projection pattern of the trench on the cross-section extending along the thickness direction of the substrate 101 and perpendicular to the extension direction of the etch path 10 where the trench is located is funnel-shaped. The material used to fill the trench can be insulating materials such as silicon dioxide or silicon nitride. When filling the trench, by adjusting the composition of the filling trench material or adjusting the process parameters when filling the trench, incomplete filling is achieved during trench filling to form the second air gap 32 in the substrate 101.

[0140] After forming the second air gap 32, a photolithographic pattern corresponding to the structural layer 40 is formed above the second air gap 32 by photolithography. The photolithographic pattern is then subjected to etching, circuit fabrication, metal interconnection, and other processes to form the structural layer 40. For example, the structural layer 40 may include a device structure 44 near the second air gap 32, a conductive layer 41 electrically connected to the device structure 44, and insulating regions 42 separating the multiple conductive layers 41. The method for forming the structural layer 40 is the same as or similar to the method shown in step S101 above, and will not be described in detail here.

[0141] In some possible implementations, the method for fabricating the semiconductor structure further includes:

[0142] Step S300: Form detection pins for testing on the surface of the chip area;

[0143] Step S400: An electrical connection is formed between the structural layer corresponding to the chip area and the detection pin.

[0144] In step S300, combined Figures 7 to 13 As shown, a test pin 21 for testing is formed on the surface of the chip region 20. For example, a pad, solder joint, or bump connecting the internal circuit of the chip region 20 can be formed on the surface of the chip region 20 to serve as the test pin 21. Alternatively, the chip region 20 can be etched to expose the internal circuit layer of the chip region 20 to serve as the test pin 21.

[0145] In step S400, since the chip area 20 corresponds one-to-one with the structural layer 40, for each chip area 20, a conductive plug 43 can be set between the chip area 20 and the corresponding structural layer 40. For example, a via can be formed between the chip area 20 and the structural layer 40 by means of laser drilling or mechanical drilling, and then conductive material can be filled into the via to form a conductive plug 43, so that an electrical connection is formed between the structural layer 40 corresponding to the chip area 20 and the detection pin 21, so that the electrical signal can be transmitted between the detection pin 21 and the structural layer 40, and the function of testing the chip area 20 can be realized.

[0146] The semiconductor structure fabrication method disclosed herein forms a semiconductor structure by setting air gaps inside the substrate corresponding to the dicing ridges. This reduces the mechanical strength at the dicing ridge locations, facilitating the separation of adjacent chip regions during subsequent dicing processes and preventing damage to the chip regions from external forces during wafer expansion. Furthermore, when precision errors exist in the laser stealth dicing process, such as when the cutting laser deviates from the cutting trajectory and approaches the chip region, setting air gaps at the locations corresponding to some or all dicing ridges ensures that material fracture during chip region expansion occurs at the air gap locations. This reduces damage to the chip region caused by material fracture during wafer expansion, thereby mitigating the impact of precision errors. Therefore, it is beneficial to reduce the size of the dicing ridges, facilitating the fabrication of more chip regions on the substrate and improving the effective utilization rate of the substrate.

[0147] In one exemplary embodiment, this disclosure also provides a laser cutting method, comprising: cutting the semiconductor structure 100 provided in the above embodiments of this disclosure with a laser to obtain a chip. The laser cutting method may be a laser stealth dicing (SD) method. When performing the laser stealth dicing process on the semiconductor structure 100, reference is made to... Figures 18 to 22 As shown, the cutting laser penetrates the material on the surface of the dicing track 10 and focuses inside the semiconductor structure 100 at the corresponding position of the dicing track 10, modifying the material of the substrate 101 at the corresponding position of the dicing track 10 and forming cracks. The cracks can propagate towards the top and bottom surfaces of the substrate 101. As the cutting laser moves along the extension direction of the dicing track 10, multiple cracks are also arranged along the extension direction of the dicing track 10, thereby forming a modified layer (not shown in the figure) in the substrate 101 at the corresponding position of the dicing track 10. Further, a wafer expander is used to apply opposite external forces to the chip regions 20 on both sides of the dicing track 10 after the cutting laser irradiation, so that the two adjacent chip regions 20 break apart with the modified layer at the corresponding position of the dicing track 10 as the starting point for separation, thereby obtaining two independent chips.

[0148] When the semiconductor structure 100 disclosed herein is cut with a laser, the presence of an air gap 30 in the cutting path 10 effectively pre-processes the fracture location of the substrate 101 during the wafer expansion process, thus reducing the structural strength at the cutting path 10 to some extent. This allows for better cutting results using a lower-intensity laser, preventing damage to the chip region 20 during the wafer expansion process. Simultaneously, as the laser intensity decreases, the laser spot size does not need to be excessively small to focus energy. Therefore, a cutting laser with a larger spot diameter can be used to cut the cutting path 10, increasing the cutting speed. Furthermore, the increased laser spot size reduces the probability of deviation from the cutting trajectory, lowering the accuracy requirement for laser spot positioning and movement. This eliminates the need to reserve a cutting path distance to prevent laser spot deviation, allowing for a narrower cutting path 10 size. This facilitates the placement of more chip regions 20 on the substrate 101, improving the effective utilization rate of the substrate 101. Furthermore, because the fracture location of the chip region 20 during the wafer expansion process is precise, the size of the remaining cutting tracks 10 on the chip region 20 after cutting is consistent. This reduces the number of subsequent processing steps on the bare die formed from the chip region 20, and decreases the size of the packaged chip after the bare die formed from the chip region 20 is packaged. In addition, when there is a precision error in the cutting laser, by setting an air gap 30 at the position corresponding to some or all of the cutting tracks 10, the material fracture location during the wafer expansion process of the chip region 20 can be located at the position where the air gap 30 is set, reducing the damage to the chip region 20 caused by material fracture during the wafer expansion process, thereby reducing the impact of precision errors.

[0149] In some possible implementations, refer to Figure 18 and Figure 19 As shown, the laser cutting method provided in this disclosure includes:

[0150] Step S1: Use a first laser beam to cut the semiconductor structure along two parallel first cutting trajectories; wherein the first cutting trajectories are located on the cutting trajectories and are located near the chip area of ​​the semiconductor structure.

[0151] The path along which the cutting laser moves in the extension direction of the cutting track 10 is the cutting trajectory. The first cutting trajectory 102 is in... Figure 18 and Figure 19The image is shown as a dashed line, meaning that during the cutting process, the cutting laser continuously or intermittently irradiates along the path defined by the cutting trajectory on the cutting track 10 to form cracks inside the cutting track 10 corresponding to the cutting trajectory position, so as to facilitate the wafer expansion of the chip region 20 on the semiconductor structure 100. It should be noted that since the path defined by the cutting trajectory extends along the extension direction of the cutting track 10, when the cutting track 10 is set with a cutting trajectory, the projection of the cutting trajectory on the cutting track 10 should partially or completely coincide with the projection of the air gap 30 on the cutting track 10, so that the air gap 30 can assist the wafer expansion process of the chip region 20 after the cutting laser cuts the cutting track 10, thereby reducing the damage to the chip region 20 during the wafer expansion process.

[0152] refer to Figure 18 and Figure 19 As shown, since the chip obtained after dicing does not need to undergo further testing through the structural layer 40, the structural layer 40 located on the dicing channel 10 can be discarded or damaged. Air gaps 30 are formed in the dicing channel 10 on both sides of the device structure in the structural layer 40, near the chip region 20. This results in two parallel first dicing tracks 102 being positioned on the dicing channel 10 near the chip region 20 of the semiconductor structure 100. In other words, the device structure in the structural layer 40 is located between the two parallel first dicing tracks 102. A first laser beam is used to cut the dicing channel 10 along the two parallel first dicing tracks 102. Since the first dicing tracks 102 are located close to the chip region 20, the spot area of ​​the first laser beam should be controlled to a small area to avoid damage to the chip region 20. After the first laser beam cuts along two parallel first cutting trajectories 102, two adjacent chip regions 20 can be separated based on their adjacent first cutting trajectories 102 as the starting point for separation. The device structure in the structural layer 40 is completely discarded, and no damaged device structure 44 remains on the chip region 20. The chip obtained after separation has less material left on the edge of the cutting trajectories 10, which reduces the subsequent processing steps of the chip and is conducive to the miniaturization of the packaged chip size after packaging.

[0153] In some possible implementations, refer to Figures 20 to 22 As shown, the laser cutting method includes:

[0154] Step S2: Use the second laser beam to make a single cut along the second cutting trajectory; wherein the second cutting trajectory is located in the middle of the cutting path, and the spot area of ​​the second laser beam is larger than the spot area of ​​the first laser beam.

[0155] In some embodiments, combined with Figures 20 to 21As shown, when only one row of air gaps 30 is provided in the dicing channels 10 of two adjacent chip regions 20, since the independent chips obtained by cutting do not need to undergo further testing through the device structure in the structural layer 40, the device structure provided in the dicing channel 10 can be discarded or damaged. By setting a second cutting trajectory 103 in the middle position of the dicing channel 10, the second cutting trajectory 103 partially or completely overlaps with the position of the air gap 30, so that after the second laser beam performs a single cut on the dicing channel 30 along the second cutting trajectory 103, the modified layer generated by the second laser beam partially or completely corresponds to the position of the air gap 30 on the second cutting trajectory 103, so that the air gap 30 on the second cutting trajectory 103 can play an auxiliary role in separating the two adjacent chip regions 20. For example, the second cutting trajectory 103 can pass through the device structure in the structural layer 40, so that in the subsequent wafer expansion process, the device structure provided inside the dicing channel 10 is damaged, and the chip obtained by cutting does not contain a complete device structure. Since the second cutting trajectory 103 is located in the middle of the cutting path 10, the second laser beam is less likely to damage the chip areas 20 on both sides of the cutting path 10.

[0156] In some embodiments, the spot area of ​​the second laser beam is set to be larger than that of the first laser beam, and a wider modified layer can be formed in the substrate 101 corresponding to the second cutting trajectory 103. This can improve the speed of laser stealth cutting while ensuring good separation of adjacent chip regions 20.

[0157] In other embodiments, combined with Figure 20 and Figure 22 As shown, when the air gaps 30 are positioned on both sides of the cutting channel 10 near the chip region 20, that is, along the extension direction of the cutting channel 10, two parallel rows of air gaps 30 are provided in the cutting channel 10, and a second cutting trajectory 103 is provided in the middle of the cutting channel 10. Since the spot area of ​​the second laser beam is large, it can cover the area between the two rows of air gaps 30. In other words, the spot area of ​​the second laser beam does not coincide with the position of the air gaps 30. The second laser beam can form a wider modified layer in the substrate 101 corresponding to the second cutting trajectory 103, increasing the speed of laser stealth cutting. Furthermore, since air gaps 30 are provided on both sides of the cutting channel 10 near the chip region 20, during the subsequent wafer expansion process, the position of the air gaps 30 is the location where the chip region 20 breaks, and the large spot area of ​​the second laser beam will not damage the chip region 20.

[0158] In one exemplary embodiment, this disclosure also provides a semiconductor unit comprising a chip obtained by the laser cutting method described above. The semiconductor unit can be a packaged chip comprising a single chip, or it can be an HBM (High Bandwidth Memory) comprising multiple chips; this disclosure does not limit this. Since the chip in the semiconductor unit is obtained by the laser cutting method described in the above embodiments of this disclosure, the edge structure of the chip suffers less damage, resulting in higher chip reliability. The semiconductor unit formed using this chip exhibits good electrical performance and functional reliability. Furthermore, because there is less residual cutting material at the chip edges, the semiconductor unit formed using this chip has a smaller volume.

[0159] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0160] In the description of this specification, references to the terms "embodiment," "exemplary embodiment," "some implementation," "illustrated implementation," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this disclosure.

[0161] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0162] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0163] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0164] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0165] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A semiconductor structure, characterized in that, The semiconductor structure includes a substrate, which has multiple dicing channels that divide the substrate into multiple chip regions. At least a portion of the cutting channel is provided with at least one air gap; The cutting channel is provided with a structural layer, and the air gap is provided in the structural layer; The structural layer is provided with a device structure, and the air gap is provided in the dicing channel on both sides of the device structure near the chip area; The chip area is equipped with detection pins; The device structure is a test circuit, and the test circuit is electrically connected to the detection pin.

2. The semiconductor structure according to claim 1, characterized in that, The structural layer includes multiple conductive layers spaced apart, and at least a portion of the conductive layers have the air gap.

3. The semiconductor structure according to claim 1, characterized in that, The structural layer is provided with a device structure, and the air gap is provided in the device structure.

4. The semiconductor structure according to claim 1, characterized in that, The cutting channel is provided with a structural layer, and the air gap is provided in the substrate below the structural layer.

5. The semiconductor structure according to claim 4, characterized in that, The air gap is provided in both the structural layer and the substrate below the structural layer, and the air gap in the structural layer is provided in correspondence with the air gap in the substrate.

6. The semiconductor structure according to claim 4, characterized in that, A cross section perpendicular to the extension direction of the cutting path is set as a preset cross section; The projection pattern of the air gap in the structural layer onto the preset cross section is spindle-shaped, and / or the projection pattern of the air gap in the substrate onto the preset cross section is funnel-shaped.

7. The semiconductor structure according to claim 1, characterized in that, The multiple air gaps are discretely arranged in the cutting channel, or the multiple air gaps are connected in the cutting channel to form a groove.

8. The semiconductor structure according to claim 1, characterized in that, The air gap is located on both sides of the cutting channel near the chip area.

9. A method for fabricating a semiconductor structure, characterized in that, The manufacturing method includes: Provide a base; At least one air gap is formed in at least a portion of the dicing channels of the substrate, wherein the plurality of dicing channels divide the substrate into a plurality of chip regions; The manufacturing method includes: A structural layer is formed on the cutting channel; The air gap is formed in the structural layer; The formation of the air gap in the structural layer includes: A device structure is formed on the aforementioned structural layer; The air gap is formed in the dicing channels on both sides of the device structure near the chip area; The chip area has detection pins; the device structure is a test circuit, and the test circuit is electrically connected to the detection pins.

10. The method for fabricating a semiconductor structure according to claim 9, characterized in that, The formation of the air gap in the structural layer includes: A device structure is formed on the aforementioned structural layer; The air gap is formed in the device structure.

11. The method for fabricating a semiconductor structure according to claim 9, characterized in that, The manufacturing method further includes: The air gap is formed in the substrate; The structural layer is formed above the air gap.

12. A laser cutting method, characterized in that, include: A chip is obtained by laser cutting of the semiconductor structure as described in any one of claims 1-8.

13. The laser cutting method according to claim 12, characterized in that, The laser cutting method includes: The semiconductor structure is cut using a first laser beam along two mutually parallel first cutting paths; The first cutting trajectory is located in the cutting channel and is located near the chip area of ​​the semiconductor structure.

14. The laser cutting method according to claim 12, characterized in that, The laser cutting method includes: The semiconductor structure is cut in a single pass using a second laser beam along a second cutting trajectory. The second cutting trajectory is located in the middle of the cutting path.

15. A semiconductor unit, characterized in that, include: The chip obtained by the laser cutting method according to any one of claims 12 to 14.

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