Three-dimensional memory, memory systems, and methods of manufacturing three-dimensional memory

Abstract

The embodiment of the present application provides a semiconductor layer; a stack structure located on one side of the semiconductor layer; a plurality of channel structures penetrating through the stack structure and connected with the semiconductor layer; a metal layer located on the side of the semiconductor layer away from the stack structure; a source line located on the side of the metal layer away from the stack structure; and a source contact connected between the metal layer and the source line.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a three-dimensional memory, a memory system, and a method for manufacturing the three-dimensional memory. Background Technology

[0002] As the feature size of memory cells approaches the lower limit of the process, planar processes and manufacturing technologies become challenging and costly, resulting in the storage density of planar memories approaching the upper limit.

[0003] To overcome the limitations of planar memory, the industry has developed memory with three-dimensional structures (e.g., 3D NAND memory), which increases storage density by arranging memory cells in three dimensions. Currently, optimizing the process and performance of three-dimensional memory is one of the problems that needs to be solved. Summary of the Invention

[0004] This application provides a three-dimensional memory, a memory system, and a method for manufacturing a three-dimensional memory that can at least partially solve the above-mentioned problems in related technologies or other problems in the art.

[0005] Some embodiments of this application provide a three-dimensional memory. The three-dimensional memory includes: a stacked structure located on one side of a semiconductor layer; a plurality of channel structures penetrating the stacked structure and connected to the semiconductor layer; a metal layer located on the side of the semiconductor layer away from the stacked structure; a source line located on the side of the metal layer away from the stacked structure; and a source contact connected between the metal layer and the source line.

[0006] In some implementations, the metal layer is in contact with the semiconductor layer.

[0007] In some embodiments, the three-dimensional memory further includes a metal silicide layer located between the metal layer and the semiconductor layer, and in contact with both the metal layer and the semiconductor layer.

[0008] In some embodiments, the three-dimensional memory includes an array region, a connection region, and a peripheral region, with a semiconductor layer and a metal layer located in the array region; the three-dimensional memory also includes an insulating layer, which is located on the same side of the stacked structure as the semiconductor layer, contacts the stacked structure in the connection region, and extends to the peripheral region.

[0009] In some embodiments, the three-dimensional memory further includes: a peripheral circuit structure connected to the side of the plurality of channel structures away from the semiconductor layer; and a first through contact that penetrates the insulating layer in the peripheral region and extends along the stacking direction of the stacked structure, a first end of the first through contact being connected to the source line, and a second end of the first through contact being connected to the peripheral circuit structure.

[0010] In some implementations, the three-dimensional memory also includes power lines, which are on the same layer as the source lines.

[0011] In some embodiments, the 3D memory further includes: a pad, which is on the same layer as and connected to the power line; and a second through contact, which penetrates the insulating layer in the peripheral region and extends along the stacking direction, with a first end of the second through contact connected to the power line and a second end of the second through contact connected to the peripheral circuit structure.

[0012] In some implementations, the channel structure includes a functional layer and a channel layer from the outside in, with the channel layer in contact with the semiconductor layer.

[0013] Other embodiments of this application provide a memory system. The memory system includes: at least one three-dimensional memory as mentioned in any of the embodiments above; and a controller coupled to the three-dimensional memory to control the storage of data in the three-dimensional memory.

[0014] This application also provides a method for manufacturing a three-dimensional memory. The method includes: providing a semiconductor structure, wherein the semiconductor structure includes a substrate, a stacked structure, and a plurality of initial channel structures, the stacked structure being located on one side of the substrate, and the plurality of initial channel structures penetrating the stacked structure and extending into the substrate; removing a portion of the substrate and the initial channel structures to transform the initial channel structures into channel structures; forming a semiconductor layer connected to the plurality of channel structures; forming a metal layer on the side of the semiconductor layer away from the stacked structure; and forming source contacts and source lines connected to the source contacts on the side of the metal layer away from the stacked structure.

[0015] In some embodiments, forming a metal layer on the side of the semiconductor layer away from the stacked structure includes forming a metal layer on the surface of the semiconductor layer.

[0016] In some embodiments, before forming a metal layer on the side of the semiconductor layer away from the stacked structure, the method further includes: forming a metal silicide layer on the surface of the semiconductor layer; wherein forming a metal layer on the side of the semiconductor layer away from the stacked structure includes: forming a metal layer on the surface of the metal silicide layer.

[0017] In some embodiments, the semiconductor structure includes an array region, a connection region, and a peripheral region, wherein a semiconductor layer and a metal layer are formed in the array region, the connection region, and the peripheral region. After forming a metal layer on the side of the semiconductor layer away from the stacked structure, the method further includes: removing portions of the semiconductor layer and the metal layer located in the connection region and the peripheral region to form a cavity; and forming an insulating layer within the cavity.

[0018] In some embodiments, the semiconductor structure further includes a peripheral circuit structure and a first through-port, the peripheral circuit structure being connected to the side of the plurality of channel structures away from the substrate, the first through-port extending in the peripheral region along the stacking direction of the stacked structure and connected to the peripheral circuit structure, wherein the method further includes: forming a first contact portion that penetrates the insulating layer and is connected to the first through-port; wherein forming a source contact and a source line connected to the source contact on the side of the metal layer away from the stacked structure includes: forming a source line connected to the first contact portion and the source contact.

[0019] In some embodiments, the semiconductor structure further includes a second through-hole extending in the peripheral region along the stacking direction and connected to the peripheral circuit structure. The method further includes: forming a second contact portion that penetrates the insulating layer and is connected to the second through-hole; and forming a pad and a power line connected to the second contact portion, wherein the power line and the pad are connected.

[0020] In some embodiments, the initial channel structure includes a functional layer and a channel layer extending from the outside in into the substrate. Removing a portion of the substrate and the channel structure to transform the initial channel structure into a channel structure includes: removing a portion of the functional layer extending into the substrate and using the remaining portion of the initial channel structure as the channel structure.

[0021] In some embodiments, forming a semiconductor layer connected to a plurality of channel structures includes forming a semiconductor layer that contacts a channel layer in a plurality of channel structures.

[0022] According to at least one embodiment of this application, the three-dimensional memory, memory system and manufacturing method of the three-dimensional memory provided in this application can reduce the number of source contacts by forming a metal layer on the side of the semiconductor layer away from the stacked structure and connecting the source contacts between the metal layer and the source lines, thereby freeing up the occupied area of ​​the source lines and facilitating the optimization of the layout of the metal interconnects. Attached Figure Description

[0023] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0024] Figure 1 This is a cross-sectional schematic diagram of a three-dimensional memory according to an exemplary embodiment of this application;

[0025] Figure 2 This is a schematic flowchart of a method for manufacturing a three-dimensional memory according to an exemplary embodiment of this application;

[0026] Figures 3A to 3G This is a cross-sectional schematic diagram of the manufacturing process of a three-dimensional memory according to an exemplary embodiment of this application;

[0027] Figure 4 This is a block diagram of a system with a memory system according to an exemplary embodiment of this application; and

[0028] Figure 5A and Figure 5B This is a schematic diagram of a memory system according to an exemplary embodiment of this application. Detailed Implementation

[0029] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0030] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first through contact discussed herein may also be referred to as the second through contact, and vice versa.

[0031] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0032] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0033] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0034] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0035] Furthermore, in this application, the use of "connection" or "linkage" may indicate direct or indirect contact between corresponding components, unless otherwise expressly defined or inferred from the context. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0036] It should be noted that, in the following figures, the x, y, and z directions illustrate the spatial relationships of the components in the three-dimensional memory. For example, the z direction is the stacking direction of the stacked structure, and the x and y directions are two directions perpendicular to each other on a plane perpendicular to the stacking direction. The same concepts will be used throughout this application to describe the spatial relationships of the components in the three-dimensional memory.

[0037] In the fabrication of three-dimensional memory (e.g., 3D NAND memory), the common source of the memory cell array is brought out from the back side to reduce the process challenges brought about by the increase in the number of stacked structures. However, this common source bringing-out method increases the difficulty of metal interconnect layout.

[0038] Figure 1 This is a cross-sectional schematic diagram of a three-dimensional memory according to an embodiment of this application. For example, the three-dimensional memory may be a 3D NAND memory. Figure 1As shown, in some embodiments, the three-dimensional memory 100 may include an array region 101, a connection region 102, and peripheral regions 103-1 and 103-2. A stacked structure 121 is located on one side of the semiconductor layer 111. The stacked structure 121 is located between the array region 101 and the connection region 102. The stacked structure 121 may include dielectric layers 122 and gate layers 123 alternately stacked in the z-direction. The more stacked layers of dielectric layers 122 and gate layers 123, the higher the integration of the memory cells, i.e., the greater the unit storage density. The material of the dielectric layer 122 may include silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material. The material of the gate layer 123 may include tungsten, cobalt, copper, aluminum, polysilicon, silicide, or any other suitable conductive material. For example, the gate layer 123 may include a conductive layer 125 and an adhesive layer 124 and a gate barrier layer (not shown) sequentially surrounding the conductive layer. For example, the gate layer 123 may extend laterally in a plane perpendicular to the z-direction as a word line of the three-dimensional memory 100 and terminate at the stepped structure of the stacked structure 121 located in the connection region 102.

[0039] In some embodiments, the stacked structure 121 may also extend to a portion of the peripheral region (e.g., peripheral region 103-1). In some embodiments, the insulating cover layer 145 may be located in another portion of the peripheral region (e.g., peripheral region 103-2) and extend to cover the stepped structure of the stacked structure 121 located in the connection region 102.

[0040] Multiple channel structures 131 penetrate the stacked structure 121 in the array region 101. In some embodiments, the channel structure 131 may include a functional layer 132 and a channel layer 133 arranged sequentially from the outside to the inside. For example, the functional layer 132 may be a generally open-ended tubular structure that penetrates the stacked structure 121 and extends into the semiconductor layer 111. For example, the channel layer 133 may be a generally closed-ended tubular structure that penetrates the stacked structure 121 and extends into the semiconductor layer 111. The extension distance of the channel layer 133 in the semiconductor layer 111 is greater than the extension distance of the functional layer 132 in the semiconductor layer 111. In other words, the channel layer 133 protrudes from the end face of the functional layer 132 away from the stacked structure 121. Optionally, the interior of the channel layer 133 may be at least partially filled with an insulating material. In some embodiments, the functional layer 132 may include a barrier layer, a charge trapping layer, and a tunneling layer arranged sequentially from the outside to the inside. For example, the materials of the barrier layer, charge trapping layer, and tunneling layer may sequentially include silicon oxide, silicon nitride, and silicon oxide. The material of the channel layer 133 may include silicon (e.g., amorphous silicon, polycrystalline silicon, or monocrystalline silicon) or any other suitable semiconductor material.

[0041] In some embodiments, a portion of the channel structure 131 surrounded by a gate layer 123, and a portion of the gate layer 123, constitute a memory cell. Multiple memory cells are arranged in series along the extension direction of the channel structure 131 (e.g., the z-direction) to form a memory string and share the channel layer 133. The remaining portion of the gate layer 123 can serve as a word line connecting multiple memory cells of the same height in different memory strings. For example, by applying a voltage to the gate layer 123, the memory cell can cause charge in the channel layer 133 to enter the charge trapping layer, or cause charge in the charge trapping layer to retreat back into the channel layer 133, thereby placing the memory cell in a programmed state or an erased state (unprogrammed state).

[0042] In some embodiments, dummy channel structures 134 may penetrate the stacked structure 121 through the array region 101 and extend into the semiconductor layer 111. The internal structure of the dummy channel structures 134 is similar to that of the channel structure 131, and will not be described further herein. Optionally, some dummy structures (not shown) may also penetrate the stacked structure 121 through the connection region 102 and extend from the side of the stacked structure 121 closest to the semiconductor layer 111. For example, the dummy channel structures 134 may be used to provide mechanical support and / or load balancing.

[0043] In some embodiments, the gate isolation structure 181 may extend through the stacked structure 121 and into the semiconductor layer 111. For example, the gate isolation structure 181 may extend in the x-direction. For example, the gate isolation structure 181 may serve as an insulating boundary for a memory block. In some examples, the gate isolation structure 181 may include a dielectric material layer 182 and a polysilicon layer 183 disposed sequentially from the outside in. In other examples, the gate isolation structure 181 may be made of at least one dielectric material (not shown).

[0044] In some embodiments, the semiconductor layer 111 contacts the channel layer 133 of the channel structure 131, thereby connecting the semiconductor layer 111 to the plurality of channel structures 131. In some embodiments, the surface 112 of the semiconductor layer 111 near the stack structure 121 is substantially flush, and the surface of the semiconductor layer 111 away from the stack structure 113 is irregularly shaped. For example, the surface of the semiconductor layer 111 away from the stack structure 113 is raised at the locations of the channel structures 131 and / or dummy channel structures 134, and recessed at the locations between adjacent channel structures 131 or between a channel structure 131 and a dummy channel structure 134. In other embodiments, the surface of the semiconductor layer 111 away from the stack structure 121 is substantially flush (not shown), and the specific shape of the surface of the semiconductor layer 111 away from the stack structure 121 is not specifically limited in this application. The material of the semiconductor layer 111 may include silicon (e.g., amorphous silicon, polycrystalline silicon, or polysilicon) or any other suitable semiconductor material. For example, semiconductor layer 111 may be doped with P-type or N-type dopants.

[0045] In some embodiments, the semiconductor layer 111 is in contact with the channel layer 133 of each of a plurality of channel structures 131 (e.g., a plurality of channel structures 131 located within the same memory block). For example, the semiconductor layer 111 may serve as the common source of a memory cell array within the same memory block.

[0046] In some embodiments, a metal silicide layer 156 and a metal layer 141 are sequentially located on the surface of the semiconductor layer 111 away from the stacked structure 121. In other words, the metal silicide layer 156 is located between the metal layer 141 and the semiconductor layer 111, and contacts both the metal layer 141 and the semiconductor layer 111. In a plane perpendicular to the z-direction, the projections of the metal silicide layer 156, the metal layer 141, and the semiconductor layer 111 overlap. Thus, the metal layer 141 and the semiconductor layer 111 can indirectly contact each other at various points in the overlapping projection area via the metal silicide layer 156. The material of the metal silicide layer 156 may include tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, or any combination thereof. The metal silicide layer 156 can be used to improve the electrical connection performance between the semiconductor layer 111 and the metal layer 141, for example, to reduce the contact resistance between the semiconductor layer 111 and the metal layer 141. The material of the metal layer 141 may include tungsten, cobalt, copper, aluminum, or any other suitable metallic material. In some other embodiments, the metal silicide layer 156 may be omitted (not shown), and the metal layer 141 and the semiconductor layer 111 are in direct contact at various points in the projected overlapping region.

[0047] In some embodiments, the semiconductor layer 111 and the metal layer 141 are located in the array region 101. Optionally, if the three-dimensional memory 100 includes a metal silicide layer 156, the metal silicide layer 156 located between the semiconductor layer 111 and the metal layer 141 is also located in the array region 101. The insulating layer 144 is located on the same side of the stacked structure 121 as the semiconductor layer 111 and the metal layer 141, and the insulating layer 144 is arranged side by side with the semiconductor layer 111 and the metal layer 141. For example, if the three-dimensional memory 100 does not include the metal silicide layer 156, the surface of the insulating layer 144 near the stacked structure 121 is substantially flush with the surface of the semiconductor layer 111 near the stacked structure 121, and the thickness of the insulating layer 144 is greater than or equal to the total thickness of the metal layer 141 and the semiconductor layer 111. For example, in the case where the 3D memory 100 includes a metal silicide layer 156, the surface of the insulating layer 144 near the stacked structure 121 is substantially flush with the surface of the semiconductor layer 111 near the stacked structure 121, and the thickness of the insulating layer 144 is greater than or equal to the total thickness of the metal layer 141, the metal silicide layer 156, and the semiconductor layer 111. Exemplarily, the insulating layer 144 also extends to cover the surface of the metal layer 141 away from the stacked structure 121, serving as an interlayer dielectric layer for the source contact 143. In this embodiment, by placing the semiconductor layer 111 and the metal layer 141 in the array region 101 and the insulating layer 144 in the connection region 102, electrical connection between the semiconductor layer 111 and the channel structure 131 located in the array region 101 can be ensured, while avoiding leakage between the dummy channel structure (not shown) located in the connection region 102 and the semiconductor layer 111, thus preventing issues affecting the electrical performance of the 3D memory 100. For example, the portion of the dummy channel structure located in the connection region 102 that extends from the side of the stacked structure 121 near the semiconductor layer 111 is surrounded by the insulating layer 144, thereby preventing leakage between the dummy channel structure and the semiconductor layer 111.

[0048] In some embodiments, the source contact 143 is located on the side of the metal layer 141 away from the stacked structure 121. For example, the source contact 143 penetrates the portion of the insulating layer 144 covering the metal layer 141 and is connected to the metal layer 141. The source line 142 is located on the side of the source contact 143 away from the stacked structure 121 and is connected to the source contact 143. In other words, the source contact 143 connects between the source line 142 and the metal layer 141. The materials of the source line 142 and the source contact 143 may include tungsten, cobalt, copper, aluminum, polysilicon, silicide, or any other suitable conductive material.

[0049] In some exemplary embodiments, when a metal layer is not included in the three-dimensional memory, a large number of source contacts need to be set above the semiconductor layer to ensure the electrical connection performance between the semiconductor layer and the source lines. This increases the area occupied by the source lines and affects the reasonable layout of the metal interconnects (e.g., source lines).

[0050] According to the three-dimensional memory of the present application, a metal layer is provided on the side of the semiconductor layer away from the stacked structure, and the source contacts are connected between the metal layer and the source lines. This can reduce the number of source contacts, thereby freeing up the occupied area of ​​the source lines and facilitating the optimization of the layout of the metal interconnects.

[0051] In some embodiments, the three-dimensional memory 100 may further include a peripheral circuit structure 151. For example, a stacked structure 121 and multiple channel structures 131 may be used to provide multiple memory cells for data storage. The peripheral circuit structure 151 may be used to provide peripheral circuitry to control the memory cells to perform various operations such as writing, reading, and erasing. The peripheral circuit structure 151 is connected to the side of the multiple channel structures 131 away from the semiconductor layer 111. For example, the peripheral circuit structure 151 is bonded to the channel structure 131, the first through contact 161, and the second through contact 164 in the z-direction via a bonding layer 152. For example, the bonding layer 152 may include multiple bonding contacts 153. The portion of the bonding layer 152 other than the bonding contacts 153 may be made of an insulating material. The material of the bonding contacts 153 may include, but is not limited to, tungsten, cobalt, copper, aluminum, titanium nitride, polysilicon, or any other suitable conductive material. It should be noted that the bonding referred to in this application can be any suitable bonding technique, such as hybrid bonding, anodic bonding, melt bonding, transfer bonding, adhesive bonding, eutectic bonding, etc.

[0052] In some embodiments, the peripheral circuit structure 151 may include a first substrate 154 and a plurality of peripheral devices 155. The plurality of peripheral devices 155 may be located on one side of the first substrate 154. The material of the first substrate 154 may include, but is not limited to, silicon (e.g., single-crystal silicon), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. The types of peripheral devices 155 may include metal-oxide-semiconductor field-effect transistors (MOSFETs), fin field-effect transistors (FINFETs), bipolar junction transistors (BJTs), diodes, resistors, inductors, capacitors, or any other suitable semiconductor devices. The plurality of peripheral devices 155 may constitute digital, analog, and / or mixed-signal functional circuits for implementing various functions. These functional circuits may, for example, control the memory cell array via word lines and / or bit lines to implement various operations such as write, read, and erase. Functional circuits may include, but are not limited to, page buffers / sensor amplifiers, decoders (e.g., row decoders or column decoders), word line drivers, input / output (I / O) circuits, charge pumps, voltage sources or voltage generators, current or voltage references, etc.

[0053] In some embodiments, the first through-contact 161 penetrates the insulating layer 144 in the peripheral region 103-1 and extends along the z-direction. A first end of the first through-contact 161 is connected to the source line 142, and a second end of the first through-contact 161 is connected to the peripheral circuit structure 151. Exemplarily, the first through-contact 161 may include a first contact portion 162 and a first through-contact portion 163. The first contact portion 162 penetrates the insulating layer 144, and its first end is connected to the source line 142. The first through-contact portion 163 penetrates the stacked structure 121, and its first end is connected to the second end of the first contact portion 162, and its second end is connected to the peripheral circuit structure 151, for example, through the bonding contact 153 of the bonding layer 152. Thus, the semiconductor layer 111, serving as a common source, can be electrically connected to the peripheral circuit structure 151 through the source line 142 and the first through-contact 161, thereby enabling signal transmission.

[0054] In some embodiments, the power line 146 is disposed on the same layer as the source line 142. For example, the source line 142 and the power line 146 are approximately at the same height in the z-direction, and their thicknesses are approximately the same. Optionally, the pad 147 is disposed on the same layer as the power line 146 and connected to the power line 146. For example, the power line 146 and the pad 147 are approximately at the same height in the z-direction, and their thicknesses are approximately the same. As another example, the pad 147 and the power line 146 are connected to each other (not shown) in a plane perpendicular to the z-direction.

[0055] In some embodiments, the second through contact 164 penetrates the insulating layer 144 in the peripheral region 103-2 and extends along the z-direction. In some examples, such as Figure 1 As shown, the first end of the second through contact 164 is connected to the pad 147, and the second end of the second through contact 164 is connected to the peripheral circuit structure 151. Exemplarily, the second through contact 164 may include a second contact portion 165 and a second through portion 166. The second contact portion 165 penetrates the insulating layer 144, and its first end is connected to the pad 147. The second through portion 166 penetrates the insulating cover layer 145, and its first end is connected to the second end of the second contact portion 165, and its second end is connected to the peripheral circuit structure 151, for example, through a bonding contact 153 of the bonding layer 152. In this example, the pad 147 can be used to receive external signals (e.g., power signals), such that the external signals can be electrically connected to the peripheral circuit structure 151 through the pad 147 and the second through contact 164, thereby enabling signal transmission. In other examples, the first end of the second through contact is connected to the power line 146, and the second end of the second through contact is connected to the peripheral circuit structure 151 (not shown). In this example, since pad 147 and power line 146 are connected to each other, external signals can be electrically connected to the peripheral circuit structure 151 through pad 147, power line 146 and the second through contact in this example, thereby realizing signal transmission.

[0056] In some exemplary embodiments, reference Figure 1 The pads 147 and power lines 146 can be disposed on the side of the peripheral circuit structure 151 away from the stacked structure 121. Compared with the above exemplary embodiments, the three-dimensional memory according to the embodiments of this application, since the area occupied by the source line 142 is freed up, the power line 146, pads 147 and source line 142 can be disposed on the same layer, thereby eliminating the manufacturing process of separately forming the pads 147 and power lines 146 on the side of the peripheral circuit structure 151 away from the stacked structure 121, which is beneficial to reduce manufacturing costs and reduce process steps.

[0057] This application provides a method for manufacturing a three-dimensional memory through some embodiments. Figure 2This is a schematic flowchart illustrating a method for manufacturing a three-dimensional memory according to an exemplary embodiment of this application. Figure 2 As shown, the semiconductor device manufacturing method 200 (hereinafter referred to as manufacturing method 200) includes steps S210 to S250.

[0058] S210 provides a semiconductor structure, wherein the semiconductor structure includes a substrate, a stacked structure and a plurality of initial channel structures, the stacked structure being located on one side of the substrate, and the plurality of initial channel structures penetrating the stacked structure and extending into the substrate.

[0059] S220, removes a portion of the substrate and the initial channel structure to transform the initial channel structure into a channel structure.

[0060] S230 forms a semiconductor layer connected to multiple channel structures.

[0061] S240, a metal layer is formed on the side of the semiconductor layer away from the stacked structure.

[0062] S250 forms a source contact and a source line connected to the source contact on the side of the metal layer away from the stacked structure.

[0063] According to the manufacturing method of the three-dimensional memory provided in the embodiments of this application, by forming a metal layer on the side of the semiconductor layer away from the stacked structure, and forming source contacts and source lines connected to the source contacts on the side of the metal layer away from the stacked structure, the number of source contacts can be reduced, thereby freeing up the occupied area of ​​the source lines and facilitating the optimization of the layout of metal interconnects.

[0064] Figures 3A to 3G This is a cross-sectional schematic diagram of the manufacturing process of a three-dimensional memory according to an exemplary embodiment of this application. The following is in conjunction with... Figures 3A to 3G as well as Figure 1 Steps S210 to S250 described above are illustrated by way of example.

[0065] S210, Provides semiconductor structure.

[0066] In step S210, as Figure 3A As shown, in semiconductor structure 100a, a stacked structure 121 may be formed on one side of substrate 148 (hereinafter referred to as second substrate 148). For example, a stop layer 149 may be present between the stacked structure 121 and the second substrate 148. The material of the second substrate 148 may include, but is not limited to, silicon (e.g., single-crystal silicon), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. For example, the second substrate 148 may be a composite substrate with a multilayer structure (not shown).

[0067] In some embodiments, the semiconductor structure 100a may include an array region 101, a connection region 102, and peripheral regions 103-1 and 103-2. In some embodiments, the stacked structure 121 may include a dielectric layer 122 and a gate layer 123 alternately stacked in the z-direction. For example, the gate layer 123 may be formed by a "gate displacement" process. The portion of the stacked structure 121 located in the connection region 102 may have a stepped structure. For example, the stepped structure may be formed by a "trimming-etching" process. In some embodiments, the stacked structure 121 also extends to a portion of the peripheral region (e.g., peripheral region 103-1). In some embodiments, an insulating capping layer 145 may be located in another portion of the peripheral region (e.g., peripheral region 103-2) and extend to cover the stepped structure located in the connection region 102.

[0068] In some embodiments, the first through-hole 163 may extend along the z-direction in the peripheral region 103-1. For example, the first through-hole 163 penetrates the stacked structure 121, and one end of it extends to the stop layer 149. The second through-hole 166 may extend along the z-direction in the peripheral region 103-2. For example, the second through-hole 166 penetrates the insulating cover layer 145, and one end of it extends to the stop layer 149.

[0069] In some embodiments, the semiconductor structure 100a may further include a peripheral circuit structure 151. As described in detail above, the peripheral circuit structure 151 may include a first substrate 154 and a plurality of peripheral devices 155. The plurality of peripheral devices 155 may be located on one side of the first substrate 154. The peripheral circuit structure 151 may be connected in the z-direction to the initial channel structure 131', the first through-hole 163, and the second through-hole 166 via a bonding layer 152.

[0070] The initial channel structure 131' extends through the stacked structure 121 and into the second substrate 148. The initial channel structure 131' may include a functional layer 132 and a channel layer 133 from the outside in, both extending into the second substrate 148. For example, the functional layer 132 in the initial channel structure 131' may be a generally closed-end tubular structure, with the closed end extending into the second substrate 148. The channel layer 133 in the initial channel structure 131' may be a generally closed-end tubular structure located inside the functional layer 132.

[0071] In some embodiments, where a stop layer 149 is present between the stacked structure 121 and the second substrate 148, the material of the stop layer 149 may be different from the material of the functional layer 132. For example, the material of the stop layer 149 may include polysilicon. The stop layer 149 may serve as an etching stop layer for removing a portion of the functional layer 132 of the initial channel structure 131' in a subsequent step S220.

[0072] S220, Remove a portion of the substrate and the initial channel structure to transform the initial channel structure into a channel structure. .

[0073] In step S220, as Figure 3A and Figure 3B As shown, in some embodiments, an etching process (e.g., dry etching or wet etching) can be used to remove the second substrate 148 to expose the initial channel structure 131'. Optionally, before removing the second substrate 148 using an etching process, a chemical mechanical polishing (CMP) process can be used to remove a portion of the second substrate 148 to improve removal efficiency. Next, as... Figure 3B and Figure 3C As shown, an etching process (e.g., dry etching or wet etching) can be used to remove the portion of the functional layer 132 in the initial channel structure 131' that extends into the second substrate 148, so as to expose the channel layer 133 in the initial channel structure 131'.

[0074] After the above process, the initial channel structure 131' can be transformed into channel structure 131. In other words, the remaining part of the initial channel structure 131' after removing part of the functional layer 132 can be used as channel structure 131.

[0075] S230, Forming a semiconductor layer connected to multiple channel structures .

[0076] In step S230, as Figure 3D As shown, in some embodiments, when a stop layer 149 is present on the surface of the stacked structure 121, a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof can be used to form an initial semiconductor layer 111' covering the stop layer 149 and the channel layer 133 of the channel structure 131. For example, the material of the initial semiconductor layer 111' can be the same as the material of the stop layer 149. Optionally, the initial semiconductor layer 111' can be doped with a P-type or N-type dopant. When the materials of the stop layer 149 and the initial semiconductor layer 111' are the same, they do not have a clear interface. The stop layer 149 and the initial semiconductor layer 111' can together constitute the semiconductor layer 111. Thus, the semiconductor layer 111 can contact a plurality of channel structures 131 (e.g., channel layers 133 of each channel structure 131), thereby connecting the semiconductor layer 111 to the plurality of channel structures 131.

[0077] In some embodiments, the initial semiconductor layer 111' may be conformally deposited on the surfaces of the stop layer 149 and the channel layer 133. When the initial semiconductor layer 111' is thin, the surface of the initial semiconductor layer 111' (or semiconductor layer 111) away from the stacked structure 121 is uneven. When the initial semiconductor layer 111' is thick, the surface of the initial semiconductor layer 111' (or semiconductor layer 111) away from the stacked structure 121 is substantially flush.

[0078] In some embodiments, where the surface of the stacked structure 121 does not have a stop layer 149, a semiconductor layer (not shown) that directly covers the channel layer 133 of the stacked structure 121 and the channel structure 131 can be formed using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Similarly, depending on the thickness of the semiconductor layer, the surface of the semiconductor layer away from the stacked structure 121 can be flush or have an uneven shape.

[0079] S240, A metal layer is formed on the side of the semiconductor layer away from the stacked structure. .

[0080] In step S240, as Figure 3E As shown, in some embodiments, a metal silicide layer 156 may be formed on the surface of the semiconductor layer 111 away from the stacked structure 121 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, or any other known process. The material of the metal silicide layer 156 may include tungsten silicide, titanium silicide, cobalt silicide, nickel silicide, platinum silicide, or any combination thereof. Next, a metal layer 141 may be formed on the surface of the metal silicide layer 156 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The material of the metal layer 141 may include tungsten, cobalt, copper, aluminum, or any other suitable metallic material. It should be noted that, depending on the thickness of the metal silicide layer 156 and the metal layer 141, the surfaces of the metal silicide layer 156 and the metal layer 141 away from the stacked structure 121 may be flush or have an uneven shape, and this application is not limited in this regard. The metal silicide layer 156 can reduce the contact resistance between the metal layer 141 and the semiconductor layer 111, further improving their conductivity.

[0081] In some embodiments, the step of forming the metal silicide layer 156 may be omitted. In other words, a metal layer 141 may be formed on the surface of the semiconductor layer 111 away from the stacked structure 121, so that the semiconductor layer 111 and the metal layer 141 are in direct contact.

[0082] In some implementations, such as Figure 3EAs shown, the semiconductor layer 111, metal silicide layer 156, and metal layer 141 formed by the above process can be formed in the array region 101, the connection region 102, and the peripheral regions 103-1 and 103-2. After forming the semiconductor layer 111, metal silicide layer 156, and metal layer 141, photolithography and etching (e.g., dry etching and / or wet etching) processes can be used to remove portions of the semiconductor layer 111, metal silicide layer 156, and metal layer 141 located in the connection region 102 and the peripheral regions 103-1 and 103-2 to form cavities (not shown). Next, as... Figure 3F As shown, an insulating layer 144 can be formed within the cavity using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. Optionally, during the formation of the insulating layer 144 within the cavity, the insulating layer 144 can be formed on the surface of the metal layer 141 away from the stacked structure 121. In this embodiment, both electrical connection between the semiconductor layer 111 and the channel structure 131 located in the array region 101 can be ensured, and leakage between the dummy channel structure (not shown) located in the connection region 102 and the semiconductor layer 111 can be avoided.

[0083] S250, A source contact and a source electrode connected to the source contact are formed on the side of the metal layer away from the stacked structure. Wire .

[0084] In step S250, as Figure 3G As shown, in some embodiments, photolithography and etching (e.g., dry etching and / or wet etching) processes can be used to form source contact holes (corresponding to the outer contour of source contacts 143) penetrating the insulating layer 144 on the surface portion of the metal layer 141. The source contact holes expose the metal layer 141. Optionally, during the formation of the source contact holes, a first contact hole (corresponding to the outer contour of the first contact portion 162) and a second contact hole (corresponding to the outer contour of the second contact portion 165) penetrating the insulating layer 144 can be formed in peripheral regions 103-1 and 103-2, respectively. The first contact hole is at least partially aligned with the first through portion 163; for example, the first contact hole at least partially exposes the first through portion 163. Similarly, the second contact hole is at least partially aligned with the second through portion 166; for example, the second contact hole at least partially exposes the second through portion 166.

[0085] Next, a conductive material can be filled into the source contact holes using a thin-film deposition process such as CVD, PVD, ALD, or any combination thereof to form source contacts 143. Thus, source contacts 143 are electrically connected to the metal layer 141. Optionally, the conductive material can also be filled into the first contact hole and the second contact hole to form a first contact portion 162 and a second contact portion 165. Thus, the first contact portion 162 and the first through portion 163 are electrically connected, forming a first through contact 161. The second contact portion 165 and the second through portion 166 are electrically connected, forming a second through contact 164.

[0086] In step S250, as Figure 1 As shown, in some embodiments, an insulating material layer is first deposited on the surfaces of the insulating layer 144, source contact 143, first contact portion 162, and second contact portion 165 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Then, the insulating material layer is patterned using photolithography and etching processes (e.g., dry etching and / or wet etching), and conductive material is filled into the patterned insulating material layer to form, for example, source lines 142, power lines 146, and pads 147.

[0087] In some embodiments, the source line 142, power line 146, and pad 147 may have a preset pattern on a plane perpendicular to the z-direction. For example, the source line 142 and power line 146 may be referred to as metal interconnects. In some embodiments, the source line 142 can be connected to the source contact 143 and the first through contact 161 (e.g., the first contact portion 162) respectively by patterning the formation of the source line 142. For example, on a projection plane perpendicular to the z-direction, the projections of the source contact 143 and the first through contact 161 are located within the projection of the source line 142. As mentioned above, one end of the first through contact 161 (e.g., the first through portion 163) is connected to the peripheral circuit structure 151, and signal transmission between the semiconductor layer 111 and the peripheral circuit structure 151 is achieved through the first through contact 161, the source line 142, and the metal layer 141.

[0088] In some embodiments, the power line 146 and the pad 147 can be connected to each other by patterning the power line 146 and the pad 147, and the power line 146 can be connected to some second through contacts (not shown) by patterning the power line 146. For example, on a projection plane perpendicular to the z-direction, the projections of these second through contacts are located within the projection of the power line 146. External signals are transmitted to the peripheral circuit structure 151 through the pad 147, the power line 146, and the second through contacts. Alternatively, the pad 147 can be directly connected to some second through contacts 164 (e.g., second contact portions 165) by patterning the pad 147. For example, on a projection plane perpendicular to the z-direction, the projections of these second through contacts 164 are located within the projection of the pad 147. External signals are transmitted to the peripheral circuit structure 151 through the pad 147 and these second through contacts 164.

[0089] In some embodiments, a passivation layer 171 covering the source line 142 and power line 146 and exposing the pad 147 may be formed using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The material of the passivation layer 171 may include silicon nitride or any other suitable material.

[0090] According to the manufacturing method of the three-dimensional memory provided in the embodiments of this application, by forming a metal layer on the side of the semiconductor layer away from the stacked structure, and forming source contacts and source lines connected to the source contacts on the side of the metal layer away from the stacked structure, the number of source contacts can be reduced, thereby freeing up the occupied area of ​​the source lines and facilitating the optimization of the layout of metal interconnects.

[0091] Some embodiments of this application also provide a memory system. Figure 4 This is a block diagram of a system with a memory system according to an exemplary embodiment of this application.

[0092] like Figure 4 As shown, system 11 can be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a memory system 12 located therein). Figure 4 As shown, system 11 may include a host 18 and a memory system 12, the memory system 12 having one or more three-dimensional memories 14 and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to and from the three-dimensional memories 14.

[0093] The three-dimensional memory 14 can be implemented as the three-dimensional memory described in any embodiment of this application, for example, Figure 1The illustrated three-dimensional memory 100. According to some embodiments, a controller 16 is coupled to the three-dimensional memory 14 and a host 18, and is configured to control the three-dimensional memory 14. The controller 16 can manage data stored in the three-dimensional memory 14 and communicate with the host 18. In some embodiments, the controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the controller 16 is designed to operate in a high duty cycle environment, such as a solid-state drive (SSD) or embedded multi-media card (eMMC) used as a data storage device in mobile devices such as smartphones, tablets, laptops, etc. The controller 16 can be configured to control the operation of the three-dimensional memory 14, such as read, erase, and program operations. The controller 16 may also be configured to manage various functions related to data stored in or to be stored in the 3D memory 14, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the controller 16 is further configured to process error correction codes (ECCs) related to data read from or written to the 3D memory 14. The controller 16 may also perform any other appropriate functions, such as formatting the 3D memory 14. The controller 16 may communicate with external devices (e.g., host 18) according to a specific communication protocol.For example, the controller 16 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Internet Small Computer System Interface (SCSI), Enhanced Small Device Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0094] The controller 16 and one or more three-dimensional memories 14 can be integrated into various types of memory systems, for example, included in the same package (such as a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 12 can be implemented and packaged into different types of end electronic products. Figure 5A In one example shown, the controller 16 and a single three-dimensional memory 14 may be integrated into the memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 22 may further include a connection between the memory card 22 and a host (e.g., Figure 4 The host 18) is coupled to the memory card connector 24. In such a way... Figure 5B In another example shown, the controller 16 and multiple 3D memories 14 may be integrated into the SSD 26. The SSD 26 may further include a connection between the SSD 26 and a host (e.g., Figure 4 The SSD connector 28 is coupled to the host 18. In some embodiments, the storage capacity and / or operating speed of the SSD 26 is higher than that of the memory card 22.

[0095] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A three-dimensional memory, characterized in that, include: Semiconductor layer; A stacked structure is located on one side of the semiconductor layer; Multiple channel structures extend through the stacked structure and are connected to the semiconductor layer; A metal layer is located on the side of the semiconductor layer away from the stacked structure; The source line is located on the side of the metal layer away from the stacked structure; as well as The source contact is connected between the metal layer and the source line.

2. The three-dimensional memory according to claim 1, wherein, The metal layer is in contact with the semiconductor layer.

3. The three-dimensional memory according to claim 1, wherein, It also includes a metal silicide layer located between the metal layer and the semiconductor layer, and in contact with both the metal layer and the semiconductor layer.

4. The three-dimensional memory according to any one of claims 1 to 3, wherein, The three-dimensional memory includes an array region, a connection region, and a peripheral region, with the semiconductor layer and the metal layer located in the array region; The three-dimensional memory also includes an insulating layer, which is located on the same side of the stacked structure as the semiconductor layer, contacts the stacked structure in the connection area and extends to the peripheral area.

5. The three-dimensional memory according to claim 4, wherein, Also includes: The peripheral circuit structure is connected to the side of the plurality of channel structures away from the semiconductor layer; as well as A first through-contact penetrates the insulating layer in the peripheral region and extends along the stacking direction of the stacked structure. A first end of the first through-contact is connected to the source line, and a second end of the first through-contact is connected to the peripheral circuit structure.

6. The three-dimensional memory according to claim 5, wherein, It also includes a power line, which is on the same layer as the source line.

7. The three-dimensional memory according to claim 6, wherein, Also includes: The pads are on the same layer as the power lines and are connected to the power lines. as well as The second through contact penetrates the insulating layer in the peripheral area and extends along the stacking direction. The first end of the second through contact is connected to the power line, and the second end of the second through contact is connected to the peripheral circuit structure.

8. The three-dimensional memory according to claim 1, wherein, The channel structure includes a functional layer and a channel layer from the outside to the inside, and the channel layer is in contact with the semiconductor layer.

9. A memory system, characterized in that, include: At least one three-dimensional memory as described in any one of claims 1 to 8; as well as A controller is coupled to the three-dimensional memory to control the storage of data in the three-dimensional memory.

10. A method for manufacturing a three-dimensional memory, characterized in that, include: A semiconductor structure is provided, wherein the semiconductor structure includes a substrate, a stacked structure, and a plurality of initial channel structures, the stacked structure being located on one side of the substrate, and the plurality of initial channel structures penetrating the stacked structure and extending into the substrate; Remove the substrate and a portion of the initial channel structure to transform the initial channel structure into a channel structure; A semiconductor layer is formed that is connected to the plurality of said channel structures; A metal layer is formed on the side of the semiconductor layer away from the stacked structure; and A source contact and a source line connected to the source contact are formed on the side of the metal layer away from the stacked structure.

11. The manufacturing method according to claim 10, wherein, Forming a metal layer on the side of the semiconductor layer away from the stacked structure includes: The metal layer is formed on the surface of the semiconductor layer.

12. The manufacturing method according to claim 10, wherein, Before forming a metal layer on the side of the semiconductor layer away from the stacked structure, the method further includes: A metal silicide layer is formed on the surface of the semiconductor layer; The formation of a metal layer on the side of the semiconductor layer away from the stacked structure includes: The metal layer is formed on the surface of the metal silicide layer.

13. The manufacturing method according to claim 10, wherein, The semiconductor structure includes an array region, a connection region, and a peripheral region. The semiconductor layer and the metal layer are formed in the array region, the connection region, and the peripheral region. After forming the metal layer on the side of the semiconductor layer away from the stacked structure, the method further includes: Removing portions of the semiconductor layer and the metal layer located in the connection region and the peripheral region to form a cavity; and An insulating layer is formed inside the cavity.

14. The manufacturing method according to claim 13, wherein, The semiconductor structure further includes a peripheral circuit structure and a first through-portion. The peripheral circuit structure is connected to the side of the plurality of channel structures away from the substrate. The first through-portion extends in the peripheral region along the stacking direction of the stacked structure and is connected to the peripheral circuit structure. The method further includes: A first contact portion is formed that penetrates the insulating layer and is connected to the first penetration portion; The formation of a source contact and a source line connected to the source contact on the side of the metal layer away from the stacked structure includes: The source line is formed to connect the first contact portion and the source contact.

15. The manufacturing method according to claim 14, wherein, The semiconductor structure further includes a second through-portion extending along the stacking direction in the peripheral region and connected to the peripheral circuit structure, wherein the method further includes: A second contact portion is formed that penetrates the insulating layer and is connected to the second through portion; and A pad is formed and a power line is connected to the second contact portion, wherein the power line and the pad are connected.

16. The manufacturing method according to claim 10, wherein, The initial channel structure includes a functional layer and a channel layer extending from the outside in, the functional layer and the channel layer extending into the substrate, wherein removing a portion of the substrate and the channel structure to transform the initial channel structure into a channel structure includes: Remove the portion of the functional layer that extends into the substrate, and use the remaining portion of the initial channel structure as the channel structure.

17. The manufacturing method according to claim 16, wherein, Forming a semiconductor layer connected to the plurality of said channel structures includes: The semiconductor layer that forms a contact with the channel layer in the plurality of said channel structures.

Images