Semiconductor structure and forming method thereof

Abstract

Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary method includes depositing a dummy gate material layer over a first fin-shaped active region, patterning the dummy gate material layer to form a dummy gate electrode, where the dummy gate electrode has a footing feature at an interface between the first fin-shaped active region and the dummy gate electrode, the footing feature and sidewall portions of the dummy gate electrode are oxidized to form a dielectric gate spacer, and a remaining portion of the dummy gate electrode is replaced with a gate structure.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor structures and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. During the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs. This scaling down has also increased the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are needed to achieve these advances.

[0003] Three-dimensional field effect transistors, such as fin FETs (FinFETs) and gate-all-around (GAA) FETs (GAA-FETs), have been integrated into various memory and core devices to reduce the IC chip footprint while maintaining reasonable processing margins. Although methods of forming these FETs are generally adequate, they are not completely satisfactory in all respects. For example, reducing parasitic capacitance between the gate structure and adjacent source / drain contacts formed above the source / drain components remains a challenge. Therefore, for at least this reason, improvements in methods of manufacturing FinFETs, GAA-FETs, and the like are desirable. Summary of the invention

[0004] An embodiment of the present disclosure provides a method for forming a semiconductor structure, comprising: receiving a workpiece, the workpiece including a device region, the device region having a fin-shaped active region protruding from a substrate and extending along a first direction; forming a gate electrode intersecting the fin-shaped active region, wherein, in a top view, the gate electrode includes a main portion and an auxiliary portion, the main portion extending along a second direction perpendicular to the first direction, and the auxiliary portion is located in the device region and extends laterally from the main portion; performing processing to convert the auxiliary portion and the side of the main portion of the gate electrode into a first dielectric spacer; forming a source / drain component adjacent to the first dielectric spacer in the device region; selectively removing the remaining portion of the main portion of the gate electrode to form a gate trench; and forming a gate structure in the gate trench.

[0005] Another embodiment of the present disclosure provides a method for forming a semiconductor structure, comprising: depositing a dummy gate material layer above a first fin-shaped active region; patterning the dummy gate material layer to form a dummy gate electrode, wherein the dummy gate electrode has a base component at an interface between the first fin-shaped active region and the dummy gate electrode; oxidizing the base component and a sidewall portion of the dummy gate electrode to form a dielectric gate spacer; and replacing a remaining portion of the dummy gate electrode with a gate structure.

[0006] Yet another embodiment of the present disclosure provides a semiconductor structure, comprising: a source / drain component coupled to a channel region of a fin; a gate structure located above a substrate and comprising a first portion directly disposed above the channel region and a second portion adjacent to the first portion; a first gate spacer comprising a first portion extending along a sidewall surface of the first portion of the gate structure and a second portion extending along a sidewall surface of the second portion of the gate structure, wherein, in a cross-sectional view cut through the second portion of the gate structure but not through the channel region, the second portion of the first gate spacer comprises an uneven thickness. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 A flowchart is shown of an exemplary method for forming a semiconductor structure according to various embodiments of the present disclosure.

[0009] Figure 2A , Figure 3A , Figure 4A , Figure 5A , Fig. 6A , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Fig.11A , Fig. 12A , Fig.13A , Fig.14A , Fig.15A , Fig.16A and Fig.17A ( FIG. 2A to FIG. 17A ) depicts various aspects of the present disclosure Figure 1 Partial top view of a workpiece during various manufacturing stages of the method.

[0010] Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Fig. 9B , Fig. 13B , Fig. 14B , Fig. 14B '、 Fig. 15B , Fig. 15B '、 Fig. 16B and Fig. 17B Describes various aspects of the present disclosure Figure 1 During the various manufacturing stages of the method of Figure 2A A partial cross-sectional view of the workpiece taken as shown).

[0011] Figure 2C , Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Fig. 9C , Fig. 13C , Fig. 14C , Fig. 14C '、 Fig. 15C , Fig. 15C '、 Fig. 16C and Fig. 17C Describes various aspects of the present disclosure Figure 1 During the various manufacturing stages of the method, along line CC (eg Figure 2A A partial cross-sectional view of the workpiece taken as shown).

[0012] Figure 2D and Figure 3D Describes various aspects of the present disclosure Figure 1 During the various manufacturing stages of the method along line DD (eg Figure 2A A partial cross-sectional view of the workpiece taken as shown).

[0013] Fig.10E , Fig.11E and Fig.12E Describes various aspects of the present disclosure Figure 1 During the various manufacturing stages of the method along line EE (eg Figure 4A A partial cross-sectional view of the workpiece taken as shown).

[0014] Figure 4F , Fig. 5F , Fig. 6F , Figure 7F , Figure 8F , Fig.9F , Fig.10F , Fig.11F and Fig.12F Describes various aspects of the present disclosure Figure 1 During the various manufacturing stages of the method of Figure 4A A partial cross-sectional view of the workpiece taken as shown).

[0015] Figure 4 The present invention shows various aspects of the present disclosure. Figure 4A A partial perspective view of the workpiece shown in FIG.

[0016] Fig.18 A flow chart of a first alternative method for forming a semiconductor structure according to various embodiments of the present disclosure is shown.

[0017] Fig.19A Describes various aspects of the present disclosure Fig.18 Partial top view of a workpiece during various manufacturing stages of the method.

[0018] Fig.19B , Fig. 20B , Fig.21B , Fig. 22B , Fig. 23B and Fig. 24B Describes various aspects of the present disclosure Fig.18 During the various manufacturing stages of the method of Fig.19A A partial cross-sectional view of the workpiece taken as shown).

[0019] Fig.19C , Fig. 20C , Fig. 21C , Fig. 22C , Fig.23C and Fig.24C Describes various aspects of the present disclosure Fig.18 During the various manufacturing stages of the method, along line CC (eg Fig.19A A partial cross-sectional view of the workpiece taken as shown).

[0020] Fig.19E , Fig.20E and Fig.22E Describes various aspects of the present disclosure Fig.18 During the various manufacturing stages of the method along line EE (eg Fig.19A A partial cross-sectional view of the workpiece taken as shown).

[0021] Fig.19F , Fig.20F and Fig.22F Describes various aspects of the present disclosure Fig.18 During the various manufacturing stages of the method of Fig.19A A partial cross-sectional view of the workpiece taken as shown).

[0022] Figure 19G, Figure 20G and Figure 22G Describes various aspects of the present disclosure Fig.18 During the various manufacturing stages of the method along line GG (such as Fig.19A A partial cross-sectional view of the workpiece taken as shown).

[0023] Fig.25 A flow chart of a second alternative method for forming a semiconductor structure according to various embodiments of the present disclosure is shown.

[0024] Fig.26A , Fig.27A , Fig.28A , Fig.29A , Fig. 30A , Fig.31A , Fig.32A , Fig.33A and Fig.34A Describes various aspects of the present disclosure Fig.25 Partial top view of a workpiece during various manufacturing stages of the method.

[0025] Fig.26B , Fig.27B , Fig.28B , Fig.29B , Fig. 30B , Fig.31B , Fig.32B , Fig.33B and Fig.34B Describes various aspects of the present disclosure Fig.25 A partial cross-sectional view of a workpiece taken along line BB during various manufacturing stages in the method of FIG.

[0026] Fig.26F , Fig.27F , Fig.28F , Fig.29F , Fig.30F , Fig.31F , Fig.32F , Fig.33F and Fig.34F Describes various aspects of the present disclosure Fig.25 A partial cross-sectional view of a workpiece taken along line FF during various manufacturing stages in the method. DETAILED DESCRIPTION

[0027] The following disclosure provides many different embodiments or examples for realizing the different features of the present disclosure. The specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following present disclosure, the formation of a component on another component, connected to another component and / or coupled to another component can include an embodiment in which the component is formed as direct contact, and can also include an additional component that can be formed between the components so that the component can not directly contact the embodiment. In addition, spatial relative terms (e.g., "bottom", "upper", "horizontal", "vertical", "above", "above", "below", "below", "upward", "downward", "top", "bottom", etc. and their derivatives (e.g., "horizontally", "downwardly", "upwardly", etc.)) are used to facilitate the present disclosure to describe the relationship between a component and another component. Spatial relative terms are intended to cover the different orientations of the device including the component.

[0028] In addition, when "about," "approximately," or the like is used to describe a numerical value or a range of numerical values, the term is intended to include numerical values ​​within a reasonable range, taking into account variations inherent during manufacturing as understood by those of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing components having features associated with the numerical value, the numerical value or range of numerical values ​​includes a reasonable range of the described numerical value, such as within + / - 10% of the described numerical value. For example, a material layer having a thickness of "about 5 nm" may include a size range of 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with the deposited material layer is known to those of ordinary skill in the art to be + / - 15%. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0029] Multi-gate devices, such as fin field effect transistors (FinFETs) and gate-all-around (GAA) transistors, have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short channel effects (SCEs). FinFETs have an elevated channel wrapped by a gate on more than one side (e.g., the gate wraps around the top and sidewalls of a "fin" of semiconductor material extending from a substrate). GAA transistors have a gate structure that can extend partially or completely around the channel region to provide access to the channel region on two or more sides. The channel region of a GAA transistor can be formed by nanowires, nanosheets, or other nanostructures, and therefore, GAA transistors can also be referred to as nanowire transistors or nanosheet transistors. The three-dimensional structure of multi-gate devices allows them to be aggressively scaled while maintaining gate control and mitigating SCEs. As component sizes continue to decrease, replacing polysilicon gates with functional gate structures has led to improvements in device performance. Typically, after forming a gate structure in a three-dimensional field effect transistor (e.g., a fin field effect transistor or FinFET, a gate-all-around FET or GAA FET, etc.), a variety of methods may be implemented independently or in combination to further process the gate structure according to specific design requirements. In one example, the gate structure may be cut into two or more parts and then separated by a gate isolation structure in a process called cut metal gate (CMG).

[0030] As multi-gate device (e.g., FinFET, GAAFET) technology moves toward smaller component sizes, advanced techniques are needed to precisely control the profile and / or size of the gate structure and gate isolation structure to ensure and optimize device reliability. For example, a polysilicon gate (or a pseudo-gate electrode) may have a gate footing disposed along the bottom of the polysilicon gate. The presence of the gate footing may increase the difficulty of forming a satisfactory gate isolation structure without effectively cutting the pseudo-gate electrode into electrically and physically isolated parts. In addition, the scaling down process also results in a reduction in the distance between the pseudo-gate electrode (to be replaced by the gate structure) and the adjacent source / drain contact, and thus increases the parasitic capacitance. Therefore, improvements in methods for forming semiconductor structures having reduced parasitic capacitance and satisfactory gate isolation structures are desired.

[0031] The present disclosure provides a semiconductor structure and a method for forming a gate spacer and a gate isolation structure in the semiconductor structure. In an embodiment, after patterning a polysilicon layer to form a dummy gate electrode, an oxidation process is performed to convert the side and gate footing of the dummy gate electrode into a dielectric layer as a gate spacer. By replacing the gate footing with a dielectric material (e.g., silicon oxide) without performing additional lithography and / or etching processes, the combination of the dielectric material and the gate isolation structure will provide satisfactory isolation, and the distance between the rest of the dummy gate electrode (and therefore the gate structure) and the source / drain contact can be increased to help reduce parasitic capacitance.

[0032] Various aspects of the disclosure will now be described in more detail with reference to the accompanying drawings. Figure 1 1 is a flow chart showing a method 100 for forming a semiconductor structure including a gate isolation structure and a gate spacer. FIG. 2A to FIG. 17C Method 100 is described. Fig.18 is a flow chart showing a first optional method 100'. Figure 1 and FIG. 19A to FIG. 24C Method 100' is described. Fig.25 is a flow chart showing a second alternative method 100". Figure 1 and FIG. 26A to FIG. 34F Describe Method 100".

[0033] Method 100 / 100' / 100" is merely an example and is not intended to limit the present disclosure to the contents explicitly described therein. Additional steps may be provided before, during and / or after method 100 / 100' / 100", and some of the steps described may be replaced, eliminated or rearranged for additional embodiments of the method. For simplicity, not all steps are described in detail here. Because workpiece 200 will be manufactured into a semiconductor structure after the manufacturing process is completed, workpiece 200 may be referred to as semiconductor structure 200 as the context requires. For the avoidance of doubt, the X, Y and Z directions in the figures are perpendicular to each other and are used consistently throughout the present disclosure. In the present disclosure, unless otherwise specified, the same reference numerals represent the same components. For ease of description, the figure marked with letter A depicts a partial cross-sectional view of the workpiece taken along line AA, the figure marked with letter B or letter B' depicts a partial cross-sectional view of the workpiece taken along line BB, the figure marked with letter C or letter C' depicts a partial cross-sectional view of the workpiece taken along line CC, the figure marked with letter D depicts a partial cross-sectional view of the workpiece taken along line DD, the figure marked with letter E depicts a partial cross-sectional view of the workpiece taken along line EE, the figure marked with letter F depicts a partial cross-sectional view of the workpiece taken along line FF, and the figure marked with letter G depicts a partial cross-sectional view of the workpiece taken along line GG.

[0034] Reference now Figure 1and FIG. 2A to FIG. 2D , the method 100 includes block 102 , where a workpiece 200 is received. Figure 2A A partial top view of workpiece 200 is depicted. Figure 2B , Figure 2C , Figure 2D Depicted along the Figure 2A The workpiece 200 includes a device region (eg, device region 200A / 200B) for forming a semiconductor device and a connector region 200C adjacent to the device region. Figure 2A As shown, the connector region 200C includes a first region 200C1 close to the device region 200A, a second region 200C2 close to the device region 200B, and a third region 200C3 located between the first region 200C1 and the second region 200C2. The first region 200C1, the second region 200C2, and the third region 200C3 of the connector region 200C may be referred to as the connector region 200C1, the connector region 200C2, and the connector region 200C3, respectively. It should be understood that the workpiece 200 may include other suitable numbers of device regions and connector regions.

[0035] The workpiece 200 includes a substrate 202. The substrate 202 may include an element (single element) semiconductor, such as silicon (Si), germanium (Ge), and / or other suitable materials; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials; an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials. The substrate 202 may be a single layer material with a uniform composition. Alternatively, the substrate 202 may include a plurality of material layers with similar or different compositions suitable for IC device manufacturing. The substrate 202 may include various doped regions, which may be disposed in or on the semiconductor substrate 202. Depending on design requirements, the doped regions may be doped with n-type dopants (such as phosphorus or arsenic) and / or p-type dopants (such as boron or BF2). The doped regions may be formed directly on the semiconductor substrate 202 in a p-well structure, an n-well structure, a double-well structure, or a convex structure. The doped regions may be formed by implantation of dopant atoms, in-situ doping epitaxial growth, and / or other suitable techniques. These examples are for illustrative purposes only and are not intended to be limiting.

[0036] The workpiece 200 includes a fin-shaped active area (or fin) 204 formed in the device area 200A. The fin 204 protrudes from the substrate 202 and extends along the X direction. The fin 204 can be manufactured using a suitable process, including a photolithography and etching process. The photolithography process may include forming a photoresist layer (photoresist) on the substrate 202, exposing the photoresist to a pattern, performing a post-exposure baking process, and developing the photoresist to form a masking element (not shown) including the photoresist. The masking element is then used to etch a groove in the substrate 202, leaving the fin 204 protruding from the substrate 202. The etching process may include dry etching, wet etching, reactive ion etching (RIE), other suitable processes, or combinations thereof. Many other embodiments of the method for forming the fin 204 may be suitable. For example, the fin 204 may be patterned using a double patterning or multiple patterning process. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, allowing the creation of patterns having, for example, a pitch smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fins 204.

[0037] The workpiece 200 includes an isolation feature 208 (eg, Figure 2C to Figure 2D ). The isolation feature 208 may include silicon oxide (SiO and / or SiO2), borophosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), low-k (dielectric constant less than that of silicon oxide, which has a dielectric constant of about 3.9) dielectric materials, other suitable materials, or combinations thereof. Other isolation structures (such as field oxide, local oxidation of silicon (LOCOS), and / or other suitable structures) may also be implemented as the isolation feature 208. In some examples, the isolation feature 208 may include a multi-layer structure, for example, with one or more thermal oxide liner layers. In the present embodiment, forming the isolation feature 208 includes depositing a dielectric material over the substrate 202 to fill the trenches separating the fins 204, applying one or more chemical mechanical planarization (CMP) processes to planarize the workpiece 200, and then etching back portions of the dielectric material to form the isolation feature 108, such that a top surface of the isolation feature 208 is lower than a top surface 204t of the fin 204. The dielectric material may be deposited by any suitable method, such as CVD, flowable CVD (FCVD), spin-on-glass (SOG), other suitable methods, or combinations thereof.After depositing and planarizing the isolation material, a curing process may be applied.

[0038] Reference now Figure 1and FIG. 3A to FIG. 3D The method 100 includes block 104 in which a dummy dielectric layer 210 is formed over the workpiece 200 . Figure 3A is a partial top view of the workpiece 200 . Figure 3B , Figure 3C , Figure 3D Depicted along the Figure 3A A partial cross-sectional view of the workpiece 200 taken along lines BB, CC, and DD shown in FIG. The dummy dielectric layer 210 may be conformally deposited over the workpiece 200, including the top surface and sidewalls of the fin 204 and over the top surface of the isolation feature 208 and the substrate 202. For ease of describing a layer having a substantially uniform thickness over various regions, the term “conformal” may be used herein. In some embodiments, the dummy dielectric layer 210 may be deposited by any suitable method, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), other suitable methods, or combinations thereof, and may include an oxide material, such as silicon oxide, a low-k dielectric material, tetraethyl orthosilicate (TEOS), doped silicon oxide (e.g., BPSG, FSG, PSG, BSG, etc.), other suitable dielectric materials, or combinations thereof.

[0039] Still refer to Figure 1 and FIG. 3A to FIG. 3D , the method 100 includes a block 106, wherein a dummy electrode layer 212 is deposited over the dummy dielectric layer 210. The dummy electrode layer 212 may be deposited on the dummy dielectric layer 210 by any suitable method, such as CVD, ALD, PVD, other suitable methods, or combinations thereof. A planarization process (e.g., chemical mechanical polishing) may be performed to provide a flat top surface for the deposited dummy electrode layer 212. The dummy electrode layer 212 may be formed of any suitable material. In an embodiment, the dummy electrode layer 212 includes polysilicon. FIG. 3B to FIG. 3D As shown, the dummy electrode layer 212 includes a top portion 212 t formed above the top surface 204 t of the fin 204 and a bottom portion 212 b formed below the top surface 204 t of the fin 204 .

[0040] Reference now Figure 1 , FIG. 3A to FIG. 3D and Figure 4A , Figure 4B , Figure 4C , Figure 4F and Figure 4 , the method 100 includes block 108 , in which the dummy electrode layer 212 is patterned to form a dummy gate electrode. Figure 4A is a partial top view of the workpiece 200, Figure 4B , Figure 4C , Figure 4F Depicted along the Figure 4A The partial cross-sectional view of the workpiece 200 is taken along the lines BB, CC and FF shown in FIG. Figure 4 A partial perspective view of a device region 200A of a workpiece 200 is depicted. In an example process, reference FIG. 3B to FIG. 3D , a hard mask layer 214 is formed above the dummy electrode layer 212. The hard mask layer 214 may be a single-layer structure or a multi-layer structure, and may be formed by any suitable method, such as CVD, atomic layer deposition (ALD), other suitable methods, or a combination thereof. In the present embodiment, the hard mask layer 214 includes silicon nitride (SiN), carbon-containing silicon nitride (SiCN), carbon-containing silicon oxide (SiOC), oxygen-containing silicon nitride (SiON), Si, carbon and oxygen-doped silicon nitride (SiOCN), low-k dielectric material, other suitable materials, or a combination thereof. After the hard mask layer 214 is formed, the hard mask layer 214 is patterned using a photolithography process to form a patterned hard mask layer 214, which exposes portions of the dummy electrode layer 212 to be removed while covering other portions.

[0041] refer to Figure 4B , Figure 4C , Figure 4F and Figure 4 , and then the patterned hard mask layer 214 is applied as an etching mask in the etching process to pattern the dummy electrode layer 212. The etching process selectively etches the dummy electrode layer 212, while substantially not etching the patterned hard mask layer 214 and the dummy dielectric layer 210. The patterning of the dummy electrode layer 212 forms one or more dummy gate electrodes. For ease of description, the dummy gate electrode and the dummy electrode layer 212 use the same reference numerals. The dummy gate electrode 212 has a top 212t located above the top surface 204t of the fin 204 and a bottom 212b located below the top 212t. The number of dummy gate electrodes 212 shown in the figure is only an example and is not intended to be limiting.

[0042] The top portion 212t of the dummy gate electrode 212 has a gate length L g1 , gate length L g1 The distance (or length) that current (e.g., carriers, such as electrons or holes) travels between the source / drain regions of the fin 204 is defined. The dummy gate electrode 212 has a gate footing GF (also referred to as a gate skirt, gate ridge, or footing feature) disposed along a bottom 212 b of the dummy gate electrode 212, which results in the bottom 212 b of the dummy gate electrode 212 having a gate length L greater than a top 212 t of the dummy gate electrode 212. g1 Large gate length L g2 The gate foot GF has a tapered width that decreases along the Z direction, so that the gate length L g2The gate footing GF (or bottom gate profile) of the dummy gate electrode 212 may vary depending on the patterning environment (e.g., isolated pattern or dense pattern), the location of the dummy gate electrode 212 on the wafer (e.g., edge or center), and / or the proximity of the region of the dummy gate electrode 212 to the fin 204 (e.g., a gate region directly adjacent to the fin 204 or a gate region far from the fin 204). In some embodiments, as Figure 4A As shown, the gate footing GF only exists at the interface region between the fin 204 and the dummy gate electrode 212, such as at the corner between the fin 204 and the dummy gate electrode 212. In this depicted example, the gate footing GF appears in the device regions 200A and 200B, and also appears in the connector regions 200C1 and 200C2 adjacent to the device regions 200A, 200B. The portion of the dummy gate electrode 212 in the connector region 200C3 does not have the gate footing GF. That is, in the cross-sectional view cut through line EE, the profile of the dummy gate electrode 212 is similar to that of the dummy gate electrode 212. Figure 4C and, in a cross-sectional view cut through line FF, the outline of the dummy gate electrode 212 is similar to a rectangle and is similar to Figure 4C The profile of the dummy gate electrode 212 shown in FIG. 1 is different. It should be noted that Figure 4A and Figure 4 Some features are omitted (e.g., dummy dielectric layer 210, isolation features 208, patterned hard mask layer 214). Figure 4A In the illustrated embodiment, the dummy gate electrode 212 can be regarded as a uniform length L extending along the Y direction. g1 The main portion 212m and the auxiliary portion (ie, the gate foot GF) extending outwardly and laterally from the main portion 212m.

[0043] The gate footing GF presents a challenge to forming a gate isolation structure that is configured to provide isolation between different portions of a gate structure. For example, due to the presence of the gate footing GF, a gate isolation structure that is capable of cutting a portion of a gate structure in the connector region 200C3 may not be able to cut a portion of a gate structure in the connector region 200B1 / 200C2, resulting in isolation failure and electrical shorts. The presence of the gate footing GF also reduces the distance between the gate structure and the adjacent source / drain contacts, which adversely affects parasitic capacitance. The manufacturing techniques proposed in the present disclosure address these issues.

[0044] Reference now Figure 1 and FIG. 5A to FIG. 5C and Fig. 5F The method 100 includes block 110 , in which an oxidation process is performed to oxidize the side portions of the dummy gate electrode 212 and the footer feature GF to form a first gate spacer 216 . Figure 5Ais a partial top view of the workpiece 200, Figure 5B , Figure 5C and Fig. 5F Depicted along the Figure 5A The partial cross-sectional view of the workpiece 200 is taken along the lines BB, CC and FF shown in FIG. Figure 5A The cross-sectional view of the workpiece 200 taken along line EE shown in FIG. Figure 5C The cross-sectional views shown are substantially similar and are therefore omitted for simplicity.

[0045] When the patterned hard mask layer 214 is used to protect the top surface of the dummy gate electrode 212, an oxidation process is performed to oxidize the portion of the dummy gate electrode 212 that is not covered by the patterned hard mask layer 214 (including the sidewall and the gate foot GF). The dummy gate electrode 212 after the oxidation is performed may be referred to as a dummy gate electrode 212'. The dummy gate electrode 212' has a top portion 212t' located above the top surface 204t of the fin 204 and a bottom portion 212b' located below the top surface 204t of the fin 204. The top portion 212t' and the bottom portion 212b' of the dummy gate electrode 212' have the same length L along the X direction. g3 Due to the oxidation treatment, the length L g3 Less than length L g2 In an embodiment, the length L g3 With length L g1 The ratio is not less than 0.6.

[0046] The first gate spacer 216 extends along the sidewall surface of the dummy gate electrode 212' and has a top portion 216t located above the top surface 204t of the fin 204 and a bottom portion located below the top surface 204t of the fin 204. The top portion 216t has a uniform width W1, and a portion of the bottom portion 216b located in the connector region 200C3 has the same width W1 as the top portion 216t. Due to the oxidation of the gate footing GF, as shown in FIG. Figure 5A and Figure 5C As shown, the portion of the bottom 216b in the device region 200A / 200B and the connector region 200C1 / 200C2 has a tapered width W2 that changes (e.g., gradually increases) along the Z direction. In an embodiment, the width W2 is twice the width W1. Due to the formation of the first gate spacer 216, the dummy gate electrode 212' has a substantially uniform length L g3 , the length L g3 Less than length L g1 or L g2Therefore, the distance between the source / drain contacts and the gate structure that will replace the dummy gate electrode 212' is increased, resulting in a reduction in parasitic capacitance. In addition, since the oxidation process is performed to convert the footing feature GF of the dummy gate electrode 212 from polysilicon to a dielectric layer (i.e., the first gate spacer 216), the gate isolation structure will be able to provide satisfactory isolation between parts of the gate structure without increasing manufacturing complexity.

[0047] In an embodiment, the oxidation process includes thermal oxidation, chemical oxidation, other suitable methods, or combinations thereof. For embodiments where the dummy gate electrode 212 includes polysilicon and the oxidation process includes providing oxygen, the first gate spacer 216 includes silicon oxide, such as SiO and / or SiO2. The oxidation process may provide other gases, such as NH3, and the resulting first gate spacer 216 may include silicon oxynitride. In some embodiments, the first gate spacer 216 may also include silicon oxynitride, silicon carbonitride, other suitable materials. In an optional embodiment, the first gate spacer 216 is a multilayer structure, and the following will refer to 17A to 17C The details of this alternative embodiment are further described.

[0048] Reference now Figure 1 and FIG. 6A to FIG. 6C , Fig. 6F , 7A to 7C and Figure 7F The method 100 includes block 112 where a second gate spacer 218 ′ is adjacent to the first gate spacer 216 . Fig. 6A is a partial top view of the workpiece 200, Figure 6B , Figure 6C and Fig. 6F Depicted along the Fig. 6A The partial cross-sectional view of the workpiece 200 is taken along the lines BB, CC and FF shown in FIG. Fig. 6A The cross-sectional view of the workpiece 200 taken along line EE is shown in FIG. Figure 6C The cross-sectional views shown are substantially similar and are therefore omitted for simplicity. Fig. 7A is a partial top view of the workpiece 200, Figure 7B , Figure 7C and Figure 7F Depicted along the Fig. 7A The partial cross-sectional view of the workpiece 200 is taken along the lines BB, CC and FF shown in FIG. Fig. 7A The cross-sectional view of the workpiece 200 taken along line EE is shown in FIG. Figure 7C The cross-sectional views shown are substantially similar and are therefore omitted for simplicity.

[0049] In the example process, reference FIG. 6A to FIG. 6C and Fig. 6FIn the present embodiment, a dielectric layer 218 is deposited as a blanket layer over the workpiece 200 by a suitable method (such as CVD, ALD, PVD, other suitable methods, or combinations thereof). The dielectric layer 218 may include SiN, SiCN, SiOC, SiON, SiOCN, Al2O3, HfO2, low-k dielectric materials, other suitable materials, or combinations thereof. In the present embodiment, the dielectric layer 218 has a different composition than the first gate spacer 216. Subsequently, referring to 7A to 7C and Figure 7F , an etching process is performed to anisotropically remove portions of the dielectric layer 218 deposited over the top surfaces of the patterned hard mask layer 214, the isolation features 208, and the fins 204, leaving portions along the sidewalls of the patterned hard mask layer 214 and the first gate spacers 216 as the second gate spacers 218'. It should be noted that Fig. 7A The second gate spacer 218 ′ is omitted in the following top views.

[0050] Reference now Figure 1 and FIG. 8A to FIG. 8C and Figure 8F , the method 100 includes a block 114, in which source / drain features 220 are formed in the device regions 200A and 200B. The formation of the source / drain features 220 includes performing an etching process to form source / source recesses in the source / drain regions of the fins 204. The etching process also removes portions of the dummy dielectric layer 210 on the source / drain regions of the fins 204. Then, epitaxial source / drain features 220 are formed in the source / drain recesses by using an epitaxial process such as vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. Thus, the source / drain features 220 are coupled to the channel regions of the fins 204. The source / drain features 220 may be n-type source / drain features or p-type source / drain features, depending on the conductivity type of the transistor to be formed. Exemplary n-type source / drain features may include silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable materials, and may be doped in situ during the epitaxial process by introducing n-type dopants such as phosphorus, arsenic, or antimony, or ex situ using a junction implantation process. Exemplary p-type source / drain features may include germanium, gallium-doped silicon germanium, boron-doped silicon germanium, or other suitable materials, and may be doped in situ during the epitaxial process by introducing p-type dopants such as boron or gallium, or ex situ using a junction implantation process.

[0051] Reference now Figure 1 and 9A to 9C and Fig.9F, the method 100 includes a block 116, in which a dielectric structure 222 is formed over the workpiece 200. In an example process, the formation of the dielectric structure 222 includes forming a contact etch stop layer (CESL) over the workpiece 200 and forming an interlayer dielectric layer (ILD) over the CESL. The CESL may include silicon nitride, silicon oxynitride, and / or other known materials, and may be formed by an ALD, a plasma enhanced chemical vapor deposition (PECVD) process, and / or other suitable deposition or oxidation processes. After depositing the CESL, an ILD layer is deposited over the workpiece 200 by a PECVD process or other suitable deposition technique. The ILD layer may include materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), and / or other suitable dielectric materials. A planarization process may then be performed to remove excess material over the dummy gate electrode 212 ′ to expose a top surface of the dummy gate electrode 212 ′.

[0052] Reference now Figure 1 and Fig. 10A , Fig.10E , Fig.10F , Fig.11A , Fig.11E , Fig.11F , Fig. 12A , Fig.12E and Fig.12F The method 100 includes block 118 , in which a gate isolation structure is formed in the connector region 200C to cut the dummy gate electrode 212 ′ into a plurality of portions. Fig. 10A is a partial top view of the workpiece 200, Fig.10E and Fig.10F Depicted along the Fig. 10A 0 is a partial cross-sectional view of the workpiece 200 taken along lines EE and FF shown in FIG. Fig.11A is a partial top view of the workpiece 200, Fig.11E and Fig.11F Depicted along the Fig.11A 0 is a partial cross-sectional view of the workpiece 200 taken along lines EE and FF shown in FIG. Fig. 12A is a partial top view of the workpiece 200, Fig.12E and Fig.12F Depicted along the Fig. 12A 0 is a partial cross-sectional view of the workpiece 200 taken along lines EE and FF shown in FIG.

[0053] refer to Fig. 10A , Fig.10E and Fig.10F, forming a patterned mask layer 224 above the workpiece 200. In some embodiments, the patterned mask layer 224 may include photoresist, aluminum oxide, silicon oxide, silicon nitride, silicon carbon nitride, silicon oxycarbide, silicon oxynitride, silicon carbon oxynitride, other suitable materials, or combinations thereof, and may be formed by CVD, ALD, PVD, other suitable methods, or combinations thereof. The patterned mask layer 224 includes openings (e.g., openings 224a and 224b) that expose portions of the dummy gate electrode 212' in the connector region 200C to facilitate the formation of the gate isolation structure. In the depicted embodiment, the opening 224a exposes a portion of a dummy gate electrode 212' in the connector region 200C1, and the opening 224b exposes different portions of another dummy gate 212' in the connector region 200C2.

[0054] refer to Fig.11A , Fig.11E and Fig.11F , while using the patterned mask layer 224 as an etching mask, an etching process is performed on the workpiece 200 to selectively remove the portion of the dummy gate electrode 212' exposed by the opening (e.g., the openings 224a and 224b) to form trenches (e.g., the first trench 226a and the second trench 226b). Each trench divides the corresponding dummy gate electrode 212' into a plurality of portions. In some embodiments, the etching process may be a dry etching process.

[0055] refer to Fig. 12A , Fig.12E and Fig.12F, a dielectric layer is deposited over the workpiece 200, including in the trenches (e.g., the first trench 226a and the second trench 226b). A planarization process may then be performed to remove excess portions of the dielectric layer outside the trenches, thereby forming gate isolation structures (e.g., gate isolation structures 228a and 228b) in the trenches (e.g., the first trench 226a and the second trench 226b). The dielectric layer may be deposited by CVD, ALD, other suitable methods, or combinations thereof. In some embodiments, the gate isolation structures (e.g., gate isolation structures 228a and 228b) may include a nitrogen-containing dielectric material (e.g., silicon nitride (SiN), silicon oxycarbonitride (SiOCN), silicon oxynitride (SiON)). The combination of the first gate spacer 216 and the gate isolation structure will provide satisfactory isolation between different portions of the gate structure. In some other optional embodiments, by performing another etching process to selectively remove the portion of the dummy dielectric layer 210 exposed by the first trench 226 a and the second trench 226 b, the first trench 226 a and the second trench 226 b may extend vertically along the Z direction. The gate isolation structure (e.g., gate isolation structures 228 a and 228 b ) may extend through the dummy dielectric layer 210 and directly contact the isolation feature 208 or further extend into the isolation feature 208 .

[0056] Reference now Figure 1 and FIG. 13A to FIG. 13C The method 100 includes block 120 , where a remaining portion of the dummy gate electrode 212 ′ is selectively removed to form a gate trench 229 . Fig.13A is a partial top view of the workpiece 200, Fig. 13B and Fig. 13C Depicted along the Fig.13A A partial cross-sectional view of the workpiece 200 taken along lines BB and CC shown in FIG. With the top surface of the dummy gate electrode 212′ exposed, a first etching process is performed to selectively remove the remaining portion of the dummy gate electrode 212′ that is not replaced by the gate isolation structure (e.g., gate isolation structures 228a and 228b) to form a gate trench 229.

[0057] Reference now Figure 1 and Fig.14A , Fig. 14B , Fig. 14C as well as Fig. 14B 'and Fig. 14C ', the method 100 includes block 122, wherein the portion of the dummy dielectric layer 210 exposed by the gate trench 229 in the core device region (not shown) is selectively removed, but the portion of the dummy dielectric layer 210 above the I / O device region (not shown) is retained. More specifically, for embodiments in which the workpiece 200 is to be manufactured as part of a core device, Fig.14Ais a partial top view of the workpiece 200 in the core device area, Fig. 14B and Fig. 14C Depicted along the Fig.14A 2 is a partial cross-sectional view of the workpiece 200 taken along lines BB and CC shown in FIG. The formation of the gate trench 229 exposes a portion of the dummy dielectric layer 210. A second etching process may be performed to remove the exposed portion of the dummy dielectric layer 210 to vertically extend the gate trench 229. In an embodiment, the second etching process selectively etches the dummy dielectric layer 210 without substantially etching the first gate spacer 216. After performing the second etching process, the gate trench 229 exposes the top surface 204t of the fin 204 and the top surface of the isolation feature 208. For embodiments where the workpiece 200 is to be fabricated to form a portion of an I / O device, as shown in FIG. Fig. 14B 'and Fig. 14C ', which are partial cross-sectional views of the workpiece 200 of the I / O device, the portion of the dummy dielectric layer 210 exposed by the gate trench 229 in the I / O device region will remain.

[0058] Reference now Figure 1 and Fig.15A , Fig. 15B , Fig. 15C , Fig. 15B 'and Fig. 15C ', the method 100 includes block 124, in which a gate structure 230 is formed in the gate trench 229 in the core device region, and a gate structure 230' is formed in the gate trench 229 in the I / O device region. Fig.15A is a partial top view of the workpiece 200 in the core device area, Fig. 15B and Fig. 15C Depicted along the Fig.15A 1 is a partial cross-sectional view of the workpiece 200 taken along line BB and line CC shown in FIG. Fig. 15B 'and Fig. 15C 'Describes the Fig.15AA partial cross-sectional view of the workpiece 200 in the I / O device area taken by lines BB and CC shown in . Each gate structure 230 includes a gate dielectric layer and a gate electrode layer located above the gate dielectric layer. In some embodiments, the gate dielectric layer includes an interface layer and a high-k dielectric layer 230a located above the interface layer. Here, the high-k dielectric layer 230a refers to a dielectric material having a dielectric constant greater than the dielectric constant of silicon dioxide (about 3.9). In some embodiments, the interface layer includes silicon oxide and can be formed by a thermal oxidation process. A high-k dielectric layer 230a is then deposited above the interface layer using ALD, CVD and / or other suitable methods. The high-k dielectric layer 230a may include hafnium oxide. Alternatively, the high-k dielectric layer 230a may include other high-k dielectrics, such as titanium oxide, hafnium zirconium oxide, tantalum oxide, hafnium silicon oxide, zirconium silicon oxide, lanthanum oxide, aluminum oxide, yttrium oxide, SrTiO3, BaTiO3, BaZrO, hafnium lanthanum oxide, lanthanum silicon oxide, aluminum silicon oxide, hafnium tantalum oxide, hafnium titanium oxide, (Ba,Sr)TiO3 (BST), silicon nitride, silicon oxynitride, combinations thereof, or other suitable materials.

[0059] A gate electrode layer is then deposited over the high-k dielectric layer 230a using ALD, PVD, CVD, electron beam evaporation, or other suitable methods. The gate electrode layer may include a single layer or an optional multilayer structure, such as a metal layer (work function metal layer) having a selected work function to enhance device performance, a liner layer, a wetting layer, an adhesion layer, a metal alloy, or various combinations of metal silicides. In an embodiment, the gate electrode layer includes a first work function metal layer 230b formed on the high-k dielectric layer 230a, a second work function metal layer 230c formed on the first work function metal layer 230b, and a low resistance metal layer 230d formed on the second work function metal layer 230c. For example, the first work function metal layer 230b and the second work function metal layer 230c may include titanium nitride, titanium aluminum, titanium aluminum nitride, tantalum nitride, tantalum aluminum, tantalum aluminum nitride, tantalum aluminum carbide, tantalum carbonitride, and the metal layer 230d may include aluminum, tungsten, nickel, titanium, ruthenium, cobalt, platinum, copper, other refractory metals or other suitable metal materials or combinations thereof. Fig.15A In the illustrated embodiment, some gate structures 230 are cut into multiple segments or portions by gate isolation structures (e.g., gate isolation structures 228a-228b). The gate structure 230' in the I / O device region is similar to the gate structure 230 in the core device region, with one difference including that the gate structure 230' does not have a high-k dielectric layer 230a and is located above and in direct contact with the dummy dielectric layer 210, as shown in FIG. Fig. 15B 'and Fig. 15C 'shown.

[0060] Reference now Figure 1 and FIG. 16A to FIG. 16C, the method 100 includes block 126, performing further processes. Such further processes may include forming device-level contacts, such as gate contacts 232 formed over segments of the gate structure 230, silicide layers 234 formed on the source / drain features 220, and source / drain contacts 236 formed over the source / drain features 220. Such further processes may also include forming a multi-layer interconnect (MLI) structure (not shown) over the workpiece 200. The MLI may include various interconnect features, such as vias and conductive lines disposed in dielectric layers, such as etch stop layers and ILD layers. In some embodiments, the vias are vertical interconnect features configured to interconnect device-level contacts.

[0061] In the above embodiment, the first gate spacer 216 is a single-layer structure. 17A to 17C In the illustrated alternative embodiment, the first gate spacer 216 may be a multi-layer structure. In an embodiment, to form a double-layer first gate spacer 216, the oxidation process includes providing a first gas (e.g., oxygen) to promote the formation of a first layer 216A of the first gate spacer 216, and then providing a second gas (e.g., NH3) to promote the formation of a second layer 216B of the first gate spacer 216 on the sidewalls of the first layer 216A. The first layer 216A has a uniform thickness from bottom to top, and the second layer 216B has a non-uniform thickness. In some embodiments, the profile of the second layer 216B is similar to the reference FIG. 5A to FIG. 5C and Fig. 5F The profile of the single-layer first gate spacer 216 is described to be substantially similar.

[0062] Fig.18 A flow chart of a first alternative method 100' for forming a semiconductor structure according to various embodiments of the present disclosure is shown. The method 100' is similar to the method 100, and one of the differences between the methods 100 and 100' includes that the method 100' also includes performing operations to enlarge the gate trenches in the device region 200A / 200B. Fig.18 and FIG. 14A to FIG. 14C , the method 100' includes blocks 102-122 of the method 100. For simplicity, repeated description of the operations of blocks 102-122 of the method 100 is omitted.

[0063] Reference now Fig.18 and FIG. 19A to FIG. 19C , FIG. 19E to FIG. 19G , FIG. 20B to FIG. 20C and FIG. 20E to FIG. 20G The method 100 ′ includes block 123 a , in which a recessed sacrificial layer 231 is formed in the gate trench 229 to expose portions of the first gate spacers 216 in the device regions 200A and 200B. FIG. 19A to FIG. 19C and FIG. 19E to FIG. 19G, a sacrificial layer 231 is formed over the workpiece 200 to fill the gate trench 229 . Fig.19A is a partial top view of the workpiece 200 in the core device area, Fig.19B , Fig.19C , Fig.19E , Fig.19F and Figure 19G Depicted along the Fig.19A , a partial cross-sectional view of the workpiece 200 taken along lines BB, CC, EE, FF, and GG shown in FIG. In some embodiments, the sacrificial layer 231 includes a polymer material, such as a polymer material used for a bottom anti-reflective coating (BARC) in a multilayer photoresist material. After forming the sacrificial layer 231, a patterned photoresist layer 233 is formed to cover the components in the connector region 200C of the workpiece 200, and the components in the device regions 200A and 200B remain exposed. Then, referring to FIG. 20B to FIG. 20C and FIG. 20E to FIG. 20G , an etching process is performed to recess portions of the sacrificial layer 231 formed in the gate trenches 229 in the device regions 200A and 200B. FIG. 20B to FIG. 20C As shown, in the device region 200A / 200B, the recessed sacrificial layer 231 fills the lower portion of the gate trench 229 and thus covers at least the lower portion of the first gate spacer 216, leaving the upper portion of the first gate spacer 216 exposed. FIG. 20B to FIG. 20C In the illustrated embodiment, the top surface of the sacrificial layer 231 is coplanar with or lower than the top surface 204t of the fin 204. That is, the sacrificial layer 231 covers the bottom 216b of the first gate spacer 216. Figure 20G As shown, the sacrificial layer 231 remains intact in the connector region 200C. After recessing the sacrificial layer 231 in the device regions 200A and 200B, the patterned photoresist layer 233 may be selectively removed.

[0064] refer to Fig.18 and FIG. 21B to FIG. 21C, the method 100' includes a frame 123b, in which an etching process is performed to remove the exposed portion of the first gate spacer 216 (e.g., the top 216t) to expand the gate trench 229 in the device region 200A / 200B. In the present embodiment, the etching process is configured to selectively etch the exposed portion of the first gate spacer 216 without substantially etching the sacrificial layer 231 and the bottom of the first gate spacer 216 adjacent to the sacrificial layer 231. The etching process can use an etchant that is configured to remove the first gate spacer 216 at a much higher rate than the sacrificial layer 231. Due to the removal of the portion of the first gate spacer 216 not covered by the sacrificial layer 231 (e.g., the top 216t), the gate trench 229 in the device region 200A / 200B is laterally expanded along the X direction. Fig.21B In the illustrated embodiment, after removing a portion of the first gate spacer 216, the enlarged gate trench 229 exposes a portion of the dummy dielectric layer 210. Since the first gate spacer 216 in the connector region 200C is protected by a gate isolation structure (e.g., gate isolation structure 228a / 228b) or sacrificial layer 231, it will not be substantially etched during the etching process of the operation in block 123b. Therefore, the gate trench 229 in the connector region 200C will not be enlarged. As a result, the parasitic capacitance associated with the portion of the gate structure 230 in the connector region 200C will not be disadvantageously increased.

[0065] refer to Fig.18 and FIG. 22B to FIG. 22C and FIG. 22E to FIG. 22G , the method 100' includes block 123c, where the sacrificial layer 231 is selectively removed. For embodiments where the sacrificial layer 231 includes a polymer material, such as a polymer material used in a BARC, an etching process, which may be a photoresist stripping process or a plasma ashing process, may be performed to selectively remove the sacrificial layer 231.

[0066] Still reference Fig.18 and FIG. 22B to FIG. 22C and FIG. 22E to FIG. 22G The method 100 ′ includes blocks 124 and 126 of the method 100 . After the gate trench 229 in the device region 200A / 200B is laterally enlarged, a gate structure 230 is formed in the gate trench 229 . Fig. 22B and Fig. 22C The gate structure 230 in the device region 200A / 200B shown follows the shape of the enlarged gate trench 229 and thus has a larger FIG. 15A to FIG. 15C The volume of the gate structure 230 shown is large. Therefore, the parasitic resistance and work function of the gate structure 230 in the device region 200A / 200B can be adjusted by changing the height of the first gate spacer 216 . FIG. 22E to FIG. 22FA partial cross-sectional view of gate isolation structures 228a and 228b is depicted. Gate isolation structures 228a and 228b follow the shape of gate trenches 229 in connector regions 200C1 and 200C3, respectively. Figure 22G Depicts the line GG (such as Fig.19A The gate structure 230 in the connector region 200C is formed in the gate trench 229 which has not been enlarged.

[0067] In reference FIG. 20B to FIG. 20C In the depicted embodiment, the top surface of the recessed sacrificial layer 231 is coplanar with or lower than the top surface 204 t of the fin 204 , and the top 216 t of the first gate spacer 216 is removed. FIG. 23B to FIG. 23C In the illustrated alternative embodiment, the top surface of the recessed sacrificial layer 231 is located above the top surface 204t of the fin 204. That is, the recessed sacrificial layer 231 also covers the lower portion of the top 216t of the first gate spacer 216. The operations in blocks 123b, 123c, and 124 are then performed. FIG. 24B to FIG. 24C As shown, the gate structure 230 in the device region 200A / 200B follows the shape of the adjusted gate trench 229 and therefore has a non-uniform length in the gate trench 229 . FIG. 24B to FIG. 24C The volume ratio of the gate structure 230 is shown as FIG. 15A to FIG. 15C The gate structure 230 shown is larger than FIG. 22B to FIG. 22C The gate structure 230 is shown to be small in size.

[0068] In reference Figure 4A In the above described embodiment, when viewed from the top, the main portion 212m of the dummy gate electrode 212 has a uniform length L g1 .exist Figures 25 to 30F In the illustrated alternative embodiment, in order to further reduce the parasitic capacitance, the main portion 212m of the dummy gate electrode 212 has a non-uniform length L g1 For example, the portion of the dummy gate electrode 212 in the connector region 200C (and thus the gate structure 230 in the connector region 200C) may have a length less than L g1 Length L g4 .

[0069] Fig.25 A flow chart of a second alternative method 100" for forming a semiconductor structure according to various embodiments of the present disclosure is shown. The method 100" is similar to the method 100, and one of the differences between the methods 100 and 100" includes that the method 100" also includes performing operations to reduce the length L of the portion of the dummy gate electrode 212 (and thus the gate structure 230) in the connector region 200C. g1 . refer to Fig.25 and Figure 1 , method 100" includes blocks 102-108 of method 100. For simplicity, repeated description of the operations of blocks 102-108 of method 100 is omitted.

[0070] Reference now Fig.25 , FIG. 4A to FIG. 4 C and Figure 4F as well as Fig.26A , Fig.26B , Fig.26F , Fig.27A , Fig.27B and Fig.27F , the method 100 ″ includes block 109 a , where a first etching process 260 is performed to reduce the width of the patterned hard mask layer 214 in the connector region 203C. Fig.26A depicts a partial top view of a workpiece 200, Fig.26B and Fig.26F Depicted along the Fig.26A 8 is a partial cross-sectional view of the workpiece 200 taken along lines BB and FF shown in FIG. Fig.27A depicts a partial top view of a workpiece 200, Fig.27B and Fig.27F Depicted along the Fig.27A 8 is a partial cross-sectional view of the workpiece 200 taken along lines BB and FF shown in FIG.

[0071] refer to Fig.26A , Fig.26B and Fig.26F After performing the operations in block 108, a mask layer 252 is formed over the workpiece, and then the mask layer 252 is patterned to cover features in the device region 200A and not to cover features in at least a portion of the connector region 200C (e.g., the connector region 200C3). In an embodiment, the mask layer 252 includes a bottom layer 252a and a photosensitive layer 252b located over the bottom layer 252a.

[0072] refer to Fig.27A , Fig.27B and Fig.27F , while using the patterned mask layer 252 as an etching mask, a first etching process 260 is performed to selectively etch the patterned hard mask layer 214 not covered by the patterned mask layer 252. In the present embodiment, after performing the first etching process 260, the width of the patterned hard mask layer 214 in the connector region 200C3 changes from W3 to W3'. W3 is equal to L g1 (like Figure 4C and Figure 4F), and W3' is less than W3. In some embodiments, although not shown, the execution of the first etching process 260 also reduces the thickness of the patterned hard mask layer 214 in the connector region 200C3. After the first etching process 260 is performed, the patterned hard mask layer 214 in the connector region 200C3 may be referred to as a patterned hard mask layer 214'.

[0073] refer to Fig.25 and Fig.28A , Fig.28B and Fig.28F , the method 100 ″ includes block 109 b , where a second etching process 262 is performed to etch a portion of the dummy gate electrode 212 in the connector region 203C. Fig.28A depicts a partial top view of a workpiece 200, Fig.28B and Fig.28F Depicted along the Fig.28A . After forming the patterned hard mask layer 214', a second etching process 262 is performed while using the patterned hard mask layer 214' as an etching mask to trim the dummy gate electrode 212 in the connector region 200C3 by removing the portion of the dummy gate electrode 212 not covered by the patterned hard mask layer 214' or the patterned hard mask layer 214. When the second etching process 262 is completed, the length L of the trimmed dummy gate electrode 212 in the connector region 200C3 is g1 'Shorter than length L g1 In an embodiment, the length L g1 ' is equal to the width W3'. By increasing the length of the dummy gate electrode 212 from L g1 Reduce to L g1 ', the distance between the gate structure 230 and the source / drain contact 236 in the final structure of the workpiece 200 can be further reduced. After performing the second etching process 262, the patterned mask layer 252 can be selectively removed.

[0074] In an embodiment, after performing the operation in block 109b, referring to Fig.25 and Fig.29A , Fig.29B , Fig.29F , Fig. 30A , Fig. 30B and Fig.30F , method 100" continues to path A to perform the operations in blocks 110-126 of method 100. For example, Fig.29A , Fig.29B and Fig.29F As shown, execute reference Figure 5A The oxidation process described above is used to form the first gate spacer 216. Fig. 30A , Fig. 30B and Fig.30F , forming gate isolation structures (eg, gate isolation structures 228a and 228b) and gate structure 230, replacing dummy gate electrode 212' in a manner similar to the above-described method 100. Since the length L of dummy gate electrode 212 g1 'Shorter than length L g1 ,therefore Fig. 30A , Fig. 30B and Fig.30F The distance between the gate structure 230 and the source / drain contacts 236 depicted in FIG. 2 is increased. As a result, the parasitic capacitance can be further reduced.

[0075] In another embodiment, after performing the operation in block 109b, referring to Fig.25 and Fig.31A , Fig.31B , Fig.31F , the method 100 ″ continues to path B to perform the operation in block 109 c , where a third etching process 264 is performed to trim the bottom 212 b of the dummy gate electrode 212 ′ while using the patterned hard mask layers 214 ′ and 214 as an etching mask. Fig.31A depicts a partial top view of a workpiece 200, Fig.31B and Fig.31F Depicted along the Fig.31A A partial cross-sectional view of the workpiece 200 taken along line BB and line FF shown in FIG. Fig.31F As shown, after performing the third etching process 264, in the connector region 200C3, the bottom 212b of the dummy gate electrode 212 has an uneven length along the X direction, which is smaller than the length L of the top 212t of the dummy gate electrode 212. g1 '.

[0076] After performing the operation in block 109c, refer to Fig.25 and Fig.32A , Fig.32B , Fig.32F , Fig.33A , Fig.33B , Fig.33F , Fig.34A , Fig.34B and Fig.34F , method 100" includes blocks 110-126 of method 100. For example, an oxidation process is performed to form Fig.32A , Fig.32B and Fig.32F The first gate spacer 216 is shown. A gate isolation structure (eg, gate isolation structures 228a and 228b) and / or a gate structure 230 are formed to replace the dummy gate electrode 212' in a manner similar to the method 100 described above. Fig.33A , Fig.33B and Fig.33F represents an embodiment in which the dummy gate electrode 212' is replaced by the gate structure 230, and Fig.34A , Fig.34B and Fig.34F 2. The dummy gate electrode 212' is replaced by a gate structure 230 and a gate isolation structure (eg, gate isolation structures 228a and 228b). In some embodiments, the gate isolation structure and the gate structure 230 are arranged along the same direction (eg, Fig. 30A and Fig.34A The Y direction shown in FIG. 1 extends.

[0077] Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits to semiconductor structures and their formation. For example, forming a dummy gate electrode includes patterning a dummy electrode layer. The present embodiment provides a method for eliminating the gate footing of the dummy gate electrode and reducing the length of the dummy gate electrode without introducing additional lithography and etching processes. Eliminating the gate footing of the dummy gate electrode can facilitate the formation of a satisfactory gate isolation structure; and reducing the length of the dummy gate electrode increases the distance between the dummy gate electrode (to be replaced by a functional gate structure) and the source / drain contact, and thus helps to reduce parasitic capacitance.

[0078] The present disclosure provides many different embodiments. Semiconductor structures and methods for manufacturing the same are disclosed herein. In one exemplary aspect, the present disclosure relates to a method. The method includes receiving a workpiece including a device region having a fin-shaped active region protruding from a substrate and extending along a first direction, forming a gate electrode intersecting the fin-shaped active region, wherein, in a top view, the gate electrode includes a main portion extending along a second direction substantially perpendicular to the first direction and an auxiliary portion located in the device region and extending laterally from the main portion, performing processing to convert the auxiliary portion and the side of the main portion of the gate electrode into a first dielectric spacer, and forming a source / drain component adjacent to the first dielectric spacer in the device region, selectively removing a remaining portion of the main portion of the gate electrode to form a gate trench, and forming a gate structure in the gate trench.

[0079] In some embodiments, the execution of the process may include oxidizing the side of the auxiliary portion and the main portion of the gate electrode, and the first dielectric spacer may include silicon oxide or silicon oxynitride. In some embodiments, the method may also include conformally forming a sacrificial dielectric layer over the workpiece before forming the gate electrode. The formation of the gate electrode may also include depositing a pseudo conductive material layer over the sacrificial dielectric layer, performing a planarization process on the pseudo conductive material layer, forming a patterned mask on the planarized pseudo conductive material layer, and selectively etching the planarized pseudo conductive material layer without etching the sacrificial dielectric layer. In some embodiments, the method may also include selectively removing a portion of the sacrificial dielectric layer exposed by the gate trench to extend the gate trench after forming the gate trench, and a gate structure may be formed in the extended gate trench. In some embodiments, the method may also include, after performing the process, forming a second dielectric spacer extending along the sidewall surface of the first dielectric spacer and the patterned mask. In some embodiments, the workpiece may also include a connector region adjacent to the device region, wherein the connector region may include an isolation component, the isolation component is located on the substrate and is in direct contact with the bottom of the fin-shaped active region, and wherein, in a top view, the main portion of the gate electrode extends into the connector region. The method may further include replacing at least a portion of a main portion of the gate electrode in the connector region with a dielectric layer after forming the source / drain features. In some embodiments, the method may further include reducing a length of a main portion of the gate electrode in the connector region along the first direction before performing the processing. In some embodiments, the first dielectric spacer may include a non-uniform thickness. In some embodiments, the method may further include, after forming the gate trench, selectively recessing the first dielectric spacer to laterally expand the gate trench.

[0080] In another exemplary aspect, the present disclosure is directed to a method. The method includes depositing a dummy gate material layer over a first fin-shaped active region, patterning the dummy gate material layer to form a dummy gate electrode, wherein the dummy gate electrode has a footing feature at an interface between the first fin-shaped active region and the dummy gate electrode, oxidizing the footing feature and a sidewall portion of the dummy gate electrode to form a dielectric gate spacer, and replacing a remaining portion of the dummy gate electrode with a gate structure.

[0081] In some embodiments, the method may further include, before depositing the dummy gate material layer, forming an isolation component to isolate the first fin-shaped active area from the second fin-shaped active area. The dummy gate electrode has a first portion located above the isolation component and in direct contact with the isolation component, and the first portion may include a distal portion adjacent to the first fin-shaped active area, a proximal portion adjacent to the second fin-shaped active area, and an intermediate portion extending from the distal portion to the proximal portion, wherein, in a cross-sectional view cut through the intermediate portion and the isolation component, the outline of the dummy gate electrode is similar to a rectangle. In some embodiments, the base footing component may be directly above the isolation component, and the top surface of the base footing component may be coplanar with or lower than the top surface of the first fin-shaped active area. In some embodiments, patterning of the dummy gate material layer may include forming a patterned mask layer on the dummy gate material layer, and performing a first etching process to etch the dummy gate material layer while using the patterned mask layer as an etching mask. In some embodiments, the method may further include, after forming the dummy gate electrode, reducing the size of a portion of the patterned mask layer formed on the first portion of the dummy gate electrode, performing a second etching process to reduce the size of the first portion of the dummy gate electrode, and selectively removing the patterned mask layer. In some embodiments, the method may further include, after forming the dielectric gate spacer, replacing a portion of the first portion of the dummy gate electrode with a gate isolation structure. In some embodiments, the method may further include forming another gate spacer extending along the dielectric gate spacer, and forming a source / drain feature adjacent to the other gate spacer.

[0082] In yet another exemplary aspect, the present disclosure is directed to a semiconductor structure. The semiconductor structure includes: a source / drain component coupled to a channel region of a fin; a gate structure located above a substrate and including a first portion disposed directly above the channel region and a second portion adjacent to the first portion; a first gate spacer including a first portion extending along a sidewall surface of the first portion of the gate structure and a second portion extending along a sidewall surface of the second portion of the gate structure, wherein in a cross-sectional view cut through the second portion of the gate structure but not through the channel region, the second portion of the first gate spacer may include a non-uniform thickness.

[0083] In some embodiments, an upper portion of the second portion of the first gate spacer located above the top surface of the fin may have a uniform thickness. In some embodiments, a width of a lower portion of the second portion of the first gate spacer may gradually increase along a direction from the top surface of the fin toward the substrate. In some embodiments, the semiconductor structure may further include an isolation component, the isolation component being located on the substrate and in direct contact with the bottom of the fin; and a second gate spacer extending along a sidewall surface of the first gate spacer, and the first gate spacer and the second gate spacer being isolated from the isolation component by a dielectric layer.

[0084] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: receiving a workpiece including a device region having a fin-shaped active region protruding from a substrate and extending along a first direction; forming a gate electrode intersecting the fin-shaped active region, wherein in a top view, the gate electrode comprises a main portion and an auxiliary portion, the main portion extending along a second direction perpendicular to the first direction, the auxiliary portion being located in the device region and extending laterally from the main portion; performing a process to convert the auxiliary portion and the side portions of the main portion of the gate electrode into a first dielectric spacer; forming a source / drain feature in the device region adjacent to the first dielectric spacer; selectively removing a remaining portion of the main portion of the gate electrode to form a gate trench; and A gate structure is formed in the gate trench.

2. The method according to claim 1, wherein: The performing of the process includes oxidizing the auxiliary portion and the side portions of the main portion of the gate electrode, and wherein the first dielectric spacer includes silicon oxide or silicon oxynitride.

3. The method according to claim 1, further comprising: before forming the gate electrode, conformally forming a sacrificial dielectric layer over the workpiece, Wherein, the formation of the gate electrode comprises: depositing a dummy conductive material layer over the sacrificial dielectric layer; performing a planarization process on the pseudo conductive material layer; forming a patterned mask on the planarized dummy conductive material layer; and The planarized dummy conductive material layer is selectively etched without etching the sacrificial dielectric layer.

4. The method according to claim 3, further comprising: After forming the gate trench, selectively removing a portion of the sacrificial dielectric layer exposed by the gate trench to extend the gate trench, Wherein, the gate structure is formed in an extended gate trench.

5. The method according to claim 3, further comprising: After performing the process, a second dielectric spacer is formed extending along the first dielectric spacer and the sidewall surface of the patterned mask.

6. The method according to claim 1, wherein: The workpiece further includes a connector region adjacent to the device region, wherein the connector region includes an isolation feature located on the substrate and in direct contact with a bottom of the fin-shaped active region, and wherein, in the top view, the main portion of the gate electrode extends into the connector region, Wherein, the method further comprises: After forming the source / drain features, at least part of the main portion of the gate electrode in the connector region is replaced with a dielectric layer.

7. The method according to claim 6, further comprising: Before performing the process, the length of the main portion of the gate electrode in the connector region along the first direction is reduced.

8. The method according to claim 1, wherein: The first dielectric spacer includes a non-uniform thickness.

9. A method of forming a semiconductor structure, comprising: depositing a dummy gate material layer over the first fin-shaped active region; patterning the dummy gate material layer to form a dummy gate electrode, wherein the dummy gate electrode has a footing feature at an interface between the first fin-shaped active region and the dummy gate electrode; oxidizing the footing feature and sidewall portions of the dummy gate electrode to form dielectric gate spacers; and The remaining portion of the dummy gate electrode is replaced with a gate structure.

10. A semiconductor structure comprising: a source / drain component coupled to the channel region of the fin; a gate structure located above the substrate and comprising a first portion disposed directly above the channel region and a second portion proximate to the first portion; a first gate spacer including a first portion extending along a sidewall surface of the first portion of the gate structure and a second portion extending along a sidewall surface of the second portion of the gate structure, Wherein, in a cross-sectional view cut through the second portion of the gate structure but not through the channel region, the second portion of the first gate spacer comprises a non-uniform thickness.

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