Semiconductor device and forming method thereof

Abstract

The embodiment of the invention provides a semiconductor device and a forming method thereof. A method according to one embodiment of the present disclosure includes forming an epitaxial stack of a channel layer and a sacrificial layer on a semiconductor substrate; patterning the epitaxial stack to form a first fin-shaped structure in the first region and a second fin-shaped structure in the second region; etching the first fin-shaped structure to form a first source / drain groove; etching the second fin-shaped structure to form a second source / drain groove; forming a first internal spacer in the first region; forming a second internal spacer in the second region; recessing the second inner spacer laterally; forming a first source / drain feature in the first source / drain recess; and forming a second source / drain feature in the second source / drain recess. After the second inner spacer is recessed laterally, the second inner spacer has a thickness that is less than the first inner spacer.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, each with smaller and more complex circuits than the previous generation. In the course of IC development, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. Such shrinking has also increased the complexity of processing and manufacturing ICs.

[0003] Recently, multi-gate transistors have been introduced in an attempt to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short channel effect (SCE). One such multi-gate transistor that has been introduced is the fin field effect transistor (FinFET). FinFETs are named for the fin-like structure that extends from the substrate on which they are formed, and the fin-like structure is used to form the FET channel. A further type of multi-gate transistor (introduced in part to address performance challenges associated with some configurations of FinFETs) is the all-around gate (GAA) transistor. GAA devices are named for the gate structure that extends completely around the channel region, providing access to the channel on four sides. GAA devices are compatible with conventional complementary metal oxide semiconductor (CMOS) processes, and their structure allows them to be aggressively scaled while maintaining gate control and mitigating SCE. Typically, GAA devices can be implemented, for example, in instances where FinFETs can no longer meet performance requirements. However, GAA device manufacturing can be challenging, and current approaches continue to face challenges with respect to device manufacturing and performance. For example, in a GAA process flow, the size of the internal spacer may be important for device performance. However, in advanced submicron nodes, further optimization of the performance for n-type transistors and p-type transistors may require internal spacers of different sizes. Therefore, while current methods of internal spacer formation in a GAA process flow have been satisfactory in many aspects, challenges regarding the performance of the resulting device may not be satisfactory in all aspects. Summary of the invention

[0004] Some embodiments of the present application provide a method for forming a semiconductor device, comprising: forming an epitaxial stack of a channel layer and a sacrificial layer on a semiconductor substrate, wherein the channel layer and the sacrificial layer have different material compositions and are alternately stacked in a vertical direction; patterning the epitaxial stack to form a first fin-shaped structure protruding from a first region of the semiconductor substrate and a second fin-shaped structure protruding from a second region of the semiconductor substrate; etching the first fin-shaped structure to form a first source / drain groove in the first region; etching the second fin-shaped structure to form a second source / drain groove in the second region; and making the sacrificial layer in the first fin-shaped structure laterally recessing to form a first internal spacer groove; recessing the sacrificial layer in the second fin-shaped structure laterally to form a second internal spacer groove; forming a first internal spacer in the first internal spacer groove; forming a second internal spacer in the second internal spacer groove; recessing the second internal spacer laterally to partially expose the second internal spacer groove, wherein after recessing the second internal spacer laterally, the second internal spacer has a thickness less than that of the first internal spacer; forming a first source / drain component in the first source / drain groove; and forming a second source / drain component in the second source / drain groove.

[0005] Some other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a fin-shaped structure including a stack located on top of a substrate, the stack including a plurality of channel layers interlaced with a plurality of sacrificial layers, the substrate protruding from a substrate, the fin-shaped structure including a channel region and a source / drain region; forming a dummy gate stack above the channel region of the fin-shaped structure; depositing a gate spacer layer above the dummy gate stack; recessing the source / drain region to form a source / drain trench exposing the sidewalls of the channel layer and the sacrificial layer; selectively recessing the sacrificial layer selectively and partially recessing to form a plurality of inner spacer recesses; forming a plurality of inner spacers in the inner spacer recesses; depositing an undoped epitaxial layer in the source / drain trenches; selectively and partially recessing the inner spacers to reduce the thickness of the inner spacers; depositing a doped epitaxial layer over the undoped epitaxial layer in the source / drain trenches, the doped epitaxial layer contacting the channel layer; after depositing the doped epitaxial layer, removing the dummy gate stack; releasing the channel layer in the channel region; and forming a gate structure wrapping each of the channel layers.

[0006] Still other embodiments of the present application provide a semiconductor device, comprising: a plurality of first channel members suspended above a first region of a substrate; a plurality of first internal spacers interlaced with the first channel members; a first gate structure wrapping each of the first channel members; a first source / drain component adjacent to the first channel member; a plurality of second channel members suspended above a second region of the substrate; a plurality of second internal spacers interlaced with the second channel members; a second gate structure wrapping each of the second channel members; and a second source / drain component adjacent to the second channel member, wherein a thickness of the second internal spacer is less than a thickness of the first internal spacer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The disclosed embodiments are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustration purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 A flow chart of a method for forming a semiconductor device according to one or more aspects of an embodiment of the present disclosure is shown.

[0009] Figure 2A The workpiece according to one or more aspects of the embodiments of the present disclosure is shown in Figure 1 A perspective view of the method during the manufacturing process.

[0010] Figure 2B The workpiece according to one or more aspects of the embodiments of the present disclosure is shown in Figure 1 Top view of the method during the manufacturing process.

[0011] Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5A , Figure 5B , Fig. 6A , Figure 6B , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig.9A , Fig. 9B , Fig. 10A , Fig. 10B , Fig.11A , Fig. 11B , Fig. 12A , Fig. 12B , Fig.13A , Fig. 13B , Fig.14A , Fig. 14B , Fig.15A , Fig. 15B , Fig.16A , Fig. 16B , Fig.17A and Fig. 17B The workpiece according to one or more aspects of the embodiments of the present disclosure is shown in Figure 1 A partial cross-sectional view during the manufacturing process of the method. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] For ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as shown in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

[0014] In addition, when "about," "approximately," or the like is used to describe a numerical value or a range of numerical values, as understood by one of ordinary skill in the art, the term is intended to encompass numerical values ​​within a reasonable range that takes into account variations that inherently occur during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing components having properties associated with the numerical values, the numerical value or range of numerical values ​​encompasses a reasonable range that includes the described numerical value, such as within + / - 10% of the described numerical value. For example, a material layer having a thickness of "about 5 nm" may cover a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with the deposited material layer known to one of ordinary skill in the art is + / - 15%. Further, the disclosed embodiments may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] The disclosed embodiments relate generally to multi-gate transistors and methods of fabrication, and more particularly, to internal spacer formation during fabrication of gate-all-around (GAA) transistors.

[0016] Multi-gate transistors include those transistors whose gate structures are formed on at least two sides of the channel region. These multi-gate devices may include p-type metal oxide semiconductor devices or n-type metal oxide semiconductor devices. Considering their fin-like structures, specific examples may be presented herein and referred to as FinFETs. An embodiment of a multi-gate transistor called a full-ring gate (GAA) device is also presented herein. A GAA device includes any device having a gate structure or a portion thereof formed on 4 sides of the channel region (e.g., a portion surrounding the channel region). The device presented herein also includes an embodiment of a channel region arranged in a nanowire channel, a strip channel, and / or other suitable channel configuration. Presented herein are embodiments of devices that may have one or more channel regions (e.g., nanosheets) associated with a single, continuous gate structure. However, a person of ordinary skill will recognize that the teaching may be applicable to a single channel (e.g., a single nanosheet) or any number of channels. A person of ordinary skill may recognize other examples of semiconductor devices that may benefit from various aspects of the embodiments of the present disclosure.

[0017] In a GAA transistor, the gate of the transistor is made completely around the channel so that the channel is surrounded or wrapped by the gate. Such a transistor has the advantage of improving the electrostatic control of the channel by the gate, which also reduces the leakage current. The GAA transistor includes an internal spacer and an external gate sidewall spacer (or simply referred to as a gate spacer, or referred to as a gate spacer layer), etc. The internal spacer is usually formed by an additional process relative to the gate spacer. For example, after the gate spacer and the epitaxial growth source / drain components are made, the spacer for the internal spacer is made by removing the sacrificial layer arranged alternately with the channel layer. Then, the internal spacer is formed by dielectric material deposition and removing part of the dielectric material from the channel area. Typically, the internal spacer at the n-type transistor region (or simply referred to as the n-type region) and the p-type transistor region (or simply referred to as the p-type region) is formed simultaneously. Therefore, the internal spacers at the n-type region and the p-type region are generally of similar size. However, further optimization of n-type transistors and p-type transistors may require different internal spacer sizes. For example, the internal spacing dimensions suitable for n-type transistors may adversely affect p-type transistor DC / AC performance, such as ON / OFF current ratio and ring oscillator (RO) performance. One reason is that the internal spacer separates the source / drain components from the gate edge and affects the underlap condition to which the p-type transistor is more sensitive. The underlap condition can be defined as a structure in which the source / drain region is spaced apart from the gate edge. The source / drain region can refer to the source or drain, individually or together depending on the context. The underlap condition is also called junction underlap. Compared with n-type transistors, the relatively small lateral distance between the source / drain components and the gate edge in the p-type transistor can mitigate the negative effects caused by the junction underlap. The purpose of the disclosed embodiment is to design an internal spacer formation method so as to provide different internal spacer sizes in different regions, in particular to provide relatively thin internal spacers in the p-type region, so as to improve the p-type transistor performance with relatively thick internal spacers in the n-type region without compromising the performance of the n-type transistor.

[0018] Various aspects of the disclosed embodiments will now be described in more detail with reference to the accompanying drawings. Figure 1 1 is a flow chart illustrating a method 100 of forming a semiconductor device from a workpiece according to an embodiment of the present disclosure. The method 100 is merely an example and is not intended to limit the disclosed embodiments to what is explicitly shown in the method 100. Additional steps may be provided before, during, and after the method 100, and some of the steps described may be replaced, eliminated, or moved around for additional embodiments of the method. For the sake of simplicity, not all steps are described in detail herein. FIG. 2A to FIG. 2B and FIG. 3A to FIG. 17B Describing method 100, FIG. 2A to FIG. 2B They are a three-dimensional view and a top view of the workpiece 200, respectively. FIG. 3A to FIG. 17B is based on Figure 1 1 and 1. The workpiece 200 of the embodiment of the method 100 in FIG. 1 is a partial cross-sectional view of a workpiece 200 at different manufacturing stages. Because the workpiece 200 is to be manufactured as a semiconductor device, the workpiece 200 may be referred to as a semiconductor device 200 herein as the context requires. For avoidance, FIG. 2A to FIG. 17B The X, Y and Z directions are perpendicular to each other. Throughout the embodiments of the present disclosure, the same reference numerals denote the same components unless otherwise specified.

[0019] refer to Figure 1 , FIG. 2A to FIG. 2B and FIG. 3A to FIG. 3B The method 100 includes a frame 102, wherein a workpiece 200 is provided with: a plurality of fin structures 212 (e.g., fin structures 212N, 212P) protruding from a substrate 202 and oriented longitudinally along an X direction; and a plurality of dummy gate stacks 220 (e.g., dummy gate stacks 220A-220F) spanning the fin structures 212 and oriented longitudinally along a Y direction. Figure 3A It passes through Figure 2A and Figure 2B The cross-sectional view is cut along the AA′ line in FIG. 2 , and the cross-sectional view is cut along the longitudinal direction of the fin structure 212N. The fin structure 212N is located in the n-type region 202N where an n-type transistor will be formed. Figure 3B It passes through Figure 2A and Figure 2B FIG. 2 is a cross-sectional view taken along line BB′ in FIG. 2 , which is cut in the longitudinal direction of the fin structure 212P. The fin structure 212P is located in a p-type region 202P where a p-type transistor will be formed.

[0020] In some embodiments, substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. Substrate 202 may include various doping configurations, depending on design requirements known in the art. In embodiments where the semiconductor device is p-type, an n-type doping profile (i.e., an n-type well or n-well) may be formed on a portion of substrate 202 located in p-type region 202P. In some embodiments, an n-type dopant for forming an n-type well may include phosphorus (P) or arsenic (As). In embodiments where the semiconductor device is n-type, a p-type doping profile (i.e., a p-type well or p-well) may be formed on a portion of substrate 202 located in n-type region 202N. In some embodiments, a p-type dopant for forming a p-type well may include boron (B) or gallium (Ga). Suitable doping may include ion implantation and / or diffusion processes of dopants. Substrate 202 may also include other semiconductors, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, substrate 202 may include a compound semiconductor and / or an alloy semiconductor. Additionally, the substrate 202 may optionally include an epitaxial layer (epi layer), may be strained for performance enhancement, may include a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) structure, and / or may have other suitable enhancement features.

[0021] Each fin structure 212 includes a stack 204 of alternating semiconductor layers atop a fin base 212B. The formation of the fin structure 212 may include: depositing the stack 204 on the substrate 202 in an epitaxial growth process; and patterning the stack 204 and the top portion of the substrate 202 to form the fin structure 212. Because the fin base 212B is formed by patterning the top portion of the substrate 202, the fin base 212B may still be considered to be the top portion of the substrate 202 as the context requires.

[0022] The stack 204 includes sacrificial layers 206 of a first semiconductor composition interlaced with channel layers 208 of a second semiconductor composition. The first semiconductor composition and the second semiconductor composition may be different. In some embodiments, the sacrificial layers 206 include silicon germanium (SiGe) and the channel layers 208 include silicon (Si). It should be noted that in the depicted embodiment, three (3) layers of sacrificial layers 206 and three (3) layers of channel layers 208 are arranged alternately, which is for illustrative purposes only and is not intended to be limiting beyond what is specifically recited in the claims. It is understood that any number of epitaxial layers may be formed in the stack 204. The number of layers depends on the desired number of channel components for the semiconductor device 200. In some embodiments, the number of channel layers 208 is between 1 and 20.

[0023] In some embodiments, all sacrificial layers 206 may have a substantially uniform first thickness between about 3 nm and about 10 nm, and all channel layers 208 may have a substantially uniform second thickness between about 3 nm and about 15 nm. The first thickness and the second thickness may be the same or different. As described in more detail below, the channel layer 208 or a portion thereof may be used as a channel member for a subsequently formed multi-gate device, and the thickness of each of the channel layers 208 is selected based on device performance considerations. The sacrificial layer 206 in the channel region may be eventually removed and used to define the vertical distance between adjacent channel regions for a subsequently formed multi-gate device, and the thickness of each of the sacrificial layers 206 is selected based on device performance considerations.

[0024] The layers in stack 204 may be deposited using a molecular beam epitaxy (MBE) process, a vapor phase epitaxy (VPE) process, and / or other suitable epitaxial growth processes. Therefore, stack 204 is also referred to as epitaxial stack 204. As described above, in at least some examples, sacrificial layer 206 includes an epitaxially grown silicon germanium (SiGe) layer, and channel layer 208 includes an epitaxially grown silicon (Si) layer. In some embodiments, sacrificial layer 206 and channel layer 208 are substantially free of dopants (i.e., have a dopant content of from about 0 cm -3 About 1×10 17 cm -3 extrinsic dopant concentration), where, for example, no intentional doping is performed during the epitaxial growth process for the stack 204 .

[0025] In some embodiments, the fin structure 212 can be patterned from the stack 204 and the substrate 202 using a photolithography process and an etching process. The photolithography process may include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. In some embodiments, a double patterning or multiple patterning process may be used to define a fin structure having, for example, a smaller pitch than that obtainable using a single, direct photolithography process. For example, in one embodiment, a material layer is formed above a substrate and patterned using a photolithography process. Spacers are formed next to the patterned material layer using a self-aligned process. The material layer is then removed, and then the remaining spacers or mandrels can be used to pattern the fin structure 212 by etching the top portion of the stack 204 and the substrate 202. In some examples, the width of each fin structure 212 along the Y direction is measured between about 6 nm and about 80 nm, and the distance between opposite sidewalls of two adjacent fin structures 212 along the Y direction is measured between about 10 nm and about 115 nm.

[0026] The workpiece 200 includes an isolation feature 214 deposited in a trench between opposite sidewalls of two adjacent fin structures 212. In some embodiments, the isolation feature 214 may be formed in the trench to isolate the fin structure 212 from an adjacent fin structure. The isolation feature 214 may also be referred to as a shallow trench isolation (STI) feature 214. For example, in some embodiments, a dielectric layer is first deposited over the substrate 202 to fill the trench with the dielectric layer. In some embodiments, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials. In various instances, the dielectric layer may be deposited by a CVD process, a sub-atmospheric CVD (SACVD) process, a flowable CVD process, a spin coating process, and / or other suitable processes. Then, the deposited dielectric material is thinned and planarized, for example, by a chemical mechanical polishing (CMP) process. The planarized dielectric layer is further recessed or pulled back to form the STI feature 214 by a dry etching process, a wet etching process, and / or a combination thereof. After being recessed, the fin structure 212 rises above the STI feature 214. The recessed top surface of the STI feature 214 may be flush with the top surface of the fin base 212B.

[0027] The formation of the dummy gate stack 220 may include the deposition of layers in the dummy gate stack 220 and the patterning of these layers. A dummy dielectric layer 216, a dummy electrode layer 218, and a gate top hard mask layer (not shown) may be blanket deposited over the workpiece 200. In some embodiments, the dummy dielectric layer 216 may be formed on the fin structure 212 using a chemical vapor deposition (CVD) process, an ALD process, an oxygen plasma oxidation process, or other suitable processes. In some instances, the dummy dielectric layer 216 may include silicon oxide. Thereafter, the dummy electrode layer 218 may be deposited over the dummy dielectric layer 216 using a CVD process, an ALD process, or other suitable processes. In some instances, the dummy electrode layer 218 may include polysilicon. For patterning purposes, a gate top hard mask layer may be deposited on the dummy electrode layer 218 using a CVD process, an ALD process, or other suitable processes. The dummy electrode layer 218 and the dummy dielectric layer 216 may then be patterned using the gate top hard mask layer as a patterning mask to form the dummy gate stack 220. For example, the patterning process may include a photolithography process (e.g., photolithography or electron beam lithography), which may further include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods.

[0028] The dummy gate stack 220 is formed over the corresponding channel region of the fin structure 212. In some embodiments, a gate replacement process (or gate last process) is used, in which the dummy gate stack 220 is used as a reserve to undergo various processes and will be removed and replaced by a functional gate structure. At the intersection of the fin structure 212 and the functional gate structure, transistors such as transistors T1-T8 are formed. Figure 2B In the depicted embodiment, with the dummy gate stack 220 formed above the fin structure 212, the fin structure 212 is divided into a channel region 212C located below the dummy gate stack 220 and a source / drain region 212SD not located below the dummy gate stack 220. The channel region 212C is adjacent to the source / drain region 212SD. Figure 3A and Figure 3B As shown in FIG. 1 , each channel region 212C is disposed between two source / drain regions 212SD along the X direction.

[0029] like Figure 2BThe transistors T1-T8 shown in can form part of a functional circuit. In one non-limiting embodiment, transistors T1-T8 form an SRAM cell, such as a two-port SRAM cell. In an exemplary two-port SRAM cell, the transistor T1 to be formed at the intersection of the fin structure 212N and the pseudo gate stack 220A is an n-type transistor and can be used as the first transmission gate transistor (PG-1) in the write port of the SRAM cell. The transistor T2 to be formed at the intersection of the fin structure 212N and the pseudo gate stack 220B is an n-type transistor and can be used as the first pull-down transistor (PD-1) in the write port of the SRAM cell. The transistor T3 to be formed at the intersection of the fin structure 212N and the pseudo gate stack 220C is an n-type transistor and can be used as the second pull-down transistor (PD-2) in the write port of the SRAM cell. The transistor T4 to be formed at the intersection of the fin structure 212N and the pseudo gate stack 220D is an n-type transistor and can be used as the second transmission gate transistor (PG-2) in the write port of the SRAM cell. The transistor T5 to be formed at the intersection of the fin structure 212P and the pseudo gate stack 220E is a p-type transistor and can be used as a transfer gate transistor (PG-R1) in the first read port of the SRAM cell. The transistor T6 to be formed at the intersection of the fin structure 212P and the pseudo gate stack 220B is a p-type transistor and can be used as the first pull-up transistor (PU-1) in the write port of the SRAM cell. The transistor T7 to be formed at the intersection of the fin structure 212P and the pseudo gate stack 220C is a p-type transistor and can be used as the second pull-up transistor (PU-2) in the write port of the SRAM cell. The transistor T8 to be formed at the intersection of the fin structure 212P and the pseudo gate stack 220F is a p-type transistor and can be used as a transfer gate transistor (PG-R2) in the second read port of the SRAM cell.

[0030] Furthermore, as suggested in the depicted embodiment, Figure 2BAs shown in , after the gate replacement process, the functional gate structure of the replacement dummy gate stack 220B will extend into the n-type region 202N and the p-type region 202P, so that the transistors T2 and T6 share the same gate structure. Similarly, the functional gate structure of the replacement dummy gate stack 220C will extend into the n-type region 202N and the p-type region 202P, so that the transistors T3 and T7 share the same gate structure. In comparison, the functional gate structure of the replacement dummy gate stack 220A will be separated from the functional gate structure of the replacement dummy gate stack 220E by a gate isolation component (also referred to as a gate cutting component or a cutting metal gate component), and the functional gate structure of the replacement dummy gate stack 220D will be separated from the functional gate structure of the replacement dummy gate stack 220F by another gate isolation component.

[0031] Furthermore, in the depicted embodiment, Figure 2B As shown in , the dummy gate stacks in the n-type region 202N and the p-type region 202P may have the same pitch but different gate widths (also referred to as gate CD). For example, the portion of the dummy gate stack 220 located in the n-type region 202N may have a uniform gate width (also referred to as gate CD) G1, and the portion of the dummy gate stack 220 located in the p-type region 202P may have a uniform gate width G2 greater than G1. In some embodiments, the gate width G1 is measured in the X direction in a range between about 9 nm and 11 nm, and the gate width G2 is measured in the X direction in a range between about 12 nm and about 14 nm. The larger gate width G2 of the p-type region 202P improves gate control in the p-type transistor and compensates for the relatively low mobility of carrier holes in the p-type transistor. In the case of having the same gate pitch P in the n-type region 202N and the p-type region 202P, the larger gate width G2 also translates into a smaller gate spacing D2 between opposite sidewalls of two adjacent dummy gate stacks in the p-type region 202P compared to the larger gate spacing D1 in the n-type region 202N. In other words, the source / drain region 212SD in the p-type region 202P is narrower than the source / drain region 212SD in the n-type region 202N along the X direction, and the channel region 212C in the p-type region 202P is longer than the channel region 212C in the n-type region 202N.

[0032] refer to Figure 1 and FIG. 4A to FIG. 4B, the method 100 includes a frame 104, wherein a gate spacer layer 226 is deposited over the dummy gate stack 220. In some embodiments, the gate spacer layer 226 is conformally deposited over the workpiece 200, including over the top surface and sidewalls of the dummy gate stack 220. The term "conformal" may be used herein to easily describe a layer having a substantially uniform thickness over various regions. The gate spacer layer 226 may be a single layer or multiple layers. At least one layer of the gate spacer layer 226 may include silicon carbonitride, silicon oxycarbide, silicon carbon oxynitride, or silicon nitride. The gate spacer layer 226 may be deposited over the dummy gate stack 220 using a process such as a CVD process, a sub-atmospheric pressure CVD (SACVD) process, an ALD process, or other suitable process. In the depicted embodiment, the gate spacer layer 226 includes a first layer 226a and a second layer 226b disposed over the first layer 226a. The first layer 226a may include silicon oxynitride, and the second layer may include silicon nitride. In some embodiments, the gate spacer layer 226 has a thickness measured along the X direction between about 5 nm and about 15 nm. The gate spacer layer 226 may also be referred to as a gate spacer 226 .

[0033] refer to Figure 1 and FIG. 5A to FIG. 5B , the method 100 includes a block 106, in which the source / drain region 212SD of the fin structure 212 is recessed to form a source / drain trench 228. In some embodiments, the source / drain region 212SD not covered by the dummy gate stack 220 and the gate spacer layer 226 is etched by dry etching or a suitable etching process to form the source / drain trench 228. For example, the dry etching process may be implemented with an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. In some embodiments, the source / drain region 212SD of the fin structure 212 is recessed to expose the sidewalls of the sacrificial layer 206 and the channel layer 208. In some embodiments, source / drain trenches 228 extend below stack 204 into fin-shaped base 212B.

[0034] refer to Figure 1 , FIG. 6A to FIG. 6B , FIG. 7A to FIG. 7B and FIG. 8A to FIG. 8B , the method 100 includes block 108, in which an internal spacer 234 is formed. The operations in block 108 may include: selectively and partially removing the sacrificial layer 206 to form the internal spacer groove 230 ( FIG. 6A to FIG. 6B ); depositing an inner spacer material 232 over the workpiece 200 ( FIG. 7A to FIG. 7Band etching back the inner spacer material 232 to form an inner spacer 234 in the inner spacer recess 230 ( FIG. 8A to FIG. 8B ). FIG. 6A to FIG. 6B , the sacrificial layer 206 exposed in the source / drain trench 228 is selectively and partially recessed to form an internal spacer recess 230, while the gate spacer layer 226, the exposed portion of the fin-shaped base 212B (substrate 202), and the channel layer 208 are substantially unetched. In an embodiment where the channel layer 208 is primarily composed of silicon (Si) and the sacrificial layer 206 is primarily composed of silicon germanium (SiGe), the selective recessing of the sacrificial layer 206 can be implemented using a selective wet etching process or a selective dry etching process. The selective and partial recessing of the sacrificial layer 206 can include a SiGe oxidation process and subsequent SiGe oxide removal. In this embodiment, the SiGe oxidation process can include the use of ozone. In some other embodiments, the selective dry etching process can include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. The selective wet etching process can include APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture).

[0035] Due to the smaller gate width in the n-type region 202N than in the p-type region 202P and the substantially same thickness of the gate spacer layer 226 in the n-type region 202N and the p-type region 202P, the length of the channel layer 208 in the n-type region 202N (denoted as Lc1) can be smaller than the length of the channel layer 208 in the p-type region 202P (denoted as Lc2). In some embodiments, the channel length Lc1 in the n-type region 202N is in a range between about 29 nm and about 31 nm, and the channel length Lc2 in the p-type region 202P is in a range between about 32 nm and about 34 nm. In comparison, the length of the sacrificial layer 206 in the n-type region 202N (denoted as Ls1) and the length of the sacrificial layer 206 in the p-type region 202P (denoted as Ls2) can be substantially the same. In some embodiments, the sacrificial layer lengths Ls1 and Ls2 are each in a range between about 12 nm and about 14 nm. The similar lengths of the sacrificial layer 206 in the n-type region 202N and the p-type region 202P may be due to the greater lateral etch rate of the sacrificial layer 206 in the p-type region 202P along the X direction and the resulting greater lateral recess distance. In other words, the length of the inner spacer recess 230 in the n-type region 202N (denoted as Lr1) may be less than the length of the inner spacer recess 230 in the p-type region 202P (denoted as Lr2). In some optional embodiments, the lengths Lr1 and Lr2 of the inner spacer recess 230 may be substantially the same, and the sacrificial layer length Ls1 in the n-type region 202N is less than the sacrificial layer length Ls2 in the p-type region 202P.

[0036] refer to FIG. 7A to FIG. 7B After forming the inner spacer recess 230, the inner spacer material 232 is deposited over the workpiece 200, including over the inner spacer recess 230. The inner spacer material 232 may include a metal oxide, silicon oxide, silicon oxycarbonitride, silicon nitride, silicon oxynitride, carbon-rich silicon carbonitride, or a low-k dielectric material. The metal oxide may include aluminum oxide, zirconium oxide, tantalum oxide, yttrium oxide, titanium oxide, lanthanum oxide, or other suitable metal oxides. Although not explicitly shown, the inner spacer material 232 may be a single layer or multiple layers. In some embodiments, the inner spacer material 232 may be deposited using CVD, PECVD, SACVD, ALD, or other suitable methods. The inner spacer material 232 is deposited in the inner spacer recess 230 and over the sidewalls of the channel layer 208 exposed in the source / drain trench 228.

[0037] refer to FIG. 8A to FIG. 8B, and then etch back the deposited inner spacer material 232 to remove the inner spacer material 232 from the sidewalls of the channel layer 208 to form the inner spacer 234 in the inner spacer recess 230. The inner spacer material 232 may also be removed from the sidewalls of the gate spacer 226. In some embodiments, the etch back operation performed in block 108 may include using hydrogen fluoride (HF), fluorine gas (F2), hydrogen (H2), ammonia (NH3), nitrogen trifluoride (NF3), or other fluorine-based etchants. Each of the inner spacers 234 is in direct contact with the recessed sacrificial layer 206 and is disposed between two adjacent channel layers 208. In the depicted embodiment, each of the inner spacers 234 has a straight sidewall that is flush with the sidewalls of the gate spacer 226. Optionally, the sidewalls of the inner spacers 234 may be concave (i.e., curved inwardly toward the corresponding sacrificial layer 206) or convex (i.e., curved outwardly toward the corresponding source / drain trench 228). The source / drain trench 228 in the n-type region 202N has a width W1, measured between opposite sidewalls of the inner spacer 234 along the X direction, that is greater than a width W2 of the source / drain trench 228 in the p-type region 202P. As discussed above, the length of the inner spacer recess 230 in the n-type region 202N can be less than the length of the inner spacer recess 230 in the p-type region 202P, and thus the length of the inner spacer 234 in the n-type region 202N (denoted as Lin1) can be less than the length of the inner spacer 234 in the p-type region 202P (denoted as Lin2) along the X direction. In some examples, the inner spacer length Lin1 in the n-type region 202N measures between about 7.5 nm and about 8.5 nm, and the inner spacer length Lin2 in the p-type region 202P measures between about 9 nm and about 10 nm. In some alternative embodiments, the inner spacer lengths Lin1 and Lin2 may be substantially the same, such as both within a range between about 7.5 nm and about 8.5 nm.

[0038] refer to Figure 1 and FIG. 9A to FIG. 9B, the method 100 includes a frame 110, in which a base epitaxial layer 236 is deposited in the bottom of the source / drain trench 228 in the n-type region 202N and the p-type region 202P. In some embodiments, the base epitaxial layer 236 includes the same material as the substrate 202 and the channel layer 208, such as silicon (Si), except for the dopant conditions (doping elements and / or doping concentrations). For example, the base epitaxial layer 236 is made of undoped silicon, the substrate 202 is made of doped silicon, and the channel layer 208 is made of undoped silicon or doped silicon. In some embodiments, the base epitaxial layer 236 includes the same material as the sacrificial layer 206, such as silicon germanium (SiGe), but has a different germanium (Ge) content. In other embodiments, the base epitaxial layer 236, the channel layer 208, and the sacrificial layer 206 are made of semiconductor materials that are different from each other. In various embodiments, the base epitaxial layer 236 does not contain dopants, where, for example, no intentional doping is performed during the epitaxial growth process. In comparison, substrate 202 may be lightly doped and have a higher doping concentration than base epitaxial layer 236. Base epitaxial layer 236 provides a high resistance path from the source / drain region to the semiconductor substrate, thereby suppressing leakage current in the semiconductor substrate (i.e., through fin-shaped base 212B). Internal spacer 234 limits the vertical growth of base epitaxial layer 236 because epitaxial growth cannot occur from the dielectric surface. Base epitaxial layer 236 may exhibit growth with small facets when it reaches the bottommost internal spacer 234. Therefore, in some embodiments, base epitaxial layer 236 may partially overlap the bottom portion of the bottommost internal spacer 234, but does not grow vertically beyond the top surface of the bottommost internal spacer 234 (which is also the bottom surface of the bottommost channel layer 208).

[0039] Suitable epitaxial processes for block 110 include vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), selective CVD, and / or other suitable processes. Various deposition parameters may be adjusted to selectively deposit semiconductor material on the exposed semiconductor surface in the source / drain trench 228, such as deposition gas composition, carrier gas composition, deposition gas flow rate, carrier gas flow rate, deposition time, deposition pressure, deposition temperature, source power, RF bias voltage, DC bias voltage, RF bias power, DC bias power, other suitable deposition parameters, or combinations thereof. In some embodiments, when forming the base epitaxial layer 236, the workpiece 200 is exposed to a deposition mixture including DCS and / or SiH4 (silicon-containing precursor), H2 (carrier precursor), and HCl (etchant-containing precursor). In some embodiments, the selective CVD process implements a deposition temperature of about 600°C to about 750°C. In some embodiments, the selective CVD process implements a deposition pressure of about 10 Torr to about 100 Torr. In some embodiments, the selective CVD process is configured as a bottom-up deposition process, so that the base epitaxial layer 236 grows from the exposed semiconductor surface at the bottom of the source / drain trench 228, but does not grow from the exposed end portion of the channel layer 208. In some embodiments, a post-deposition etch is performed after the selective CVD process to remove semiconductor material (if any) of the base epitaxial layer 236 that may remain on the end portion of the channel layer 208. The post-deposition etch includes dry etching, wet etching, other suitable etching processes, or combinations thereof.

[0040] Due to the different profiles of the source / drain trenches 228 in the n-type region 202N and the p-type region 202P, the base epitaxial layer 236 has different profiles and volumes in the two regions. For example, due to the narrower openings of the source / drain trenches 228 in the p-type region 202P, the epitaxial growth rate in the Z direction in the p-type region 202P can be greater than the epitaxial growth rate in the n-type region 202N. Therefore, the thickness T1 of the base epitaxial layer 236 in the n-type region 202N can be less than the thickness T2 of the base epitaxial layer 236 in the p-type region 202P, and the top surface of the base epitaxial layer 236 in the n-type region 202N can be lower than the top surface of the base epitaxial layer 236 in the p-type region 202P. Even though the thickness T1 of the base epitaxial layer 236 in the n-type region 202N may be smaller than the thickness T2 of the base epitaxial layer 236 in the p-type region 202P, the volume of the base epitaxial layer 236 in the n-type region 202N may still be larger than the volume of the base epitaxial layer 236 in the p-type region 202P due to the larger opening of the source / drain trenches 228 in the n-type region 202N.

[0041] refer to Figure 1 and FIG. 10A to FIG. 10B, the method 100 includes a block 112, in which a patterned mask layer 238 is formed covering the n-type region 202N. The patterned mask layer 238 covers the n-type region 202N with an opening exposing the p-type region 202P. In some embodiments, the patterned mask layer 238 is a hard mask layer including a single layer or multiple layers. For example, the hard mask layer may include a silicon oxide layer and a silicon nitride layer above the silicon oxide layer. In some other examples, the patterned mask layer 238 may include a metal oxide or a metal nitride, such as La2O3, Al2O3, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Y2O3, AlON, TaCN, or a combination thereof. The hard mask layer can be formed using chemical vapor deposition (CVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, electron beam (e-beam) evaporation or other suitable deposition techniques or combinations thereof. The hard mask layer is patterned using any suitable method, such as a photolithography process, which can include: forming a resist layer on the hard mask layer; exposing the resist through a photolithography exposure process; performing a post-exposure bake process; developing the photoresist layer to form a patterned photoresist layer that exposes a portion of the hard mask layer; patterning the hard mask layer; and finally removing the patterned resist layer. Alternatively, the photolithography process can be replaced by other suitable techniques, such as electron beam writing, ion beam writing, maskless patterning, or molecular printing.

[0042] In some embodiments, the patterned mask layer 238 is a resist layer, such as a three-layer resist layer including a bottom layer, a middle layer, and a top photoresist layer. In further embodiments, the bottom layer may include a carbon-rich polymer material (e.g., C x H y O z ), the intermediate layer may include a silicon-rich polymer material (e.g., SiC x H y O z ), and the top photoresist layer may include a carbon-rich polymer material (e.g., C x H y O z ). Patterning of the top photoresist layer can be achieved, for example, by using an immersion lithography system to expose portions of the top photoresist layer and developing the exposed or unexposed portions depending on whether a positive or negative photoresist is used. The middle layer is then etched through the openings in the top photoresist layer. In this way, the top photoresist layer serves as an etching mask that limits the etching process in the p-type region 202P. The bottom layer is then etched through the openings in the top photoresist layer and the middle layer. In this way, the top photoresist layer and the middle layer together serve as an etching mask that limits the etching process in the p-type region 202P.

[0043] refer to Figure 1 and FIG. 11A to FIG. 11B , the method 100 includes a block 114, in which the inner spacer 234 in the p-type region 202P is further recessed along the X direction. In some embodiments, the recessing process may include a dry etching process, a wet etching process, and / or a combination thereof. In some embodiments, the lateral recessing depth is controlled (e.g., by controlling the etching time) so as to thin down the inner spacer 234 in the p-type region 202P to partially expose the inner spacer groove 230 again. In some embodiments, the recessing process implemented in block 114 is a dry etching process using a fluorine-based etchant, such as hydrogen fluoride (HF), fluorine gas (F2), hydrogen (H2), ammonia (NH3), nitrogen trifluoride (NF3), CH3F, or other suitable etchants. In one example, the recessing process includes applying an etchant (e.g., a mixture of CH3F, O2, and Ar) with a pressure of about 3 mTorr to about 20 mTorr and a bias power of about 500 W to about 1500 W for a duration of about 10 s to about 30 s. In some embodiments, the recessing process is a wet etching process using H3PO4 or other suitable etchants. In some embodiments, after the recessing process, the internal spacer length Lin2 in the p-type region 202P is reduced to a range between about 3 nm and about 6 nm. This range is not insignificant. If the internal spacer length Lin2 is less than about 3 nm, the internal spacer in the p-type region 202P may be too thin and there is a risk of breakdown in subsequent processes; if the internal spacer length Lin2 is greater than about 6 nm, the internal spacer in the p-type region 202P may be too thick to effectively alleviate the junction underlap in the p-type region 202P. The thinned internal spacer 234 in the p-type region 202P may have a uniform internal spacer length Lin2. Optionally, from top to bottom, the thinned internal spacer 234 in the p-type region 202P may have a gradually increasing internal spacer length Lin2, which may be due to the etching load effect at different depths of the source / drain trench 228. That is, in the depicted embodiment, the middle inner spacers 234 may be thicker in the X direction than the topmost inner spacers 234, and the bottommost inner spacers 234 may be thicker in the X direction than the middle inner spacers 234. After the recess process, the inner spacer length Lin1 in the n-type region 202N may be greater than any inner spacer length Lin2 in the p-type region 202P. At the end of block 114, the patterned mask layer 238 is removed from the n-type region 202N in an etching process, an ashing process, or other suitable removal process.

[0044] refer to Figure 1 and FIG. 12A to FIG. 12B, the method 100 includes a frame 116, wherein a doped epitaxial layer 240 is formed in the source / drain trench 228 in the n-type region 202N and the p-type region 202P. The doped epitaxial layer 240 may also be referred to as a source / drain component. Sometimes, the term "source / drain component" includes the doped epitaxial layer 240 and the underlying substrate epitaxial layer 236. In an embodiment, forming the doped epitaxial layer 240 includes epitaxially growing a semiconductor layer by an MBE process, a chemical vapor deposition process, and / or other suitable epitaxial growth process. For an n-type transistor, the doped epitaxial layer 240 in the n-type region 202N may include silicon doped with phosphorus or arsenic. For a p-type transistor, the doped epitaxial layer 240 in the p-type region 202P may include silicon germanium doped with boron. In each region, the doped epitaxial layer 240 covers the substrate epitaxial layer 236 and contacts the internal spacer 234. In the p-type region 202P, the doped epitaxial layer 240 also extends into the inner spacer recess 230, so that the extended portion of the doped epitaxial layer 240 is staggered with the end portion of the adjacent channel layer 208. That is, in the depicted embodiment, the doped epitaxial layer 240 in the p-type region 202P contacts the vertical sidewalls and the top and bottom surfaces of the end portion of the channel layer 208, while the doped epitaxial layer 240 in the n-type region 202N may contact the vertical sidewalls of the channel layer 208, but not the top and bottom surfaces thereof. In some embodiments, a void 242 (also referred to as an air pocket) may be laterally retained between the thinned inner spacer 234 and the extended portion of the doped epitaxial layer 240 in the p-type region 202P. In some embodiments, with the extended portion, the volume of the doped epitaxial layer 240 in the p-type region 202P may be greater than the volume of the doped epitaxial layer 240 in the n-type region 202N.

[0045] refer to Figure 1 and FIG. 13A to FIG. 16B , the method 100 includes block 118, where further processing is performed. Such further processing may include, for example, depositing a contact etch stop layer (CESL) 248 ( FIG. 13A to FIG. 13B ); an interlayer dielectric (ILD) layer 250 is deposited over the CESL 248 ( FIG. 13A to FIG. 13B ); removing the dummy gate stack 220 ( FIG. 14A to FIG. 14B ); selectively removing the sacrificial layer 206 in the channel region 212C to release the channel layer 208 as a channel member ( FIG. 15A to FIG. 15B ); and forming a gate structure 256 ( FIG. 16A to FIG. 16B ). Now refer to FIG. 13A to FIG. 13B, the CESL 248 is formed before forming the ILD layer 250. In some instances, the CESL 248 includes silicon nitride, silicon oxynitride, and / or other materials known in the art. The CESL 248 may be formed by an ALD, a plasma enhanced chemical vapor deposition (PECVD) process, and / or other suitable deposition processes. The ILD layer 250 is then deposited over the CESL 248. In some embodiments, the ILD layer 250 includes materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused quartz glass (FSG), phosphosilicate glass (PSG), boron-doped silica glass (BSG), and / or other suitable dielectric materials. The ILD layer 250 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, after forming the ILD layer 250, the workpiece 200 may be annealed to improve the integrity of the ILD layer 250. FIG. 13A to FIG. 13B As shown in FIG. 2 , the CESL 248 is disposed directly on the top surface of the doped epitaxial layer 240 .

[0046] refer to FIG. 14A to FIG. 14B , after depositing the CESL 248 and the ILD layer 250, the workpiece 200 may be planarized by a planarization process to expose the dummy gate stack 220. For example, the planarization process may include a chemical mechanical planarization (CMP) process. The exposure of the dummy gate stack 220 allows the dummy gate stack 220 to be removed and the channel layer 208 to be released. In some embodiments, the removal of the dummy gate stack 220 creates a gate trench 252 above the channel region 212C. Removing the dummy gate stack 220 may include one or more etching processes that are selective to the material of the dummy gate stack 220. For example, removing the dummy gate stack 220 may be implemented using a selective wet etch, a selective dry etch, or a combination thereof that is selective to the dummy gate stack 220. After removing the dummy gate stack 220, the sidewalls of the channel layer 208 and the sacrificial layer 206 in the channel region 212C are exposed in the gate trench 252.

[0047] refer to FIG. 15A to FIG. 15B, after removing the dummy gate stack 220, the method 100 may include the operation of selectively removing the sacrificial layer 206 between the channel layers 208 in the channel region 212C. The selective removal of the sacrificial layer 206 releases the channel layer 208 to form a channel member (also numbered 208). The selective removal of the sacrificial layer 206 also leaves a space 254 between the channel members 208. The selective removal of the sacrificial layer 206 can be implemented by selective dry etching, selective wet etching, or other selective etching processes. An exemplary selective dry etching process may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. An exemplary selective wet etching process may include APM etching (e.g., ammonia hydroxide-hydrogen peroxide-water mixture).

[0048] refer to FIG. 16A to FIG. 16B , the method 100 may include further operations to form a gate structure 256 to wrap around each of the channel members 208. In some embodiments, the gate structure 256 is formed in the gate trench 252 and in the space 254 left by removing the sacrificial layer 206. At this point, the gate structure 256 wraps around each of the channel members 208. The gate structure 256 includes a gate dielectric layer 258 and a gate electrode layer 260 above the gate dielectric layer 258. In some embodiments, although not explicitly shown in the figure, the gate dielectric layer 258 includes an interface layer and a high-K gate dielectric layer. High-K dielectric materials (as used and described herein) include dielectric materials with high dielectric constants, for example, greater than the dielectric constant of thermal silicon oxide (~3.9). The interface layer may include a dielectric material, such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-K gate dielectric layer may include hafnium oxide. Alternatively, the high-K gate dielectric layer may include other high-K dielectric materials, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium oxide silicon (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba, Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. The high-K gate dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods.

[0049] The gate electrode layer 260 of the gate structure 256 may include a single layer or optionally a multi-layer structure, such as a metal layer (work function metal layer) having a selected work function to enhance device performance, a liner layer, a wetting layer, an adhesion layer, a metal alloy or various combinations of metal silicides. For example, the gate electrode layer 260 may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals or other suitable metal materials or combinations thereof. In various embodiments, the gate electrode layer 260 may be formed by ALD, PVD, CVD, electron beam evaporation or other suitable processes. In various embodiments, a CMP process may be performed to remove excess metal, thereby providing a substantially planar top surface of the gate structure 256. The gate structure 256 includes a portion between the channel members 208 in the channel region 212C.

[0050] Still reference FIG. 16A to FIG. 16B At the end of the operation in block 118, a plurality of n-type transistors 280N (eg, Figure 2B ) and a plurality of p-type transistors 280P (eg, Figure 2BThe transistors T5-T6 therein). Each of the transistors 280N and 280P includes a channel member 208 vertically stacked along the Z direction. Each of the channel members 208 is wrapped by a gate structure 256. The channel members 208 extend in the X direction or are sandwiched between two source / drain components 240. Below the source / drain components 240 is a substrate epitaxial layer 236. The substrate epitaxial layer 236 can be an undoped epitaxial layer and exhibits a high resistivity, thus providing a high-resistance path from the source / drain components 240 to the substrate 202, thereby suppressing leakage current into the substrate 202. The gate structure 256 in the n-type transistor 280N has a gate width G1, and the gate structure 256 in the p-type transistor 280P has a gate width G2 greater than G1 (G2 > G1). The channel member 208 in the n-type transistor 280N has a length Lc1, and the channel member 208 in the p-type transistor 280P has a length Lc2 greater than Lc1 (Lc2 > Lc1). The source / drain component 240 in the n-type transistor 280N has a width W1, and the source / drain component 240 in the p-type transistor 280P has a width W2 less than W1 (W2 < W1). The substrate epitaxial layer 236 in the n-type transistor 280N has a thickness T1, and the substrate epitaxial layer 236 in the p-type transistor 280P has a thickness T2 greater than T1 (T2 > T1). The internal spacer 234 in the n-type transistor 280N has a thickness (or length) Lin1, and the internal spacer 234 in the p-type transistor 280P has a thickness (or length) Lin2 less than Lin1 (Lin2 < Lin1). The thinned internal spacer 234 in the p-type transistor 280P allows the source / drain component 240 to have an extended portion that is staggered with the channel member 208 in the p-type transistor 280P. The extended portion of the source / drain component 240 effectively reduces the lateral distance between the edge of the source / drain component 240 and the gate structure 256. The reduced lateral distance between the edge of the source / drain component 240 and the gate structure 256 alleviates the underlap condition and counteracts the negative impact caused by junction underlap, which improves the performance of the p-type transistor without degrading the performance of the n-type transistor.

[0051] In FIG. 17A to FIG. 17B an alternative embodiment of the workpiece 200 is shown. FIG. 17A to FIG. 17B and FIG. 16A to FIG. 16B many aspects of the workpiece 200 in FIG. 17A to FIG. 17B, the frame 110 of forming the base epitaxial layer 236 may be performed after the frames 112 and 114 of laterally recessing the inner spacers in the p-type region 202P. That is, the inner spacers 234 in the p-type region 202P have been thinned downward during the epitaxial growth of the base epitaxial layer 236. Because the epitaxial growth rate in the p-type region 202P in the Z direction may be greater than the epitaxial growth rate in the n-type region 202N due to the narrower opening of the source / drain trench 228 in the p-type region 202P, the base epitaxial layer 236 in the p-type region 202P may be thicker and reach the bottom surface of the bottommost channel member 208 and separate the source / drain feature 240 from the bottommost inner spacer 234. The extended portion of the base epitaxial layer 236 in the p-type region 202P intersects with the top surface of the bottommost channel member 208 and the fin-shaped base 212B. The void 242' may also be sandwiched between the faceted surface of the extended portion of the base epitaxial layer 236 and the bottommost inner spacer 234. The bottom surface of the source / drain feature 240 in the p-type region 202P may be located above the bottom surface of the bottommost channel member 208. In comparison, the base epitaxial layer 236 in the n-type region 202N has a smaller thickness and may be located below the bottom surface of the bottommost channel member 208. The source / drain feature 240 in the n-type region 202N may still contact the top portion of the bottommost inner spacer 234.

[0052] Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits to semiconductor devices and their formation. For example, embodiments of the present disclosure provide p-type transistors having internal spacers of reduced thickness compared to counterparts in n-type transistors. The thinned internal spacers reduce the lateral distance between the source / drain components and the edge of the gate structure. The reduced lateral distance alleviates the under-lap condition and offsets the negative effects caused by junction under-lap, which improves the performance of the p-type transistor without compromising the performance of the n-type transistor.

[0053] In one exemplary aspect, the disclosed embodiments are directed to a method. The method includes: forming an epitaxial stack of a channel layer and a sacrificial layer on a semiconductor substrate, the channel layer and the sacrificial layer having different material compositions and being alternately stacked in a vertical direction; patterning the epitaxial stack to form a first fin-shaped structure protruding from a first region of the semiconductor substrate and a second fin-shaped structure protruding from a second region of the semiconductor substrate; etching the first fin-shaped structure to form a first source / drain groove in the first region; etching the second fin-shaped structure to form a second source / drain groove in the second region; laterally recessing the sacrificial layer in the first fin-shaped structure to form a first internal spacer groove; laterally recessing the sacrificial layer in the second fin-shaped structure to form a second internal spacer groove; forming a first internal spacer in the first internal spacer groove; forming a second internal spacer in the second internal spacer groove; laterally recessing the second internal spacer to partially expose the second internal spacer groove, and after laterally recessing the second internal spacer, the second internal spacer has a thickness less than the first internal spacer; forming a first source / drain component in the first source / drain groove; and forming a second source / drain component in the second source / drain groove. In some embodiments, the first region is an n-type transistor region, and the second region is a p-type transistor region. In some embodiments, a portion of the second source / drain feature extends into the second inner spacer recess. In some embodiments, the method also includes: depositing a first undoped layer in the first source / drain recess; and depositing a second undoped layer in the second source / drain recess. The first undoped layer is directly below the first source / drain feature, and the second undoped layer is directly below the second source / drain feature. In some embodiments, depositing the first undoped layer and depositing the second undoped layer are performed before the second inner spacer is laterally recessed. In some embodiments, depositing the first undoped layer and depositing the second undoped layer are performed after the second inner spacer is laterally recessed. In some embodiments, the second undoped layer has a thickness greater than the first undoped layer. In some embodiments, the method also includes: before the second inner spacer is laterally recessed, depositing a mask layer covering the first source / drain recess, so that the first inner spacer remains intact during the second inner spacer is laterally recessed. In some embodiments, before the second inner spacer is laterally recessed, the thickness of the second inner spacer is greater than the first inner spacer. In some embodiments, after laterally recessing the second inner spacer, the second inner spacer has a thickness in a range between about 3 nm and about 6 nm.

[0054] In another exemplary aspect, the disclosed embodiments relate to a method. The method includes: forming a fin-shaped structure including a stack located on top of a substrate, the stack including multiple channel layers interlaced with multiple sacrificial layers, the substrate protruding from the substrate, the fin-shaped structure including a channel region and a source / drain region; forming a dummy gate stack above the channel region of the fin-shaped structure; depositing a gate spacer layer above the dummy gate stack; recessing the source / drain region to form a source / drain trench exposing the sidewalls of the channel layer and the sacrificial layer; selectively and partially recessing the sacrificial layer to form multiple internal spacer grooves; forming multiple internal spacers in the internal spacer grooves; depositing an undoped epitaxial layer in the source / drain trench; selectively and partially recessing the internal spacer to reduce the thickness of the internal spacer; depositing a doped epitaxial layer above the undoped epitaxial layer in the source / drain trench, the doped epitaxial layer contacting the channel layer; after depositing the doped epitaxial layer, removing the dummy gate stack; releasing the channel layer in the channel region; and forming a gate structure that wraps each of the channel layers. In some embodiments, after depositing the doped epitaxial layer, portions of the doped epitaxial layer are vertically stacked between adjacent channel layers. In some embodiments, the reduced thickness of the internal spacer is in a range between about 3 nm and about 6 nm. In some embodiments, depositing the undoped epitaxial layer is performed before selectively and partially recessing the internal spacer. In some embodiments, depositing the undoped epitaxial layer is performed after selectively and partially recessing the internal spacer. In some embodiments, portions of the undoped epitaxial layer are vertically stacked between the bottommost one of the channel layers and the top surface of the substrate. In some embodiments, the gate structure, the channel layer, and the doped epitaxial layer are portions of a p-type transistor.

[0055] In another exemplary aspect, the disclosed embodiments relate to a semiconductor device. The semiconductor device includes: a plurality of first channel members suspended above a first region of a substrate; a plurality of first internal spacers interlaced with the first channel members; a first gate structure wrapping each of the first channel members; a first source / drain component adjacent to the first channel member; a plurality of second channel members suspended above a second region of the substrate; a plurality of second internal spacers interlaced with the second channel members; a second gate structure wrapping each of the second channel members; and a second source / drain component adjacent to the second channel member. The thickness of the second internal spacer is less than the thickness of the first internal spacer. In some embodiments, the first region is an n-type transistor region, and the second region is a p-type transistor region. In some embodiments, the second source / drain component is interlaced with the second channel member.

[0056] Some embodiments of the present application provide a method for forming a semiconductor device, comprising: forming an epitaxial stack of a channel layer and a sacrificial layer on a semiconductor substrate, wherein the channel layer and the sacrificial layer have different material compositions and are alternately stacked in a vertical direction; patterning the epitaxial stack to form a first fin-shaped structure protruding from a first region of the semiconductor substrate and a second fin-shaped structure protruding from a second region of the semiconductor substrate; etching the first fin-shaped structure to form a first source / drain groove in the first region; etching the second fin-shaped structure to form a second source / drain groove in the second region; and making the sacrificial layer in the first fin-shaped structure laterally recessing to form a first internal spacer groove; recessing the sacrificial layer in the second fin-shaped structure laterally to form a second internal spacer groove; forming a first internal spacer in the first internal spacer groove; forming a second internal spacer in the second internal spacer groove; recessing the second internal spacer laterally to partially expose the second internal spacer groove, wherein after recessing the second internal spacer laterally, the second internal spacer has a thickness less than that of the first internal spacer; forming a first source / drain component in the first source / drain groove; and forming a second source / drain component in the second source / drain groove.

[0057] In some embodiments, the first region is an n-type transistor region and the second region is a p-type transistor region.

[0058] In some embodiments, a portion of the second source / drain feature extends into the second inner spacer recess.

[0059] In some embodiments, the method also includes: depositing a first undoped layer in the first source / drain groove; and depositing a second undoped layer in the second source / drain groove, wherein the first undoped layer is directly located below the first source / drain component and the second undoped layer is directly located below the second source / drain component.

[0060] In some embodiments, depositing the first undoped layer and depositing the second undoped layer are performed before laterally recessing the second inner spacer.

[0061] In some embodiments, depositing the first undoped layer and depositing the second undoped layer are performed after laterally recessing the second inner spacer.

[0062] In some embodiments, the second undoped layer has a thickness greater than that of the first undoped layer.

[0063] In some embodiments, the method further includes, before laterally recessing the second inner spacer, depositing a mask layer covering the first source / drain recess, such that the first inner spacer remains intact during laterally recessing the second inner spacer.

[0064] In some embodiments, the thickness of the second interior spacer is greater than the thickness of the first interior spacer prior to laterally recessing the second interior spacer.

[0065] In some embodiments, after laterally recessing the second inner spacer, the thickness of the second inner spacer ranges between about 3 nm and about 6 nm.

[0066] Some other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a fin-shaped structure including a stack located on top of a substrate, the stack including a plurality of channel layers interlaced with a plurality of sacrificial layers, the substrate protruding from a substrate, the fin-shaped structure including a channel region and a source / drain region; forming a dummy gate stack above the channel region of the fin-shaped structure; depositing a gate spacer layer above the dummy gate stack; recessing the source / drain region to form a source / drain trench exposing the sidewalls of the channel layer and the sacrificial layer; selectively recessing the sacrificial layer selectively and partially recessing to form a plurality of inner spacer recesses; forming a plurality of inner spacers in the inner spacer recesses; depositing an undoped epitaxial layer in the source / drain trenches; selectively and partially recessing the inner spacers to reduce the thickness of the inner spacers; depositing a doped epitaxial layer over the undoped epitaxial layer in the source / drain trenches, the doped epitaxial layer contacting the channel layer; after depositing the doped epitaxial layer, removing the dummy gate stack; releasing the channel layer in the channel region; and forming a gate structure wrapping each of the channel layers.

[0067] In some embodiments, after depositing the doped epitaxial layer, portions of the doped epitaxial layer are vertically stacked between adjacent channel layers.

[0068] In some embodiments, the reduced thickness of the inner spacer ranges between about 3 nm and about 6 nm.

[0069] In some embodiments, depositing the undoped epitaxial layer is performed before selectively and partially recessing the inner spacers.

[0070] In some embodiments, depositing the undoped epitaxial layer is performed after selectively and partially recessing the inner spacers.

[0071] In some embodiments, a portion of the undoped epitaxial layer is vertically stacked between a bottommost one of the channel layers and a top surface of the substrate.

[0072] In some embodiments, the gate structure, the channel layer, and the doped epitaxial layer are part of a p-type transistor.

[0073] Still other embodiments of the present application provide a semiconductor device, comprising: a plurality of first channel members suspended above a first region of a substrate; a plurality of first internal spacers interlaced with the first channel members; a first gate structure wrapping each of the first channel members; a first source / drain component adjacent to the first channel member; a plurality of second channel members suspended above a second region of the substrate; a plurality of second internal spacers interlaced with the second channel members; a second gate structure wrapping each of the second channel members; and a second source / drain component adjacent to the second channel member, wherein a thickness of the second internal spacer is less than a thickness of the first internal spacer.

[0074] In some embodiments, the first region is an n-type transistor region and the second region is a p-type transistor region.

[0075] In some embodiments, the second source / drain features are interleaved with the second channel member.

[0076] The features of several embodiments are summarized above so that those of ordinary skill in the art can better understand the various aspects of the embodiments of the present disclosure. Those of ordinary skill in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those of ordinary skill in the art should also be aware that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: forming an epitaxial stack of a channel layer and a sacrificial layer on a semiconductor substrate, wherein the channel layer and the sacrificial layer have different material compositions and are alternately stacked in a vertical direction; patterning the epitaxial stack to form a first fin-shaped structure protruding from a first region of the semiconductor substrate and a second fin-shaped structure protruding from a second region of the semiconductor substrate; etching the first fin structure to form a first source / drain recess in the first region; etching the second fin structure to form a second source / drain recess in the second region; laterally recessing the sacrificial layer in the first fin structure to form a first inner spacer recess; laterally recessing the sacrificial layer in the second fin structure to form a second inner spacer recess; forming a first inner spacer in the first inner spacer groove; forming a second inner spacer in the second inner spacer groove; laterally recessing the second inner spacer to partially expose the second inner spacer groove, wherein after laterally recessing the second inner spacer, the second inner spacer has a thickness less than the first inner spacer; forming a first source / drain feature in the first source / drain recess; and A second source / drain feature is formed in the second source / drain recess.

2. The method according to claim 1, wherein: The first region is an n-type transistor region, and the second region is a p-type transistor region.

3. The method according to claim 1, wherein: Portions of the second source / drain feature extend into the second inner spacer recess.

4. The method according to claim 1, further comprising: depositing a first undoped layer in the first source / drain groove; as well as A second undoped layer is deposited in the second source / drain recess, wherein the first undoped layer is directly below the first source / drain feature and the second undoped layer is directly below the second source / drain feature.

5. The method according to claim 4, wherein: Depositing the first undoped layer and depositing the second undoped layer are performed before laterally recessing the second inner spacer.

6. The method according to claim 4, wherein: Depositing the first undoped layer and depositing the second undoped layer are performed after laterally recessing the second inner spacer.

7. The method according to claim 4, wherein: The second undoped layer has a thickness greater than that of the first undoped layer.

8. The method according to claim 1, further comprising: Prior to laterally recessing the second inner spacer, a masking layer is deposited covering the first source / drain recesses, such that the first inner spacer remains intact during laterally recessing the second inner spacer.

9. A method of forming a semiconductor device, comprising: forming a fin structure including a stack atop a base, the stack including a plurality of channel layers interleaved with a plurality of sacrificial layers, the base protruding from the substrate, the fin structure including a channel region and a source / drain region; forming a dummy gate stack over the channel region of the fin structure; depositing a gate spacer layer over the dummy gate stack; recessing the source / drain region to form a source / drain trench exposing sidewalls of the channel layer and the sacrificial layer; selectively and partially recessing the sacrificial layer to form a plurality of inner spacer recesses; forming a plurality of internal spacers in the internal spacer grooves; depositing an undoped epitaxial layer in the source / drain trench; selectively and partially recessing the inner spacer to reduce the thickness of the inner spacer; Depositing a doped epitaxial layer over the undoped epitaxial layer in the source / drain trenches, the doped epitaxial layer contacting the channel layer; After depositing the doped epitaxial layer, removing the dummy gate stack; releasing the channel layer in the channel region; as well as A gate structure is formed that wraps each of the channel layers.

10. A semiconductor device comprising: a plurality of first channel members suspended above the first region of the substrate; a plurality of first interior spacers interleaved with the first channel members; a first gate structure wrapping each of the first channel members; a first source / drain feature adjacent to said first channel member; a plurality of second channel members suspended above a second region of the substrate; a plurality of second interior spacers interleaved with the second channel members; a second gate structure wrapping each of the second channel members; as well as a second source / drain feature adjacent to said second channel member, Wherein, the thickness of the second internal spacer is smaller than the thickness of the first internal spacer.

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