A testing device and method for quantum chips

Abstract

This application provides a testing apparatus and method for quantum chips. The apparatus includes a wire-binding board and a test board detachably connected to the wire-binding board. The wire-binding board includes a first connection structure, and the test board includes a second connection structure adapted to the first connection structure. When the first connection structure and the second connection structure are connected together, a communication connection is achieved between the wire-binding board and the test board. The quantum chip testing apparatus of this application separates the test board and the wire-binding board, and through a plug-in or snap-fit ​​design, provides a quantum chip testing solution suitable for wire-binded packaging from room temperature to ultra-low temperature. This not only enables simultaneous testing of multiple chips in ultra-low temperature environments, reducing chip damage caused by soldering and improving testing efficiency, but also allows for flexible plug-in or snap-fit ​​connections, enabling convenient operation and reusability of the test board. Furthermore, it is compatible with different testing instruments, improving efficiency, reducing costs, and enhancing scalability.

Description

Technical Field

[0001] This application relates to the field of chip testing technology, and in particular to a testing device and method for quantum chips. Background Technology

[0002] After quantum chips are fabricated, their parameters and performance need to be tested to ensure high quality. Current chip testing methods employ wire bonding, connecting the chip's internal circuitry to a gold-plated copper foil test circuit board using gold or aluminum wires. After bonding, black adhesive is applied for insulation and protection before testing. However, quantum chips require ultra-low temperature environments (as low as 10 mK, approximately -273°C) to maintain their quantum states. The measurement and control circuitry of qubits and other surrounding circuits need to be set up in ultra-low temperature environments at different temperatures. Compared to chip testing for conventional consumer electronics applications, ultra-low temperature chip testing for quantum computing is far more demanding in terms of temperature, and the ultra-low temperature environment presents challenges to instruments, packaging methods, and testing hardware. Therefore, traditional wire bonding methods cannot meet the requirements for quantum chip testing. Furthermore, existing testing devices use disposable wire bonding boards, with the test board fixed to the board; the entire board must be replaced for each test, increasing testing costs. Therefore, how to achieve convenient and practical quantum chip testing in ultra-low temperature environments is a current technical challenge.

[0003] Therefore, existing technologies still need to be improved and developed. Summary of the Invention

[0004] In view of the shortcomings of the prior art, this application provides a testing device and method for quantum chips, which separates the test board and the wire bonding board, and realizes a quantum chip testing solution suitable for wire-bonded packaging from room temperature to ultra-low temperature through plug-in or snap-in design. It can not only realize the simultaneous testing of multiple chips in ultra-low temperature environment, reduce the damage to the chips caused by soldering, but also flexibly plug or snap, realize convenient operation and reusability of test board, and be compatible with different testing instruments, improve efficiency, reduce costs and improve scalability.

[0005] This application is achieved through the following technical solution:

[0006] A first aspect of this application is to provide a testing apparatus for a quantum chip, including a wire-binding plate and a test board detachably connected to the wire-binding plate;

[0007] Specifically, the wire binding plate includes a first connection structure, and the test board includes a second connection structure adapted to the first connection structure. When the first connection structure and the second connection structure are connected together, a communication connection between the wire binding plate and the test board is realized.

[0008] Specifically, the first connection structure is a plug structure, and the second connection structure is a slot structure that can accommodate the plug and is adapted to the plug.

[0009] Specifically, the second connection structure is the plug structure, and the first connection structure is the slot structure that can accommodate the plug structure and is adapted to the plug structure.

[0010] Specifically, the bonding plate further includes a chip fixing area for fixing the chip, and there is a gap between the chip fixing area and the first connection structure to facilitate bonding the chip. The chip is fixed on the chip fixing area by a bonding process.

[0011] Specifically, the binding plate further includes a first wire, which connects the first connection structure and the chip fixing area to provide a communication connection between the quantum chip and the first connection structure to achieve signal transmission.

[0012] Specifically, the test board further includes a second conductor and an interface; the interface includes a microwave high-frequency interface, a ribbon cable interface, and a micro-device interface, used to provide devices suitable for different testing scenarios. The two ends of the second conductor are respectively connected to the interface and the second connection structure, used to provide a communication connection between the interface and the second connection structure to realize the transmission of the signal.

[0013] Specifically, the test board further includes functional modules for improving the performance of the test device according to test requirements; the functional modules include one or more electrostatic discharge modules, line conversion modules, and analog-to-digital conversion modules. The electrostatic discharge module is used to prevent static electricity and improve the robustness of the test board; the multiplexing module is used to control the signal transmission lines; and the analog-to-digital conversion module is used to convert analog signals into digital signals.

[0014] Specifically, the testing apparatus for the quantum chip of this application further includes a quantum computer, a testing module, and a third wire; the testing module and the quantum computer are respectively communicatively connected to the testing board through the third wire to realize the transmission of the signal. The testing module is communicatively connected to the quantum computer to realize the transmission of the signal.

[0015] Specifically, the testing module includes a parsing unit, a signal generation unit, and a signal processing unit. The parsing unit receives test commands and sends them to the signal generation unit; the signal generation unit receives the test commands, generates pulse signals, and sends them to the test board; the signal processing unit receives the result signals returned by the chip, analyzes them, and sends them to the quantum computer.

[0016] The test board also includes functional modules for improving the performance of the test device according to test requirements. These functional modules include one or more electrostatic discharge modules, a circuit conversion module, and an analog-to-digital conversion module. The electrostatic discharge module is connected to the interface and the quantum computer via the third wire to prevent static electricity and improve the robustness of the test board. The multiplexing module is connected to the interface and the quantum computer via the third wire to control the signal transmission lines during the testing of multiple chips. The analog-to-digital conversion module is connected to the interface and the quantum computer via the third wire to convert analog signals emitted by the quantum computer into digital signals.

[0017] A second aspect of this application is to provide a testing method for a quantum chip, comprising: performing testing using a quantum chip testing apparatus as described above.

[0018] Compared with the prior art, this application has the following advantages: Compared with the prior art, the quantum chip testing device of this application has the following advantages:

[0019] (1) Low cost: In the prior art, the wire bonding board and the test board are integrated, and the test board cannot be reused. However, this application uses a flexible plug-in or snap-on structure to set the wire bonding board as a disposable consumable, and the test board can be reused, which reduces the cost of the test board and its interface and functional modules.

[0020] (2) High compatibility and expandability: Different ultra-low temperature test devices with different cooling capabilities or different application types of chip testing correspond to different interfaces. The separate design of the wire bonding board and the test board in this application uses the wire bonding board as a consumable and the test board as a reusable test platform. As a result, the test board, which was originally limited by cost, can accommodate more different test interfaces and adopt higher-level soldering technology. Additional test systems such as digital control multiplexers, analog-to-digital converters, and digital signal processing modules can be added to create a well-packaged, highly compatible, and powerful expandable multi-purpose test board, which is more suitable for different chips, test instruments, or test environments.

[0021] (3) High testing efficiency and reliability: The application of plug-in or snap-on structures in this application simplifies the connection between chip samples and testing equipment. When testing multiple samples, changing samples only requires the matching connection of the first and second connection structures. By designing the internal circuit interface of the chip and pre-planning the position of the chip fixing area on the wire bonding board, multiple sample operations can be changed by simply plugging or snapping without changing the rest of the wiring, which greatly reduces the testing difficulty and significantly improves the testing efficiency in ultra-low temperature chip testing with a long testing cycle. In addition, the same testing instrument can correspond to the same test board. The universal plug-in or snap-on structure greatly unifies the signal path between different samples. Furthermore, by designing the wires on the test board and selecting the interface specifications and types, the testing conditions can be made more rigorous, avoiding signal loss or errors caused by different path interfaces and additional adapter boards, and improving the reliability of the data obtained from chip testing. In addition, during ultra-low temperature environment testing, multiple test boards can be connected at once and placed in the ultra-low temperature environment to perform performance testing on the chips on multiple test boards simultaneously, avoiding the long heating and cooling time required in the prior art. Therefore, this application can improve the testing efficiency of quantum chips in ultra-low temperature environments.

[0022] (4) Scientific nature, fundamental nature and rich application prospects: This application improves the disadvantage of low-cost wire bonding packaging method in integration and transfer operation by separating the wire bonding board and the test board, and enhances the compatibility function of the test board. As a fundamental design, adding additional equipment or expansion modules can extend the design to different test application directions and achieve good transformation. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a structural diagram of a quantum chip testing device according to an embodiment of this application.

[0025] Figure 2 This is a schematic diagram of a test board connected to multiple wire-binding plates, according to an embodiment of this application.

[0026] Figure 3 This is a schematic diagram of the signal transmission of a test apparatus for a quantum chip according to an embodiment of this application.

[0027] Figure 4This is a flowchart of a testing method for a quantum chip according to an embodiment of this application. Detailed Implementation

[0028] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0029] It should be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the embodiments of this application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0030] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0031] After quantum chips are fabricated, their parameters and performance need to be tested to ensure high quality. Current chip testing methods employ wire bonding, connecting the chip's internal circuitry to a gold-plated copper foil test circuit board using gold or aluminum wires. After bonding, black adhesive is applied for insulation and protection before testing. However, quantum chips require ultra-low temperature environments (as low as 10 mK, approximately -273°C) to maintain their quantum states. The measurement and control circuitry of qubits and other surrounding circuits need to be set up in ultra-low temperature environments at different temperatures. Compared to chip testing for conventional consumer electronics applications, ultra-low temperature chip testing for quantum computing is far more demanding in terms of temperature, and the ultra-low temperature environment presents challenges to instruments, packaging methods, and testing hardware. Therefore, traditional wire bonding methods cannot meet the requirements for quantum chip testing. Furthermore, existing testing devices use disposable wire bonding boards, with the test board fixed to the board; the entire board must be replaced for each test, increasing testing costs. Therefore, how to achieve convenient and practical quantum chip testing in ultra-low temperature environments is a current technical challenge.

[0032] In view of the shortcomings of the prior art, this application provides a testing device and method for quantum chips, which separates the test board and the wire bonding board, and realizes a quantum chip testing solution suitable for wire-bonded packaging from room temperature to ultra-low temperature through a pluggable design. It can not only realize testing in ultra-low temperature environment and reduce the damage to the chip caused by soldering, but also flexibly plug and unplug, realize convenient operation and reusability of test board, and be compatible with different testing instruments. It can also test multiple quantum chips at one time, improve efficiency and reduce costs.

[0033] like Figure 1 As shown, a first aspect of this application is to provide a testing apparatus for a quantum chip, including a wire-binding plate 10, a test board 20, a test module 30, and a quantum computer 40.

[0034] The wire binding plate 10 and the test board 20 are separate from each other but detachably connected. The wire binding plate 10 includes a first connection structure 11, and the test board 20 includes a second connection structure 21 adapted to the first connection structure 11. When the first connection structure and the second connection structure are connected together, the wire binding plate and the test board are connected to each other.

[0035] The first connection structure 11 and the second connection structure 21 are snapped together to realize the communication connection between the wire binding plate 10 and the test board 20.

[0036] Specifically, the first connection structure 11 and the second connection structure 21 are plug-in connected, and plugging in the first connection structure 11 and the second connection structure 21 realizes the communication connection between the cable tie plate 10 and the test board 20. Optionally, the first connection structure 11 is a plug structure, and the second connection structure 21 is a slot structure that can accommodate the plug and is adapted to the plug. Specifically, one test board 20 can connect to multiple cable tie plates 10, such as... Figure 2 As shown, the second connection structure 21 of the test board 20 is a slot structure, and the first connection structure 11 of the wire-binding board 10 is a plug structure. When the plug is inserted into the slot, the wire-binding board and the test board can be connected. When the plug is pulled out of the slot, the wire-binding board 10 and the test board 20 can be separated. This design facilitates insertion and removal; each test only requires replacing the wire-binding board 10 with a different chip, and the test board can be reused, which helps save testing costs. At the same time, in conventional test devices where the wire-binding board and the test board are fixed together, replacing the chip requires disassembling the wires and resoldering the chip, which may damage the chip and cause additional losses. The pluggable design of this application can avoid multiple wire-binding and packaging, reduce chip wear, and the wire-binding board is for single use, while the test board can be reused multiple times.

[0037] Alternatively, the first connection structure 11 can be designed as a slot structure and the second connection structure 21 as a plug structure, which can also realize the plug-in connection function. However, the disadvantage is that since the slot is larger than the plug, if the slot is installed on the cable tie plate 10, the thickness of the slot may affect the bonding of the chip.

[0038] Optionally, a test board can be equipped with multiple second connection structures 21 for connecting multiple binding plates, enabling simultaneous performance testing of multiple quantum chips. Since quantum chips require an environment of -273℃ to maintain their quantum state, testing their performance necessitates placing the chip inside a cryostat, which takes approximately 3 hours to cool from room temperature to ultra-low temperature. After testing, the chip can only be removed after returning to room temperature, again requiring approximately 3 hours. Therefore, each test consumes a significant amount of time during the temperature rise and fall process. Furthermore, once the sample is placed in the cryostat, it cannot be manipulated or its appearance observed during the entire testing process. With this device, the binding plate 10 and the test board 20 are independent structures, allowing for plug-and-play connection and disconnection of the binding plates. Multiple binding plates 10 can be connected to a single test board 20, with one chip placed on each binding plate 10. This allows for simultaneous testing of multiple chips and implementation of multiple test schemes without repeated temperature rise and fall cycles, thus improving testing efficiency.

[0039] Specifically, such as Figure 1 As shown, the bonding plate 10 further includes a chip fixing area 12 and a first wire 13. The chip fixing area is used to fix the chip, and there is a gap between the chip fixing area 12 and the first connecting structure 11 to facilitate bonding the chip. Preferably, the main body of the bonding plate 10 is square, the center of the chip fixing area 12 coincides with the center of the bonding plate, the first connecting structure 11 is located on one side of the square and protrudes towards the test board 20, and the protruding plug is adapted to the groove size of the second connecting structure 21.

[0040] The chip is fixed to the chip fixing area using a bonding process. Specifically, the internal circuitry of the chip is connected to the gold-plated copper foil (gold finger) area (not shown in the figure) of the bonding plate 10 using gold or aluminum wires. After bonding, black adhesive is applied for insulation and protection. The first conductor 13 connects the first connection structure 11 and the chip fixing area 12 to provide a communication connection between the quantum chip and the first connection structure 11, thereby enabling signal transmission. The first conductor 13 can be directly printed on the bonding plate 10.

[0041] Preferably, the wire binding plate 10 may also be provided with an interface (not shown), which can be connected to a testing instrument via a wire, thereby enabling performance testing of the chip fixed on the wire binding plate 10.

[0042] Specifically, the test board 20 also includes an interface 22, a functional module 23, and a second wire 24.

[0043] Specifically, the two ends of the second wire are respectively connected to the interface 22 and the second connection structure 21, providing a communication connection between the interface 22 and the second connection structure 21 to realize signal transmission. Specifically, the interface 22 is connected to the test module 30 via the third wire, receiving signals from the test module 30. The signals emitted by the test module 30 sequentially pass through the third wire 31, interface 22, second wire 24, second connection structure 21, first connection structure 11, and first wire 13, and are transmitted to the quantum chip fixed in the chip fixing area 12. The response signal generated by the quantum chip is then transmitted back to the test module 30, thereby realizing a closed-loop signal in the performance testing process. Different interface types can be set according to testing requirements. Preferably, the interface includes microwave high-frequency interface (SMA interface), 60-channel ribbon cable interface, WeChat device interface (such as 15-pin Micro D interface), etc. The SMA interface can adapt to different testing scenarios and has a high signal transmission speed. The 15-pin Micro D interface has 15 signal transmission channels, is small in size, and has many channels.

[0044] The functional module 23 is connected to the quantum computer 40 via a third wire 31, and is used to set different performance enhancements for the testing device according to testing requirements. The functional module includes one or more parallel-connected electrostatic discharge (ESD) modules, line conversion modules, and analog-to-digital conversion modules. The ESD module is connected to the interface and the quantum computer via the third wire, respectively, to prevent static electricity and improve the robustness of the test board. The multiplexing module is connected to the interface and the quantum computer via the third wire, respectively, to control the signal transmission lines when testing multiple chips, especially when testing multiple chips simultaneously. It controls the signal transmission lines by connecting multiple chip-bearing bonding plates to the test board at once, controlling the signals sent to different chips and receiving result signals from different chips, and transmitting them to the quantum computer. This allows for simultaneous testing of the performance of multiple chips, avoiding the repeated steps of installing and connecting the test board and bonding plates. In particular, in the prior art, when testing quantum chips in low-temperature or even ultra-low-temperature testing environments, the cooling and heating processes of the refrigerator are lengthy. The pluggable test board and wire-binding board of this application allow for the simultaneous connection of multiple wire-binding boards, avoiding the need to wait for the temperature to drop to an ultra-low temperature environment before chip replacement and the need to wait for the temperature to rise to room temperature after testing, thus improving testing efficiency. The analog-to-digital converter (ADC) module is used to convert analog signals into digital signals. Other functional module types are also possible.

[0045] In addition, the refrigerator has internal temperature zones during cooling. Only the bottom of the cold finger is the ultra-low temperature (4K) environment that meets the requirements for quantum chip performance testing. Since the refrigerator is a vacuum environment and vacuum does not conduct heat, in order to make the temperature of the sample reach the ultra-low temperature, it is necessary to select a material with good thermal conductivity to ensure that the binding plate and the cold finger are in full contact and that the sample is kept at the ultra-low temperature.

[0046] Optionally, the wire bonding board 10 and the test board 20 are PCB boards, and circuits can be printed directly on the PCB board. Therefore, the first wire 13 can be directly printed on the wire bonding board 10, and the second wire 24 can be directly printed on the test board 20.

[0047] like Figure 3 As shown, the test module 30 comprises various types of testing instruments, including a parsing unit 32, a signal generation unit 33, and a signal processing unit 34. The quantum computer includes an interface terminal 41. After the chip is bonded to the bonding plate 10 and the bonding plate 10 is connected to the test board, the signal transmission process during testing is as follows: control commands are sent from the interface terminal of the quantum computer 40 to the test module 30. The parsing unit 32 of the test module 30 analyzes the commands and sends them to the signal generation unit 33. The signal generation unit 33 generates pulse signals and sends them to the test board 20. The test board 20 sends the signals to the chip on the bonding plate 10, and then the result signal is returned from the chip to the test board 20, and then transmitted to the signal processing unit 34 of the test module. The signal processing unit analyzes the result signal and sends it to the interface terminal, thus displaying the test result information on the quantum computer 40. Simultaneously, the interface terminal 41 on the quantum computer 40 can also directly control the test board 20, specifically controlling the functional modules 23 on the test board 20, such as... Figure 1 As shown, the quantum computer 40 is connected to the functional module 23 via a third wire, thereby enabling control of circuit switching.

[0048] Preferably, the testing module is a testing instrument, which can be selected according to the actual testing requirements. The quantum computer can also be replaced by a numerical control system.

[0049] The first and second connection structures of this application can also be configured as detachable and mutually compatible snap-fit ​​structures. The snap-fit ​​structure can also provide communication connection, enabling flexible connection between the test board and the wire bonding board.

[0050] Compared with existing technologies, the quantum chip testing device of this application has the following advantages:

[0051] (1) Low cost: In the prior art, the wire bonding board and the test board are integrated, and the test board cannot be reused. However, this application uses a flexible plug-in or snap-on structure to set the wire bonding board as a disposable consumable, and the test board can be reused, which reduces the cost of the test board and its interface and functional modules.

[0052] (2) High compatibility and expandability: Different ultra-low temperature test devices with different cooling capabilities or different application types of chip testing correspond to different interfaces. The separate design of the wire bonding board and the test board in this application uses the wire bonding board as a consumable and the test board as a reusable test platform. As a result, the test board, which was originally limited by cost, can accommodate more different test interfaces and adopt higher-level soldering technology. Additional test systems such as digital control multiplexers, analog-to-digital converters, and digital signal processing modules can be added to create a well-packaged, highly compatible, and powerful expandable multi-purpose test board, which is more suitable for different chips, test instruments, or test environments.

[0053] (3) High testing efficiency and reliability: The application of plug-in or snap-on structures in this application simplifies the connection between chip samples and testing equipment. When testing multiple samples, changing samples only requires the matching connection of the first and second connection structures. By designing the internal circuit interface of the chip and pre-planning the position of the chip fixing area on the wire bonding board, multiple sample operations can be changed by simply plugging or snapping without changing the rest of the wiring, which greatly reduces the testing difficulty and significantly improves the testing efficiency in ultra-low temperature chip testing with a long testing cycle. In addition, the same testing instrument can correspond to the same test board. The universal plug-in or snap-on structure greatly unifies the signal path between different samples. Furthermore, by designing the wires on the test board and selecting the interface specifications and types, the testing conditions can be made more rigorous, avoiding signal loss or errors caused by different path interfaces and additional adapter boards, and improving the reliability of the data obtained from chip testing. In addition, during ultra-low temperature environment testing, multiple test boards can be connected at once and placed in the ultra-low temperature environment to perform performance testing on the chips on multiple test boards simultaneously, avoiding the long heating and cooling time required in the prior art. Therefore, this application can improve the testing efficiency of quantum chips in ultra-low temperature environments.

[0054] (4) Scientific nature, fundamental nature and rich application prospects: This application improves the disadvantage of low-cost wire bonding packaging method in integration and transfer operation by separating the wire bonding board and the test board, and enhances the compatibility function of the test board. As a fundamental design, adding additional equipment or expansion modules can extend the design to different test application directions and achieve good transformation.

[0055] A second aspect of this application is to provide a testing method for a quantum chip, implemented using the aforementioned quantum chip testing apparatus, such as... Figure 4 As shown, the specific steps include:

[0056] S1. Bind the quantum chip onto the wire bonding board, connect the wire bonding board to the test board, and then connect the test board to the test module and the quantum computer.

[0057] S2. Place the binding plate in a test environment at room temperature or ultra-low temperature;

[0058] S3. Select a control circuit on the control interface of the quantum computer and send instructions;

[0059] S4. Record the result information on the control interface to complete the performance test.

[0060] Specifically, the process of converting instructions into result information involves the transmission and conversion of model numbers in different components, as follows:

[0061] S5. The parsing unit parses the instruction and sends it to the signal generation unit, thereby generating a pulse signal and sending it to the test board;

[0062] S6. The test board receives the pulse signal and sends it to the quantum chip on the wire bonding board;

[0063] S7. The quantum chip generates a response signal based on the pulse signal and sends it to the test board. The test board then sends the response signal to the signal processing unit of the test module.

[0064] S8, the signal processing unit analyzes the response signal and sends the analysis results to the interface terminal, thereby completing the performance test.

[0065] In summary, this application provides a testing device for quantum chips, including a wire-binding board and a test board detachably connected to the wire-binding board. The wire-binding board includes a first connection structure, and the test board includes a second connection structure adapted to the first connection structure. When the first connection structure and the second connection structure are connected together, a communication connection is achieved between the wire-binding board and the test board. This quantum chip testing device separates the test board and the wire-binding board, and through a plug-in or snap-fit ​​design, provides a quantum chip testing solution suitable for wire-binded packaging from room temperature to ultra-low temperature. It not only enables simultaneous testing of multiple chips in ultra-low temperature environments, reducing chip damage caused by soldering, but also allows for flexible plug-in or snap-fit ​​connections, facilitating convenient operation and reusability of the test board. Furthermore, it is compatible with different testing instruments, improving efficiency, reducing costs, and enhancing scalability.

[0066] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions are not in essence a departure from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A testing device for a quantum chip, characterized in that, Includes a wire binding plate and a test plate detachably connected to the wire binding plate; The wire-binding plate includes a first connection structure, and the test board includes a second connection structure adapted to the first connection structure. When the first connection structure and the second connection structure are connected together, a communication connection between the wire-binding plate and the test board is realized. The cable binding board is a PCB board; The wire-binding plate also includes a chip fixing area for fixing the quantum chip. There is a gap between the chip fixing area and the first connection structure to facilitate the binding of the quantum chip. The quantum chip is fixed on the chip fixing area by a wire-binding process. The wire bonding plate also includes a first wire directly printed on the wire bonding plate. The first wire connects the first connection structure and the chip fixing area respectively to provide a communication connection between the quantum chip and the first connection structure to realize signal transmission. The first connection structure and the second connection structure are pluggable connections, and the first connection structure and the second connection structure are plugged in to realize the communication connection between the wire binding plate and the test board; The quantum chip is used for testing in an ultra-low temperature environment; The test board also includes: a second wire and an interface; The interfaces include microwave high-frequency interfaces, ribbon cable interfaces, and micro device interfaces, which are used to provide devices suitable for different testing scenarios; The two ends of the second conductor are respectively connected to the interface and the second connection structure to provide a communication connection between the interface and the second connection structure to realize the transmission of the signal; the test board is a PCB board, and the second conductor is directly printed on the test board.

2. The testing device for a quantum chip according to claim 1, characterized in that, The first connection structure is a plug structure, and the second connection structure is a slot structure that can accommodate the plug and is adapted to the plug; or, the second connection structure is the plug structure, and the first connection structure is the slot structure that can accommodate the plug structure and is adapted to the plug structure.

3. The testing device for a quantum chip according to claim 1, characterized in that, It also includes a quantum computer, a test module, and a third wire; The test module and the quantum computer are respectively connected to the test board via the third wire to realize the transmission of the signal; The test module is communicatively connected to the quantum computer to enable the transmission of the signal.

4. The testing device for a quantum chip according to claim 3, characterized in that, The test module includes a parsing unit, a signal generation unit, and a signal processing unit; The parsing unit is used to receive test commands and send them to the signal generation unit; The signal generation unit receives the test command, generates a pulse signal, and sends it to the test board; The signal processing unit receives the result signal returned by the chip, analyzes it, and sends it to the quantum computer.

5. The testing device for a quantum chip according to claim 3, characterized in that, The test board also includes functional modules for improving the performance of the test device according to test requirements; the functional modules include one or more electrostatic discharge modules, circuit conversion modules, and analog-to-digital conversion modules. The electrostatic discharge module is connected to the interface and the quantum computer respectively via the third wire to prevent static electricity and improve the robustness of the test board. The line conversion module is connected to the interface and the quantum computer respectively via the third wire, and is used to control the signal transmission line during the testing of multiple chips; The analog-to-digital conversion module is connected to the interface and the quantum computer via the third wire, and is used to convert the analog signals emitted by the quantum computer into digital signals.

6. A testing method for a quantum chip, characterized in that, include: The test was performed using the test apparatus for the quantum chip as described in any one of claims 1-5.

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