Time sequence error detection circuit and method, chip and electronic equipment

Abstract

The embodiment of the invention provides a time sequence error detection circuit and method, a chip and electronic equipment, and relates to the field of integrated circuits, the time sequence error detection circuit comprises a clock input end, N first data input ends, a delay inverting unit and a detection unit; the clock input end is used for receiving a clock input signal which is the same as that of the to-be-tested time sequence unit; for any first data input end, the first data input end is used for receiving a data input signal which is the same as a corresponding second data input end in the time sequence unit to be tested; the delay inverting unit is connected with the N first data input ends and is used for performing specified processing on the received N data input signals to obtain respective corresponding delay inverting signals; and the detection unit is connected with the N first data input ends, the clock input end and the delay inversion unit respectively, and is used for outputting a time sequence error result under the condition that the clock input signal is an effective level and the level of at least one data input signal is the same as that of the corresponding delay inversion signal.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of integrated circuit technology, and in particular, to a timing detection circuit, method, chip and electronic device. Background Art

[0002] During the manufacturing and operation of the chip, the actual parameters of the chip may deviate from the results of theoretical analysis to varying degrees due to the influence of the manufacturing process, operating voltage and temperature. In the prior art, a timing error detection circuit can be used to monitor in real time whether there is a timing error during the operation of the chip to obtain the actual performance of the chip.

[0003] However, the timing error detection circuit in the prior art usually sets a timing unit corresponding to the additional storage bit, and compares the sampling results of the timing units corresponding to the original storage bit and the additional storage bit to determine whether a timing error occurs at the clock input terminal and the data input terminal of the timing unit corresponding to the original storage bit.

[0004] Since the timing error detection circuit in the prior art adds timing units, sampling and comparison circuits corresponding to additional storage bits, the number of circuit elements increases, resulting in the existing timing error detection circuit having problems of large area overhead and slow response time. Summary of the invention

[0005] In view of the above problems, the embodiments of the present application propose a timing error detection circuit, method, chip and electronic device to solve the problems of large area overhead and slow response time of the timing error detection circuit in the prior art.

[0006] In a first aspect, an embodiment of the present application provides a timing error detection circuit, the timing error detection circuit comprising a clock input terminal, N first data input terminals, a delay inversion unit and a detection unit; N is a positive integer;

[0007] The clock input terminal is used to receive the same clock input signal as the timing unit to be tested, and send the clock input signal to the detection unit;

[0008] For any of the first data input terminals, the first data input terminal is used to receive a data input signal identical to a corresponding second data input terminal in the timing unit to be tested, and send the data input signal to the delay inversion unit and the detection unit;

[0009] The delayed inverting unit is connected to the N first data input terminals respectively, and is used to perform designated processing on the received N data input signals to obtain the corresponding delayed inverted signals, and send the N delayed inverted signals to the detection unit; the delayed inverted signal is opposite in phase to the corresponding data input signal and has a preset phase difference;

[0010] The detection unit is connected to the N first data input terminals, the clock input terminal and the delayed inverting unit respectively, and is used to output a timing error result when the clock input signal is at a valid level and the level of at least one of the data input signals and the corresponding delayed inverting signal is the same.

[0011] Optionally, the detection unit includes a falling edge detection subunit and a rising edge detection subunit;

[0012] The falling edge detection subunit and the rising edge detection subunit are respectively connected to the N first data input terminals, the clock input terminal and the delay inversion unit;

[0013] The falling edge detection subunit is used to output the timing error result when the clock input signal is at a valid level and at least one of the data input signals and the corresponding delayed inverted signal are at a low level;

[0014] The rising edge detection subunit is used to output the timing error result when the clock input signal is at a valid level and at least one of the data input signals and the corresponding delayed inverted signal are both at a high level.

[0015] Optionally, the timing error result is a high level signal; the effective level is a high level; the falling edge detection subunit includes a first power supply terminal, a first ground terminal, a first detection output terminal, a first transistor and a first detection component;

[0016] The first detection component is connected to the N first data input terminals, the delayed inverting unit, the first power supply terminal and the first detection output terminal respectively, and is used to conduct the first power supply terminal and the first detection output terminal when at least one of the data input signals and the corresponding delayed inverting signal are both at low levels;

[0017] One end of the first transistor is connected to the first detection output end, and the other end is connected to the first ground end, and is used to disconnect the first detection output end and the first ground end when the inverted signal corresponding to the clock input signal is at a low level;

[0018] The first detection output terminal is used to output a high level signal corresponding to the first power terminal when it is connected to the first power terminal and disconnected from the first ground terminal.

[0019] Optionally, the timing error result is a high level signal; the effective level is a high level; the rising edge detection subunit includes a second power supply terminal, a third power supply terminal, a second ground terminal, a second detection output terminal, a second transistor, a third transistor and a second detection component;

[0020] The second detection component is connected to the N first data input terminals, the delayed inverting unit, the third transistor and the second ground terminal respectively, and is used to turn on the third transistor and the second ground terminal when at least one of the data input signals and the corresponding delayed inverting signal are both at high levels;

[0021] One end of the second transistor is connected to the second power supply end, and the other end is connected to the third transistor, and is used to disconnect the second power supply end and the third transistor when the clock input signal is at a high level;

[0022] The third transistor is connected to the third power supply terminal and the second detection output terminal respectively, and is used to conduct the third power supply terminal and the second detection output terminal when the third transistor is connected to the second ground terminal;

[0023] The second detection output terminal is used to output a high level signal corresponding to the third power supply terminal.

[0024] Optionally, the first detection component includes N pairs of fourth transistors and fifth transistors;

[0025] For any of the fourth transistors, the fourth transistor is connected to the delay inversion unit, the first power supply terminal and the fifth transistor respectively, and is used to turn on the first power supply terminal and the fifth transistor when the delayed inversion signal obtained from the delay inversion unit is at a low level;

[0026] For any of the fifth transistors, the fifth transistor is respectively connected to the corresponding first data input terminal, the fourth transistor and the first detection output terminal, and is used to turn on the first power supply terminal and the first detection output terminal when the data input signal obtained from the corresponding first data input terminal is at a low level.

[0027] Optionally, the second detection component includes N pairs of sixth transistors and seventh transistors;

[0028] For any of the sixth transistors, the sixth transistor is connected to the corresponding first data input terminal, the seventh transistor and the second ground terminal respectively, and is used to turn on the seventh transistor and the second ground terminal when the data input signal obtained from the corresponding first data input terminal is at a high level;

[0029] For any of the seventh transistors, the seventh transistor is connected to the delayed inverting unit, the third transistor and the sixth transistor respectively, and is used to turn on the third transistor and the second ground terminal when the delayed inverting signal obtained from the delayed inverting unit is at a high level.

[0030] Optionally, the delay inversion unit includes N inverters;

[0031] For any of the inverters, the inverter is connected to the corresponding first data input terminal and the detection unit respectively, and is used to perform specified processing on the data input signal obtained from the corresponding first data input terminal to obtain a corresponding delayed inverted signal, and send the delayed inverted signal to the detection unit.

[0032] In a second aspect, an embodiment of the present application provides a timing error detection method, which is applied to the timing error detection circuit as described in the first aspect, wherein the timing error detection circuit includes a clock input terminal, N first data input terminals, a delay inversion unit, and a detection unit, and the method includes:

[0033] Receiving a clock input signal identical to that of the timing unit to be tested through the clock input terminal, and sending the clock input signal to the detection unit;

[0034] For any of the first data input terminals, receiving a data input signal identical to a corresponding second data input terminal in the timing unit to be tested through the first data input terminal, and sending the data input signal to the delay inversion unit and the detection unit;

[0035] The N received data input signals are processed by the delayed inversion unit to obtain corresponding delayed inversion signals, and the N delayed inversion signals are sent to the detection unit; the delayed inversion signal is opposite in phase to the corresponding data input signal and has a preset phase difference;

[0036] The detection unit outputs a timing error result when the clock input signal is at a valid level and the levels of at least one of the data input signals and the corresponding delayed inverted signal are the same.

[0037] In a third aspect, an embodiment of the present application provides a chip, wherein the chip includes the timing error detection circuit as described in the first aspect.

[0038] In a fourth aspect, an embodiment of the present application provides an electronic device, which includes the chip as described in the third aspect.

[0039] In a fifth aspect, an embodiment of the present application provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the steps of the method described in the second aspect are implemented.

[0040] In the embodiment of the present application, a delayed inverted signal having a phase opposite to that of the data input signal and having a preset phase difference is obtained by a delayed inverted unit. When the clock input signal is at an effective level, if the detection unit detects that the data input signal and the corresponding delayed inverted signal are in the same phase, it indicates that a signal jump has occurred in the data input signal, and the data input signal becomes the same phase as the delayed inverted signal, and the data input signal after the jump has a region with the same phase as the delayed inverted signal. In the prior art, when the clock input signal is at an effective level, if the timing of the data input signal and the clock input signal of the timing unit to be tested is correct, the data input signal will not undergo a signal jump. The timing error detection circuit of the embodiment of the present application receives a clock input signal and N data input signals that are the same as those of the timing unit to be tested through a clock input terminal and N first data input terminals. When the clock input signal is at a valid level, if the detection unit detects that at least one data input signal and the corresponding delayed inverted signal have the same level, it indicates that a timing error has occurred in the timing unit to be tested. In this way, it is possible to avoid adding timing units, sampling and comparison circuits corresponding to additional storage bits. Timing error detection of the timing unit to be tested can be achieved only by using delayed inverted units and detection units. The detection logic is simple and the number of circuit elements required is small. Therefore, the area overhead of the detection circuit can be reduced, and the reduction in the number of circuit elements can improve the response time of the circuit to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It is one of the schematic diagrams of an edge jump detection circuit in the prior art;

[0042] Figure 2 It is a schematic diagram of the circuit structure of a jump detector and a detection clock generator in the prior art;

[0043] Figure 3 This is the second schematic diagram of an edge jump detection circuit in the prior art;

[0044] Figure 4 It is one of the structural schematic diagrams of a timing error detection circuit provided in an embodiment of the present application;

[0045] Figure 5 It is a circuit diagram of a timing error detection circuit provided in an embodiment of the present application detecting a single-input trigger;

[0046] Figure 6 is a phase diagram of a data input signal and a delayed inverted signal provided in an embodiment of the present application;

[0047] Figure 7 It is a circuit diagram of a timing error detection circuit provided in an embodiment of the present application detecting a multi-input trigger;

[0048] Figure 8This is the second structural diagram of a timing error detection circuit provided in an embodiment of the present application;

[0049] Fig. 9 This is a third structural diagram of a timing error detection circuit provided in an embodiment of the present application;

[0050] Fig.10 It is a schematic diagram of the steps of a timing error detection method provided in an embodiment of the present application;

[0051] Fig.11 It is a structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0053] The terms "first", "second", etc. in the specification and claims of this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or at least two. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0054] In the prior art, a typical sequential circuit system includes a combinational logic circuit and a sequential logic circuit. The combinational logic circuit is used to implement the computing function, and the sequential logic circuit is used to maintain the state, which is mostly implemented by a trigger. The timing analysis of the sequential circuit system is based on a basic model consisting of two-level sequential units, called the transmitter and the capture end, and a combinational logic unit between the transmitter and the capture end. Assume that the clock period is T, and the maximum value of the sampling-output delay of the trigger is t c2q-max The maximum value of the combinational logic propagation delay or the maximum value of the data path is t dp-max The setup time of the trigger is required to be t setup , then the following timing constraints must be met to ensure the circuit works correctly, that is, formula (1):

[0055] T≥t c2q-max +t dp-max +t setup(1)

[0056] There are many non-ideal factors in the manufacturing and working process of the chip, which cause the actual parameters of the chip to deviate to varying degrees compared with the results of theoretical analysis. The parameter fluctuation of the chip mainly refers to the impact of the manufacturing process, voltage and temperature (Process Voltage Temperature, PVT) on the chip. The manufacturing process deviation directly causes the physical parameters of the chip to change, such as the substrate doping concentration, gate oxide thickness, channel length and width, and interconnection line width and thickness, which further leads to changes in the electrical characteristics of the chip, such as the threshold voltage, saturation current, gate capacitance of the transistor, and the capacitance and resistance of the interconnection line. These changes in electrical characteristics ultimately lead to changes in time parameters such as device delay, flip time, and wire propagation delay. The electrical performance of the device is closely related to its power supply voltage, which directly affects the size of the transistor's drive current. The decrease in the chip power supply voltage will inevitably lead to an increase in device delay. The temperature parameter is closely related to important parameters such as transistor threshold and mobility, and also affects the size of the resistance and capacitance of the interconnection line. Changes in temperature will inevitably lead to changes in device delay.

[0057] From formula (1), we can see that in order to ensure the correct operation of the sequential circuit, sufficient timing margin t must be reserved in the design. margin , and the timing margin must satisfy formula (2):

[0058] t margin =Tt c2q-max -t dp-max -t setup (2)

[0059] The reduction of silicon post due to the above-mentioned PVT fluctuations may eventually lead to performance degradation or even functional errors of the chip. In order to obtain the true silicon post, field timing detection technology is needed. Field timing detection can obtain the true performance of the chip. Field timing detection is an important method for quantitatively studying the differences between silicon pre- and silicon post-chips. It is of great significance for improving chip silicon post-performance and guiding silicon pre-design. Field timing detection circuits can be divided into two categories according to different detection methods: double sampling and edge jump detection. Double sampling detection circuits are mostly based on static complementary metal oxide semiconductors (CMOS). They use additional storage bits such as triggers or latches to compare with the sampling results of the original storage bits to determine whether a timing error has occurred. Edge jump detection circuits are mostly based on dynamic CMOS. They determine the timing error of the circuit by detecting whether the input data has a signal jump within a certain time window. Compared with edge jump detection circuits, double sampling detection circuits usually have the advantages of low design complexity and high circuit reliability, while edge jump detection circuits have an absolute advantage in circuit area overhead.

[0060] Figure 1 It is one of the schematic diagrams of the edge jump detection circuit in the prior art, such as Figure 1 As shown in FIG. 1 , the edge transition detection circuit is composed of a single latch, a detection clock (DC) generator, and a transition detector (TD). The transition detector (TD) is controlled by the detection clock (DC). The circuit structure of the transition detector TD and the detection clock (DC) generator is shown in FIG. Figure 2 As shown. If the data transition arrives before the rising edge of the clock signal, the short negative pulse on DC will turn off the detection function of TD, so the circuit will not report an error. If the input data transition time is later than the rising edge of the clock and is within the transparent window of the latch, the enabled TD will detect the transition of the latch internal node signal and generate a valid error signal.

[0061] Figure 3 This is the second schematic diagram of the edge jump detection circuit in the prior art, such as Figure 3 As shown in the figure, the warning flip-flop converts both the detection clock and the delayed data into short pulses. Figure 3 The edge detector based on the transmission gate can convert the data jump signal after buffer delay into a short pulse data signal. The alarm clock is a pulse clock signal converted from the system clock. Finally, the delayed data edge and the alarm clock signal are input into the dynamic NAND gate, and the dynamic NAND gate outputs the detection value. Figure 1 and Figure 3The two circuit structures in the present invention both use the edge jump detection method to construct the field timing detection circuit, but both have the problem that the number of circuit elements is large when constructing the circuit, resulting in excessive area overhead and slow circuit response time.

[0062] The embodiments of the present application are described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0063] Figure 4 FIG. 4 shows a schematic diagram of a timing error detection circuit provided in an embodiment of the present application. Figure 4 As shown, the timing error detection circuit 10 includes a clock input terminal 101, N first data input terminals 102, a delay inversion unit 103 and a detection unit 104; N is a positive integer;

[0064] The clock input terminal 101 is used to receive the same clock input signal as the timing unit to be tested, and send the clock input signal to the detection unit 104;

[0065] For any of the first data input terminals 102, the first data input terminal 102 is used to receive a data input signal identical to a corresponding second data input terminal in the timing unit to be tested, and send the data input signal to the delay inversion unit 103 and the detection unit 104;

[0066] The delayed inverting unit 103 is connected to the N first data input terminals 102 respectively, and is used to perform designated processing on the received N data input signals to obtain the corresponding delayed inverted signals, and send the N delayed inverted signals to the detection unit 104; the delayed inverted signal is opposite in phase to the corresponding data input signal and has a preset phase difference;

[0067] The detection unit 104 is respectively connected to the N first data input terminals 102, the clock input terminal 101 and the delayed inverting unit 103, and is used to output a timing error result when the clock input signal is at a valid level and the levels of at least one of the data input signals and the corresponding delayed inverting signal are the same.

[0068] In an embodiment of the present application, a timing error refers to a data input signal not meeting the timing requirements of the setup time and hold time of the corresponding clock input signal. Specifically, a signal jump occurs in the data input signal when the clock input signal is at a valid level, such as a high level. For example, the data input signal jumps from a high level to a low level, or the data input signal jumps from a low level to a high level.

[0069] In an embodiment of the present application, the timing unit to be tested may be a timing unit with a single storage bit or multiple storage bits. A timing unit with a single storage bit may include a second data input terminal, such as a single-input trigger, a single-input latch, etc. A timing unit with multiple storage bits may include multiple second data input terminals, such as multiple-input triggers, multiple-input latches, etc. This is only an example, and the embodiment of the present application does not limit this. Among them, a single storage bit is a single bit, and multiple storage bits are multiple bits. When N is 1, the timing error detection circuit 10 of the embodiment of the present application can perform timing error detection on a single-bit data input signal. When N is greater than 1, the timing error detection circuit 10 can perform timing error detection on a multi-bit data input signal.

[0070] In the embodiment of the present application, the clock input terminal 101 can be connected to the clock input terminal of the sequential unit to be tested, so as to receive the same clock input signal as the sequential unit to be tested. The N first data input terminals 102 can be connected to the N second data input terminals of the sequential unit to be tested in a one-to-one correspondence, so that any first data input terminal can receive the same data input signal as the corresponding second data input terminal.

[0071] In an embodiment of the present application, a data input signal enters a timing unit to be tested, and data sampling and data transmission are performed under the control of a clock input signal. For specific implementation methods, reference may be made to relevant descriptions in the prior art, and the embodiment of the present application does not impose any limitation thereto.

[0072] In the embodiment of the present application, the delayed inversion unit 103 may include N inverters, and the N inverters are connected to the N first data input terminals 102 in a one-to-one correspondence. The inverters may perform inversion processing on the acquired data input signal to obtain an inverted signal corresponding to the data input signal, and delay the inverted signal corresponding to the data input signal according to a preset phase difference to obtain a delayed inverted signal. The specific implementation of the inversion processing and the delay processing can refer to the relevant description of the prior art, which will not be repeated here.

[0073] In the embodiment of the present application, the detection unit 104 receives the clock input signal sent by the clock input terminal 101, receives N data input signals sent by the N first data input terminals 102, and receives N delayed inverted signals sent by the delayed inverted unit 103. When the clock input signal is at a valid level, the detection unit 104 can compare the N data input signals with their corresponding delayed inverted signals. If it is detected that a data input signal and the corresponding delayed inverted signal have the same phase, it indicates that a signal jump has occurred in the data input signal. Since there is a preset phase difference between the data input signal and the corresponding delayed inverted signal, the delayed inverted signal does not have a signal jump when the data input signal has a signal jump, so that after the data input signal has a signal jump, there is a region with the same phase as the corresponding delayed inverted signal, that is, a timing error has occurred.

[0074] In the embodiment of the present application, when the clock input signal is at a valid level, if the detection unit 104 detects that only one of the N data input signals has the same phase as the corresponding delayed inverted signal, then a timing error result is output. The timing error result may be a signal of a preset specific level, such as a high level signal. This is only an example, and the embodiment of the present application does not limit this.

[0075] In the embodiment of the present application, a delayed inverted signal having a phase opposite to that of the data input signal and having a preset phase difference is obtained by a delayed inverted unit. When the clock input signal is at an effective level, if the detection unit detects that the data input signal and the corresponding delayed inverted signal are in the same phase, it indicates that a signal jump has occurred in the data input signal, and the data input signal becomes the same phase as the delayed inverted signal, and the data input signal after the jump has a region with the same phase as the delayed inverted signal. In the prior art, when the clock input signal is at an effective level, if the timing of the data input signal and the clock input signal of the timing unit to be tested is correct, the data input signal will not undergo a signal jump. The timing error detection circuit of the embodiment of the present application receives a clock input signal and N data input signals that are the same as those of the timing unit to be tested through a clock input terminal and N first data input terminals. When the clock input signal is at a valid level, if the detection unit detects that at least one data input signal and the corresponding delayed inverted signal have the same level, it indicates that a timing error has occurred in the timing unit to be tested. In this way, it is possible to avoid adding timing units, sampling and comparison circuits corresponding to additional storage bits. Timing error detection of the timing unit to be tested can be achieved only by using delayed inverted units and detection units. The detection logic is simple and the number of circuit elements required is small. Therefore, the area overhead of the detection circuit can be reduced, and the reduction in the number of circuit elements can improve the response time of the circuit to a certain extent.

[0076] Figure 5A schematic diagram of a circuit for detecting a single-input trigger using a timing error detection circuit provided in an embodiment of the present application. Figure 5 As shown, the single-input flip-flop 20 includes a clock input terminal 201 and a second data input terminal 202. The first data input terminal 102 of the timing error detection circuit 10 is connected to the second data input terminal 202 of the single-input flip-flop, and receives a data input signal identical to the second data input terminal 202. The clock input terminal 101 of the timing error detection circuit 10 receives the same clock input signal as the single-input flip-flop 20. The data input signal enters the single-input flip-flop 20, and data sampling and data transmission are performed under the control of the clock input signal. The data input signal enters the timing error detection circuit 10, and the delay inversion unit 103 performs a specified process on the data input signal, obtains a corresponding delayed inversion signal, and sends it to the detection unit 104. The detection unit 104 compares the data input signal with the corresponding delayed inversion signal when the clock input signal is at a valid level, and outputs a timing error result when the data input signal and the corresponding delayed inversion signal have the same level.

[0077] Figure 6 is a phase diagram of a data input signal and a delayed inverted signal provided in an embodiment of the present application, such as Figure 6 As shown, when the data input signal D undergoes a signal jump, the data input signal D and the corresponding delayed inverted signal D_N have an overlap region with the same level. Specifically, when the data input signal D jumps from a high level to a low level, the overlap region with the delayed inverted signal D_N is a low level, and when the data input signal D jumps from a low level to a high level, the overlap region with the delayed inverted signal D_N is a high level.

[0078] Figure 7 A schematic diagram of a circuit for detecting a multi-input trigger by a timing error detection circuit provided in an embodiment of the present application. Figure 7As shown, the multi-input trigger 30 includes a clock input terminal 301 and N second data input terminals 302. The N first data input terminals 102 of the timing error detection circuit 10 are connected to the N second data input terminals 302 of the multi-input trigger in a one-to-one correspondence, and receive the same data input signal as the corresponding second data input terminal 302. The clock input terminal 101 of the timing error detection circuit 10 receives the same clock input signal as the multi-input trigger 30. The N data input signals enter the multi-input trigger 30, and data sampling and data transmission are performed under the control of the clock input signal. The N data input signals enter the timing error detection circuit 10, and the delay inversion unit 103 performs designated processing on the N data input signals respectively, obtains N corresponding delayed inversion signals and sends them to the detection unit 104. When the clock input signal is at a valid level, the detection unit 104 compares the N data input signals with the corresponding delayed inversion signals respectively, and outputs the timing error result when the level of at least one data input signal and the corresponding delayed inversion signal are the same.

[0079] Optionally, the detection unit 104 includes a falling edge detection subunit and a rising edge detection subunit;

[0080] The falling edge detection subunit and the rising edge detection subunit are connected to the N first data input terminals 102, the clock input terminal 101 and the delay inversion unit 103 respectively;

[0081] The falling edge detection subunit is used to output the timing error result when the clock input signal is at a valid level and at least one of the data input signals and the corresponding delayed inverted signal are at a low level;

[0082] The rising edge detection subunit is used to output the timing error result when the clock input signal is at a valid level and at least one of the data input signals and the corresponding delayed inverted signal are both at a high level.

[0083] In the embodiment of the present application, the data input signal undergoes a signal transition including: a high level transitions to a low level, and a low level transitions to a high level. When the data input signal transitions from a high level to a low level, a falling edge occurs, and when the data input signal transitions from a low level to a high level, a rising edge occurs.

[0084] In the embodiment of the present application, the falling edge detection subunit is used to detect whether the data input signal has a falling edge when the clock input signal is at a valid level, that is, the data input signal jumps from a high level to a low level, so that the data input signal and the corresponding delayed inverted signal are both at a low level, indicating that the data input signal and the clock input signal received by the timing detection circuit have a timing error, and therefore, the same data input signal and the clock input signal in the timing unit to be tested also have a timing error. The rising edge detection subunit is used to detect whether the data input signal has a rising edge when the clock input signal is at a valid level, that is, the data input signal jumps from a low level to a high level, so that the data input signal and the corresponding delayed inverted signal are both at a high level, indicating that the data input signal and the clock input signal received by the timing detection circuit have a timing error, and therefore, the same data input signal and the clock input signal in the timing unit to be tested also have a timing error.

[0085] In the embodiment of the present application, the data input signal and the corresponding delayed inverted signal are both low levels, indicating that the data input signal has a falling edge when the clock input signal is at a valid level, that is, the data input signal jumps from a high level to a low level, and the data input signal and the corresponding delayed inverted signal are both high levels, indicating that the data input signal has a rising edge when the clock input signal is at a valid level, that is, the data input signal jumps from a low level to a high level. The timing error detection circuit of the embodiment of the present application detects whether the data input signal has a falling edge or a rising edge through a falling edge detection subunit and a rising edge detection subunit respectively. In this way, the circuit parts used for falling edge detection and rising edge detection can be separated, so that the number of circuit elements passed by the timing error results corresponding to the falling edge or rising edge of the data input signal is reduced, and the response time of the timing error detection circuit can be improved to a certain extent.

[0086] Optionally, the timing error result is a high level signal; the effective level is a high level; the falling edge detection subunit includes a first power supply terminal, a first ground terminal, a first detection output terminal, a first transistor and a first detection component;

[0087] The first detection component is connected to the N first data input terminals 102, the delayed inverting unit 103, the first power supply terminal and the first detection output terminal respectively, and is used to conduct the first power supply terminal and the first detection output terminal when at least one of the data input signals and the corresponding delayed inverting signal are both at low levels;

[0088] One end of the first transistor is connected to the first detection output end, and the other end is connected to the first ground end, and is used to disconnect the first detection output end and the first ground end when the inverted signal corresponding to the clock input signal is at a low level;

[0089] The first detection output terminal is used to output a high level signal corresponding to the first power terminal when it is connected to the first power terminal and disconnected from the first ground terminal.

[0090] In the embodiment of the present application, the effective level corresponding to the clock input signal is a high level, indicating that the detection time window of the timing error detection circuit is a high level interval of the clock input signal. When the clock input signal is a low level, that is, when the timing error detection circuit is not in the detection time window, in order to prevent the signal jump of the data input signal outside the detection time window from causing an erroneous judgment, the level of the first detection output terminal can be set to be lower than the threshold voltage of the transistor, so that the first detection output terminal is recognized as a low level by the subsequent circuit.

[0091] In an embodiment of the present application, the first detection component can serve as a pull-up network. When the first detection component turns on the first power supply terminal and the first detection output terminal when at least one data input signal and the corresponding delayed inverted signal are both at a low level, the first power supply terminal can charge the first detection output terminal.

[0092] In an embodiment of the present application, the falling edge detection subunit may further include an inverter, which is connected to the clock input terminal, for obtaining a corresponding inverted signal according to the clock input signal, and sending the inverted signal corresponding to the clock input signal to the first transistor. The first transistor may be an N-type metal-oxide-semiconductor (N-Metal-Oxide-Semiconductor, NMOS) transistor, the gate of the NMOS transistor is connected to the inverter, the drain of the NMOS transistor is connected to the first detection output terminal, and the source of the NMOS transistor is connected to the first ground terminal. When the inverted signal corresponding to the clock input signal is at a low level, the NMOS transistor is turned off, thereby disconnecting the first detection output terminal from the first ground terminal.

[0093] In an embodiment of the present application, when the first detection output terminal is connected to the first power supply terminal and disconnected from the first ground terminal, the output signal of the first detection output terminal is pulled up by the first detection component, so that the first detection output terminal can output a high-level signal corresponding to the first power supply terminal, that is, output a timing error result.

[0094] In the embodiment of the present application, by determining whether at least one data input signal and the corresponding delayed inverted signal are both at a low level, it is convenient to control whether the first detection component is connected to the first detection output terminal and the first power supply terminal, and by determining whether the inverted signal corresponding to the clock input signal is at a low level, it is convenient to control whether the first transistor is connected to the first detection output terminal and the first ground terminal. In this way, when a timing error occurs, the first detection output terminal can be controlled to output a high-level signal corresponding to the first power supply terminal, i.e., a timing error result, when the first detection output terminal is connected to the first power supply terminal and disconnected from the first ground terminal, thereby realizing timing error detection. The detection logic is simple and the required circuit elements are relatively small, which can improve the practicality of the timing error detection circuit of the embodiment of the present application to a certain extent.

[0095] Optionally, the timing error result is a high level signal; the effective level is a high level; the rising edge detection subunit includes a second power supply terminal, a third power supply terminal, a second ground terminal, a second detection output terminal, a second transistor, a third transistor and a second detection component;

[0096] The second detection component is connected to the N first data input terminals 102, the delayed inverting unit 103, the third transistor and the second ground terminal respectively, and is used to turn on the third transistor and the second ground terminal when at least one of the data input signals and the corresponding delayed inverting signal are both at high levels;

[0097] One end of the second transistor is connected to the second power supply end, and the other end is connected to the third transistor, and is used to disconnect the second power supply end and the third transistor when the clock input signal is at a high level;

[0098] The third transistor is connected to the third power supply terminal and the second detection output terminal respectively, and is used to conduct the third power supply terminal and the second detection output terminal when the third transistor is connected to the second ground terminal;

[0099] The second detection output terminal is used to output a high level signal corresponding to the third power supply terminal.

[0100] In the embodiment of the present application, the effective level corresponding to the clock input signal is a high level, indicating that the detection time window of the timing error detection circuit is a high level interval of the clock input signal. When the clock input signal is a low level, that is, when the timing error detection circuit is not in the detection time window, in order to prevent the signal jump of the data input signal outside the detection time window from causing an erroneous judgment, the level of the second detection output terminal can be set to be lower than the threshold voltage of the transistor, so that the first detection output terminal is recognized as a low level by the subsequent circuit. Specifically, the type and size of the transistor can be adjusted to make the level of the second detection output terminal lower than the threshold voltage of the transistor. The adjustment method can refer to the relevant description in the prior art and will not be repeated here.

[0101] In the embodiment of the present application, the second transistor and the third transistor may be P-type metal-oxide-semiconductor (PMOS) transistors. The gate of the second transistor (PMOS transistor) is connected to the clock input terminal, the source is connected to the second power supply terminal, and the drain is connected to the third transistor. When the clock input signal is at a high level, the second transistor (PMOS transistor) turns itself off, thereby disconnecting the second power supply terminal and the third transistor.

[0102] In the embodiment of the present application, the gate of the third transistor (PMOS transistor) is connected to the second detection component, the source of the third transistor is connected to the third power supply terminal, and the drain of the third transistor is connected to the second detection output terminal. The second detection component can be used as a pull-down network. When the second detection component conducts the gate of the third transistor and the second ground terminal when at least one data input signal and the corresponding delayed inverted signal are both at a high level, the second ground terminal can discharge the third transistor.

[0103] In the embodiment of the present application, when the second detection component turns on the gate of the third transistor and the second ground terminal to discharge the third transistor, the third transistor (PMOS transistor) itself is turned on. Further, the third transistor (PMOS transistor) can turn on the third power supply terminal and the second detection output terminal, so that the second detection output terminal can output a high-level signal corresponding to the third power supply terminal, that is, output a timing error result.

[0104] In an embodiment of the present application, by determining whether at least one data input signal and a corresponding delayed inverted signal are both at a high level, it is convenient to control whether the second detection component turns on the third transistor and the second ground terminal, and by determining whether the clock input signal is at a high level, it is convenient to control whether the second transistor turns on the second power supply terminal and the third transistor. The third transistor can be controlled to be disconnected from the second power supply terminal and turned on the second ground terminal when a timing error occurs, so that the third transistor itself is turned on. Further, the third transistor can turn on the third power supply terminal and the second detection output terminal. In this way, the second detection output terminal can output a high-level signal corresponding to the third power supply terminal, i.e., a timing error result, when a timing error occurs, thereby realizing timing error detection. The detection logic is simple and fewer circuit elements are required, which can improve the practicality of the timing error detection circuit of the embodiment of the present application to a certain extent.

[0105] Optionally, the first detection component includes N pairs of fourth transistors and fifth transistors;

[0106] For any of the fourth transistors, the fourth transistor is connected to the delay inversion unit 103, the first power supply terminal and the fifth transistor respectively, and is used to turn on the first power supply terminal and the fifth transistor when the delayed inversion signal obtained from the delay inversion unit 103 is at a low level;

[0107] For any of the fifth transistors, the fifth transistor is respectively connected to the corresponding first data input terminal 102, the fourth transistor and the first detection output terminal, and is used to turn on the first power supply terminal and the first detection output terminal when the data input signal obtained from the corresponding first data input terminal 102 is at a low level.

[0108] In the embodiment of the present application, the fourth transistor and the fifth transistor may be PMOS transistors. Any pair of the fourth transistor and the fifth transistor may be connected in series with each other, and a pair of the fourth transistor and the fifth transistor may be connected in parallel with other pairs of the fourth transistor and the fifth transistor.

[0109] In the embodiment of the present application, for any pair of the fourth transistor and the fifth transistor, the source of the fourth transistor (PMOS transistor) is connected to the first power supply terminal, the gate of the fourth transistor is connected to the corresponding inverter in the delayed inversion unit 103, the drain of the fourth transistor is connected to the source of the fifth transistor (PMOS transistor), the gate of the fifth transistor is connected to the corresponding first data input terminal 102, and the drain of the fifth transistor is connected to the first detection output terminal.

[0110] In the embodiment of the present application, when the delayed inverting signal obtained from the delayed inverting unit 103 is at a low level, the fourth transistor (PMOS transistor) itself is turned on, and then the fourth transistor turns on the first power supply terminal and the source of the fifth transistor. When the data input signal obtained from the corresponding first data input terminal 102 is at a low level, the fifth transistor (PMOS transistor) itself is turned on, and then the fifth transistor turns on the first power supply terminal and the first detection output terminal, so that the first detection output terminal can output a high level signal corresponding to the first power supply terminal.

[0111] In the embodiment of the present application, for any pair of the N pairs of fourth transistors and fifth transistors, when the delayed inverted signal to be received by the fourth transistor and the data input signal received by the fifth transistor are both at a low level, the first power supply terminal and the first detection output terminal can be turned on, so that the first detection output terminal can output a high-level signal corresponding to the first power supply terminal, that is, a timing error result, thereby realizing timing error detection. In addition, the timing error detection circuit of the embodiment of the present application can determine the value of N according to the number of data input terminals of the timing unit to be tested, that is, flexibly set the number of pairs of the fourth transistor and the fifth transistor in the first detection component, thereby improving the flexibility of the circuit and reducing the circuit area overhead to a certain extent.

[0112] Optionally, the second detection component includes N pairs of sixth transistors and seventh transistors;

[0113] For any of the sixth transistors, the sixth transistor is connected to the corresponding first data input terminal 102, the seventh transistor and the second ground terminal respectively, and is used to turn on the seventh transistor and the second ground terminal when the data input signal obtained from the corresponding first data input terminal 102 is at a high level;

[0114] For any of the seventh transistors, the seventh transistor is connected to the delay inversion unit 103, the third transistor and the sixth transistor respectively, and is used to turn on the third transistor and the second ground terminal when the delayed inversion signal obtained from the delay inversion unit 103 is at a high level.

[0115] In the embodiment of the present application, the sixth transistor and the seventh transistor may be NMOS transistors. Any pair of the sixth transistor and the seventh transistor may be connected in series with each other, and a pair of the sixth transistor and the seventh transistor may be connected in parallel with other pairs of the sixth transistor and the seventh transistor.

[0116] In the embodiment of the present application, for any pair of the sixth transistor and the seventh transistor, the source of the sixth transistor (NMOS transistor) is connected to the second ground terminal, the gate of the sixth transistor is connected to the corresponding first data input terminal 102, the drain of the sixth transistor is connected to the source of the seventh transistor (NMOS transistor), the gate of the seventh transistor is connected to the corresponding inverter in the delay inversion unit 103, and the drain of the seventh transistor is connected to the third transistor. The source of the sixth transistor is also connected to the second ground terminal.

[0117] In the embodiment of the present application, when the data input signal obtained from the corresponding first data input terminal 102 is at a high level, the sixth transistor (NMOS transistor) is turned on, and then the sixth transistor turns on the source of the seventh transistor and the second ground terminal. When the delayed inversion signal obtained from the corresponding inverter in the delayed inversion unit 103 is at a high level, the seventh transistor (NMOS transistor) is turned on, and then the seventh transistor turns on the gate of the third transistor and the second ground terminal, so that the second ground terminal discharges the third transistor, thereby turning on the third transistor itself.

[0118] In the embodiment of the present application, for any pair of the sixth transistor and the seventh transistor among the N pairs of the sixth transistor and the seventh transistor, when the data input signal received by the sixth transistor and the delayed inverted signal received by the seventh transistor are both at a high level, the third transistor and the second ground terminal can be turned on, so that the third transistor itself is turned on, and further, the third transistor can turn on the third power supply terminal and the second detection output terminal, so that the second detection output terminal can output a high-level signal corresponding to the third power supply terminal, that is, a timing error result, when a timing error occurs, thereby realizing timing error detection. In addition, the timing error detection circuit of the embodiment of the present application can determine the value of N according to the number of data input terminals of the timing unit to be tested, that is, flexibly set the number of pairs of the sixth transistor and the seventh transistor in the second detection component, thereby improving the flexibility of the circuit and reducing the circuit area overhead to a certain extent.

[0119] Optionally, the delay inversion unit 103 includes N inverters;

[0120] For any of the inverters, the inverter is connected to the corresponding first data input terminal 102 and the detection unit respectively, and is used to perform specified processing on the data input signal obtained from the corresponding first data input terminal 102 to obtain a corresponding delayed inverted signal, and send the delayed inverted signal to the detection unit 104.

[0121] In the embodiment of the present application, the inverter may be a complementary metal-oxide-semiconductor (CMOS) NOT gate circuit, and the CMOS NOT gate circuit includes a PMOS transistor and an NMOS transistor. This is only an example, and the embodiment of the present application does not limit this.

[0122] In the embodiment of the present application, the input terminals of the N inverters can be connected to the N first data input terminals in a one-to-one correspondence, and the output terminals of the N inverters can be connected to the N fourth transistors and the N seventh transistors in the detection unit in a one-to-one correspondence. For any inverter, the inverter can invert the data input signal obtained from the corresponding first data input terminal 102, and delay it according to a preset phase difference to obtain a corresponding delayed inverted signal, and send the delayed inverted signal to the corresponding fourth transistor and the seventh transistor in the detection unit 104, so as to control the conduction and closing of the corresponding fourth transistor and the seventh transistor.

[0123] In the embodiment of the present application, by performing designated processing on N data input signals respectively through N inverters, the overall efficiency of obtaining the delayed inverted signals corresponding to each of the N data input signals can be improved, and the response time of the timing error detection circuit of the embodiment of the present application can be improved to a certain extent.

[0124] In the embodiment of the present application, when the timing unit to be tested includes N second data input terminals, the timing error detection circuit includes N first data input terminals, 1 clock input terminal, the delay inversion unit includes N inverters, the detection unit includes N pairs of fourth transistors and fifth transistors, and the first power supply terminal, the first ground terminal, the first detection output terminal, the first transistor, the second power supply terminal, the second ground terminal, the second transistor, the third transistor and the second detection output terminal which do not change with the number represented by N. Among them, the inverter may include a pair of PMOS transistors and NMOS transistors, then the timing error detection circuit includes 6N+3 transistors, and the average detection of each bit of input data requires 6N+3 transistors. transistors, that is, except for the number of transistors in the detection unit and the number of inverters in the delay inversion unit, other circuit elements will not increase due to the number of second data input terminals of the timing unit to be tested, which can reduce the circuit area overhead of the timing error detection circuit to a certain extent.

[0125] Figure 8 2 is a schematic diagram of the structure of the timing error detection circuit provided in the embodiment of the present application. Figure 8As shown, N is 1, that is, the timing error detection circuit includes a clock input terminal, a first data input terminal, a delayed inverting unit and a detection unit. The second transistor, the third transistor, the fourth transistor and the fifth transistor are PMOS transistors, and the first transistor, the sixth transistor and the seventh transistor are NMOS transistors. The first data input terminal receives the same data input signal D as the corresponding second data input terminal in the timing unit to be tested, and the clock input terminal receives the same clock input signal CLK as the timing unit to be tested. The first data input terminal sends the data input signal D to the delayed inverting unit, that is, the inverter 08, to obtain the corresponding delayed inverting signal D_N, and the inverter 08 sends the delayed inverting signal D_N to the fourth transistor, that is, the PMOS transistor 01 and the seventh transistor, that is, the NMOS transistor 05. The first data input terminal also sends the data input signal D to the fifth transistor, that is, the PMOS transistor 02 and the sixth transistor, that is, the NMOS transistor 06. The clock input terminal sends the clock input signal CLK to the second transistor, namely the PMOS transistor 04 , and after obtaining the inverted signal ˜CLK corresponding to the clock input signal CLK through a dedicated inverter, sends the ˜CLK signal to the first transistor, namely the NMOS transistor 03 .

[0126] Figure 8 In the embodiment, the PMOS transistor 01 is connected to the first power supply terminal and the PMOS transistor 02, the PMOS transistor 02 is also connected to the first detection output terminal Out, and the NMOS transistor 03 is connected to the first detection output terminal Out and the first ground terminal. The first power supply terminal, the first ground terminal, the first detection output terminal Out, the NMOS transistor 03, the PMOS transistor 01 and the PMOS transistor 02 constitute a falling edge detection subunit. The PMOS transistor 04 is connected to the second power supply terminal and the gate A of the third transistor, that is, the PMOS transistor 07, the NMOS transistor 05 is connected to the gate A of the PMOS transistor 07 and the NMOS transistor 06, the NMOS transistor 06 is also connected to the second ground terminal, and the PMOS transistor 07 is also connected to the third power supply terminal and the second detection output terminal Out.

[0127] Fig. 9 3 is a schematic diagram of the structure of the timing error detection circuit provided in the embodiment of the present application. Fig. 9As shown, N is 4, that is, the timing error detection circuit includes a clock input terminal, four first data input terminals, a delayed inverting unit and a detection unit. The second transistor, the third transistor, the fourth transistor and the fifth transistor are PMOS transistors, and the first transistor, the sixth transistor and the seventh transistor are NMOS transistors. The four first data input terminals respectively receive the same data input signals D0, D1, D2 and D3 as the corresponding second data input terminals, and the clock input terminal receives the same clock input signal CLK as the timing unit to be tested. The four first data input terminals respectively send the data input signals D0, D1, D2 and D3 to the four inverters 20, 21, 22 and 23 in the delayed inverting unit to obtain the corresponding delayed inverting signals D0_N, D1_N, D2_N and D3_N. The inverters 20, 21, 22 and 23 send the delayed inverting signals D0_N, D1_N, D2_N and D3_N to the PMOS transistors 01, 03, 05 and 07 respectively. The inverter 20 , 21, 22 and 23 also send delayed inverted signals D0_N, D1_N, D2_N and D3_N to NMOS transistors 10, 12, 14 and 16 respectively. The four first data input terminals send data input signals D0, D1, D2 and D3 to PMOS transistors 02, 04, 06 and 08, and the four first data input terminals also send data input signals D0, D1, D2 and D3 to NMOS transistors 11, 13, 15 and 17. The clock input terminal sends the clock input signal CLK to the PMOS transistor 18, and after obtaining the inverted signal ~CLK corresponding to the clock input signal CLK through a special inverter, the ~CLK signal is sent to the NMOS transistor 09.

[0128] Fig. 9In the embodiment, PMOS transistors 01, 03, 05 and 07 are connected to the first power supply terminal, and are respectively connected to PMOS transistors 02, 04, 06 and 08 in one-to-one correspondence. PMOS transistors 02, 04, 06 and 08 are also connected to the first detection output terminal Out and the source of NMOS transistor 09. NMOS transistor 09 is connected to the first detection output terminal Out and the first ground terminal. The first power supply terminal, the first ground terminal, the first detection output terminal Out, NMOS transistor 09, PMOS transistors 01, 03, 05 and 07, and PMOS transistors 02, 04, 06 and 08 constitute a falling edge detection subunit. The PMOS transistor 18 is connected to the second power supply terminal and the gate A of the PMOS transistor 19, the NMOS transistors 10, 12, 14 and 16 are connected to the gate A of the PMOS transistor 19, the NMOS transistors 10, 12, 14 and 16 are also connected to the NMOS transistors 11, 13, 15 and 17 one by one, the NMOS transistors 11, 13, 15 and 17 are connected to the second ground terminal, and the PMOS transistor 19 is also connected to the third power supply terminal and the second detection output terminal Out. The second power supply terminal, the third power supply terminal, the second ground terminal, the second detection output terminal Out, the PMOS transistor 18, the PMOS transistor 19, the NMOS transistors 10, 12, 14 and 16, and the NMOS transistors 11, 13, 15 and 17 constitute a rising edge detection subunit. Fig. 9 In the timing error detection circuit, only 6.75 transistors are needed for a second data input terminal, which has a small circuit area overhead. The embodiment of the present application proposes a timing error detection circuit based on edge jump, which has the characteristics of small area overhead and fast response time, and can be an application scenario for timing units with single storage bits or multiple storage bits. The timing error detection circuit proposed in the embodiment of the present application can monitor in real time whether the timing behavior of the chip during operation is correct. Although the timing error detection circuit proposed in the embodiment of the present application is also constructed based on the edge jump detection method, it requires fewer circuit elements. For example, only 9 transistors are needed when N is 1. Compared with the circuit in the prior art, it has a smaller area overhead and a faster response time.

[0129] Fig.10 is a schematic diagram of the steps of a timing error detection method provided by an embodiment of the present application, such as Fig.10 As shown, the timing error detection method is applied to the timing error detection circuit as described in the above embodiment, the timing error detection circuit includes a clock input terminal, N first data input terminals, a delay inversion unit and a detection unit, and the method includes:

[0130] Step 401, receiving a clock input signal identical to that of a timing unit to be tested through the clock input terminal, and sending the clock input signal to the detection unit;

[0131] Step 402, for any of the first data input terminals, receiving a data input signal identical to a corresponding second data input terminal in the timing unit to be tested through the first data input terminal, and sending the data input signal to the delay inversion unit and the detection unit;

[0132] Step 403, performing designated processing on the received N data input signals through the delayed inversion unit to obtain respective corresponding delayed inversion signals, and sending the N delayed inversion signals to the detection unit; the delayed inversion signal is opposite in phase to the corresponding data input signal and has a preset phase difference;

[0133] Step 404: Output a timing error result through a detection unit when the clock input signal is at a valid level and the levels of at least one of the data input signals and the corresponding delayed inverted signal are the same.

[0134] In the embodiment of the present application, the implementation methods of the relevant steps of the clock input terminal, the first data input terminal, the delay inversion unit and the detection unit can refer to the relevant description in the aforementioned circuit embodiment and will not be repeated here.

[0135] The timing error detection method provided in the embodiment of the present application has the same advantages as those of the prior art and the timing error detection circuit of the aforementioned embodiment, which will not be described in detail here.

[0136] Optionally, the detection unit includes a falling edge detection subunit and a rising edge detection subunit; the falling edge detection subunit and the rising edge detection subunit are respectively connected to the N first data input terminals, the clock input terminal and the delay inversion unit; step 404 may include:

[0137] Step 4041: Output the timing error result through the falling edge detection subunit when the clock input signal is at a valid level and at least one of the data input signals and the corresponding delayed inverted signal are at a low level.

[0138] Step 4042: Output the timing error result through the rising edge detection subunit when the clock input signal is at a valid level and at least one of the data input signals and the corresponding delayed inverted signal are at a high level.

[0139] In the embodiment of the present application, the implementation method of the related steps of the falling edge detection subunit and the rising edge detection subunit can refer to the relevant description in the aforementioned circuit embodiment, which will not be repeated here.

[0140] Optionally, the timing error result is a high level signal; the effective level is a high level; the falling edge detection subunit includes a first power supply terminal, a first ground terminal, a first detection output terminal, a first transistor and a first detection component; the first detection component is respectively connected to the N first data input terminals, the delay inversion unit, the first power supply terminal and the first detection output terminal; one end of the first transistor is connected to the first detection output terminal, and the other end is connected to the first ground terminal; step 4041 may include:

[0141] Step 4041a: When at least one of the data input signals and the corresponding delayed inverted signal are both at a low level, the first power supply terminal and the first detection output terminal are turned on by the first detection component.

[0142] Step 4041b: disconnecting the first detection output terminal from the first ground terminal through the first transistor when the inverted signal corresponding to the clock input signal is at a low level.

[0143] Step 4041c: output a high level signal corresponding to the first power supply end through the first detection output end when the first detection output end is connected to the first power supply end and disconnected from the first ground end.

[0144] In the embodiment of the present application, the implementation method of the related steps of the first detection component, the first transistor and the first detection output terminal can refer to the related description in the aforementioned circuit embodiment, which will not be repeated here.

[0145] Optionally, the timing error result is a high level signal; the effective level is a high level; the rising edge detection subunit includes a second power supply terminal, a third power supply terminal, a second ground terminal, a second detection output terminal, a second transistor, a third transistor and a second detection component; the second detection component is respectively connected to the N first data input terminals, the delay inversion unit, the third transistor and the second ground terminal; one end of the second transistor is connected to the second power supply terminal, and the other end is connected to the third transistor; the third transistor is respectively connected to the third power supply terminal and the second detection output terminal; step 4042 may include:

[0146] Step 4042a: When at least one of the data input signals and the corresponding delayed inverted signal are both at a high level, the third transistor and the second ground terminal are turned on by the second detection component.

[0147] Step 4042b, disconnecting the second power supply terminal and the third transistor through the second transistor when the clock input signal is at a high level.

[0148] Step 4042c, when the third transistor is conductively connected to the second ground terminal, the third power supply terminal and the second detection output terminal are conductively connected.

[0149] Step 4042d, outputting a high level signal corresponding to the third power supply terminal through the second detection output terminal.

[0150] In the embodiment of the present application, the implementation methods of the related steps of the second detection component, the second transistor, the third transistor and the second detection output terminal can refer to the related description in the aforementioned circuit embodiment, which will not be repeated here.

[0151] Optionally, the first detection component includes N pairs of fourth transistors and fifth transistors; for any of the fourth transistors, the fourth transistor is connected to the delay inversion unit, the first power supply terminal and the fifth transistor respectively; for any of the fifth transistors, the fifth transistor is connected to the corresponding first data input terminal, the fourth transistor and the first detection output terminal respectively; the step 4041a may include:

[0152] Sub-step A11, for any of the fourth transistors, when the delayed inversion signal obtained from the delayed inversion unit is at a low level, the first power supply terminal and the fifth transistor are turned on by the fourth transistor;

[0153] Sub-step A12: for any of the fifth transistors, when the data input signal obtained from the corresponding first data input terminal is at a low level, the first power supply terminal and the first detection output terminal are turned on by the fifth transistor.

[0154] In the embodiment of the present application, the implementation method of the related steps of the fourth transistor and the fifth transistor can refer to the related description in the aforementioned circuit embodiment, which will not be repeated here.

[0155] Optionally, the second detection component includes N pairs of sixth transistors and seventh transistors; for any of the sixth transistors, the sixth transistor is connected to the corresponding first data input terminal, the seventh transistor and the second ground terminal respectively; for any of the seventh transistors, the seventh transistor is connected to the delay inversion unit, the third transistor and the sixth transistor respectively; the step 4042a may include:

[0156] Sub-step A21, for any of the sixth transistors, when the data input signal obtained from the corresponding first data input terminal is at a high level, the seventh transistor and the second ground terminal are turned on by the sixth transistor.

[0157] Sub-step A22: for any of the seventh transistors, when the delayed inversion signal obtained from the delayed inversion unit is at a high level, the third transistor and the second ground terminal are turned on by the seventh transistor.

[0158] In the embodiment of the present application, the implementation method of the relevant steps of the sixth transistor and the seventh transistor can refer to the relevant description in the aforementioned circuit embodiment, which will not be repeated here.

[0159] Optionally, the delay inversion unit includes N inverters; for any of the inverters, the inverter is connected to the corresponding first data input terminal and the detection unit respectively; the step 403 may include:

[0160] Step 4031: for any of the inverters, perform specified processing on the data input signal obtained from the corresponding first data input terminal through the inverter to obtain a corresponding delayed inverted signal, and send the delayed inverted signal to the detection unit.

[0161] In the embodiment of the present application, the implementation method of the relevant steps of the inverter can refer to the relevant description in the aforementioned circuit embodiment, which will not be repeated here.

[0162] The timing error detection method provided in the embodiment of the present application has the same advantages as those of the prior art and the timing error detection circuit of the aforementioned embodiment, which will not be described in detail here.

[0163] An embodiment of the present application provides a chip, which includes the timing error detection circuit as described in the above embodiment.

[0164] An embodiment of the present application provides an electronic device, which includes the chip described in the above embodiment.

[0165] Fig.11 is a schematic diagram of the structure of another electronic device provided in an embodiment of the present application, such as Fig.11 As shown, the electronic device includes: a chip, a memory, a communication interface and a communication bus, and the chip, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the chip to execute the timing error detection method of the aforementioned embodiment.

[0166] An embodiment of the present application provides a non-temporary computer-readable storage medium. When instructions in the storage medium are executed by a program or processor of a terminal, the terminal is enabled to execute the timing error detection method of the aforementioned embodiment.

[0167] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0168] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, devices, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0169] The embodiments of the present application are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0170] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0171] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0172] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present application.

[0173] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0174] A method and device, an electronic device and a storage medium provided by the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for a person skilled in the art, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A timing error detection circuit, characterized in that: The timing error detection circuit comprises a clock input terminal, N first data input terminals, a delay inversion unit and a detection unit; N is a positive integer; The clock input terminal is used to receive the same clock input signal as the timing unit to be tested, and send the clock input signal to the detection unit; For any of the first data input terminals, the first data input terminal is used to receive a data input signal identical to a corresponding second data input terminal in the timing unit to be tested, and send the data input signal to the delay inversion unit and the detection unit; The delayed inverting unit is connected to the N first data input terminals respectively, and is used to perform designated processing on the received N data input signals to obtain the corresponding delayed inverted signals, and send the N delayed inverted signals to the detection unit; The delayed inverted signal is opposite in phase to the corresponding data input signal and has a preset phase difference; The detection unit is connected to the N first data input terminals, the clock input terminal and the delayed inverting unit respectively, and is used to output a timing error result when the clock input signal is at a valid level and the level of at least one of the data input signals and the corresponding delayed inverting signal is the same.

2. The circuit according to claim 1, characterized in that The detection unit includes a falling edge detection subunit and a rising edge detection subunit; the falling edge detection subunit and the rising edge detection subunit are respectively connected to the N first data input terminals, the clock input terminal and the delay inversion unit; The falling edge detection subunit is used to output the timing error result when the clock input signal is at a valid level and at least one of the data input signals and the corresponding delayed inverted signal are at a low level; The rising edge detection subunit is used to output the timing error result when the clock input signal is at a valid level and at least one of the data input signals and the corresponding delayed inverted signal are both at a high level.

3. The circuit according to claim 2, characterized in that The timing error result is a high level signal; the effective level is a high level; the falling edge detection subunit includes a first power supply terminal, a first ground terminal, a first detection output terminal, a first transistor and a first detection component; The first detection component is connected to the N first data input terminals, the delayed inverting unit, the first power supply terminal and the first detection output terminal respectively, and is used to conduct the first power supply terminal and the first detection output terminal when at least one of the data input signals and the corresponding delayed inverting signal are both at low levels; One end of the first transistor is connected to the first detection output end, and the other end is connected to the first ground end, and is used to disconnect the first detection output end and the first ground end when the inverted signal corresponding to the clock input signal is at a low level; The first detection output terminal is used to output a high level signal corresponding to the first power terminal when it is connected to the first power terminal and disconnected from the first ground terminal.

4. The circuit according to claim 2, characterized in that The timing error result is a high level signal; the effective level is a high level; the rising edge detection subunit includes a second power supply terminal, a third power supply terminal, a second ground terminal, a second detection output terminal, a second transistor, a third transistor and a second detection component; The second detection component is connected to the N first data input terminals, the delayed inverting unit, the third transistor and the second ground terminal respectively, and is used to turn on the third transistor and the second ground terminal when at least one of the data input signals and the corresponding delayed inverting signal are both at high levels; One end of the second transistor is connected to the second power supply end, and the other end is connected to the third transistor, and is used to disconnect the second power supply end and the third transistor when the clock input signal is at a high level; The third transistor is connected to the third power supply terminal and the second detection output terminal respectively, and is used to conduct the third power supply terminal and the second detection output terminal when the third transistor is connected to the second ground terminal; The second detection output terminal is used to output a high level signal corresponding to the third power supply terminal.

5. The circuit according to claim 3, characterized in that The first detection component includes N pairs of fourth transistors and fifth transistors; For any of the fourth transistors, the fourth transistor is connected to the delay inversion unit, the first power supply terminal and the fifth transistor respectively, and is used to turn on the first power supply terminal and the fifth transistor when the delayed inversion signal obtained from the delay inversion unit is at a low level; For any of the fifth transistors, the fifth transistor is respectively connected to the corresponding first data input terminal, the fourth transistor and the first detection output terminal, and is used to turn on the first power supply terminal and the first detection output terminal when the data input signal obtained from the corresponding first data input terminal is at a low level.

6. The circuit according to claim 4, characterized in that The second detection component includes N pairs of sixth transistors and seventh transistors; For any of the sixth transistors, the sixth transistor is connected to the corresponding first data input terminal, the seventh transistor and the second ground terminal respectively, and is used to turn on the seventh transistor and the second ground terminal when the data input signal obtained from the corresponding first data input terminal is at a high level; For any of the seventh transistors, the seventh transistor is connected to the delayed inverting unit, the third transistor and the sixth transistor respectively, and is used to turn on the third transistor and the second ground terminal when the delayed inverting signal obtained from the delayed inverting unit is at a high level.

7. The circuit according to claim 1, characterized in that The delay inversion unit includes N inverters; For any of the inverters, the inverter is connected to the corresponding first data input terminal and the detection unit respectively, and is used to perform specified processing on the data input signal obtained from the corresponding first data input terminal to obtain a corresponding delayed inverted signal, and send the delayed inverted signal to the detection unit.

8. A timing error detection method, characterized in that: Applied to the timing error detection circuit according to any one of claims 1 to 7, the timing error detection circuit comprises a clock input terminal, N first data input terminals, a delay inversion unit and a detection unit, the method comprising: Receiving a clock input signal identical to that of the timing unit to be tested through the clock input terminal, and sending the clock input signal to the detection unit; For any of the first data input terminals, receiving a data input signal identical to a corresponding second data input terminal in the timing unit to be tested through the first data input terminal, and sending the data input signal to the delay inversion unit and the detection unit; The N received data input signals are processed by the delayed inversion unit to obtain corresponding delayed inversion signals, and the N delayed inversion signals are sent to the detection unit; the delayed inversion signal is opposite in phase to the corresponding data input signal and has a preset phase difference; The detection unit outputs a timing error result when the clock input signal is at a valid level and the levels of at least one of the data input signals and the corresponding delayed inverted signal are the same.

9. A chip, characterized in that: The chip includes a timing error detection circuit as described in any one of claims 1-7.

10. An electronic device, characterized in that: The electronic device comprises the chip according to claim 9.

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