Display driving architecture based on multi-level chip and construction method and maintenance method thereof
By configuring a multi-level chip display driver architecture and its maintenance method, the problem of the inability to quickly build and troubleshoot display driver architectures in the existing technology is solved, and efficient video stream processing and fault repair are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- DONGFENG ELECTRONICS TECH
- Filing Date
- 2024-11-12
- Publication Date
- 2026-07-21
AI Technical Summary
Existing technologies cannot quickly build display driver architectures that adapt to different video stream processing needs, nor can they quickly handle faults.
By using a multi-level chip-based display driver architecture, the chip-related attributes and initial priorities of peripheral chips are configured, a variable period detection method is used to detect the chip's operating status, and initialization operations are performed in order of priority in case of a fault.
It improves the efficiency of display driver architecture construction and fault repair, reduces computational load, and enables rapid adaptation to video stream processing requirements and rapid fault handling.
Smart Images
Figure CN119314442B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display driver architecture, specifically to a multi-level chip-based display driver architecture and its construction and maintenance methods. Background Technology
[0002] There are many types of LCD instrument panels in automobiles, and the peripheral chips that enable the display are also diverse. Some are directly driven, such as SoC chips that are directly connected to the display screen. Others are driven by first-level chips, or by second-level, third-level, or even more levels of chips. How to quickly configure the display driver architecture required for different display screens is a problem that needs to be solved.
[0003] In addition, existing fault diagnosis methods for display driver architectures change with the architecture. After different architectures are built, corresponding fault diagnosis methods need to be specified for each architecture. There is a lack of unified planning, which makes it impossible to quickly restore the screen when it is abnormal. Summary of the Invention
[0004] This application provides a display driver architecture based on a multi-level chip, as well as its construction and maintenance methods, which can solve the technical problems in the prior art that it is impossible to quickly construct a display driver architecture that can adapt to different video stream processing requirements and that it is impossible to quickly handle faults during the operation of the display driver architecture.
[0005] In a first aspect, embodiments of this application provide a method for constructing a display driver architecture based on a multi-level chip, the method comprising:
[0006] Multiple peripheral chips are invoked according to the video stream processing flow, and each peripheral chip is used to complete a processing step in the processing flow; the chip-related attributes and initial priorities of each peripheral chip are configured according to the order of the processing steps. The chip-related attributes are used for the operation and maintenance of the chip, and the initial priority gradually increases according to the order of the processing flow; the peripheral chips include SoC chips and various video processing chips, with the SoC chip having the lowest initial priority.
[0007] The peripheral chips are initialized sequentially from low to high priority to build a display driver architecture based on multi-level chips.
[0008] In conjunction with the first aspect, in one embodiment, the chip-related attributes include power operation attributes, initialization and deinitialization attributes, input / output interface attributes, operation interface attributes, and fault diagnosis interface attributes.
[0009] Power operation attributes are used to acquire and control the power status of peripheral chips;
[0010] The initialization and deinitialization attributes are used to perform initialization and deinitialization operations on peripheral chips;
[0011] Input / output interface attributes are used to obtain and control the input and output video stream formats of peripheral chips;
[0012] The operation interface attribute is used to acquire and control the internal operations of the peripheral chip. The internal operations include processing operations on the video and control operations to control the working state of the peripheral chip. The working state of the peripheral chip includes normal working state, abnormal working state, and sleep state.
[0013] The fault diagnosis interface attributes are used to obtain the cause of the peripheral chip's fault and to control the fault repair operation of the peripheral chip.
[0014] In conjunction with the first aspect, in one embodiment, the method further includes:
[0015] Peripheral chips whose initialization operations do not depend on the results of other peripheral chips are defined as single-row chips. The priority of single-row chips is adjusted according to custom information to obtain the final priority of all peripheral chips.
[0016] Secondly, embodiments of this application provide a display driver architecture based on a multi-level chip, which is constructed using the aforementioned method for constructing a display driver architecture based on a multi-level chip.
[0017] Thirdly, embodiments of this application provide a maintenance method for a multi-level chip-based display driver architecture, based on the aforementioned multi-level chip-based display driver architecture; the maintenance method includes:
[0018] A variable period detection method is used to detect whether each video processing chip is operating normally, and the detection results are obtained. The variable period detection method divides the detection period into a fast period and a slow period. The fast period detects the video processing chip according to a first frequency, and the slow period detects the video processing chip according to a second frequency. The first frequency is greater than the second frequency. Within a first specified time after the video processing chip is powered on or woken up, the video processing chip is detected according to the fast period. If the detection results are abnormal multiple times in a row, the video processing chip is determined to be operating abnormally. If the duration of the fast period exceeds the second specified time and the detection results are all normal, the system switches to the slow period. If the detection results are abnormal, the system switches back to the fast period. The first specified time is less than the second specified time.
[0019] When the detection result indicates that the video processing chip is malfunctioning, the initialization operation is performed on each peripheral chip in order of priority, starting from the malfunctioning video processing chip.
[0020] In conjunction with the third aspect, in one implementation method, determining whether the detection result is abnormal specifically includes the following steps:
[0021] Obtain the actual register value of the video processing chip and determine whether the actual register value is consistent with the theoretical register value of the video processing chip. If it is consistent, the detection result of the video processing chip is determined to be normal; otherwise, the detection result of the video processing chip is determined to be abnormal.
[0022] In conjunction with the third aspect, in one implementation method, determining whether the detection result is abnormal specifically includes the following steps:
[0023] If the video input parameters of the next priority video processing chip are normal, the detection result of the previous priority video processing chip is considered normal; otherwise, the detection result of the previous priority video processing chip is considered abnormal.
[0024] In conjunction with the third aspect, in one embodiment, the method further includes:
[0025] Upon receiving the system hibernation command, the peripheral chips at each level are deinitialized in descending order of priority.
[0026] In conjunction with the third aspect, in one embodiment, the maintenance method further includes:
[0027] The system detects whether the video stream received by the SoC chip is normal. If it is, a variable period detection method is used to check whether each video processing chip is operating normally. If not, the system controls the SoC chip to perform fault handling according to the built-in fault handling process.
[0028] In conjunction with the third aspect, in one embodiment, the maintenance method further includes:
[0029] The system checks whether the output image of the connected display screen is normal. If it is, it uses a variable period detection method to check whether each video processing chip is operating normally. If not, while using the variable period detection method to check whether each video processing chip is operating normally, it controls the display screen to perform fault handling according to the built-in fault handling procedure.
[0030] The beneficial effects of the technical solutions provided in this application include:
[0031] The peripheral chips required by the display driver architecture are retrieved according to the processing flow of different video streams. The peripheral chips corresponding to each priority are initially configured according to the order of processing steps. The peripheral chips are initialized in order of priority from low to high, thereby building a display driver architecture based on multi-level chips, which improves the construction efficiency of the display driver architecture. During the operation of the display driver architecture, a variable period detection method is used to detect whether each video processing chip is running normally, which improves the detection accuracy and reduces the computational load. When a chip is found to be abnormal, all chips with higher priority than the abnormal chip are re-initialized, starting from the abnormal chip, to improve the fault repair efficiency. Attached Figure Description
[0032] Figure 1 This is a flowchart illustrating an embodiment of the method for constructing a display driver architecture based on a multi-level chip according to this application;
[0033] Figure 2 This is a flowchart illustrating an embodiment of the maintenance method for a multi-level chip-based display driver architecture according to this application. Detailed Implementation
[0034] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.
[0035] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.
[0036] In a first aspect, embodiments of this application provide a method for constructing a display driver architecture based on a multi-level chip.
[0037] In one embodiment, reference is made to Figure 1 , Figure 1 This is a flowchart illustrating an embodiment of the method for constructing a multi-level chip-based display driver architecture according to this application. Figure 1 As shown, the construction method of a display driver architecture based on multi-level chips includes:
[0038] Step S1: Retrieve multiple peripheral chips according to the video stream processing flow. Each peripheral chip is used to complete one processing step in the processing flow.
[0039] Step S2: Configure the chip-related attributes and initial priorities of each peripheral chip according to the order of the processing steps. The chip-related attributes are used for chip operation and maintenance, and the initial priorities gradually increase according to the order of the processing flow. The aforementioned peripheral chips include SoC chips and various video processing chips, with SoC chips having the lowest initial priority.
[0040] Step S3: Initialize each peripheral chip in order of priority from low to high to build a display driver architecture based on multi-level chips.
[0041] In this embodiment, the peripheral chips required by the display driver architecture are retrieved according to the processing flow of different video streams, and the peripheral chips corresponding to each priority are initially configured according to the order of processing steps. The peripheral chips are initialized in order of priority from low to high, thereby constructing a display driver architecture based on multi-level chips and improving the construction efficiency of the display driver architecture.
[0042] Furthermore, in one embodiment, the aforementioned chip-related attributes include power operation attributes, initialization and deinitialization attributes, input / output interface attributes, operation interface attributes, and fault diagnosis interface attributes.
[0043] Power operation attributes are used to acquire and control the power status of peripheral chips.
[0044] The initialization and deinitialization attributes are used to perform initialization and deinitialization operations on peripheral chips.
[0045] Input / output interface attributes are used to obtain and control the input and output video stream formats of peripheral chips.
[0046] The operation interface attributes are used to acquire and control the internal operations of the peripheral chip. These internal operations include processing operations on the video and control operations to control the working state of the peripheral chip. The working state of the peripheral chip includes normal working state, abnormal working state, and sleep state.
[0047] The fault diagnosis interface attributes are used to obtain the cause of the peripheral chip's fault and to control the fault repair operation of the peripheral chip.
[0048] In this embodiment, while configuring the priority of the peripheral chip, the chip-related attributes of the peripheral chip are also configured, thereby quickly building a display driver architecture that adapts to different video stream processing flows.
[0049] In one specific embodiment, configuring power operation attributes allows for real-time monitoring and control of the power status of peripheral chips. For example, an external terminal can acquire and control the power status of the SoC chip, and after the SoC chip starts up, the control software inside the SoC chip can acquire and control the power status of other video processing chips.
[0050] After configuring the initialization and deinitialization attributes, you can set the initialization and deinitialization methods for the registers.
[0051] After configuring the input / output interface properties, you can set the video input interface properties and video output interface properties of the peripheral chip. For example, the video formats that the peripheral chip can receive or output through the video input interface include RGB, LVDS, MIPI-DSI, etc. The video formats that the video input interface can receive are determined by the video format output by the previous level chip, and the video formats that the video output interface can output are determined by the video processing operations that the current level chip needs to perform.
[0052] After configuring the operation interface attributes, you can obtain, modify and control the current working state of the chip. The working state is divided into normal working state (also known as running state), abnormal working state (also known as fault state or abnormal state), and sleep state.
[0053] After configuring the fault diagnosis interface properties, you can set and retrieve the diagnostic methods for peripheral chips.
[0054] Furthermore, in one embodiment, the above method further includes:
[0055] Before initializing the first peripheral chip, check if the video stream is normal and output the video stream detection result.
[0056] After initializing each peripheral chip, the result of the initialization operation is output.
[0057] Furthermore, in one embodiment, the above method further includes:
[0058] Peripheral chips whose initialization operations do not depend on the results of other peripheral chips are defined as single-row chips. The priority of single-row chips is adjusted according to custom information to obtain the final priority of all peripheral chips.
[0059] In this embodiment, the peripheral chips required by the display driver architecture are retrieved according to the processing flow of different video streams, and the peripheral chips corresponding to each priority are initially configured according to the order of processing steps. Then, based on whether there is a dependency relationship when different chips perform initialization operations, the peripheral chips that do not depend on the initialization operation results of other peripheral chips are given priority separately, thereby quickly completing the initialization and forming the display driver architecture.
[0060] In one specific embodiment, the video stream processing flow includes steps one, two, three, and four. Assuming step one is video stream pass-through, step two is video format conversion (e.g., RGB to LVDS or MIPI-DSI), step three is image compositing and segmentation, and step four is image color adjustment, then, according to the above processing flow, the SoC chip, video processing chip a1, video processing chip a2, and video processing chip a3 are invoked. The SoC chip is used to complete step one, video processing chip a1 is used to complete step two, video processing chip a2 is used to complete step three, and video processing chip a3 is used to complete step four.
[0061] The initial priority of the SoC chip is 1, the initial priority of video processing chip a1 is 2, the initial priority of video processing chip a2 is 3, and the initial priority of video processing chip a3 is 4. Video processing chip a1 depends on the initialization result of the SoC chip; regardless of whether the SoC chip's initialization is successful, video processing chip a1 can only perform its initialization operation after the SoC chip has completed its initialization. Video processing chip a2 depends on the initialization result of video processing chip a1, while video processing chip a3 does not depend on the initialization results of other chips. Therefore, the final priorities of the SoC chip, video processing chip a1, and video processing chip a2 are 1, 2, and 3, respectively. The final priority of video processing chip a3 can be customized by the user. Chips with the same priority can perform initialization operations simultaneously, thereby improving architecture construction efficiency.
[0062] Secondly, embodiments of this application also provide a display driver architecture based on a multi-level chip, which is constructed using a method for constructing a display driver architecture based on a multi-level chip.
[0063] Thirdly, embodiments of this application provide a maintenance method for a display driver architecture based on a multi-level chip.
[0064] In one embodiment, reference is made to Figure 2 , Figure 2 This is a flowchart illustrating an embodiment of the maintenance method for a multi-level chip-based display driver architecture according to this application. Figure 2 As shown, the maintenance methods for a multi-level chip-based display driver architecture include:
[0065] Step A1: Use a variable period detection method to check whether each video processing chip is operating normally and obtain the detection results. The variable period detection method divides the detection period into a fast period and a slow period. The fast period detects the video processing chip at a first frequency, and the slow period detects the video processing chip at a second frequency. The first frequency is greater than the second frequency. Within a first specified duration after the video processing chip is powered on or woken up, the fast period is used to detect the video processing chip. If multiple consecutive detection results are abnormal, the video processing chip is determined to be operating abnormally. If the fast period duration exceeds a second specified duration and all detection results are normal, switch to the slow period. If an abnormal detection result occurs, switch back to the fast period. The first specified duration is less than the second specified duration.
[0066] Step A2: When the detection result indicates that the video processing chip is malfunctioning, start with the malfunctioning video processing chip and perform initialization operations on each peripheral chip in order of priority.
[0067] In this embodiment, a variable period detection method is used to detect whether each video processing chip is operating normally. This improves detection accuracy while reducing computational load. When a chip is determined to be abnormal, all chips with higher priority than the abnormal chip are re-initialized, starting from the abnormal chip, thereby improving fault repair efficiency.
[0068] In one specific embodiment, the detection cycle of the video processing chip is divided into two cycles: a fast cycle and a slow cycle. The fast cycle is executed within one minute after power-on or wake-up, checking once every 1 second. If two consecutive abnormalities are detected in the video processing chip, it is determined that the video processing chip is faulty. The slow cycle is entered after the fast cycle has not detected any faults within one minute. The slow cycle checks once every 5 seconds. If a video processing chip fault is detected, it immediately switches to the fast cycle for detection. The video processing chip fault is determined by the fast cycle. This method can reduce CPU utilization while ensuring that recovery is possible.
[0069] Furthermore, in one embodiment, the above-mentioned determination of whether the detection result is abnormal specifically includes the following steps:
[0070] Obtain the actual register values of the video processing chip and determine whether they match the theoretical register values. If they do, the detection result of the video processing chip is considered normal. If not, the detection result of the video processing chip is considered abnormal.
[0071] Furthermore, in one embodiment, the above-mentioned determination of whether the detection result is abnormal specifically includes the following steps:
[0072] The system checks if the video input parameters of the next-priority video processing chip are normal. If so, the detection result of the previous-priority video processing chip is considered normal. If not, the detection result of the previous-priority video processing chip is considered abnormal.
[0073] In this embodiment, by determining whether the video input parameters of the next-level chip are normal, the method can determine whether the video output parameters of the previous level are normal. This method can perform detection through chips at different levels to ensure the integrity of input and output.
[0074] Furthermore, in one embodiment, the above method further includes:
[0075] Upon receiving the system hibernation command, the peripheral chips at each level are deinitialized in descending order of priority.
[0076] Furthermore, in one embodiment, the above maintenance method further includes:
[0077] The system checks whether the video stream received by the SoC chip is normal. If so, it uses a variable period detection method to check whether each video processing chip is operating normally. If not, it controls the SoC chip to handle the fault according to its built-in fault handling procedure.
[0078] Furthermore, in one embodiment, the above maintenance method further includes:
[0079] The system checks if the output image from the connected display is normal. If so, it uses a variable-cycle detection method to check if each video processing chip is functioning correctly. If not, while using the variable-cycle detection method to check if each video processing chip is functioning correctly, it controls the display to perform fault handling according to the built-in fault handling procedure.
[0080] It should be noted that the sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.
[0081] The terms "comprising" and "having," and any variations thereof, in the specification, claims, and accompanying drawings of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus. The terms "first," "second," and "third," etc., are used to distinguish different objects, etc., and do not indicate a sequence, nor do they limit "first," "second," and "third" to different types.
[0082] In the description of the embodiments of this application, terms such as "exemplary," "for example," or "for instance" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplary," "for example," or "for instance" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary," "for example," or "for instance" is intended to present the relevant concepts in a concrete manner.
[0083] In the description of the embodiments of this application, unless otherwise stated, " / " means "or". For example, A / B can mean A or B. The "and / or" in the text is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist simultaneously, and B exists alone. In addition, in the description of the embodiments of this application, "multiple" means two or more.
[0084] In some processes described in the embodiments of this application, multiple operations or steps are included in a specific order. However, it should be understood that these operations or steps may not be executed in the order they appear in the embodiments of this application, or they may be executed in parallel. The sequence number of the operation is only used to distinguish different operations, and the sequence number itself does not represent any execution order. In addition, these processes may include more or fewer operations, and these operations or steps may be executed sequentially or in parallel, and these operations or steps may be combined.
[0085] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a terminal device to execute the methods described in the various embodiments of this application.
[0086] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. A method for constructing a display driver architecture based on a multi-level chip, characterized in that, The construction method includes: Multiple peripheral chips are invoked according to the video stream processing flow, and each peripheral chip is used to complete a processing step in the processing flow; the chip-related attributes and initial priorities of each peripheral chip are configured according to the order of the processing steps. The chip-related attributes are used for the operation and maintenance of the chip, and the initial priority gradually increases according to the order of the processing flow; the peripheral chips include SoC chips and various video processing chips, with the SoC chip having the lowest initial priority. Peripheral chips whose initialization operations do not depend on the results of initialization operations of other peripheral chips are defined as single-row chips. The priority of the single-row chips is adjusted according to the custom information to obtain the final priority of all peripheral chips. The peripheral chips are initialized sequentially from low to high according to their final priority. Chips with the same priority can be initialized simultaneously to build a display driver architecture based on a multi-level chip.
2. The method for constructing a display driver architecture based on a multi-level chip as described in claim 1, characterized in that, The chip-related attributes include power operation attributes, initialization and deinitialization attributes, input / output interface attributes, operation interface attributes, and fault diagnosis interface attributes; Power operation attributes are used to acquire and control the power status of peripheral chips; The initialization and deinitialization attributes are used to perform initialization and deinitialization operations on peripheral chips; Input / output interface attributes are used to obtain and control the input and output video stream formats of peripheral chips; The operation interface attribute is used to acquire and control the internal operations of the peripheral chip. The internal operations include processing operations on the video and control operations to control the working state of the peripheral chip. The working state of the peripheral chip includes normal working state, abnormal working state, and sleep state. The fault diagnosis interface attributes are used to obtain the cause of the peripheral chip's fault and to control the fault repair operation of the peripheral chip.
3. A display driver architecture based on a multi-level chip, characterized in that, It is constructed using the method described in claim 1 for constructing a display driver architecture based on a multi-level chip.
4. A maintenance method for a display driver architecture based on a multi-level chip, characterized in that, Based on the multi-level chip-based display driver architecture described in claim 3; The maintenance method includes: A variable period detection method is used to detect whether each video processing chip is operating normally, and the detection results are obtained. It is then determined whether the detection results are abnormal. The variable period detection method divides the detection period into a fast period and a slow period. The fast period detects the video processing chip at a first frequency, and the slow period detects the video processing chip at a second frequency. The first frequency is greater than the second frequency. Within a first specified time after the video processing chip is powered on or woken up, the video processing chip is detected according to the fast period. If the detection results are abnormal multiple times in a row, the video processing chip is determined to be operating abnormally. If the duration of the fast period exceeds the second specified time and the detection results are all normal, the system switches to the slow period. If the detection results are abnormal, the system switches back to the fast period. The first specified time is less than the second specified time. When the detection result indicates that the video processing chip is malfunctioning, the initialization operation is performed on each peripheral chip in order of priority, starting from the malfunctioning video processing chip.
5. The maintenance method for a display driver architecture based on a multi-level chip as described in claim 4, characterized in that, Determining whether a test result is abnormal involves the following steps: Obtain the actual register value of the video processing chip and determine whether the actual register value is consistent with the theoretical register value of the video processing chip. If it is consistent, the detection result of the video processing chip is determined to be normal; otherwise, the detection result of the video processing chip is determined to be abnormal.
6. The maintenance method for a display driver architecture based on a multi-level chip as described in claim 4, characterized in that, Determining whether a test result is abnormal involves the following steps: If the video input parameters of the next priority video processing chip are normal, the detection result of the previous priority video processing chip is considered normal; otherwise, the detection result of the previous priority video processing chip is considered abnormal.
7. The maintenance method for a display driver architecture based on a multi-level chip as described in claim 4, characterized in that, The maintenance method also includes: Upon receiving the system hibernation command, the peripheral chips at each level are deinitialized in descending order of priority.
8. The maintenance method for a display driver architecture based on a multi-level chip as described in claim 4, characterized in that, The maintenance method also includes: The system detects whether the video stream received by the SoC chip is normal. If it is, a variable period detection method is used to check whether each video processing chip is operating normally. If not, the system controls the SoC chip to perform fault handling according to the built-in fault handling process.
9. The maintenance method for a display driver architecture based on a multi-level chip as described in claim 4, characterized in that, The maintenance method also includes: The system checks whether the output image of the connected display screen is normal. If it is, it uses a variable period detection method to check whether each video processing chip is operating normally. If not, while using the variable period detection method to check whether each video processing chip is operating normally, it controls the display screen to perform fault handling according to the built-in fault handling procedure.