Semiconductor devices and manufacturing methods thereof

Abstract

The present invention relates to a bipolar transistor semiconductor device, comprising: a substrate layer; a collector epitaxial layer supported by the substrate layer; a base region supported by a portion of the collector epitaxial layer; and an emitter region supported by a portion of the base region, wherein the emitter region comprises polycrystalline silicon material.

Description

[0001] This application is a divisional application of patent application No. 2019112416152, filed on December 6, 2019, entitled "Semiconductor Device and Method of Manufacturing Thereof". Technical Field

[0002] This disclosure relates to semiconductor devices, methods of manufacturing semiconductor devices, and electronic devices including semiconductor devices. More specifically, this disclosure relates to bipolar junction transistor (BJT) semiconductor devices, also known as bipolar transistors. Background Technology

[0003] Bipolar transistors are commonly used for current amplification in analog and digital circuits. In its simplest form, as shown in Figure 1, a discrete NPN bipolar transistor 100 includes an emitter region 101 electrically coupled to the emitter terminal 101a, a collector region 103 electrically coupled to the collector terminal 103a, and a base region 102 electrically coupled to the base terminal 102a. When constructed in common-emitter mode, this bipolar transistor 100 can operate as a current amplifier, allowing the input base current I to... B Small changes can cause the output collector / emitter current I to change. C Significant changes.

[0004] The current amplification characteristics of a bipolar transistor are controlled by the current gain or amplification factor hFE (also known as β). The amplified output collector / emitter current I... C The size is typically determined by the bipolar transistor's hFE and base current I. B Defined by the product of.

[0005] Typically, a high current gain hFE characteristic is preferred, allowing bipolar transistors driven only by a small base current to saturate in devices with high collector currents. Conventional BJTs typically have hFE values ​​ranging from about 10 to 500.

[0006] A conventional discrete bipolar transistor device structure includes a diffused emitter and a base formed within the collector epitaxial layer. The emitter and base contacts are located on the front 104 of the device wafer, while the collector terminal is located on the rear 105 of the wafer.

[0007] To achieve a bipolar transistor with high hFE, the device must achieve a high emitter Gummel number. The emitter Gummel number is a parameter used to measure the emitter efficiency of a transistor and is related to the effective doping of the emitter. The emitter Gummel number is limited by bandgap narrowing and carrier lifetime. While those skilled in the art will recognize that this parameter can be used to evaluate and assist in bipolar transistor design processes, a detailed discussion of the application of the Gummel number in transistor design is beyond the scope of this disclosure. Furthermore, a low base Gummel number is also required for bipolar transistors. This value is related to the total base doping and is limited by the breakdown voltage BVCBO. BVCBO is the collector-base breakdown voltage with the emitter floating. The limitation is that the base must contain total critical doping to include the depletion region of BVCBO; otherwise, punch-through will occur.

[0008] Therefore, in order to achieve a high hFE in a bipolar transistor, the emitter must be highly doped, the base must be lightly doped, and / or have the narrowest possible width.

[0009] To achieve bipolar transistors with an hFE value of 700 or greater, conventional processes are limited by the maximum effective emitter dopant available and process extensions associated with producing low-doped and narrow bases (i.e., variations in properties / characteristics between and within devices). In practice, for narrow bases, base width can become very difficult to control. Due to higher doping, the emitter diffuses faster than the base. Thus, for very narrow bases, even the slightest doping variation will result in inhomogeneity in the base region. As the base becomes narrower, this inhomogeneity will worsen within a given time in the furnace.

[0010] Using known processes, discrete bipolar transistors with hFE of 1000 or higher can be manufactured, but at the cost of compromised device performance, such as having to accept large process extensions (i.e., due to low doping and narrow bases), resulting in considerable yield losses, or having to use Darlington transistor arrangements, which makes it impossible for the transistor to saturate (because it prevents VBC from changing polarity), which limits the maximum current the transistor can conduct, thus limiting the device rating.

[0011] It is well known that polysilicon emitter-based transistors can be used in integrated circuits (ICs) for high-frequency applications. Typically, such transistors used in ICs have their emitter, base, and collector contacts on one side of the wafer (i.e., the front side of the wafer). However, in the field of discrete high-current transistors such as bipolar transistors, polysilicon emitter-based transistors, which have collector contacts on the side of the wafer opposite to the base and emitter contacts (i.e., the back side of the wafer), have not yet been used, thus providing the ability to deliver high collector current for a given die size. C The process requirement is that, for a given die size, the current flows laterally in the collector region of the transistor and then returns to the front of the wafer for contact. Because the emitter area can be reduced, this causes the current gain curve to drop to a lower collector current Ie. C Furthermore, since the current needs to flow laterally to the collector contacts on the front side, the resistance of the collector region is further increased.

[0012] In view of the foregoing, various aspects and embodiments of the present invention have been designed. Summary of the Invention

[0013] According to one aspect of the present invention, a bipolar transistor semiconductor device is provided, comprising: a substrate layer; a collector epitaxial layer supported by the substrate layer; a base region supported by a portion of the collector epitaxial layer; and an emitter region supported by a portion of the base region, wherein the emitter region comprises polycrystalline silicon material.

[0014] Alternatively, the substrate may include silicon (Si) doped with at least one of antimony (Sb), arsenic (As), and phosphorus (P).

[0015] Optionally, the collector epitaxial layer may include silicon (Si) doped with at least one of arsenic (As) and phosphorus (P).

[0016] Alternatively, the base region may include boron-doped silicon (Si).

[0017] Alternatively, the emitter region may include arsenic-doped silicon (Si) or polycrystalline silicon.

[0018] Alternatively, the emitter region may include phosphorus-doped silicon (Si) or polycrystalline silicon.

[0019] Optionally, the device may also include a titanium (Ti) layer and / or an aluminum (Al) layer, the titanium and / or aluminum layers being supported by a collector epitaxial layer, a base region, and an emitter region.

[0020] Optionally, the titanium layer and / or aluminum layer may also include AlSi and / or AlSiCu.

[0021] Optionally, the device may also include an AlSi layer supported by a collector epitaxial layer, a base region, and an emitter region.

[0022] Optionally, the device may also include an AlSiCu layer supported by a collector epitaxial layer, a base region, and an emitter region.

[0023] Optionally, the device may include a back metal stack for the assembly.

[0024] According to another aspect of the present invention, a method for manufacturing a bipolar transistor semiconductor device is provided, the bipolar transistor semiconductor device including a substrate layer, a collector epitaxial layer, an emitter region and a base region, the method comprising: forming a collector epitaxial layer on a surface of the substrate layer; forming a base region on a portion of the collector epitaxial layer; and forming an emitter region on a portion of the base region, wherein the emitter comprises a polycrystalline silicon material.

[0025] Optionally, forming a collector epitaxial layer on the surface of the substrate may include: depositing a low-doped N epitaxial layer on a highly doped N substrate.

[0026] Optionally, forming a base region on a portion of the collector epitaxial layer may include: forming an opening on a portion of the base region of the collector epitaxial layer; and forming a plasma oxide layer on the opening of the collector epitaxial layer to form the base region.

[0027] Optionally, forming an emitter region in a portion of the base region may include: removing a region in a portion of the base region; depositing a polycrystalline silicon material layer in the region;

[0028] And by injecting a high dose of dopant into the region to form the emitter region. Attached Figure Description

[0029] To gain a more complete understanding of this disclosure, reference is now made to the following description in conjunction with the accompanying drawings, which are provided by way of non-limiting example only, in which:

[0030] Figure 1 shows a discrete bipolar transistor, which includes an emitter region electrically coupled to the emitter terminal, a collector region electrically coupled to the collector terminal, and a base region electrically coupled to the base terminal.

[0031] Figures 2a to 2l The invention illustrates process steps for manufacturing an NPN bipolar junction transistor semiconductor device according to one or more embodiments of the invention. Detailed Implementation

[0032] Now refer to Figures 2a to 2lThis is provided, by way of example only, as a step-by-step description of the fabrication process of a bipolar transistor according to one or more embodiments. In this example, the bipolar device is an NPN device. An equivalent PNP device can be implemented by simply swapping the dopant N and the dopant P.

[0033] Figure 2a An initial substrate 201 for fabricating a semiconductor device according to an embodiment is shown. At this stage, a collector epitaxial layer 201a is deposited on the top surface of the substrate 201, such that the semiconductor device may include a lightly doped N collector epitaxial layer deposited on a heavily doped N substrate 201. For a substrate resistivity in the range of about 1 mΩcm to 10 mΩcm, the N doping in the substrate 201 is substantially 10,000 times higher than the N doping in the collector epitaxial layer. In this example, a high doping of the substrate 201 is required to achieve a low saturation voltage drop V. sat For N-type, the relationship between substrate resistivity and substrate doping is given. A first oxide layer 202 is formed on top of the lightly doped N-type collector epitaxial layer. The first oxide layer 202 can be deposited on the top surface of the lightly doped N-type collector epitaxial layer by any suitable technique or method. For example, the first oxide layer 202 can be thermally grown on the collector epitaxial layer. Other methods for forming the first oxide layer 202, such as chemical oxidation and electro-induced oxidation, can also be used. The first oxide layer 202 can be formed from an electrically insulating material such as silicon oxide. However, the oxide layer formed from silicon oxide is only an example, and it can be formed from another electrically insulating material.

[0034] Figure 2b It shows that in such Figure 2a Two channel implantations 203a are formed at the periphery or a portion of the first oxide layer 202 of the illustrated semiconductor device 200. The two channels 203 are first formed at the edge of the first oxide layer 202. The channels 203 can be formed by removing the ends of the first oxide layer 202 or opening the ends of the first oxide layer 202, for example, using dry (plasma) etching, wet (chemical) etching, reactive ion etching (RIE), or any other suitable etching process. A thin scattering oxide layer 203b is grown on the base of each channel 203. Highly doped N-doped N-doping is performed through the thin scattering oxide layer 203b using an ion or plasma implantation process to form the two channel implantations 203a. The channel implantations can be used to prevent any crosstalk between chips on the wafer and to prevent leakage current from flowing laterally from the collector to the base of the device. The channel implantations 203a can optionally be formed at different locations on the first oxide layer 202, depending on the physical layout of the semiconductor wafer 200a.

[0035] In the next stage, refer to Figure 2cA portion of the first oxide layer 202 is etched away using, for example, dry (plasma) etching, wet (chemical) etching, reactive ion etching (RIE), or any other suitable etching process. Figure 2b An opening 204 for base implantation is formed on the semiconductor device 200 shown. For example... Figure 2c As shown, an opening 204 for base implantation is formed between the channel implantations 203a of the semiconductor device 200. A thin scattering oxide layer 204b is grown on the opening 204 for base implantation. Then, a base implantation 204a, including a lightly doped P implantation, is formed by ion or plasma implantation through the thin scattering oxide layer 204b. The distance from the base edge to the channel diffusion should be chosen to be large enough to prevent lateral breakdown between the base and collector of the device.

[0036] Figure 2d It shows the formation in such Figure 2c A second oxide layer 205 is shown on the top surface of the semiconductor device 200. In this stage, a second oxide layer 205 is formed on the semiconductor device such that the oxide layer covers the top surface of the semiconductor device and is densified. Plasma-enhanced chemical vapor deposition (PECVD) can be used to form the oxide to maintain a low thermal budget, i.e., to achieve shallow junctions. The second oxide layer 205 can be a plasma oxide layer. Any known process, such as chemical oxidation and electro-induced oxidation, can be used to grow and densify the plasma oxide layer.

[0037] Figure 2e It shows in Figure 2d Another opening 206 for the emitter region 207 is formed on the surface of the base region 208 of the semiconductor device 200. The opening 206 is formed by etching away a portion of the second oxide layer 205 using, for example, dry (plasma) etching, wet (chemical) etching, reactive ion etching (RIE), or any other suitable etching process. The purpose of the opening 206 is to accommodate the bulk of the emitter region 207, as will be described in the following paragraphs. The emitter opening can be a single region as shown in the opening 206, or a single region as a grid of oxide pillars (not shown) within the emitter region, in which a base contact can be formed.

[0038] Figure 2f It shows the formation in Figure 2e The polysilicon layer 211 on the top surface of the semiconductor device 200. For example... Figure 2f As shown, the polysilicon layer 211 comprises two layers, an upper layer 209 and a lower layer 210. In an optional embodiment, the polysilicon layer 211 may comprise any number of polysilicon layers. In this example, the lower layer 210 of the polysilicon layer 211 is an undoped polysilicon layer. Firstly... Figure 2e A lower layer 210 is deposited on the top surface of the semiconductor device 200. Then, an upper layer 209 of a polysilicon layer 211 is deposited, and a high dose of N dopant is implanted into it to form an N-doped layer. Then, the polysilicon layer 211 is driven in, causing the N dopant in the upper layer 209 to diffuse into the lower layer 210.

[0039] In the next stage, we can... Figure 2f In the semiconductor device 200, unwanted polysilicon formed in the previous stage is removed, i.e., the polysilicon portion that is not part of the emitter. In this stage, a polysilicon layer 211 can be constructed such that only the portion that is not part of the emitter is retained. Figure 2g The polysilicon layer 211 shown is formed in a portion of the emitter region 207 of the semiconductor device 200, i.e., a polysilicon emitter layer. The polysilicon layer 211 can be constructed using any suitable technique or method.

[0040] In the next stage, such as Figure 2h As shown, in Figure 2g A third oxide layer 213 is formed on the exposed top surface of the semiconductor device 200. The oxide layer is a plasma oxide layer formed by plasma oxidation. Other methods for forming the oxide layer, such as chemical oxidation and electro-induced oxidation, can also be used.

[0041] Figure 2i It shows in Figure 2h An opening 214 for base contact diffusion is formed within the base region 208 of the semiconductor device 200. The opening 214 is etched into the base region 208, for example, by dry (plasma) etching, wet (chemical) etching, reactive ion etching (RIE), or any other suitable etching process. The purpose of the opening 214 is to receive base contact diffusion implantation of P-doped material higher than that of the base region.

[0042] In the next stage, refer to Figure 2j The base contact diffusion implantation 214a is injected into the opening 214 using ion or plasma implantation. At this stage, as... Figure 2i All dopants in the illustrated semiconductor device 200 are diffused into various regions of the semiconductor device 200. The polysilicon is protected from P-implantation by an oxide layer. Diffusion can be performed in a single step or multiple steps. The diffusion process results in the emitter polysilicon layer 212 being fully doped 215.

[0043] In the next stage, refer to Figure 2k ,exist Figure 2jAn opening 216 is formed on the top surface of the emitter region 207 of the illustrated semiconductor device 200. The opening 216 is formed by etching (e.g., dry (plasma) etching, wet (chemical) etching, reactive ion etching (RIE), or any other suitable etching process). The opening 216 is formed to accommodate a metal alloy, thereby contacting the fully doped emitter polysilicon layer 215. The metal alloy includes conductive materials such as titanium (Ti), aluminum (Al), and combinations thereof. Other suitable conductive materials may also be used. At this stage, the base contact opening is formed by a short acid dip to remove any unwanted oxides formed on the semiconductor device. The acid includes dilute hydrofluoric acid (HF) or any suitable acid. Because the oxides in the base contact are thinner than those on the polysilicon, only the opening for the emitter contact is formed on the polysilicon. Otherwise, the base contact would be severely over-etched. The short acid dip at this stage ensures that the base contact opening is free of oxides, preparing it for the next process step.

[0044] In the final stage, refer to Figure 2l In such Figure 2k Conductive material 217 is deposited on the top surface of the semiconductor device 200 shown. For example... Figure 2l As shown, conductive material 217 is deposited and constructed by sputtering. The sputtering deposition used can be, for example, ion beam deposition, ion-assisted deposition, reactive or gas flow sputtering, high target utilization sputtering (HiTUS), or high power pulsed magnetron sputtering (HiPIMS). Conductive material 217 can include titanium (Ti) and aluminum (Al). Other suitable conductive materials can also be used. Then... Figure 2k The top surface of the semiconductor device 200 is deposited and passivated and constructed. Then, according to an embodiment, a suitable back metal stack for assembly is applied to the top layer of the semiconductor device 200 to form... Figure 2l The bipolar transistor semiconductor device 200 in the middle.

[0045] According to this disclosure, a polysilicon emitter is used in a discrete bipolar transistor device having a collector on the back side of the wafer, i.e., the collector is located on the same (back side of the wafer) side as the base and emitter of the device. As described above, this can be achieved in one step by implanting a shallow base into a collector epitaxial layer, depositing polysilicon onto the emitter region, implanting the polysilicon region, and gently diffusing from the polysilicon into the silicon in the emitter.

[0046] According to this disclosure, a polysilicon emitter is used in a bipolar transistor semiconductor device having a collector on the back side of the device wafer. The bipolar transistor semiconductor device includes a substrate layer supporting a collector epitaxial layer. The device also includes a base region supported by a portion of the collector epitaxial layer. The base region of the device supports an emitter region made of polysilicon material. Terminals comprising Ti and Al extend from each of the collector epitaxial layer, the base region, and the emitter region.

[0047] As a result, the thermal budget of a bipolar transistor with this device structure can be reduced by about one-third or half that of a conventional bipolar transistor with similar ratings, thus allowing hFE greater than or equal to 1000 without being limited by process technology. This is achieved even with only a very small base current I... B During driving, bipolar transistors can also enter a high collector current I. C High hFE is achieved by combining a highly emitter-doped emitter (i.e., an emitter with a high emitter Grimm number) with a well-controlled narrow and low-doped base (i.e., a base with a low base Grimm number). The process range remains minimal, even for extremely narrow bases, due to the realization of a very low device thermal budget.

[0048] The proposed semiconductor device operates similarly to a standard BJT. However, due to the structural design, the hFE of the semiconductor device is increased (i.e., approximately twice that of an equivalent conventional bipolar transistor), and a base current of about half that of an equivalent conventional bipolar transistor is sufficient to bring the semiconductor device into operation for a given collector current I. C Saturation at that time. Because the base current needs to flow through 0.7V... BE Therefore, for power transistors, the power loss of the device can be quite considerable. For example, consider a 15A rated bipolar transistor, which has a power loss of approximately 10A. C At 15A, a base current of 1A is required to keep the transistor in saturation mode. This will result in a power loss on the BE diode (base-emitter diode) (I*V = 1A * 0.7V = 700mW). In this example, by providing a bipolar transistor with double hFE, the IV power loss on the BE diode can be halved, i.e., changed to 0.5A * 0.7V = 350mW.

[0049] In at least one embodiment, according to the embodiment Figure 2l The bipolar transistor semiconductor device 200 is suitable for high-power applications requiring high current amplification and device energy efficiency, but with limited package space. In other words, the BJT device can handle high load current and is compact in size, i.e., has a small device coverage area in a thermally efficient package.

[0050] In the automotive industry, BJTs can be used in a variety of vehicle electronic systems, such as load switches during airbag deployment, pre-drivers for driving high-current trench MOSFETs commonly used in fuel pumps, overvoltage protection, low-dropout regulation, LED backlight switching, and Royer converters for LCD backlights in instrument clusters. Figure 2l The bipolar transistor semiconductor device 200 can be suitable for deployment in any of the above applications and can handle high load current applications, but is also energy efficient and compact, thus occupying a very small package space in vehicles.

[0051] Features described in the context of a single embodiment may also be provided in combination in a single embodiment. Conversely, for the sake of brevity, the various features described in the context of a single embodiment may also be provided individually or in any suitable sub-combination.

[0052] The term "comprising" does not exclude other elements or steps, and the terms "a" or "an" do not exclude multiple. Reference numerals in the claims should not be construed as limiting the scope of the claims.

[0053] In view of the above description, it will be apparent to those skilled in the art that various modifications can be made within the scope of this invention.

[0054] The scope of this disclosure includes any novel feature or combination of features, or any generalization thereof, explicitly or implicitly disclosed herein, whether or not it relates to the claimed invention or alleviates any or all the problems solved by the invention. The applicant is thus drawn to note that new claims may be made for these features during the examination of this application or any such further application derived therefrom. In particular, with reference to the appended claims, features from dependent claims may be combined with features from independent claims, and features from individual independent claims may be combined in any suitable manner, not just the specific combinations listed in the claims.

Claims

1. A bipolar transistor semiconductor device, comprising: Substrate layer; A collector epitaxial layer directly supported on the substrate layer; Multiple channels are implanted in the collector epitaxial layer; A base region supported by a portion of the collector epitaxial layer, the base region being formed in the collector epitaxial layer; An emitter region supported by a portion of the base region, wherein the emitter region comprises polycrystalline silicon material; Base contact diffusion injection in the portion of the base region that does not support the emitter region, wherein the base contact diffusion injection is between the plurality of channel injections; and A titanium (Ti) layer and / or an aluminum (Al) layer, wherein the titanium and / or aluminum layers are supported by the plurality of channel implantations in the collector epitaxial layer, the base contact diffusion implantations in the base region and the emitter region, and wherein the titanium and / or aluminum layers further include AlSi and / or AlSiCu.

2. The bipolar transistor semiconductor device as claimed in claim 1, wherein, The substrate layer further includes silicon (Si) doped with at least one element from the group consisting of antimony (Sb), arsenic (As) and phosphorus (P).

3. The bipolar transistor semiconductor device as claimed in claim 1, wherein, The substrate layer and the collector epitaxial layer further include silicon (Si) doped with at least one element from the group consisting of arsenic (As) and phosphorus (P).

4. The bipolar transistor semiconductor device as claimed in claim 1, wherein, The base region also includes silicon (Si) doped with boron (B).

5. The bipolar transistor semiconductor device as claimed in claim 1, wherein, The emitter region also includes silicon (Si) doped with arsenic (As).

6. The bipolar transistor semiconductor device of claim 1, wherein, The emitter region also includes polycrystalline silicon doped with arsenic (As).

7. The bipolar transistor semiconductor device of claim 1, wherein, The emitter region also includes silicon (Si) doped with phosphorus (P).

8. The bipolar transistor semiconductor device of claim 1, wherein, The emitter region also includes polycrystalline silicon doped with phosphorus (P).

9. The bipolar transistor semiconductor device of claim 1, further comprising an AlSi layer, wherein, The AlSi layer is supported by the collector epitaxial layer, the base region, and the emitter region.

10. The bipolar transistor semiconductor device of claim 1, further comprising an AlSiCu layer, wherein, The AlSiCu layer is supported by the collector epitaxial layer, the base region, and the emitter region.

11. The bipolar transistor semiconductor device of claim 1, further comprising a back metal stack for assembly.

12. A method for manufacturing a bipolar transistor semiconductor device, the bipolar transistor semiconductor device comprising a doped substrate layer, a collector epitaxial layer, an emitter region, and a base region, the method comprising the following steps: The collector epitaxial layer is formed directly on the surface of the substrate layer, such that the collector epitaxial layer has a lower doping concentration of the same type as the doped substrate layer. Multiple channels are implanted in the collector epitaxial layer; The base region is formed on a portion of the collector epitaxial layer, such that the base region is formed in the collector epitaxial layer; A base contact diffusion injection is formed in the portion of the base region that does not support the emitter region, such that the base contact diffusion injection is formed between the plurality of channel injections; as well as The emitter region is formed on a portion of the base region, the emitter region comprising polycrystalline silicon material; as well as A titanium (Ti) layer and / or an aluminum (Al) layer are formed, wherein the titanium (Ti) layer and / or aluminum (Al) layer are supported by the plurality of channels implanted in the collector epitaxial layer, the base contact diffusion implanted in the base region and the emitter region, and wherein the titanium layer and / or aluminum layer further comprises AlSi and / or AlSiCu.

13. The method of claim 12, wherein, Forming the collector epitaxial layer on the surface of the substrate layer further includes the step of depositing a low-doped N epitaxial layer on a highly doped N substrate.

14. The method of claim 12, wherein, Forming the base region on a portion of the collector epitaxial layer further includes the following steps: An opening is formed on a portion of the base region of the collector epitaxial layer; and A plasma oxide layer is formed on the opening of the current collector epitaxial layer to form the base region.

15. The method of claim 12, wherein, Forming the emitter region in a portion of the base region further includes the following steps: Remove a portion of the base region; A polycrystalline silicon material layer is deposited in the region; and The region is implanted with a high dose of dopant to form the emitter region.

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