Semiconductor device and method of manufacturing the same, power device

Abstract

Embodiments of the present application provide a semiconductor device and a preparation method thereof, and a power device, and relate to the technical field of semiconductor. The preparation method of the semiconductor device comprises the following steps: providing a substrate, the substrate comprising an adjacent cell region and a peripheral region; forming a first dielectric layer on the substrate; forming a shielding structure and a first gate structure; forming a second dielectric layer, the second dielectric layer filling the recessed region and covering the first gate structure; removing part of the second dielectric layer and part of the first dielectric layer, the remaining second dielectric layer and the substrate forming a filling groove; the remaining first dielectric layer on the substrate forming a first mask structure; forming a second gate structure in the filling groove; and doping the exposed substrate with the first mask structure as a mask to form a first doped region and a second doped region. The embodiments of the present application can simplify the preparation process of the semiconductor device, thereby reducing the preparation difficulty of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, and a power device. Background Technology

[0002] Shielded trench MOSFETs have low on-resistance and fast switching speed, and are widely used in power devices.

[0003] Shielded-gate trench MOSFETs typically include a substrate and a shielding gate, transistor, and diode disposed within the substrate. The shielding gate reduces leakage current and improves the voltage withstand performance of the MOSFET. However, the fabrication process of shielded-gate trench MOSFETs is relatively complicated and difficult to manufacture. Summary of the Invention

[0004] In view of the above problems, this application provides a semiconductor device and its fabrication method, as well as a power device, which can simplify the fabrication process of semiconductor devices and thus reduce the difficulty of fabricating semiconductor devices.

[0005] To achieve the above objectives, the embodiments of this application provide the following technical solutions:

[0006] The first aspect of this application provides a method for fabricating a semiconductor device, comprising:

[0007] A substrate is provided, the substrate comprising adjacent cell regions and peripheral regions;

[0008] A first dielectric layer is formed, wherein the first dielectric layer is disposed on the substrate;

[0009] A shielding structure and a first gate structure are formed; the shielding structure is disposed in the cell region and extends into the substrate, wherein the top surface of the shielding structure forms a recessed region with the top surface of the first dielectric layer; the first gate structure is disposed in the peripheral region and extends into the substrate.

[0010] A second dielectric layer is formed, which fills the recessed region and covers the first gate structure;

[0011] A portion of the second dielectric layer and a portion of the first dielectric layer are removed, and the remaining second dielectric layer forms a filling groove with the substrate; wherein, the remaining first dielectric layer located on the substrate constitutes a first mask structure, and the first mask structure covers the first gate structure and a portion of the peripheral region;

[0012] A second gate structure is formed within the filling groove;

[0013] Using the first mask structure as a mask, the exposed substrate is doped to form a first doped region and a second doped region. The first doped region is located between the first gate structure and the second gate structure, and the second doped region is located on the side of the first gate structure opposite to the second gate structure.

[0014] In one possible implementation, the top surface of the second dielectric layer is flush with the top surface of the first dielectric layer.

[0015] In one possible implementation, the step of forming the shielding structure and the first gate structure includes:

[0016] The first dielectric layer and the substrate are patterned to form a first trench and a second trench, the first trench and the second trench being located in the cell region and the peripheral region, respectively;

[0017] A shielding structure is formed in the first trench and a first gate structure is formed in the second trench.

[0018] In one possible implementation, the shielding structure includes a first barrier layer, a first grid dielectric layer, and a shielding grid stacked sequentially, wherein the first barrier layer is disposed on the inner wall of the first trench; and wherein the shielding structure includes a first groove surrounding at least a portion of the shielding grid.

[0019] The first gate structure includes a second barrier layer, a second gate dielectric layer and a first gate layer stacked sequentially, wherein the second barrier layer is disposed on the inner wall of the second trench; wherein the first gate structure includes a second groove, the portion of the second groove surrounding the first gate.

[0020] In one possible implementation, the step of removing a portion of the second dielectric layer and a portion of the first dielectric layer includes:

[0021] A second mask structure is formed, which covers a portion of the peripheral region and exposes the second dielectric layer and the first dielectric layer located on the cell region;

[0022] Using the second mask structure as a mask, a portion of the second dielectric layer exposed on the cell region is removed, such that the top surface of the remaining second dielectric layer is lower than the top surface of the first dielectric layer and forms the filling groove with the substrate; and the exposed first dielectric layer is removed, the remaining first dielectric layer forming the first mask structure.

[0023] In one possible implementation, the step of forming the second gate structure within the filling groove includes:

[0024] A second gate dielectric layer is formed, which covers the inner wall of the filling groove and the top surface of the substrate;

[0025] A second gate is formed, which fills the area enclosed by the second gate dielectric layer in the filling trench; the second gate dielectric layer and the second gate constitute a second gate structure.

[0026] In one possible implementation, after the steps of forming the first doped region and the second doped region, the method includes:

[0027] The first doped region and the second doped region are subjected to heat treatment.

[0028] In one possible implementation, after the steps of forming the first doped region and the second doped region, the method includes:

[0029] A third mask structure is formed, which covers the second doped region;

[0030] Using the first mask structure and the third mask structure as masks, the first doped region is doped to form a third doped region within the first doped region; wherein the conductivity type of the first doped region is the same as that of the second doped region, and different from that of the third doped region.

[0031] In one possible implementation, after the step of forming the third doped region, the method further includes:

[0032] Remove the third mask structure;

[0033] An insulating layer is formed, which covers the third doped region, the second gate structure, the first mask structure, and the second doped region;

[0034] A conductive plug is formed within the insulating layer. The conductive plug includes a first conductive plug, a second conductive plug, a third conductive plug, and a fourth conductive plug. The first conductive plug is electrically connected to the second gate, the second conductive plug is electrically connected to the first doped region, the third conductive plug is electrically connected to the first gate, and the fourth conductive plug is electrically connected to the second doped region.

[0035] In one possible implementation, prior to the step of forming the conductive plug, the method further includes:

[0036] A heavily doped region is formed, wherein the heavily doped region is disposed at the end of the conductive plug facing the substrate.

[0037] A second aspect of this application provides a semiconductor device comprising:

[0038] The substrate includes adjacent cell regions and peripheral regions;

[0039] A shielding structure is disposed in the cell region and extends into the substrate;

[0040] A first gate structure is disposed in the peripheral region and extends into the substrate;

[0041] The second dielectric layer is disposed on the shielding structure and forms a filling groove with the substrate;

[0042] A second gate structure is disposed within the filling groove;

[0043] A first doped region and a second doped region, wherein the first doped region is located between the first gate structure and the second gate structure, and the second doped region is located on the side of the first gate structure opposite to the second gate structure.

[0044] A first mask structure is disposed on the substrate and covers the first gate structure and the region between the first gate structure and the second doped region.

[0045] In one possible implementation, the second dielectric layer wraps around a portion of the outer peripheral surface of the shielding structure and covers the top surface of the shielding structure.

[0046] In one possible implementation, a third doped region is further included, which is disposed on the first doped region, and the conductivity type of the third doped region is different from that of the first doped region.

[0047] A third aspect of this application provides a power device, including the semiconductor device described in the second aspect.

[0048] In the semiconductor devices and their fabrication methods provided in this application, as well as the power devices, during the etching back of the second dielectric layer, a portion of the first and second dielectric layers is simultaneously removed, leaving the retained first dielectric layer on the substrate to form a first mask structure. This first mask structure can be used as a mask to form the first and second doped regions using ion doping processes. This simplifies the process of re-fabricating the mask layer, thereby improving the efficiency of the fabrication method and the yield of the semiconductor device, while reducing manufacturing costs.

[0049] In addition to the technical problems solved by the embodiments of this application, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, other technical problems that the semiconductor devices and their preparation methods and power devices provided by the embodiments of this application can solve, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further explained in detail in the specific embodiments. Attached Figure Description

[0050] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0051] Figure 1 A process flow diagram of a method for fabricating semiconductor devices is provided for the embodiments of this application;

[0052] Figure 2 A schematic diagram illustrating the formation of a first dielectric layer in a method for fabricating a semiconductor device according to an embodiment of this application;

[0053] Figure 3 A schematic diagram illustrating the formation of a first photoresist layer in a method for fabricating a semiconductor device according to an embodiment of this application;

[0054] Figure 4 A schematic diagram illustrating the formation of a first trench and a second trench in a method for fabricating a semiconductor device according to an embodiment of this application;

[0055] Figure 5 A schematic diagram illustrating the formation of a first barrier material layer in a method for fabricating a semiconductor device according to an embodiment of this application;

[0056] Figure 6 A schematic diagram illustrating the formation of a first gate material layer in a method for fabricating a semiconductor device according to an embodiment of this application;

[0057] Figure 7 A schematic diagram of the removal of a portion of the first gate material layer in the fabrication method of the semiconductor device provided in this application embodiment. Figure 1 ;

[0058] Figure 8 A schematic diagram of the removal of a portion of the first gate material layer in the fabrication method of the semiconductor device provided in this application embodiment. Figure 2 ;

[0059] Figure 9 This is a schematic diagram illustrating the formation of a shielding gate in a method for fabricating a semiconductor device according to an embodiment of this application.

[0060] Figure 10 A schematic diagram illustrating the formation of a shielding structure and a first gate structure in a method for fabricating a semiconductor device according to an embodiment of this application;

[0061] Figure 11 A schematic diagram illustrating the formation of a second dielectric material layer in a method for fabricating a semiconductor device according to an embodiment of this application;

[0062] Figure 12 A schematic diagram illustrating the removal of a portion of the second dielectric material layer in the fabrication method of the semiconductor device provided in this application embodiment;

[0063] Figure 13 A schematic diagram illustrating the formation of a second dielectric layer in a method for fabricating a semiconductor device according to an embodiment of this application;

[0064] Figure 14 A schematic diagram illustrating the removal of a portion of the first dielectric layer in the fabrication method of the semiconductor device provided in this application embodiment;

[0065] Figure 15 A schematic diagram illustrating the formation of a first mask structure in a method for fabricating a semiconductor device according to an embodiment of this application;

[0066] Figure 16 A schematic diagram illustrating the formation of a third gate dielectric layer in a method for fabricating a semiconductor device according to an embodiment of this application;

[0067] Figure 17 A schematic diagram illustrating the formation of a second gate material layer in a method for fabricating a semiconductor device according to an embodiment of this application;

[0068] Figure 18 A schematic diagram illustrating the formation of a second gate structure in a method for fabricating a semiconductor device according to an embodiment of this application;

[0069] Figure 19 A schematic diagram illustrating the formation of a first doped region and a second doped region in a method for fabricating a semiconductor device according to an embodiment of this application;

[0070] Figure 20 This is a schematic diagram showing the first and second doped regions after heat treatment in the method for fabricating the semiconductor device provided in the embodiments of this application.

[0071] Figure 21 A schematic diagram illustrating the formation of a third mask structure in a method for fabricating a semiconductor device according to an embodiment of this application;

[0072] Figure 22 This is a schematic diagram illustrating the formation of a third doped region in a method for fabricating a semiconductor device according to an embodiment of this application.

[0073] Figure 23 This is a schematic diagram illustrating the formation of an insulating layer in a method for fabricating a semiconductor device according to an embodiment of this application.

[0074] Figure 24 A schematic diagram illustrating the formation of a third photoresist layer in a method for fabricating a semiconductor device according to an embodiment of this application;

[0075] Figure 25 A schematic diagram of forming etched holes in the method for fabricating a semiconductor device provided in this application embodiment. Figure 1 ;

[0076] Figure 26 A schematic diagram of forming etched holes in the method for fabricating a semiconductor device provided in this application embodiment. Figure 2 ;

[0077] Figure 27 This is a schematic diagram illustrating the formation of a heavily doped region in a method for fabricating a semiconductor device according to an embodiment of this application.

[0078] Figure 28 A schematic diagram of forming etched holes in the method for fabricating a semiconductor device provided in this application embodiment. Figure 3 ;

[0079] Figure 29 A schematic diagram illustrating the formation of a conductive plug in a method for fabricating a semiconductor device according to an embodiment of this application;

[0080] Figure 30 This is a schematic diagram of the formation of an interconnect layer in a method for fabricating a semiconductor device provided in an embodiment of this application.

[0081] Explanation of reference numerals in the attached figures:

[0082] 10: Substrate; 11: Cell region; 12: Peripheral region; 13: First trench; 14: Second trench; 15: Depression region; 16: Filling groove;

[0083] 20: First dielectric layer; 21: First sub-dielectric layer; 22: Second sub-dielectric layer; 23: Third sub-dielectric layer; 24: First mask structure;

[0084] 30: Shielding structure; 31: First barrier layer; 311: First barrier material layer; 32: First gate dielectric layer; 321: First gate dielectric material layer; 33: Shielding gate; 331: Gate material layer; 34: First groove;

[0085] 40: First gate structure; 41: Second barrier layer; 42: Second gate dielectric layer; 43: First gate; 44: Second recess;

[0086] 51: First photoresist layer; 511: First opening; 52: Second photoresist layer; 53: Third photoresist layer; 531: Second opening;

[0087] 60: Second dielectric layer; 61: Second dielectric material layer;

[0088] 70: Second mask structure;

[0089] 80: Second gate structure; 81: Third gate dielectric layer; 82: Second gate; 821: Second gate material layer;

[0090] 91: First doped region; 92: Second doped region; 93: Third doped region;

[0091] 100: Third mask structure;

[0092] 110: Insulation layer;

[0093] 121: First conductive plug; 1211: Third barrier layer; 1212: Conductive layer; 122: Second conductive plug; 123: Third conductive plug; 124: Fourth conductive plug;

[0094] 131: First etched hole; 132: Second etched hole; 133: Third etched hole; 134: Fourth etched hole; 135: Fifth etched hole;

[0095] 140: Heavily doped region;

[0096] 150: Interconnect layer. Detailed Implementation

[0097] As described in the background section, the fabrication process of shielded trench field-effect transistors in related technologies is relatively complicated. The inventors have discovered that the reason for this problem is that when etching back the second dielectric layer, the first and second dielectric layers located on the substrate are usually completely etched away. Afterwards, when etching the second dielectric layer located above the shielding structure, a mask layer needs to be prepared. Furthermore, when forming the first and second doped regions in the substrate, a mask layer also needs to be prepared again. This increases the number of steps involved in preparing and removing the mask layer, making the fabrication process of shielded trench field-effect transistors relatively complicated and thus increasing the difficulty of fabrication.

[0098] To address the aforementioned technical problems, this application provides a semiconductor device and its fabrication method, as well as a power device. During the etching of the second dielectric layer, a portion of the first and second dielectric layers is simultaneously removed, leaving the remaining first dielectric layer on the substrate to form a first mask structure. This first mask structure can be used as a mask to form the first and second doped regions using ion doping processes. This simplifies the process of re-fabricating the mask layer, thereby improving the efficiency of the fabrication method, the yield of the semiconductor device, and reducing manufacturing costs.

[0099] To make the above-mentioned objectives, features, and advantages of the embodiments of this application more apparent and understandable, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0100] Please refer to the attached document. Figure 1 This application provides a method for fabricating a semiconductor device, comprising the following steps:

[0101] Step S100: Provide a substrate, which includes adjacent cell regions and peripheral regions.

[0102] The substrate 10 serves as a support component for the semiconductor device, supporting other components disposed thereon. The substrate 10 can be made of a semiconductor material, which can be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbide compounds. It should be noted that the substrate 10 can be a single-layer structure or a multilayer structure. For example, the substrate 10 includes a substrate and an epitaxial layer disposed on the substrate.

[0103] The substrate 10 includes adjacent cell regions 11 and peripheral regions 12. Cell regions 11 are the main functional areas in a semiconductor device, typically containing multiple repeating unit structures or cells. Peripheral regions 12 are areas located around cell regions 11, typically used to support and protect the normal operation of cell regions 11.

[0104] Step S200: Form a first dielectric layer, wherein the first dielectric layer is disposed on the substrate.

[0105] The first dielectric layer 20 can be a single film layer or a stack of layers. For example, please refer to the appendix. Figure 2 The first dielectric layer 20 includes a first sub-dielectric layer 21, a second sub-dielectric layer 22 and a third sub-dielectric layer 23 stacked sequentially, with the first sub-dielectric layer 21 disposed on the substrate 10.

[0106] It should be noted that the various film layers of the first dielectric layer 20 can be prepared by deposition processes or other methods. For example, the material of the first sub-dielectric layer 21 includes silicon oxide. The first sub-dielectric layer 21 can be formed on the substrate 10 by a thermal oxidation process, which ensures that the first sub-dielectric layer 21 has high purity and quality, and makes the top surface of the first sub-dielectric layer 21 as flat as possible, thus improving the interface flatness of the first sub-dielectric layer 21.

[0107] Subsequently, a second sub-dielectric layer 22 and a third sub-dielectric layer 23 are formed on the first sub-dielectric layer 21 using a deposition process. The deposition process includes chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In this embodiment, the second sub-dielectric layer 22 is made of silicon nitride, and the third sub-dielectric layer 23 is made of silicon oxide.

[0108] In this embodiment, the thickness of the first sub-dielectric layer 21 is 30 Å to 500 Å; the thickness of the second sub-dielectric layer 22 is 100 Å to 150 Å; and the thickness of the third sub-dielectric layer 23 is 200 Å to 2500 Å.

[0109] Step S300: Form a shielding structure and a first gate structure; the shielding structure is disposed in the cell region and extends into the substrate, wherein the top surface of the shielding structure forms a recessed region with the top surface of the first dielectric layer; the first gate structure is disposed in the peripheral region and extends into the substrate.

[0110] For example, please refer to the appendix. Figure 3 and attached Figure 4 The first dielectric layer 20 and the substrate 10 are patterned to form a first trench 13 and a second trench 14, which are located in the cell region 11 and the peripheral region 12, respectively. It should be noted that the depth of the first trench 13 and the depth of the second trench 14 may be the same or different.

[0111] Please refer to the attached document. Figure 3 A first photoresist layer 51 is formed on the first dielectric layer 20, that is, the first photoresist layer 51 can be formed on the surface of the first dielectric layer 20 opposite to the substrate 10 by coating. The first photoresist layer 51 is then patterned to form spaced first openings 511 on the first photoresist layer 51. A portion of the orthographic projection of the first openings 511 onto the substrate 10 is located in the cell region 11, and a portion of the orthographic projection of the first openings 511 onto the substrate 10 is located in the peripheral region 12.

[0112] It should be noted that the number of first openings 511 in cell region 11 and the number of first openings 511 in peripheral region 12 can be selected according to the actual situation, and will not be elaborated further in this embodiment.

[0113] Please refer to the attached document. Figure 4 An etching process is used to remove the first dielectric layer 20 and part of the substrate 10 exposed in the first opening 511, so as to form a first trench 13 and a second trench 14 in the substrate 10. The depth of the first trench 13 and the second trench 14 is 3.3 μm, and the critical dimension CD of the first trench 13 and the second trench 14 is 1.0 μm.

[0114] Next, please refer to the appendix. Figure 5 To be continued Figure 10 A shielding structure 30 is formed in the first trench 13, and a first gate structure 40 is formed in the second trench 14. It should be noted that the shielding structure 30 and the first gate structure 40 can be fabricated in the same process, which can simplify the fabrication process of the shielding structure 30 and the first gate structure 40.

[0115] Please refer to the attached document. Figure 10 The shielding structure 30 includes a first barrier layer 31, a first gate dielectric layer 32, and a shielding grid 33 stacked sequentially. The first barrier layer 31 is disposed on the inner wall of the first trench 13, the first gate dielectric layer 32 is disposed on the first barrier layer 31, and the shielding grid 33 fills the area enclosed by the first gate dielectric layer 32. The shielding structure 30 also includes a first groove 34 that surrounds at least a portion of the shielding grid 33. It should be understood that the first groove 34 may surround a portion of the shielding grid 33 or the entire shielding grid 33.

[0116] Shielding gate 33 is typically grounded or connected to the source potential to shield the second gate 82 (see Appendix). Figure 18 The gate creates an electric field between the source and drain, thereby reducing gate charge and gate-drain capacitance. When a voltage is applied to the main gate, a channel is formed between the source and drain, through which current can flow. The presence of the shielded gate optimizes the electric field distribution, reducing on-resistance and switching losses.

[0117] It should be noted that the second gate is usually disposed above the shielding gate 33, and the second gate 82 (see Appendix) Figure 18 The shielding grid 33 typically employs a second dielectric layer 60 (see Appendix). Figure 11 To provide insulation, in this embodiment, the shielding structure 30 includes a first groove 34 that surrounds at least a portion of the shielding grid 33. This arrangement allows the second dielectric layer 60 (see attached diagram) to be insulated. Figure 14It not only covers the top surface of the shielding gate 33, but also wraps the sides of the shielding gate 33 to increase the contact area between the second dielectric layer 60 and the shielding gate 33. On the one hand, it can improve the interface strength between the second dielectric layer 60 and the shielding gate, and on the other hand, it can enhance the insulation performance of the shielding gate 33 and the second gate.

[0118] The first gate structure 40 includes a second barrier layer 41, a second gate dielectric layer 42, and a first gate 43 stacked sequentially. The second barrier layer 41 is disposed on the inner wall of the second trench 14, the second gate dielectric layer 42 is disposed on the second barrier layer 41, and the first gate 43 fills the area enclosed by the second barrier layer 41. The first gate structure 40 also includes a second recess 44 surrounding a portion of the first gate 43.

[0119] The transistor formed by the first gate structure 40 is used to control edge effects, optimize electric field distribution, manage heat, prevent leakage current, alleviate mechanical stress, protect the transistor located in the cell region, and improve package reliability. Furthermore, the design of the second recess 44 also helps to disperse stress and reduce the likelihood of semiconductor device failures during use.

[0120] In some possible implementations, the shielding structure 30 and the first gate structure 40 can be formed simultaneously, which can simplify the fabrication process of the semiconductor device. For example, please refer to the appendix. Figure 5 A first barrier material layer 311 and a first grid dielectric material layer 321 are formed on the inner walls of the first trench 13 and the second trench 14, and the first barrier material layer 311 covers the inner walls of the first trench 13 and the second trench 14.

[0121] Next, please refer to the appendix. Figure 6 A first gate material layer 331 is formed, which fills the area enclosed by the first gate dielectric material layer 321 and covers the top surface of the first dielectric layer 20. That is, the top surface of the first gate material layer 331 is higher than the top surface of the first dielectric layer 20. The material of the first gate material layer 331 includes polysilicon.

[0122] In this embodiment, the first barrier material layer 311 and the first gate dielectric material layer 321 can be made of the same material, for example, both including silicon oxide, but differ in their formation process. For example, the first barrier material layer 311 can be formed by oxidizing the substrate 10 exposed in the first trench 13 and the second trench 14 at 115°C using a thermal oxidation process. The thickness of the first barrier material layer 311 is 150 Å. Then, the first gate dielectric material layer 321 is formed on the first barrier material layer 311 using a deposition process. It should be understood that the first gate dielectric material layer 321 can also cover the top surface of the first dielectric layer 20. The thickness of the first gate dielectric material layer 321 is 180 Å. Afterwards, the semiconductor device can be heat-treated at 1110°C for 30 minutes. This setup can improve the performance of the first barrier material layer 311 and the first gate dielectric material layer 321, reduce the risk of breakdown of the first barrier material layer 311 and the first gate dielectric material layer 321, and thus avoid gate-induced drain leakage current.

[0123] Please refer to the attached document. Figure 7 The first gate material layer 331 is planarized using a chemical mechanical polishing (CMP) process so that the top surface of the first gate material layer 331 is flush with the top surface of the first dielectric layer 20.

[0124] Please refer to the attached document. Figure 8 Using the first dielectric layer 20 as a mask, the first gate material layer 331 is etched further so that the top surface of the first gate material layer 331 is lower than the top surface of the first dielectric layer 20. For example, the top surface of the first gate material layer 331 is flush with the top surface of the first sub-dielectric layer 21.

[0125] Please refer to the attached document. Figure 9 A second photoresist layer 52 is formed on the first dielectric layer 20, covering the peripheral region. Using the second photoresist layer 52 as a mask, the exposed first gate material layer 331 in the cell region 11 is further etched, such that the top surface of the retained first gate material layer 331 is lower than the top surface of the substrate 10. The retained first gate material layer 331 in the cell region 11 constitutes the shielding gate 33, and the retained first gate material layer 331 in the peripheral region 12 constitutes the first gate 43.

[0126] Please refer to the attached document. Figure 10The second photoresist layer 52 is removed, and using the first dielectric layer as a mask, the first barrier material layer 311 and the first gate dielectric material layer 321 are etched. The first barrier material layer 311 retained in the cell region 11 constitutes the first barrier layer 31, and the first barrier material layer 311 retained in the peripheral region 12 constitutes the second barrier layer 41. The first gate dielectric material layer 321 retained in the cell region 11 constitutes the first gate dielectric layer 32, and the first gate dielectric material layer 321 retained in the peripheral region 12 constitutes the second gate dielectric layer 42.

[0127] Furthermore, the top surface of the first gate dielectric layer 32 is lower than the shielding gate 33, so that the first barrier layer 31, the first gate dielectric layer 32, and the shielding gate 33 surround and form a first groove 34. The top surface of the second gate dielectric layer 42 is lower than the first gate 43, so that the second barrier layer 41, the second gate dielectric layer 42, and the first gate 43 surround and form a second groove 44.

[0128] It should be noted that, since the top surface of the shielding structure 30 is lower than the first dielectric layer 20, the top surface of the shielding structure 30 and the top surface of the first dielectric layer 20 form a recessed area 15.

[0129] Step S400: Form a second dielectric layer, which fills the recessed region and covers the first gate structure.

[0130] For example, please refer to the appendix. Figure 11 A second dielectric material layer 61 is formed using a deposition process. The second dielectric material layer 61 fills the recessed region 15 and covers the first gate structure 40 and the first dielectric layer 20. The material of the second dielectric material layer 61 may include silicon oxide.

[0131] Please refer to the attached document. Figure 12 A portion of the second dielectric material layer 61 is removed to form a surface where the top surface of the remaining second dielectric material layer 61 is flush with the top surface of the first dielectric layer 20. In this step, the second dielectric material layer 61 can be polished using a chemical mechanical polishing process to remove a portion of it. After removal, the semiconductor device can be heat-treated, for example, by heat-treating the semiconductor device at 950°C for 60 minutes, to improve the performance of the second dielectric material layer 61.

[0132] In this embodiment, the top surface of the second dielectric layer 60 is flush with that of the first dielectric layer 20. That is, in this step, the first dielectric layer 20 is removed to facilitate the subsequent formation of the first mask structure 24 on a portion of the first dielectric layer 20 (see attached figure). Figure 16 ).

[0133] Step S500: Remove part of the second dielectric layer and part of the first dielectric layer, and the remaining second dielectric layer and the substrate form a filling trench; wherein, the remaining first dielectric layer located on the substrate constitutes a first mask structure, and the first mask structure covers the first gate structure and part of the peripheral region.

[0134] Please refer to the attached document. Figure 13 A second mask structure 70 is formed, which covers a portion of the peripheral region 12 and exposes the second dielectric layer 60 and the first dielectric layer 20 located on the cell region 11. The second mask structure 70 can be a photoresist layer or a hard mask layer.

[0135] Please refer to the attached document. Figure 14 Using the second mask structure 70 as a mask, a portion of the second dielectric layer 60 exposed on the cell region is removed, such that the top surface of the remaining second dielectric layer 60 is lower than the top surface of the first dielectric layer 20, and forms a filling groove 16 with the substrate 10. The filling groove 16 is located within the first trench 13.

[0136] It should be noted that this step also removes a portion of the exposed first dielectric layer 20; for example, this step can remove the third sub-dielectric layer 23. Furthermore, in this embodiment, the second dielectric layer 60 and a portion of the first dielectric layer 20 are removed using a wet etching process. Therefore, the portion of the first dielectric layer 20 located below the second mask structure 70 will also be removed. In other words, this step can remove the portion of the first dielectric layer 20 whose structure can be referred to in the appendix. Figure 14 .

[0137] Please refer to the attached document. Figure 15 Using the second mask structure 70 as a mask, the exposed first dielectric layer 20 is etched to expose the top surface of the substrate 10, and the remaining first dielectric layer 20 forms the first mask structure 24.

[0138] Step S600: Form a second gate structure in the filling groove.

[0139] Please refer to the attached document. Figure 16 A third gate dielectric layer 81 is formed, which covers the inner wall of the filling trench 16 and the top surface of the substrate 10. It should be noted that the third gate dielectric layer 81 can be formed by a deposition process or an oxidation process, and the material of the third gate dielectric layer 81 includes silicon oxide. For example, the third gate dielectric layer 81 is formed by an oxidation process, wherein the preparation temperature is 1050°C.

[0140] Please refer to the attached document. Figure 17 and attached Figure 18 A second gate 82 is formed, which fills the area enclosed by the third gate dielectric layer 81 in the filling trench 16; the third gate dielectric layer 81 and the second gate 82 constitute the second gate structure 80.

[0141] A second gate material layer 821 is formed using a deposition process. The second gate material layer 821 fills the area enclosed by the third gate dielectric layer 81 within the filling trench 16 and covers both the third gate dielectric layer 81 and the first mask structure 24. The material of the second gate material layer 821 includes polysilicon. Subsequently, a chemical mechanical polishing process is used to remove a portion of the second gate material layer 821, leaving the remaining second gate material layer 821 to form the second gate 82. The top surface of the second gate 82 is flush with the top surface of the substrate 10.

[0142] Step S700: Using the first mask structure as a mask, the exposed substrate is doped to form a first doped region and a second doped region. The first doped region is located between the first gate structure and the second gate structure, and the second doped region is located on the side of the first gate structure away from the second gate structure.

[0143] Please refer to the attached document. Figure 19 A first doped region 91 and a second doped region 92 are formed on the exposed substrate 10 using a plasma doping process. The first doped region 91 and the second doped region 92 have the same conductivity type. In one example, the first doped region 91 and the second doped region 92 are P-type. In another example, the first doped region 91 and the second doped region 92 are N-type.

[0144] It should be noted that you should refer to the appendix. Figure 20 The aforementioned device can be heat-treated, specifically the first doped region 91 and the second doped region 92. For example, it can be treated at 1050°C for 60 minutes to increase the thickness of the first doped region 91 and the second doped region 92, which helps to form deeper doped regions and thus improves the electrical performance of the semiconductor device. Furthermore, it can promote the diffusion of dopant ions, making the doping concentration within the doped regions more uniform, which helps to improve the performance stability and consistency of the semiconductor device. The thickness of the first doped region 91 and the second doped region 92 is 500 Å.

[0145] In this embodiment, the first dielectric layer 20, which is retained and located on the substrate, forms the first mask structure 24. Using the first mask structure 24 as a mask, the first doped region 91 and the second doped region 92 are then formed using an ion doping process. This simplifies the process of re-fabricating the mask layer, thereby improving the efficiency of the fabrication method and the yield of semiconductor devices, and reducing manufacturing costs.

[0146] In one possible implementation, after the steps of forming the first doped region and the second doped region, the method for fabricating the semiconductor device includes:

[0147] Please refer to the attached document. Figure 21The third mask structure 100 covers the second doped region 92.

[0148] Please refer to the attached document. Figure 22 Using the first mask structure 24 and the third mask structure 100 as masks, the first doped region 91 is doped to form a third doped region 93 within the first doped region 91. The conductivity type of the first doped region 91 is the same as that of the second doped region 92, but different from that of the third doped region 93. In one example, when the conductivity type of the first doped region 91 is P-type, the conductivity type of the third doped region 93 is N-type; in another example, when the conductivity type of the first doped region 91 is N-type, the conductivity type of the third doped region 93 is P-type.

[0149] In this embodiment, the ion implantation energy is 60 keV and the implantation dose is 5 × 10¹⁵ ions / cm². 2 After ion implantation is complete, the semiconductor device can be heat-treated, for example, at 950°C for 30 minutes.

[0150] In this embodiment, the third doped region 93 and the first doped region 91 are stacked in the direction perpendicular to the substrate 10, such that the third doped region 93 constitutes the source region or drain region of the transistor, and the first doped region 91 constitutes the channel region of the transistor.

[0151] In one possible implementation, please refer to the appendix. Figure 23 Remove the third mask structure 100.

[0152] Next, please refer to the appendix. Figure 23 An insulating layer 110 is formed, which covers the third doped region 93, the second gate structure 80, the first mask structure 24, and the second doped region 92. The insulating layer 110 is formed using an atomic layer deposition process. The insulating layer 110 is made of polyethylene oxide (PEOX) and / or bisphenol S (BPS).

[0153] Please refer to the attached document. Figure 24 To be continued Figure 30 Conductive plugs are formed within the insulating layer. The conductive plugs include a first conductive plug 121, a second conductive plug 122, and a third conductive plug 123. The first conductive plug 121 is electrically connected to the second gate 82, the second conductive plug 122 is electrically connected to the third doped region 93, and the third conductive plug 123 is electrically connected to the second doped region 92.

[0154] For example, please refer to the appendix. Figure 24A third photoresist layer 53 is formed on the insulating layer 110, and the third photoresist layer 53 is patterned to form a plurality of second openings 531 within the third photoresist layer 53.

[0155] Please refer to the attached document. Figure 25 The insulating layer 110 and the first mask structure 24 exposed within the second opening 531 are removed by etching to form multiple etched holes. It should be understood that the number of etched holes can be set according to the number of devices in the substrate 10.

[0156] For example, the plurality of etch holes include a first etch hole 131, a second etch hole 132, a third etch hole 133, a fourth etch hole 134, and a fifth etch hole 135. Specifically, the first etch hole 131 exposes the top surface of the second gate 82, the second etch hole 132 exposes the top surface of the third doped region 93, the third etch hole 133 exposes the top surface of the first gate 43, the fourth etch hole 134 exposes the top surface of the second sub-dielectric layer in the first mask structure 24, and the fifth etch hole 135 exposes the top surface of the second doped region 92.

[0157] Please refer to the attached document. Figure 26 Continue along the first etch hole 131, the second etch hole 132, the third etch hole 133 and the fifth etch hole 135, such that the bottom of the first etch hole 131 extends into the second gate 82, the bottom of the second etch hole 132 extends into the first doped region 91, the bottom of the third etch hole 133 extends into the first gate 43, and the bottom of the fifth etch hole 135 extends into the second doped region 92.

[0158] It should be noted that the conductive plug formed later is electrically connected to the corresponding device. In order to reduce the contact resistance between the two, the preparation method provided in this embodiment further includes: forming a heavily doped region 140, which is disposed at the end of the conductive plug facing the substrate 10.

[0159] For example, please refer to the appendix. Figure 27 The exposed areas of each etched via are heavily doped using a plasma doping process to form heavily doped regions 140. This configuration reduces the contact resistance between the conductive plug and the corresponding device, helping to improve current transfer efficiency and reduce power loss. It also improves the overall performance of the semiconductor device, including switching speed, signal transmission speed, and current drive capability.

[0160] Please refer to the attached document. Figure 28 Continue etching along the fourth etch hole 134 to remove the first mask structure 24 exposed in the fourth etch hole 134, so as to expose the top surface of the substrate 10.

[0161] Please refer to the attached document. Figure 29Conductive plugs are formed in each etched hole through a deposition process. The multiple conductive plugs include a first conductive plug 121, a second conductive plug 122, a third conductive plug 123, and a fourth conductive plug 124. The first conductive plug 121 is electrically connected to the second gate 82, the second conductive plug 122 is electrically connected to the first doped region 91, the third conductive plug 123 is electrically connected to the first gate 43, and the fourth conductive plug 124 is electrically connected to the second doped region 92.

[0162] The conductive plug may include a third barrier layer 1211 and a conductive layer 1212. The third barrier layer 1211 is disposed on the inner wall of the etched hole and covers the insulating layer 110; the conductive layer 1212 fills the area enclosed by the third barrier layer 1211. The material of the third barrier layer 1211 includes titanium nitride, and the material of the conductive layer 1212 includes tungsten.

[0163] It should be noted that after the conductive plug is formed, an interconnect layer needs to be formed. The interconnect layer includes multiple interconnect blocks that are insulated from each other. Each interconnect block is used to electrically connect with the corresponding conductive plug to facilitate connection with external circuits. In addition, the drain of the transistor and the other electrode of the diode are usually formed on the back side of the substrate 10, which is related technology and will not be described in detail here.

[0164] This application also provides a semiconductor device, including:

[0165] The base 10 includes adjacent cell regions 11 and peripheral regions.

[0166] A shielding structure 30 is disposed in the cell region 11 and extends into the substrate 10, wherein the top surface of the shielding structure 30 forms a recessed region 15 with the top surface of the first dielectric layer 20.

[0167] A first gate structure 40 is disposed in the peripheral region 12 and extends into the substrate 10.

[0168] The second dielectric layer 60 is disposed on the shielding structure 30 and forms a filling groove 16 with the substrate 10.

[0169] The second gate structure 80 is disposed within the filling groove 16.

[0170] A first doped region 91 and a second doped region 92 are located between the first gate structure 40 and the second gate structure 80, and the second doped region 92 is located on the side of the first gate structure away from the second gate structure.

[0171] The first mask structure 24 is disposed on the substrate 10 and covers the first gate structure 40 and the area between the first gate structure 40 and the second doped region 92.

[0172] In some possible embodiments, the second dielectric layer 60 includes a portion of the outer peripheral surface of the shielding structure 30 and covers the top surface of the shielding structure 30. This arrangement increases the contact area between the second dielectric layer 60 and the shielding gate 33, which on the one hand improves the interface strength between the second dielectric layer 60 and the shielding gate, and on the other hand enhances the insulation performance of the shielding gate 33 and the second gate.

[0173] In some possible embodiments, the semiconductor device further includes a third doped region 93 disposed on the first doped region 91, and the conductivity type of the third doped region 93 is different from that of the first doped region 91. It should be noted that a fourth doped region (not shown in the figure) is also disposed on the side of the first doped region 91 opposite to the third doped region 93, and the fourth doped region has the same conductivity type as the third doped region 93, so that the third doped region 93, the first doped region 91, and the fourth doped region constitute a PNP structure or an NPN structure.

[0174] This application also provides a power device, including the semiconductor device described in any of the above embodiments. However, the power device formed in this embodiment is not limited to a shielded gate field-effect transistor (SGFET).

[0175] It should be noted that the beneficial effects of the power devices provided in this application embodiment are the same as those of the semiconductor devices provided in the above embodiments, and will not be elaborated further here. The power devices provided in this application embodiment can be applied to discrete devices, AC-DC converters, or temperature sensors.

[0176] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0177] It should be noted that the terms "one embodiment," "embodiment," "exemplary embodiment," "some embodiments," etc., mentioned in the specification indicate that the described embodiment may include a specific feature, structure, or characteristic, but not every embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the knowledge scope of those skilled in the art.

[0178] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include; A substrate is provided, the substrate comprising adjacent cell regions and peripheral regions; A first dielectric layer is formed, wherein the first dielectric layer is disposed on the substrate; A shielding structure and a first gate structure are formed; the shielding structure is disposed in the cell region and extends into the substrate, wherein the top surface of the shielding structure forms a recessed region with the top surface of the first dielectric layer; the first gate structure is disposed in the peripheral region and extends into the substrate. A second dielectric layer is formed, which fills the recessed region and covers the first gate structure; A portion of the second dielectric layer and a portion of the first dielectric layer are removed, and the remaining second dielectric layer forms a filling groove with the substrate; wherein, the remaining first dielectric layer located on the substrate constitutes a first mask structure, and the first mask structure covers the first gate structure and a portion of the peripheral region; A second gate structure is formed within the filling groove; Using the first mask structure as a mask, the exposed substrate is doped to form a first doped region and a second doped region. The first doped region is located between the first gate structure and the second gate structure, and the second doped region is located on the side of the first gate structure away from the second gate structure. The steps of removing a portion of the second dielectric layer and a portion of the first dielectric layer include: A second mask structure is formed, which covers a portion of the peripheral region and exposes a second dielectric layer and a first dielectric layer located on the cell region; Using the second mask structure as a mask, a portion of the second dielectric layer exposed on the cell region is removed, such that the top surface of the remaining second dielectric layer is lower than the top surface of the first dielectric layer and forms the filling groove with the substrate; and the exposed first dielectric layer is removed, the remaining first dielectric layer forming the first mask structure.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The top surface of the second dielectric layer is flush with the top surface of the first dielectric layer.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The steps of forming the shielding structure and the first gate structure include: The first dielectric layer and the substrate are patterned to form a first trench and a second trench, the first trench and the second trench being located in the cell region and the peripheral region, respectively; A shielding structure is formed in the first trench and a first gate structure is formed in the second trench.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, The shielding structure includes a first blocking layer, a first grid dielectric layer, and a shielding grid stacked sequentially, wherein the first blocking layer is disposed on the inner wall of the first trench; wherein the shielding structure includes a first groove surrounding at least a portion of the shielding grid; The first gate structure includes a second barrier layer, a second gate dielectric layer and a first gate layer stacked sequentially, wherein the second barrier layer is disposed on the inner wall of the second trench; wherein the first gate structure includes a second groove, the portion of the second groove surrounding the first gate.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of forming the second gate structure within the filling groove includes: A second gate dielectric layer is formed, which covers the inner wall of the filling groove and the top surface of the substrate; A second gate is formed, which fills the area enclosed by the second gate dielectric layer in the filling trench; the second gate dielectric layer and the second gate constitute a second gate structure.

6. The method for fabricating a semiconductor device according to any one of claims 1-5, characterized in that, After the steps of forming the first doped region and the second doped region, the method includes: The first doped region and the second doped region are subjected to heat treatment.

7. The method for fabricating a semiconductor device according to claim 6, characterized in that, After the steps of forming the first doped region and the second doped region, the method includes: A third mask structure is formed, which covers the second doped region; Using the first mask structure and the third mask structure as masks, the first doped region is doped to form a third doped region within the first doped region; wherein the conductivity type of the first doped region is the same as that of the second doped region, and different from that of the third doped region.

8. The method for fabricating a semiconductor device according to claim 7, characterized in that, After the step of forming the third doped region, the method further includes: Remove the third mask structure; An insulating layer is formed, which covers the third doped region, the second gate structure, the first mask structure, and the second doped region; A conductive plug is formed within the insulating layer. The conductive plug includes a first conductive plug, a second conductive plug, a third conductive plug, and a fourth conductive plug. The first conductive plug is electrically connected to the second gate, the second conductive plug is electrically connected to the first doped region, the third conductive plug is electrically connected to the first gate, and the fourth conductive plug is electrically connected to the second doped region.

9. The method for fabricating a semiconductor device according to claim 8, characterized in that, Prior to the step of forming the conductive plug, the method further includes: A heavily doped region is formed, wherein the heavily doped region is disposed at the end of the conductive plug facing the substrate.

10. A semiconductor device, manufactured using the method according to any one of claims 1-9, characterized in that, include: The substrate includes adjacent cell regions and peripheral regions; A shielding structure is disposed in the cell region and extends into the substrate; A first gate structure is disposed in the peripheral region and extends into the substrate; The second dielectric layer is disposed on the shielding structure and forms a filling groove with the substrate; A second gate structure is disposed within the filling groove; A first doped region and a second doped region, wherein the first doped region is located between the first gate structure and the second gate structure, and the second doped region is located on the side of the first gate structure opposite to the second gate structure. A first mask structure is disposed on the substrate and covers the first gate structure and the region between the first gate structure and the second doped region.

11. The semiconductor device according to claim 10, characterized in that, The second dielectric layer wraps around a portion of the outer peripheral surface of the shielding structure and covers the top surface of the shielding structure.

12. The semiconductor device according to claim 11, characterized in that, It also includes a third doped region, which is disposed on the first doped region, and the conductivity type of the third doped region is different from that of the first doped region.

13. A power device, characterized in that, Includes the semiconductor device according to any one of claims 10-12.

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