Semiconductor device and manufacturing method thereof, and electronic device

Abstract

The present invention provides a semiconductor device and a manufacturing method thereof, and an electronic device, the method comprising: providing a substrate, in which a body region and a drift region are formed; forming a mask layer on the surface of the substrate; patterning the mask layer to expose a portion of the drift region, and etching the substrate to form a groove in the drift region; forming a field oxide layer, the field oxide layer fills the groove, and the top surface of the field oxide layer is higher than the surface of the substrate; removing part of the mask layer so that the remaining mask layer is used as a gate dielectric layer, the gate dielectric layer covers the surface of part of the body region and part of the drift region, and a side wall of the gate dielectric layer contacts the field oxide layer; forming a gate electrode layer, the gate electrode layer covers the top surface of the gate dielectric layer and part of the field oxide layer, wherein the gate dielectric layer and the gate electrode layer constitute a gate structure. The present invention forms a mask layer, and then forms a field oxide layer in the groove using the mask layer as a mask, which can effectively suppress the bird's beak effect, reduce the width of the bird's beak region of the field oxide layer, and improve the device performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. Background Art

[0002] There are two main types of DMOS (double-diffused MOSFET): VDMOS (vertical double-diffused MOSFET) and LDMOS (lateral double-diffused MOSFET). Among them, LDMOS is widely used in the industry because it is more compatible with CMOS (Complementary Metal Oxide Semiconductor) process and has advantages in voltage resistance, gain, linearity, switching performance, heat dissipation performance, etc.

[0003] Two important parameters of LDMOS are breakdown voltage and on-resistance. In order to improve the breakdown voltage of LDMOS, a gate field plate structure is usually adopted, that is, the gate is extended to the field oxide layer to form a gate field plate structure. The field oxide layer in the gate field plate structure is generally manufactured using the Local Oxidation of Silicon (LOCOS) process.

[0004] However, if Figure 1 As shown, the field oxide layer 110 obtained by the LOCOS process in the related art will form a "bird's beak" structure due to the bird's beak effect. The "bird's beak" structure will cause the current path of the field oxide layer to become longer, resulting in a higher on-resistance of the device; and the "bird's beak" structure will also limit the thickness of the field oxide layer, making it impossible to form a thicker field oxide layer, thereby limiting the breakdown voltage of the device. Summary of the invention

[0005] A series of simplified concepts are introduced in the Summary of the Invention, which will be further described in detail in the Detailed Description of the Invention. The Summary of the Invention does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0006] In view of the existing problems, the present invention provides a method for manufacturing a semiconductor device, comprising:

[0007] Providing a substrate, wherein a body region and a drift region extending from a surface of the substrate into the substrate are formed in the substrate, the drift region has a first conductivity type, and the body region has a second conductivity type;

[0008] forming a mask layer on the surface of the substrate;

[0009] patterning the mask layer to expose a portion of the drift region, and etching the substrate to form a trench in the drift region;

[0010] forming a field oxide layer, wherein the field oxide layer fills the trench, wherein a top surface of the field oxide layer is higher than a surface of the substrate;

[0011] Removing part of the mask layer so that the remaining mask layer is used as a gate dielectric layer, the gate dielectric layer covers a part of the surface of the body region and a part of the drift region, and a side wall of the gate dielectric layer contacts the field oxide layer;

[0012] A gate electrode layer is formed, wherein the gate electrode layer covers the top surface of the gate dielectric layer and a portion of the field oxide layer, wherein the gate dielectric layer and the gate electrode layer constitute a gate structure.

[0013] Exemplarily, the material of the mask layer includes silicon oxynitride, and forming the mask layer on the surface of the substrate includes:

[0014] The mask layer is formed on the surface of the substrate by a thermal oxidation process in a nitrogen-containing atmosphere.

[0015] Exemplarily, the gas of the nitrogen-containing atmosphere includes at least one of ammonia, nitric oxide and nitrous oxide.

[0016] Exemplarily, forming the gate dielectric layer includes:

[0017] Thinning the mask layer to a predetermined thickness;

[0018] A portion of the mask layer is removed by etching to expose a portion of the surface of the substrate to form the gate dielectric layer.

[0019] Exemplarily, after removing part of the mask layer so that the remaining mask layer is used as the gate dielectric layer, the method further includes:

[0020] A source region located in the body region and a drain region located in the drift region are formed, wherein the source region and the drain region are respectively located at two sides of the gate structure, and the source region and the drain region have a first conductivity type.

[0021] Exemplarily, a well region is further formed in the substrate, the body region and the drift region are located in the well region, and the well region has a first conductivity type.

[0022] Exemplarily, the field oxide layer includes a field oxide region and a bird's beak region located on both sides of the field oxide region, and the thickness of the field oxide region ranges from 0.5µm to 0.8µm.

[0023] Exemplarily, the field oxide layer includes a field oxide region and a bird's beak region located on both sides of the field oxide region, and the width of the bird's beak region ranges from 0.1µm to 0.5µm.

[0024] Another aspect of the present invention provides a semiconductor device, wherein the semiconductor device is manufactured by using the above method.

[0025] Another aspect of the present invention provides an electronic device, comprising the above-mentioned semiconductor device.

[0026] The semiconductor device and its manufacturing method and electronic device of the embodiments of the present invention form a mask layer, and then use the mask layer as a mask to form a field oxide layer in the groove, which can effectively suppress the bird's beak effect and reduce the width of the bird's beak region of the field oxide layer, so that the current path is shorter, thereby reducing the on-resistance of the device. At the same time, a thicker field oxide layer can be formed, thereby increasing the breakdown voltage of the device, and the process stability and feasibility are strong, thereby improving the device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The following drawings of the present invention are used as part of the present invention for understanding the present invention. The drawings show embodiments of the present invention and their descriptions to explain the principles of the present invention. In the drawings:

[0028] Figure 1 A cross-sectional schematic diagram of a semiconductor device for obtaining a field oxide layer in a gate field plate structure by using a LOCOS process in the related art is shown;

[0029] Figure 2 A flowchart showing a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown;

[0030] Figure 3A-Figure 3F A cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown. DETAILED DESCRIPTION

[0031] Next, the present invention will be more fully described in conjunction with the accompanying drawings, in which embodiments of the present invention are shown. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, providing these embodiments will make the disclosure thorough and complete and fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. The same reference numerals throughout represent the same elements.

[0032] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0033] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0034] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "a", "an", and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0035] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0036] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art in the field of the present invention. It will also be understood that terms such as those defined in commonly used dictionaries should be understood to have a meaning consistent with their meaning in the context of the relevant art and / or this specification, and should not be interpreted in an ideal or overly formal sense unless expressly defined as such herein.

[0037] In order to fully understand the present invention, detailed steps and structures will be presented in the following description to illustrate the technical solution proposed by the present invention. The preferred embodiments of the present invention are described in detail below, but in addition to these detailed descriptions, the present invention may also have other implementations.

[0038] The field oxide layer in the gate field plate structure in the related art is generally manufactured by LOCOS process. Figure 1 As shown, in the process of obtaining the field oxide layer 110 by adopting the LOCOS process, a bird's beak effect will occur, that is, oxygen atoms will diffuse laterally into the active area to form a "bird's beak" structure. The "bird's beak" structure will cause the curvature of the field oxide layer to become smaller, thereby causing the current path of the field oxide layer to become longer, resulting in an increase in the on-resistance of the device and even causing the device to crash; and the "bird's beak" structure will also limit the thickness of the field oxide layer, resulting in the inability to form a thicker field oxide layer. The thicker the field oxide layer, the higher the breakdown voltage of the device. The inability to form a thicker field oxide layer will result in the inability to obtain a higher breakdown voltage, thereby limiting the device performance.

[0039] Therefore, in view of the existence of the above-mentioned technical problems, the present invention proposes a method for manufacturing a semiconductor device, such as Figure 2 As shown, it mainly includes the following steps:

[0040] Step S1, providing a substrate, wherein a body region and a drift region extending from a surface of the substrate into the substrate are formed in the substrate, the drift region has a first conductivity type, and the body region has a second conductivity type;

[0041] Step S2, forming a mask layer on the surface of the substrate;

[0042] Step S3, patterning the mask layer to expose a portion of the drift region, and etching the substrate to form a trench in the drift region;

[0043] Step S4, forming a field oxide layer, wherein the field oxide layer fills the trench, wherein a top surface of the field oxide layer is higher than a surface of the substrate;

[0044] Step S5, removing part of the mask layer so that the remaining mask layer is used as a gate dielectric layer, the gate dielectric layer covers a part of the surface of the body region and a part of the drift region, and a side wall of the gate dielectric layer contacts the field oxide layer;

[0045] Step S6, forming a gate electrode layer, wherein the gate electrode layer covers the top surface of the gate dielectric layer and a portion of the field oxide layer, wherein the gate dielectric layer and the gate electrode layer constitute a gate structure.

[0046] The method for manufacturing a semiconductor device of the present invention forms a mask layer, and then forms a field oxide layer in a groove using the mask layer as a mask, which can effectively suppress the bird's beak effect, reduce the width of the bird's beak region of the field oxide layer, make the current path shorter, and thus reduce the on-resistance of the device. At the same time, a thicker field oxide layer can be formed, and thus the breakdown voltage of the device can be increased. The process stability and feasibility are strong, and the device performance is improved.

[0047] Embodiment 1

[0048] Below, reference Figures 2 to 3F The method for manufacturing a semiconductor device of the present invention is described in detail, wherein: Figure 2 A flowchart showing a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown. Figure 3A-Figure 3F A cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of the present invention is shown.

[0049] Exemplarily, the method for manufacturing a semiconductor device of the present invention comprises the following steps:

[0050] First, step S1 is performed to provide a substrate, wherein a body region and a drift region extending from a surface of the substrate into the substrate are formed in the substrate, the drift region has a first conductivity type, and the body region has a second conductivity type.

[0051] In one example, the substrate 300 is a bulk silicon substrate, which may include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III / V compound semiconductors, or the substrate 300 may also include silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) or germanium on insulator (GeOI), etc. Although several examples of materials that can form the substrate 300 are described herein, any material that can be used as the substrate 300 falls within the spirit and scope of the present invention.

[0052] In one example, if Figure 3A As shown, the drift region 302 has a first conductivity type, and the body region 301 has a second conductivity type, wherein the first conductivity type is an N-type conductivity type and the second conductivity type is a P-type conductivity type, or the first conductivity type is a P-type conductivity type and the second conductivity type is an N-type conductivity type.

[0053] In one example, if Figure 3A As shown, a well region 303 is also formed in the substrate 300, the body region 301 and the drift region 302 are located in the well region 303, and the well region 303 has a first conductivity type. Optionally, one side of the drift region 302 is in lateral contact with the body region 301. Exemplarily, an ion implantation process may be performed on the substrate 300 to form the body region 301, the drift region 302, and the well region 303.

[0054] Next, step S2 is performed to form a mask layer on the surface of the substrate. Figure 3B As shown, a mask layer 304 is formed on the surface of the substrate 300 .

[0055] In one example, the material of the mask layer 304 includes silicon oxynitride, and forming the mask layer 304 on the surface of the substrate 300 includes: forming the mask layer 304 on the surface of the substrate 300 by a thermal oxidation process in a nitrogen-containing atmosphere. Exemplarily, the gas of the nitrogen-containing atmosphere includes at least one of ammonia, nitric oxide, and nitrous oxide. The material of the mask layer 304 can also be selected from other suitable materials according to actual needs.

[0056] Next, step S3 is performed to pattern the mask layer to expose a portion of the drift region, and to etch the substrate to form a trench in the drift region.

[0057] In one example, if Figure 3CAs shown, various etching processes commonly used in the art can be used to pattern the mask layer 304 to expose part of the drift region 302, and the exposed drift region 302 is a region where a field oxide layer is predetermined to be formed; and various etching processes commonly used in the art can be used to etch the substrate 300 to form a groove 305 in the drift region 302. Among them, the etching process can include a traditional dry etching process and a wet etching process, such as reactive ion etching, ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching process can be used, or more than one etching process can be used. Exemplarily, the depth and width of the groove 305 should be reasonably set according to actual needs. For example, the depth of the groove 305 should be set according to the thickness required for the field oxide layer to be formed subsequently. Exemplarily, the area where the groove 305 is located is defined as a field oxide region, which is a region where a field oxide layer is predetermined to be formed, and the area surrounding the field oxide region is defined as an active region, which is a region where various active components are predetermined to be formed (for example, a source region, a drain region, etc. are formed in the active region).

[0058] Next, step S4 is performed to form a field oxide layer, wherein the field oxide layer fills the trench, wherein a top surface of the field oxide layer is higher than a surface of the substrate.

[0059] In one example, if Figure 3D As shown, the LOCOS process can be used to form the field oxide layer 306 filling the trench 305, that is, the field oxide layer 306 is grown in the area not covered by the mask layer 304 by thermal oxidation, and the surface of the field oxide layer 306 is higher than the surface of the substrate 300. Specifically, during the thermal oxidation process, oxygen atoms react with silicon in the substrate 300 exposed at the bottom of the trench 305 to form an oxide layer, and because the formed oxide layer is thicker than the consumed silicon, the top surface of the formed field oxide layer 306 is lifted to be higher than the top surface of the substrate 300.

[0060] In one example, in the process of forming the field oxide layer 306, the mask layer 304 acts as a mask. Due to the existence of the mask layer 304, the bird's beak effect can be effectively suppressed, and the width of the bird's beak region of the field oxide layer 306 is reduced, making the current path shorter, thereby reducing the on-resistance of the device; at the same time, the narrower bird's beak region enables the formation of a thicker field oxide layer 306, thereby increasing the breakdown voltage of the device, and the process stability and feasibility are strong, thereby improving the device performance.

[0061] In one example, if Figure 3DAs shown, the field oxide layer 306 includes a field oxide region and a bird's beak region (i.e., a "bird's beak" structure) located on both sides of the field oxide region, wherein the field oxide region is a region of the field oxide layer 306 located in a predefined field oxide region, and the bird's beak region is a region of the field oxide layer 306 extending into the active region due to the bird's beak effect. In this embodiment, the thickness range of the field oxide region is 0.5µm-0.8µm, and in other embodiments, the thickness range of the field oxide region can also be other suitable ranges; it is worth noting that, since the bird's beak effect is suppressed in the solution of the present application, the bird's beak region is narrower, so that a thicker field oxide region can be formed, thereby increasing the breakdown voltage of the device. In this embodiment, the width range of the bird's beak region is 0.1µm-0.5µm, and in other embodiments, the width range of the bird's beak region can also be other suitable ranges; it is worth noting that since the bird's beak effect is suppressed, the bird's beak region is narrower, so that the current path is shorter, thereby reducing the on-resistance of the device. Exemplarily, the width of the bird's beak region mentioned herein refers to the width of the bird's beak region along a direction perpendicular to a contact surface between the bird's beak region and the field oxide region (ie, a lateral diffusion direction of the field oxide layer 306 ).

[0062] Next, step S5 is performed to remove part of the mask layer so that the remaining mask layer is used as a gate dielectric layer, the gate dielectric layer covers a part of the surface of the body region and a part of the drift region, and a side wall of the gate dielectric layer contacts the field oxide layer.

[0063] In one example, if Figure 3E and Figure 3F As shown, after removing part of the mask layer 304, the remaining mask layer 304 can be used as the gate dielectric layer 307 of the gate structure formed subsequently, without the need to re-form the gate dielectric layer, thereby simplifying the process steps. Figure 3E and Figure 3F As shown, the formation Figure 3F The gate dielectric layer 307 shown includes: first, Figure 3E As shown, the mask layer 304 is thinned to a predetermined thickness, which is the target thickness of the gate dielectric layer 307. The predetermined thickness should be reasonably set according to actual needs. Various conventional processes in the art can be used to thin the mask layer 304, such as a grinding process or an etching process to thin the mask layer 304. Then, as Figure 3F As shown, a portion of the mask layer is etched away to expose a portion of the surface of the substrate 300, forming a gate dielectric layer 307, the gate dielectric layer 307 covers a portion of the surface of the body region 301 and a portion of the drift region 302, and a side wall of the gate dielectric layer 307 contacts the field oxide layer 306, and the gate dielectric layer 307 plays an isolation and protection role. Exemplarily, the top surface of the field oxide layer 306 is higher than the top surface of the gate dielectric layer 307.

[0064] Finally, step S6 is performed to form a gate electrode layer, wherein the gate electrode layer covers the top surface of the gate dielectric layer and a portion of the field oxide layer, wherein the gate dielectric layer and the gate electrode layer constitute a gate structure.

[0065] In one example, if Figure 3F As shown, the gate electrode layer 308 covers the top surface of the gate dielectric layer 307 and a portion of the field oxide layer 306, and the gate dielectric layer 307 and the gate electrode layer 308 constitute a gate structure. Exemplarily, the gate electrode layer 308 is composed of polysilicon material, and generally metal, metal nitride, metal silicide or similar compounds can also be used as the material of the gate layer. Exemplarily, the number of layers of the gate electrode layer 308 can be at least one layer, and the gate electrode layer 308 can serve as a field plate.

[0066] In one example, if Figure 3F As shown, the gate structure may further include sidewalls 309 located on both sides of the gate electrode layer 308. The sidewalls 309 can increase the channel length of the device and reduce the short channel effect and the hot carrier effect caused by the short channel effect. The sidewalls 309 may be formed by various deposition methods commonly used in the art, such as chemical vapor deposition (CVD). Exemplarily, the sidewalls 309 may be a single-layer or multi-layer structure, such as a single-layer silicon dioxide structure, or a double-layer structure of a single-layer silicon dioxide and a single-layer silicon nitride, or a triple-layer structure of a double-layer silicon dioxide and a single-layer silicon nitride, and the present application does not limit this.

[0067] In one example, if Figures 3D to 3F As shown, after removing part of the mask layer 304 so that the remaining mask layer 304 is used as a gate dielectric layer 307, the method of the present application further includes: forming a source region 310 located in the body region 301 and a drain region 311 located in the drift region 302, the source region 310 extending from the surface of the body region 301 to the body region 301, and adjacent to the side of the gate structure close to the body region 301, the source region 310 and the drain region 311 are respectively located on both sides of the gate structure, the source region 310 and the drain region 311 have a first conductivity type, and the source region 310 and the drain region 311 can both be heavily doped regions. Exemplarily, the source region 310 and the drain region 311 can be formed by an ion implantation process, and then a rapid temperature rise annealing process is performed, using a high temperature of 900 degrees Celsius to 1050 degrees Celsius to activate the dopants in the source region 310 and the drain region 311, and at the same time repairing the lattice structure of the semiconductor substrate surface damaged in each ion implantation process. For example, the present application does not specifically limit the order of forming the gate electrode layer 308, the source region 310, and the drain region 311. For example, Figures 3D to 3FAs shown, after removing part of the mask layer 304 so that the remaining mask layer 304 is used as a gate dielectric layer 307, the present application also includes the step of forming a body contact region 312 in the body region 301, the body contact region 312 has a second conductivity type, the doping concentration of the body contact region 312 is higher than the doping concentration of the body region 301, and the body contact region 312 can be used as a lead-out region of the body region 301. Exemplarily, a self-aligned silicide layer can also be formed on the gate electrode layer 308, the source region 310, and the drain region 311. Exemplarily, a shallow trench isolation (STI) structure can also be formed in the body region 301 and the drift region 302.

[0068] In one example, the gate structure and the field oxide layer 306 form a gate field plate structure, and the gate field plate structure can weaken the surface electric field of the drift region 302, which is beneficial to improving the breakdown voltage of the device.

[0069] In an example, taking the case where the first conductivity type is N-type and the second conductivity type is P-type, by applying voltage to the gate structure, free electrons in the body region 301 can be attracted to approach the gate structure, and holes in the body region 301 can be repelled, thereby forming an N channel in the body region 301. At this time, free electrons can move from the source region 310 to the drain region 311 through the N channel.

[0070] In one example, the method of the present application further includes: forming a first conductive contact hole and a second conductive contact hole for respectively leading out the source region 310 and the drain region 311, wherein the first conductive contact hole is also electrically connected to the first metal layer as the source, and the second conductive contact hole is also electrically connected to the second metal layer as the drain. Optionally, a conductive contact hole electrically connected to the body contact region 312 may also be formed, and the conductive contact hole may also be electrically connected to the source. In some embodiments, the gate structure may be connected to the source.

[0071] In an example, the length direction of the body region 301 is the direction from the source region 310 to the drift region 302 , and the width direction of the body region 301 is the direction perpendicular to the length direction of the body region 301 .

[0072] In one example, along the width direction of the body region 301, the gate structure, the source region 310, the body region 301 and the drift region 302 all extend continuously, wherein the first conductive contact hole may include more than one and is selectively partially set in the source region 310, and the second conductive contact hole includes more than one and is selectively partially set in the drift region 302, for example, set in the drain region 311 in the drift region 302.

[0073] So far, the description of the key steps of the method for manufacturing the semiconductor device of the present invention has been completed. The preparation of a complete semiconductor device may also include other steps, which will not be described one by one here. It is worth mentioning that the order of the above steps can be adjusted without conflict.

[0074] In summary, the manufacturing method of the semiconductor device of the embodiment of the present invention forms a mask layer, and then forms a field oxide layer in the groove using the mask layer as a mask, which can effectively suppress the bird's beak effect, reduce the width of the bird's beak region of the field oxide layer, and make the current path shorter, thereby reducing the on-resistance of the device. At the same time, a thicker field oxide layer can be formed, thereby increasing the breakdown voltage of the device, and the process stability and feasibility are strong, thereby improving the device performance.

[0075] Embodiment 2

[0076] The present invention further provides a semiconductor device, which is prepared by the method in the above-mentioned embodiment 1. Since the device of the present application is prepared by the above-mentioned method, it has the same advantages as the above-mentioned method.

[0077] In one example, if Figure 3F As shown, the semiconductor device includes a substrate 300, in which a body region 301 and a drift region 302 are formed, the drift region 302 has a first conductivity type, and the body region 301 has a second conductivity type, wherein the first conductivity type is an N-type conductivity type and the second conductivity type is a P-type conductivity type, or the first conductivity type is a P-type conductivity type and the second conductivity type is an N-type conductivity type.

[0078] In one example, the substrate 300 is a bulk silicon substrate, which may include at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III / V compound semiconductors, or the substrate 300 may also include silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) or germanium on insulator (GeOI), etc. Although several examples of materials that can form the substrate 300 are described herein, any material that can be used as the substrate 300 falls within the spirit and scope of the present invention.

[0079] In one example, if Figure 3F As shown, a well region 303 is formed in the substrate 300 , the body region 301 and the drift region 302 are located in the well region 303 , and the well region 303 has a first conductivity type. Exemplarily, an ion implantation process may be performed on the substrate 300 to form the body region 301 , the drift region 302 and the well region 303 .

[0080] In one example, a field oxide layer 306 is further included. The field oxide layer 306 fills the trench 305 and a top surface of the field oxide layer 306 is higher than a surface of the substrate 300 .

[0081] In one example, if Figure 3F As shown, the field oxide layer 306 includes a field oxide region and a bird's beak region (i.e., a "bird's beak" structure) located on both sides of the field oxide region, wherein the field oxide region is a region of the field oxide layer 306 located in a predefined field oxide region, and the bird's beak region is a region of the field oxide layer 306 extending into the active region due to the bird's beak effect. In this embodiment, the thickness range of the field oxide region is 0.5µm-0.8µm, and in other embodiments, the thickness range of the field oxide region can also be other suitable ranges; it is worth noting that since the bird's beak effect is suppressed, the bird's beak region is narrower, so that a thicker field oxide region can be formed, thereby increasing the breakdown voltage of the device. In this embodiment, the width range of the bird's beak region is 0.1µm-0.5µm, and in other embodiments, the width range of the bird's beak region can also be other suitable ranges; it is worth noting that since the bird's beak effect is suppressed, the bird's beak region is narrower, so that the current path is shorter, thereby reducing the on-resistance of the device. Exemplarily, the width of the bird's beak region mentioned herein refers to the width of the bird's beak region along a direction perpendicular to a contact surface between the bird's beak region and the field oxide region (ie, a lateral diffusion direction of the field oxide layer 306 ).

[0082] In one example, if Figure 3F As shown, it also includes a gate dielectric layer 307 and a gate electrode layer 308, and the gate dielectric layer 307 and the gate electrode layer 308 constitute a gate structure, wherein the gate dielectric layer 307 covers the surface of part of the body region 301 and part of the drift region 302, and a side wall of the gate dielectric layer 307 contacts the field oxide layer 306, and the gate dielectric layer 307 plays an isolation and protection role; the gate electrode layer 308 covers the top surface of the gate dielectric layer 307 and part of the field oxide layer 306. Exemplarily, the gate electrode layer 308 is composed of polysilicon material, and generally metal, metal nitride, metal silicide or similar compounds can also be used as the material of the gate layer. Exemplarily, the number of layers of the gate electrode layer 308 can be at least one layer, and the gate electrode layer 308 can be used as a field plate. Exemplarily, the top surface of the field oxide layer 306 is higher than the top surface of the gate dielectric layer 307.

[0083] In one example, if Figure 3FAs shown, it also includes a source region 310 located in the body region 301 and a drain region 311 located in the drift region 302. The source region 310 extends from the surface of the body region 301 to the body region 301 and is adjacent to the side of the gate structure close to the body region 301. The source region 310 and the drain region 311 are respectively located on both sides of the gate structure. The source region 310 and the drain region 311 have a first conductivity type, and the source region 310 and the drain region 311 can both be heavily doped regions. Exemplarily, it also includes a body contact region 312 located in the body region 301, the body contact region 312 has a second conductivity type, the doping concentration of the body contact region 312 is higher than the doping concentration of the body region 301, and the body contact region 312 can be used as a lead-out region of the body region 301. Exemplarily, a self-aligned silicide layer can also be formed on the gate electrode layer 308, the source region 310 and the drain region 311. Exemplarily, an STI structure can also be formed in the body region 301 and the drift region 302.

[0084] In one example, the gate structure and the field oxide layer 306 form a gate field plate structure, and the gate field plate structure can weaken the surface electric field of the drift region 302, which is beneficial to improving the breakdown voltage of the device.

[0085] In an example, taking the case where the first conductivity type is N-type and the second conductivity type is P-type, by applying voltage to the gate structure, free electrons in the body region 301 can be attracted to approach the gate structure, and holes in the body region 301 can be repelled, thereby forming an N channel in the body region 301. At this time, free electrons can move from the source region 310 to the drain region 311 through the N channel.

[0086] In one example, it also includes: a first conductive contact hole and a second conductive contact hole for respectively leading out the source region and the drain region, wherein the first conductive contact hole is also electrically connected to the first metal layer as the source, and the second conductive contact hole is also electrically connected to the second metal layer as the drain. Optionally, it may also include a conductive contact hole electrically connected to the body contact region 312, and the conductive contact hole may also be electrically connected to the source.

[0087] The structure of the semiconductor device of the present invention has been introduced so far. The complete device may also include other component structures, which will not be described in detail here.

[0088] The semiconductor device of the embodiment of the present invention is manufactured by the above method to form a mask layer, and then a field oxide layer is formed in the groove using the mask layer as a mask. The bird's beak effect can be effectively suppressed, and the width of the bird's beak region of the field oxide layer is reduced, so that the current path is shorter, thereby reducing the on-resistance of the device. At the same time, a thicker field oxide layer can be formed, thereby increasing the breakdown voltage of the device. The process stability and feasibility are strong, thereby improving the device performance.

[0089] Embodiment 3

[0090] Another embodiment of the present invention provides an electronic device including the aforementioned semiconductor device.

[0091] The electronic device of this embodiment can be any electronic product or device such as a mobile phone, a tablet computer, a laptop computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a camera, a video camera, a voice recorder, an MP3, an MP4, a PSP, etc., or any intermediate product including the semiconductor device. The electronic device of the embodiment of the present invention has better performance due to the use of the semiconductor device.

[0092] Although multiple embodiments are described herein, it should be understood that a variety of other modifications and embodiments may be conceived by those skilled in the art, all of which will fall within the spirit and scope of the concepts disclosed in the present invention. More particularly, various modifications and changes may be made to the arrangements and / or components of the combined arrangements of the subject matter within the scope of the present disclosure, the drawings, and the appended claims. In addition to modifications and changes to the components and / or arrangements, the use of alternatives is also an obvious option for those skilled in the art.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The method comprises: Providing a substrate, wherein a body region and a drift region extending from a surface of the substrate into the substrate are formed in the substrate, the drift region has a first conductivity type, and the body region has a second conductivity type; forming a mask layer on the surface of the substrate; patterning the mask layer to expose a portion of the drift region, and etching the substrate to form a trench in the drift region; forming a field oxide layer, wherein the field oxide layer fills the trench, wherein a top surface of the field oxide layer is higher than a surface of the substrate; Removing part of the mask layer so that the remaining mask layer is used as a gate dielectric layer, the gate dielectric layer covers a part of the surface of the body region and a part of the drift region, and a side wall of the gate dielectric layer contacts the field oxide layer; A gate electrode layer is formed, wherein the gate electrode layer covers the top surface of the gate dielectric layer and a portion of the field oxide layer, wherein the gate dielectric layer and the gate electrode layer constitute a gate structure.

2. The manufacturing method according to claim 1, characterized in that: The material of the mask layer includes silicon oxynitride, and the mask layer is formed on the surface of the substrate, including: The mask layer is formed on the surface of the substrate by a thermal oxidation process in a nitrogen-containing atmosphere.

3. The manufacturing method according to claim 2, characterized in that: The nitrogen-containing atmosphere gas includes at least one of ammonia, nitric oxide and nitrous oxide.

4. The manufacturing method according to claim 1, characterized in that: Forming the gate dielectric layer includes: Thinning the mask layer to a predetermined thickness; A portion of the mask layer is removed by etching to expose a portion of the surface of the substrate to form the gate dielectric layer.

5. The manufacturing method according to claim 1, characterized in that: After removing part of the mask layer so that the remaining mask layer is used as the gate dielectric layer, the method further includes: A source region located in the body region and a drain region located in the drift region are formed, wherein the source region and the drain region are respectively located at two sides of the gate structure, and the source region and the drain region have a first conductivity type.

6. The manufacturing method according to claim 1, characterized in that: A well region is also formed in the substrate, the body region and the drift region are located in the well region, and the well region has a first conductivity type.

7. The manufacturing method according to claim 1, characterized in that: The field oxide layer includes a field oxide region and a bird's beak region located on both sides of the field oxide region, and the thickness of the field oxide region ranges from 0.5µm to 0.8µm.

8. The manufacturing method according to claim 1, characterized in that: The field oxide layer includes a field oxide region and a bird's beak region located on both sides of the field oxide region, and the width of the bird's beak region ranges from 0.1µm to 0.5µm.

9. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method according to any one of claims 1 to 8.

10. An electronic device, characterized in that: The electronic device includes the semiconductor device according to claim 9.

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