A programmable CTT structure and threshold voltage fast stabilization method
By trapping and attracting electrons in a programmable CTT structure, the stability problem of the PCTT threshold voltage is solved, achieving rapid stabilization of the threshold voltage and improving the circuit's response speed and accuracy.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NANJING UNIV
- Filing Date
- 2024-09-30
- Publication Date
- 2026-07-21
AI Technical Summary
Existing programmable charge transfer transistors (PCTTs) suffer from threshold voltage stability issues after programming, resulting in a long time required for the threshold voltage to stabilize, which affects the realization of circuit functions and efficiency.
A programmable CTT structure and a method for rapid threshold voltage stabilization are adopted. By capturing electrons from the package substrate to a high dielectric constant insulating layer during programming and attracting some electrons back to the package substrate by a light erase operation when programming is completed, the threshold voltage decay time is shortened.
It achieves rapid stabilization of programmable CTT threshold voltage, improves the immediacy and accuracy of circuit functions, reduces waiting time, and enhances the response speed and reliability of the circuit.
Smart Images
Figure CN119317163B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit design technology, and in particular to a programmable CTT structure and a method for rapid stabilization of threshold voltage. Background Technology
[0002] In the field of modern microelectronics, programmable charge transfer transistors (PCTTs), as an innovative semiconductor device, are gradually demonstrating their enormous potential in cutting-edge areas such as dynamic circuit configuration, low-power electronic system design, and neuromorphic computing. The core advantage of PCTTs lies in their unique charge transfer mechanism, which allows for dynamic adjustment of their internal charge distribution through external programming signals, thereby altering the device's conductivity characteristics, particularly its threshold voltage (Vth). This provides unprecedented possibilities for circuit flexibility and versatility.
[0003] However, a key technical challenge facing PCTT in practical applications is the stability of its threshold voltage. Specifically, after a PCTT undergoes programming, its threshold voltage increases significantly. This phenomenon is mainly attributed to the effective injection and trapping of charge during programming, which alters the potential distribution in the device's channel region. This change is crucial for achieving specific circuit functions, but it also introduces a complex dynamic process: the threshold voltage does not stabilize immediately in the initial stage after programming but undergoes a period of decay.
[0004] The causes of this degradation phenomenon are multifaceted and complex, including but not limited to: the gradual release of trapped charges generated during the programming process over time, leading to a redistribution of the potential in the channel region; changes in interface states, namely the conversion of charge states at the interface between the semiconductor and the insulating layer, the instability of these interface states also affects the threshold voltage; and the release process of internal stress in the device. Under the combined effect of these factors, the threshold voltage of PCTT needs a relatively long time to gradually stabilize after programming. Summary of the Invention
[0005] This application provides a programmable CTT structure and a method for rapid threshold voltage stabilization to solve the problem that existing CTT threshold voltage stabilization schemes require a long time.
[0006] In a first aspect, this application provides a programmable CTT structure, the structure comprising: Packaging substrate; The drain and source are respectively built into the two ends of the same side of the packaging substrate; A substrate, the substrate being disposed on the side of the packaging substrate away from the drain electrode; A high dielectric constant insulating layer is disposed on the side of the packaging substrate away from the substrate, and the high dielectric constant insulating layer is connected to the packaging substrate at a location between the drain and the source. A gate is disposed on the side of the high dielectric constant insulating layer away from the package substrate.
[0007] Preferably, the high dielectric constant insulating layer comprises: A shallow well region, which is connected to the packaging substrate; A deep well region is located on the side of the shallow well region away from the packaging substrate.
[0008] Preferably, the drain is connected to an external power supply.
[0009] Secondly, this application also provides a method for rapid stabilization of threshold voltage based on a programmable CTT structure, the method comprising: During CTT programming, electrons are trapped from the package substrate into a high-dielectric-constant insulating layer; When CTT completes programming, some electrons are attracted from the high dielectric constant insulating layer to the packaging substrate.
[0010] Preferably, the method further includes: During CTT programming, electrons are trapped from the package substrate into shallow and deep well regions; When CTT completes programming, electrons are attracted from the shallow well region into the package substrate.
[0011] Preferably, the method further includes: When CTT is programmed, an electron flow is formed between the source and the drain. The gate attracts electrons from the package substrate to the shallow well region and the deep well region. When CTT is programmed, electrons form a reverse electron flow between the high dielectric constant insulating layer and the package substrate, and the electrons in the shallow well region are attracted into the package substrate by a light erase operation.
[0012] Preferably, the source and substrate are grounded during CTT programming; The drain is connected to an external power supply, and a first positive pulse voltage is applied to the gate; the voltage of the external power supply is 0.9V.
[0013] Preferably, the method further includes: When CTT is completed, the source and gate are grounded; The drain is connected to the external power supply, and a second positive pulse voltage is applied to the substrate.
[0014] Preferably, the voltage magnitude of the second positive pulse voltage is smaller than the voltage magnitude of the first positive pulse voltage.
[0015] Preferably, the light erasure operation includes using the second positive pulse voltage to attract the reverse electron flow at the substrate, thereby attracting electrons in the shallow trap region into the package substrate.
[0016] As described above, this application provides a programmable threshold voltage stabilization (CTT) structure and a method for rapid threshold voltage stabilization. The programmable CTT structure includes a package substrate; a drain and a source, each located at opposite ends of the same side of the package substrate; a substrate disposed on the side of the package substrate away from the drain; a high-dielectric-constant insulating layer disposed on the side of the package substrate away from the substrate, with the connection point between the high-dielectric-constant insulating layer and the package substrate located between the drain and the source; and a gate disposed on the side of the high-dielectric-constant insulating layer away from the package substrate. This application solves the problem of the long threshold voltage stabilization time required by existing CTT schemes through the above structure and method. Attached Figure Description
[0017] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a schematic diagram of a programmable CTT structure during programming according to this application; Figure 2 This is a schematic diagram of a programmable CTT structure in this application during programming. Figure 3 This is a schematic diagram of a programmable CTT structure of this application during conventional threshold voltage stabilization; Figure 4 This is a schematic diagram of a programmable CTT structure of this application during rapid threshold voltage stabilization; Figure 5 This is a flowchart of a method for rapidly stabilizing threshold voltage based on a programmable CTT structure, as described in this application. Detailed Implementation
[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0020] It should be noted that the brief descriptions of terms in this application are only for the convenience of understanding the embodiments described below, and are not intended to limit the embodiments of this application. Unless otherwise stated, these terms should be understood in their ordinary and common meaning.
[0021] The terms "first," "second," "third," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar or related objects or entities, and do not necessarily imply a specific order or sequence, unless otherwise specified. It should be understood that such terms are interchangeable where appropriate.
[0022] Figure 1 This is a schematic diagram of a programmable CTT structure during programming according to this application.
[0023] See Figure 1 As can be seen, this embodiment provides a programmable CTT structure, the structure including: The packaging substrate 100, specifically in this embodiment, is an important component of semiconductor packaging technology. It serves to support the chip and provides functions such as electrical connection, protection, support, and heat dissipation. The packaging substrate 100 typically belongs to a branch of PCB (Printed Circuit Board) technology, but has higher precision, density, and performance requirements. It provides electrical connection and physical support between the chip and the PCB motherboard, and is a crucial component material of the semiconductor package.
[0024] The packaging substrate 100 needs to meet the following conditions: Since programmable CTTs may contain a large number of programmable components and complex circuit connections, their packaging substrate 100 needs to have high density and high precision to support a large number of electrical connections and signal transmissions.
[0025] The programmable CTT may generate high heat during operation, so the packaging substrate 100 needs to have good heat dissipation performance to ensure stable operation of the chip and extend its service life.
[0026] The packaging substrate 100 needs to be able to withstand various environmental conditions and stress changes to ensure the reliability and stability of the programmable CTT in various application scenarios.
[0027] The package substrate 100 needs to be matched with the electrical characteristics and physical dimensions of the programmable CTT to ensure that they can be properly connected and work together.
[0028] The structure also includes: The transistor comprises a drain 200 and a source 300, which are respectively embedded at both ends of the same side of the packaging substrate 100. Specifically, the source 300 is the electrode that provides charge carriers (electrons or holes), and the drain 200 is the electrode that collects charge carriers in the transistor. When the transistor is operating, charge carriers flow from the source 300 to the drain 200, forming a current.
[0029] In a CTT, although its unique feature lies in the charge trapping capability of the gate dielectric, the basic functions of the drain 200 and source 300 are similar to those in other transistors. When a CTT is used as a switch or amplifier, the source 300 provides charge carriers, and the drain 200 collects charge carriers, forming a current path.
[0030] The structure also includes: The substrate 400 is disposed on the side of the packaging substrate 100 away from the drain 200. Specifically, in this embodiment, the substrate 400 provides stable support for the other layers of the transistor, ensuring the structural integrity and stability of the entire transistor.
[0031] In a charge-trapping transistor, the substrate 400 serves as one of the charge transport channels. When a voltage is applied to the control gate, electrons are injected into the charge-trapping layer through the substrate 400. The interface quality between the substrate 400 and the tunneling layer has a significant impact on charge transport and trapping efficiency. A high-quality interface can reduce charge scattering and leakage, thereby improving transistor performance.
[0032] The structure also includes: A high dielectric constant insulating layer 500 is disposed on the side of the packaging substrate 100 away from the substrate 400. The high dielectric constant insulating layer 500 is connected to the packaging substrate 100 at a location between the drain 200 and the source 300. Specifically, in this embodiment, the high dielectric constant insulating layer 500 refers to an insulating material layer with a relatively high dielectric constant (εr). These materials include hafnium dioxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), and silicate compounds.
[0033] Among these advantages, high-dielectric-constant materials can provide higher capacitance values at the same physical thickness, thus helping to reduce transistor size and increase integration density. Since a thicker insulating layer can be used to achieve the same capacitance value, gate leakage current is significantly reduced, improving device efficiency and stability. The high-dielectric-constant insulating layer 500 helps solve technical challenges associated with traditional silicon dioxide gate materials, such as unstable threshold voltage (Vt), decreased carrier channel mobility, and degraded device reliability.
[0034] The structure also includes: A gate 600 is disposed on the side of the high-dielectric-constant insulating layer 500 away from the packaging substrate 100. Specifically, in this embodiment, the gate 600 is an electrode in the transistor. In this embodiment, the gate 600 is located above the packaging substrate 100 and is isolated from the packaging substrate 100 by an insulating layer (such as silicon dioxide). The main function of the gate 600 is to form an electric field on the surface of the packaging substrate 100 by applying a voltage, thereby controlling the flow of charge carriers (such as electrons and holes) in the packaging substrate 100. In a charge-trapping transistor, the gate 600 is also responsible for trapping charges in the high-dielectric-constant insulating layer 500 to achieve information storage.
[0035] The high dielectric constant insulating layer 500 includes: Shallow well region 510, which is connected to the packaging substrate 100; A deep well region 520 is disposed on the side of the shallow well region 510 away from the packaging substrate 100.
[0036] Specifically, in this embodiment, the gate 600 is used to trap charge in the shallow well region 510 and the deep well region 520.
[0037] The drain 200 is connected to an external power supply 700.
[0038] For example, the programmable CTT has the following applicability and advantages: The core of the programmable CTT lies in its powerful configuration capabilities. Users or developers can easily adjust the layout, size, shape, color, and response logic of the touch area through a graphical interface or programming interface (API). This flexibility allows the interface design to closely align with product characteristics and user needs, achieving true personalization.
[0039] To simplify the development process and improve efficiency, the programmable CTT adopts a modular design approach. The system includes various predefined functional modules, such as sliders, knobs, switches, and gesture recognition. These modules can be dragged and dropped onto the interface like building blocks, and their attributes and behaviors can be quickly configured. This design not only reduces development complexity but also accelerates time-to-market.
[0040] The programmable CTT integrates advanced touch recognition algorithms, enabling accurate identification of user touch operations, including single-point touch, multi-point touch, pressure sensing, and complex gesture recognition. Simultaneously, the system provides rich feedback mechanisms, such as tactile vibration, sound cues, and visual animations, to enhance the user experience and immersion.
[0041] To further enhance the user experience, the programmable CTT supports automatically adjusting the interface layout and interaction methods based on the application's current state or changes in the external environment. For example, in night mode, the system automatically reduces interface brightness and adjusts the color scheme to reduce eye strain; when a change in user identity is detected, the interface will also adjust accordingly to display personalized content and services.
[0042] The programmable CTT also boasts powerful remote update and maintenance capabilities. Through cloud services, manufacturers can easily push new interface configurations or feature upgrades to users without requiring any physical intervention. This capability not only reduces maintenance costs but also accelerates product iteration, enabling electronic products to remain competitive.
[0043] Figure 5 This is a flowchart of a method for rapidly stabilizing threshold voltage based on a programmable CTT structure, as described in this application.
[0044] See Figure 5 Furthermore, this embodiment also provides a method for rapid stabilization of threshold voltage based on a programmable CTT structure, the method comprising: S1, When CTT is programmed, electrons are captured from the package substrate and transferred to the high dielectric constant insulating layer. Specifically, in this embodiment, when CTT is programmed, electrons need to be captured from the package substrate and transferred to the high dielectric constant insulating layer.
[0045] During CTT programming, an electron flow is formed between the source and drain. Electrons in this flow are attracted from the package substrate to the shallow and deep well regions via the gate. Therefore, electrons are attracted to both the shallow and deep well regions of the high-dielectric-constant insulating layer.
[0046] For example, a charge-trapping transistor (CTT) device is programmed. The specific steps are as follows: A positive pulse voltage (e.g., 2V peak, 1kHz frequency, 50% duty cycle, 800ms duration) is applied to the gate, the drain is connected to 0.9V, and the source and substrate are grounded. Under these conditions, some electrons in the electron flow from the source to the drain are attracted to the gate and trapped in the deep and shallow well regions of the high-dielectric-constant insulating layer, thereby increasing the threshold voltage of the CTT device (e.g., 50mV).
[0047] When the CTT is programmed, see the following for details about the various components in the programmable CTT: Figure 2 .
[0048] When CTT is programmed, the drain is connected to an external power supply, the substrate, source and gate need to be grounded respectively, and a first positive pulse voltage is applied to the gate; the voltage of the external power supply is 0.9V.
[0049] It should be noted that when the CTT is programmed, the charge in the high-dielectric-constant insulating layer detaches from the insulating layer and returns to the transistor channel, causing a decay in the threshold voltage, such as... Figure 2 As shown. This process will continue for a considerable period of time until electrons in the high-dielectric-constant insulating layer no longer detach from the insulating layer. At this point, the threshold voltage of the transistor is in a stable state.
[0050] To stabilize the threshold voltage during CTT programming, conventional techniques propose the following scheme, the details of which can be found in [link to specific scheme]. Figure 3 Specifically, it includes: By grounding the source and gate, while keeping the drain connected to an external power supply, and inputting a voltage at the substrate end that is a positive pulse voltage equal to the first positive pulse voltage, the CTT device can be erased.
[0051] For example, by applying a positive pulse voltage (e.g., 2V peak-to-peak, 1kHz frequency, 50% duty cycle square wave, 800ms duration) to the substrate, with the drain connected to VDD and the source and gate grounded, the charge previously trapped in the deep and shallow well regions of the insulating layer is attracted out because the substrate potential is higher than the gate potential, thereby reducing the threshold voltage of the CTT device.
[0052] However, while erasing CTT devices can reduce their threshold voltage, the process still takes a relatively long time.
[0053] Figure 4 This is a schematic diagram of a programmable CTT structure of this application during rapid threshold voltage stabilization.
[0054] See Figure 4 Furthermore, the method further includes: S2, during CTT programming, a portion of electrons are attracted from the high-dielectric-constant insulating layer to the packaging substrate. Specifically, in this embodiment, based on... Figure 2 As can be seen from the above description of CTT programming, since the threshold voltage decay time is relatively long when CTT programming is completed, this embodiment provides a method to shorten the threshold voltage decay time when CTT programming is completed.
[0055] In this embodiment, a scheme is employed to attract some electrons from the high dielectric constant insulating layer to the packaging substrate to shorten the decay time of the threshold voltage when CTT completes programming.
[0056] Step S2 can be understood as attracting electrons from the shallow well region to the package substrate when CTT is completed programming; specifically, when CTT is completed programming, electrons form a reverse electron flow between the high dielectric constant insulating layer and the package substrate, and the electrons in the shallow well region are attracted to the package substrate by a light erase operation.
[0057] The light erase operation involves applying a second positive pulse voltage to the substrate, and the magnitude of the second positive pulse voltage must be less than the magnitude of the first positive pulse voltage. The light erase operation includes using the second positive pulse voltage to attract the reverse electron flow at the substrate, drawing electrons from the shallow well region into the packaging substrate. This allows only electrons in the shallow well region to be attracted, without affecting electrons in the deep well region. Since the light erase operation proposed in this embodiment only attracts electrons in the shallow well region, it avoids attracting electrons in the deep well region, which is more difficult to attract, thus enabling the peak voltage of the CTT to stabilize quickly.
[0058] For example, to accelerate the process of charge in the shallow well region detaching from the insulating layer and returning to the transistor channel, we propose a light erase operation. This operation is similar to a normal erase, but the operating voltage is much lower than the conventional erase voltage. The lower operating voltage only affects the detachment of charge from the insulating layer in the shallow well region, without interfering with the charge in the deep well region. Therefore, the light erase operation can stabilize the threshold voltage of the CTT in a short time.
[0059] For example, the voltage of the second positive pulse voltage can be 0.9V.
[0060] This embodiment has the following advantages: By employing a gentle erase operation, the threshold voltage of a programmable CTT can rapidly stabilize after programming. This technique allows for quick calibration of circuits with offset voltages without requiring lengthy waiting times to determine calibration success. Furthermore, the rapid stabilization of the threshold voltage improves the accuracy of offset voltage calibration.
[0061] Similar parts between the embodiments provided in this application can be referred to mutually. The specific implementation methods provided above are only a few examples under the overall concept of this application and do not constitute a limitation on the scope of protection of this application. For those skilled in the art, any other implementation methods extended from the solution of this application without creative effort shall fall within the scope of protection of this application.
Claims
1. A programmable CTT structure, characterized in that, The CTT structure includes: Packaging substrate (100); Drain (200) and source (300), wherein the drain (200) and source (300) are respectively built into the two ends of the same side of the packaging substrate (100); A substrate (400) is disposed on the side of the packaging substrate (100) away from the drain (200); A high dielectric constant insulating layer (500) is disposed on the side of the packaging substrate (100) away from the substrate (400), and the high dielectric constant insulating layer (500) is connected to the packaging substrate (100) at a location between the drain (200) and the source (300). A gate (600) is disposed on the side of the high dielectric constant insulating layer (500) away from the package substrate (100).
2. The programmable CTT structure according to claim 1, characterized in that, The high dielectric constant insulating layer (500) comprises: A shallow well region (510) is connected to the packaging substrate (100); A deep well region (520) is disposed on the side of the shallow well region (510) away from the packaging substrate (100).
3. The programmable CTT structure according to claim 1, characterized in that, The drain (200) is connected to an external power supply (700).
4. A method for rapid stabilization of threshold voltage based on a programmable CTT structure, characterized in that, The method is based on the programmable CTT structure according to any one of claims 1 to 3, and the method includes: During CTT programming, electrons are trapped from the package substrate into a high-dielectric-constant insulating layer; When CTT completes programming, some electrons are attracted from the high dielectric constant insulating layer to the packaging substrate.
5. The method for rapid stabilization of threshold voltage based on a programmable CTT structure according to claim 4, characterized in that, The method further includes: During CTT programming, electrons are trapped from the package substrate into shallow and deep well regions; When CTT completes programming, electrons are attracted from the shallow well region into the package substrate.
6. The method for rapid stabilization of threshold voltage based on a programmable CTT structure according to claim 5, characterized in that, The method further includes: When CTT is programmed, an electron flow is formed between the source and the drain. The gate attracts electrons from the package substrate to the shallow well region and the deep well region. When CTT is programmed, electrons form a reverse electron flow between the high dielectric constant insulating layer and the package substrate, and the electrons in the shallow well region are attracted into the package substrate by a light erase operation.
7. The method for rapid stabilization of threshold voltage based on a programmable CTT structure according to claim 6, characterized in that, The method further includes: When programming CTT, the source and substrate are grounded; The drain is connected to an external power supply, and a first positive pulse voltage is applied to the gate; the voltage of the external power supply is 0.9V.
8. The method for rapid stabilization of threshold voltage based on a programmable CTT structure according to claim 7, characterized in that, The method further includes: When CTT completes programming, the source and gate are grounded; The drain is connected to the external power supply, and a second positive pulse voltage is applied to the substrate.
9. The method for rapid stabilization of threshold voltage based on a programmable CTT structure according to claim 8, characterized in that, The voltage magnitude of the second positive pulse voltage is less than the voltage magnitude of the first positive pulse voltage.
10. A method for rapid stabilization of threshold voltage based on a programmable CTT structure according to claim 9, characterized in that, The light erasure operation includes using the second positive pulse voltage to attract the reverse electron flow at the substrate, thereby attracting electrons in the shallow trap region into the package substrate.