Back-illuminated semiconductor structure bonding method and back-illuminated image sensor

Abstract

The present disclosure provides a back-illuminated semiconductor structure bonding method and a back-illuminated image sensor, the method comprising: providing a device wafer and a carrier wafer; the device wafer comprising a device layer and an epitaxial layer located between the device layer and a substrate; the device layer comprising a photodiode array; depositing a first dielectric layer on the top surface of the device layer, and after flattening the top surface of the first dielectric layer, obtaining a height difference between a middle area of ​​the top surface of the flattened first dielectric layer and a peripheral area surrounding the middle area; depositing a fourth dielectric layer of a first thickness on the top surface of a ground third dielectric layer; chemically mechanically grinding the fourth dielectric layer to remove a second thickness of the fourth dielectric layer, wherein the second thickness is less than the first thickness; bonding the top surface of the ground fourth dielectric layer to the front side of the carrier wafer, at least reducing the warping degree of the bonded wafer, reducing the number of bubbles at the bonding interface, and improving the device yield.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular to a back-illuminated semiconductor structure bonding method and a back-illuminated image sensor. Background Art

[0002] A complementary metal oxide semiconductor (CMOS) image sensor is a sensor that can convert the color and brightness of captured light into electronic signals and transmit the electronic signals to a processor. Based on the incident direction of light, CMOS image sensors can be divided into front-side illumination (FSI) complementary metal oxide semiconductor image sensors and back-side illumination (BSI) complementary metal oxide semiconductor image sensors.

[0003] In the manufacturing process of BSI CMOS, the device wafer with the photodiode needs to be flipped over and combined with the optical board carrier, which is the wafer bonding process. However, for some BSI CMOS products, the wafer warpage is high, which makes bonding difficult, and the bubbles existing at the bonding interface affect the device yield. Summary of the invention

[0004] Based on this, it is necessary to provide a back-illuminated semiconductor structure bonding method and a back-illuminated image sensor to address the problems in the above-mentioned background technology, which can at least reduce the warping degree of the bonded wafer, reduce the number of bubbles at the bonding interface, and improve the device yield.

[0005] In order to achieve the above-mentioned purpose and other purposes, the present disclosure provides a back-illuminated semiconductor structure bonding method, comprising: providing a device wafer and a carrier wafer; the device wafer comprises a device layer and an epitaxial layer located between the device layer and the substrate; the device layer comprises a photodiode array; depositing a first dielectric layer on the top surface of the device layer, flattening the top surface of the first dielectric layer, obtaining a height difference between a middle area of ​​the top surface of the flattened first dielectric layer and a peripheral area surrounding the middle area; depositing a second dielectric layer on the top surface of the flattened first dielectric layer, and forming a third dielectric layer of a preset thickness on the top surface of the second dielectric layer; wherein, under the same grinding conditions, the third dielectric layer The removal rate of the third dielectric layer is greater than the removal rate of the second dielectric layer; a chemical mechanical polishing process is performed on the top surface of the third dielectric layer, so that the top surface step difference of the third dielectric layer after polishing is less than the target value; the preset thickness is the sum of the height difference and the polishing removal amount of the third dielectric layer, and the polishing removal amount of the third dielectric layer is related to the top surface step difference; the top surface step difference is the height difference between the highest point and the lowest point of the top surface of the third dielectric layer after polishing; a fourth dielectric layer of a first thickness is deposited on the top surface of the polished third dielectric layer; the fourth dielectric layer is processed by chemical mechanical polishing to remove the fourth dielectric layer of a second thickness, and the second thickness is less than the first thickness; the top surface of the polished fourth dielectric layer is bonded to the front side of the carrier wafer.

[0006] The back-illuminated semiconductor structure bonding method in the above-mentioned embodiment first provides a device wafer and a carrier wafer; the device wafer includes a device layer and an epitaxial layer located between the device layer and the substrate; the device layer includes a photodiode array, and then a first dielectric layer is deposited on the top surface of the device layer, and after the top surface of the first dielectric layer is planarized, a height difference between a middle area of ​​the top surface of the planarized first dielectric layer and a peripheral area surrounding the middle area is obtained, and after a second dielectric layer is deposited on the top surface of the planarized first dielectric layer, a third dielectric layer of a preset thickness is formed on the top surface of the second dielectric layer; wherein, under the same polishing conditions, the removal rate of the third dielectric layer is greater than the removal rate of the second dielectric layer, so that the height difference between the middle area of ​​the top surface of the wafer and the peripheral area surrounding the middle area can be reduced, and then a chemical mechanical polishing process is performed on the top surface of the third dielectric layer. , so that the top surface step difference of the third dielectric layer after grinding is less than the target value; the preset thickness is the sum of the height difference and the grinding removal amount of the third dielectric layer, and the grinding removal amount of the third dielectric layer is related to the top surface step difference; the top surface step difference is the height difference between the highest point and the lowest point of the top surface of the third dielectric layer after grinding, which can reduce the number of bubbles on the bonding interface; after depositing a fourth dielectric layer of a first thickness on the top surface of the ground third dielectric layer, chemically mechanically polishing the fourth dielectric layer to remove the fourth dielectric layer of a second thickness, the second thickness is less than the first thickness, and further obtaining the top surface of the ground fourth dielectric layer whose top surface flatness reaches the target value, and finally bonding the top surface of the ground fourth dielectric layer to the front side of the carrier wafer to avoid the problem of failure to bond due to high edge warping during wafer bonding, reduce the number of bubbles on the bonding interface, and improve the process efficiency. At present, the related back-illuminated semiconductor structure bonding method flips the device wafer with the photodiode, directly bonds it with the optical board carrier wafer at room temperature, and then performs annealing to improve the bonding strength, and then combines the two wafers into a whole. However, for some special BSI products, the wafer warpage is large, which makes it impossible to bond, or there are bubbles at the wafer bonding interface, which affects the device yield. The back-illuminated semiconductor structure bonding method in the disclosed embodiment deposits the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer in sequence, and performs chemical mechanical polishing on the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer, respectively, and controls the polishing removal rate, which can at least avoid the problem of wafer bonding failure due to high edge warpage during wafer bonding, reduce the number of bubbles at the bonding interface, and improve the efficiency during the process.

[0007] In one embodiment, the logarithmic value lg(q) of the top surface step difference q is negatively correlated with the polishing removal amount of the third dielectric layer.

[0008] In one of the embodiments, before forming a third dielectric layer of a preset thickness, a data fitting algorithm is used to obtain a functional relationship between the logarithmic value lg(q) of the top surface step difference q of the third dielectric layer and the grinding removal amount of the third dielectric layer; and the minimum value of the preset thickness is determined based on the functional relationship and the target value.

[0009] In one embodiment, a data fitting algorithm is used to obtain the logarithmic value lg(q) of the step difference q of the top surface of the third dielectric layer, and the functional relationship between the grinding removal amount x of the third dielectric layer is:

[0010] lg(q)=kx+b;

[0011] In the above formula, k and b are both constants, and k<0.

[0012] In one embodiment, a chemical mechanical polishing process is performed on the top surface of the third dielectric layer, including: after using a first polishing pad to perform a first chemical mechanical polishing process on the top surface of the third dielectric layer, using a second polishing pad to continue to perform a second chemical mechanical polishing process on the top surface of the third dielectric layer; the compression coefficient of the first polishing pad is different from the compression coefficient of the second polishing pad and both are greater than a preset compression coefficient threshold.

[0013] In one embodiment, after bonding the top surface of the ground fourth dielectric layer to the front surface of the carrier wafer, the method further includes: annealing the bonded back-illuminated semiconductor structure.

[0014] In one embodiment, the target value is 0-10 nm.

[0015] In one embodiment, a high-density plasma chemical vapor deposition process is used to deposit a second dielectric layer on the top surface of the planarized first dielectric layer, and the second dielectric layer is used to provide compressive stress to the device wafer to reduce the warpage of the device wafer.

[0016] Another aspect of the present disclosure provides a back-illuminated image sensor, which is manufactured using the back-illuminated semiconductor structure bonding method in any one of the embodiments of the present disclosure.

[0017] The back-illuminated semiconductor structure bonding method and back-illuminated image sensor disclosed in the present invention have the following unexpected beneficial effects:

[0018] In the back-illuminated semiconductor structure bonding method and the back-illuminated image sensor disclosed in the present invention, a device wafer and a carrier wafer are first provided; the device wafer includes a device layer and an epitaxial layer located between the device layer and the substrate; the device layer includes a photodiode array, and then a first dielectric layer is deposited on the top surface of the device layer, and after the top surface of the first dielectric layer is flattened, a height difference between a middle area of ​​the top surface of the flattened first dielectric layer and a peripheral area surrounding the middle area is obtained, and after a second dielectric layer is deposited on the top surface of the flattened first dielectric layer, a third dielectric layer of a preset thickness is formed on the top surface of the second dielectric layer; wherein, under the same grinding conditions, the removal rate of the third dielectric layer is greater than the removal rate of the second dielectric layer. The rate can avoid the occurrence of grinding gaps and reduce the edge height difference. Then, a chemical mechanical grinding process is performed on the top surface of the third dielectric layer, so that the top surface step difference of the third dielectric layer after grinding is less than the target value; the preset thickness is the sum of the height difference and the grinding removal amount of the third dielectric layer, and the grinding removal amount of the third dielectric layer is related to the top surface step difference; the top surface step difference is the height difference between the highest point and the lowest point of the top surface of the third dielectric layer after grinding, which avoids the problem of high wafer warpage caused by wafer stress, reduces the height difference of the wafer edge, and avoids wafer edge collapse. Finally, the top surface of the fourth dielectric layer after grinding is bonded to the front side of the carrier wafer, which can reduce the number of bubbles at the bonding interface and improve the device yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 is a schematic flow chart of a back-illuminated semiconductor structure bonding method provided in one embodiment;

[0021] Figure 2 A schematic diagram of the corresponding relationship between the top surface step difference logarithm lg (q) and the grinding removal amount provided in an embodiment;

[0022] Figure 3 A schematic diagram of the corresponding relationship between the compression coefficient of the polishing pad and the number of bubbles after annealing provided in an embodiment;

[0023] Figure 4 A schematic flow chart of a back-illuminated semiconductor structure bonding method provided in another embodiment;

[0024] Figure 5 A schematic diagram of the cross-sectional structure of a device wafer in a back-illuminated semiconductor structure bonding method provided in an embodiment;

[0025] Figure 6 is a schematic cross-sectional structural diagram of step S120 in a back-illuminated semiconductor structure bonding method provided in an embodiment;

[0026] Figure 7 is a cross-sectional schematic diagram of step S130 in a back-illuminated semiconductor structure bonding method provided in an embodiment;

[0027] Figure 8 FIG. 1 is a schematic cross-sectional view of step S150 in a back-illuminated semiconductor structure bonding method provided in an embodiment.

[0028] Description of reference numerals:

[0029] 100, back-illuminated semiconductor structure; 110, device wafer; 111, device layer; 112, substrate; 113, epitaxial layer; 114, first dielectric layer; 115, second dielectric layer; 116, third dielectric layer; 117, fourth dielectric layer; 120, carrier wafer. DETAILED DESCRIPTION

[0030] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0032] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0033] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0034] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0035] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic representations of ideal embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the present disclosure should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present disclosure.

[0036] CMOS image sensors are divided into front-illuminated image sensors and back-illuminated image sensors according to their structures. In a back-illuminated CMOS image sensor, light is incident from the back of the sensor and is directed to the photodiode in the pixel unit without passing through the interlayer dielectric layer and the interconnection layer. This allows the light to enter the photodiode more directly, reducing light loss. In the same unit time, a single pixel unit can obtain more light energy, which significantly improves the image quality. One of the process steps of the back-illuminated image sensor is to flip the device wafer with the photodiode and then bond it to the optical board carrier to ensure the mechanical strength of the device wafer in the subsequent thinning process. This process is a technology that directly bonds two wafers at room temperature, then anneals them to increase the bonding strength, and then combines the two wafers into a whole. However, for some BSI CMOS products, the high wafer warpage makes bonding difficult, and the bubbles at the bonding interface affect the device yield.

[0037] Please refer to Figure 1 In some embodiments, the present disclosure provides a back-illuminated semiconductor structure bonding method, comprising the following steps:

[0038] Step S110: providing a device wafer and a carrier wafer; the device wafer includes a device layer and an epitaxial layer located between the device layer and the substrate; the device layer includes a photodiode array;

[0039] Step S120: depositing a first dielectric layer on the top surface of the device layer, planarizing the top surface of the first dielectric layer, and obtaining a height difference between a middle region of the top surface of the planarized first dielectric layer and a peripheral region surrounding the middle region;

[0040] Step S130: after depositing a second dielectric layer on the top surface of the planarized first dielectric layer, a third dielectric layer of a preset thickness is formed on the top surface of the second dielectric layer; wherein, under the same polishing conditions, a removal rate of the third dielectric layer is greater than a removal rate of the second dielectric layer;

[0041] Step S140: performing a chemical mechanical polishing process on the top surface of the third dielectric layer, so that the top surface step difference of the third dielectric layer after polishing is less than a target value; the preset thickness is the sum of the height difference and the polishing removal amount of the third dielectric layer, and the polishing removal amount of the third dielectric layer is related to the top surface step difference; the top surface step difference is the height difference between the highest point and the lowest point of the top surface of the third dielectric layer after polishing;

[0042] Step S150: depositing a fourth dielectric layer of a first thickness on the top surface of the ground third dielectric layer; chemically mechanically grinding the fourth dielectric layer to remove a second thickness of the fourth dielectric layer, wherein the second thickness is less than the first thickness;

[0043] Step S160: bonding the top surface of the ground fourth dielectric layer to the front surface of the carrier wafer.

[0044] As an example, please refer to Figure 1, a back-illuminated semiconductor structure bonding method first provides a device wafer and a carrier wafer; the device wafer includes a device layer and an epitaxial layer located between the device layer and the substrate; the device layer includes a photodiode array, and then a first dielectric layer is deposited on the top surface of the device layer, and after the top surface of the first dielectric layer is planarized, a height difference between a middle area of ​​the top surface of the planarized first dielectric layer and a peripheral area surrounding the middle area is obtained, and after a second dielectric layer is deposited on the top surface of the planarized first dielectric layer, a third dielectric layer of a preset thickness is formed on the top surface of the second dielectric layer; wherein, under the same polishing conditions, the removal rate of the third dielectric layer is greater than the removal rate of the second dielectric layer, and the height difference between the middle area of ​​the top surface of the wafer and the peripheral area surrounding the middle area can be reduced, and then a chemical mechanical polishing process is performed on the top surface of the third dielectric layer, so that The step difference of the top surface of the third dielectric layer after grinding is less than the target value; the preset thickness is the sum of the height difference and the grinding removal amount of the third dielectric layer, and the grinding removal amount of the third dielectric layer is related to the step difference of the top surface; the step difference of the top surface is the height difference between the highest point and the lowest point of the top surface of the third dielectric layer after grinding, which can reduce the number of bubbles at the bonding interface; after depositing a fourth dielectric layer of a first thickness on the top surface of the ground third dielectric layer, the fourth dielectric layer is subjected to chemical mechanical grinding to remove the fourth dielectric layer of a second thickness, the second thickness is less than the first thickness, and the top surface of the ground fourth dielectric layer whose top surface flatness reaches the target value is further obtained, and finally the top surface of the ground fourth dielectric layer is bonded to the front side of the carrier wafer to avoid the problem of failure to bond due to high edge warping during wafer bonding, reduce the number of bubbles at the bonding interface, and improve the process efficiency. At present, the related back-illuminated semiconductor structure bonding method flips the device wafer with the photodiode, directly bonds it with the optical board carrier wafer at room temperature, and then performs annealing to improve the bonding strength, and then combines the two wafers into a whole. However, for some special BSI products, the wafer warpage is large, which makes it impossible to bond, or there are bubbles at the wafer bonding interface, which affects the device yield. The back-illuminated semiconductor structure bonding method in the disclosed embodiment deposits the first dielectric layer, the second dielectric layer and the third dielectric layer in sequence, and performs chemical mechanical polishing on the first dielectric layer, the second dielectric layer and the third dielectric layer respectively, and controls the polishing removal rate, which can at least avoid the problem of wafer bonding failure due to high edge warpage during wafer bonding, reduce the number of bubbles at the bonding interface, and improve the efficiency during the process.

[0045] In some embodiments, the material used for the substrate of the device wafer may be a semiconductor material, an insulating material, a conductor material, or any combination thereof. The substrate may be a single-layer structure or a multi-layer structure. For example, the substrate may be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate may be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator. Therefore, the type of substrate should not limit the scope of protection of the present disclosure.

[0046] In some embodiments, the height difference between a middle region of the top surface of the first dielectric layer and a peripheral region surrounding the middle region may be 2000 nm-20000 nm, for example, 2000 nm, 4000 nm, 6000 nm, 8000 nm, 10000 nm, 12000 nm, 14000 nm, 16000 nm, 18000 or 20000, etc.

[0047] In some embodiments, the preset thickness of the third dielectric layer may be 1000 nm-3000 nm, for example, 1000 nm, 1500 nm, 2000 nm, 2500 nm or 3000 nm, etc.

[0048] In some embodiments, before forming a third dielectric layer of a preset thickness, a data fitting algorithm is used to obtain a functional relationship between the logarithmic value lg(q) of the top surface step difference q of the third dielectric layer and the grinding removal amount of the third dielectric layer; and the minimum value of the preset thickness is determined based on the functional relationship and the target value.

[0049] In some embodiments, the logarithmic value lg(q) of the top surface step difference q is negatively correlated with the polishing removal amount of the third dielectric layer.

[0050] In some embodiments, a data fitting algorithm is used to obtain the logarithmic value lg(q) of the top surface step difference q of the third dielectric layer, and the functional relationship between the grinding removal amount x of the third dielectric layer is:

[0051] lg(q)=kx+b;

[0052] In the above formula, k and b are both constants, and k<0.

[0053] As an example, see Figure 2 The functional relationship between the logarithm lg(q) of the top surface step difference q of the third dielectric layer and the polishing removal amount of the third dielectric layer can be obtained by using the data fitting algorithm:

[0054] lg(q)=-0.0001x+3.3794;

[0055] Among them, the coefficient of determination R 2 It is 0.9798, and the functional relationship is highly fitted with the measured data. According to the functional relationship, the minimum value of the preset thickness can be obtained, thereby accurately obtaining the deposition parameters of the third dielectric layer.

[0056] As an example, see Figure 3 Different types of polishing pads have different compression coefficients. The polishing pad is selected according to actual needs. When the compression coefficient of the polishing pad is 1.9, the number of bubbles generated at the bonding interface of the device wafer and the carrier wafer in the embodiment of the present disclosure after annealing is 0. Therefore, polishing pads with different compression coefficients can be selected to reduce the number of bubbles in the bonding interface after annealing.

[0057] In some embodiments, a chemical mechanical polishing process is performed on the top surface of the third dielectric layer, including: after using a first polishing pad to perform a first chemical mechanical polishing process on the top surface of the third dielectric layer, using a second polishing pad to continue to perform a second chemical mechanical polishing process on the top surface of the third dielectric layer; the compression coefficient of the first polishing pad is different from the compression coefficient of the second polishing pad and both are greater than a preset compression coefficient threshold value, and by adjusting the compression coefficient of the pad, a polishing gap is prevented from occurring during the polishing process, and bubbles are avoided from occurring at the bonding interface.

[0058] In some embodiments, chemical mechanical polishing includes: determining appropriate polishing parameters, selecting polishing liquid according to the characteristics of the device wafer, selecting a polishing head according to the size and surface condition of the device wafer, for example, a hard polyurethane polishing head or a polypropylene polishing head may be selected, and finally performing a polishing process. During polishing, a suitable rotation speed and polishing pressure are selected according to the size of the device wafer and the material of the substrate to improve the controllability of etching and increase the stability of the polishing effect.

[0059] In some embodiments, when the first polishing pad is used to perform a first chemical mechanical polishing process on the top surface of the third dielectric layer, the polishing removal amount of the third dielectric layer can be 0-1400nm, for example, 0nm, 200nm, 400nm, 600nm, 800nm, 1000nm, 1200nm or 1400nm, etc.

[0060] In some embodiments, a high-density plasma chemical vapor deposition process is used in step S130 to deposit a second dielectric layer on the top surface of the planarized first dielectric layer. The second dielectric layer is used to provide compressive stress to the device wafer to reduce the warpage of the device wafer.

[0061] In some embodiments, after bonding the top surface of the ground fourth dielectric layer to the front surface of the carrier wafer in step S160, the method further includes:

[0062] Step S161: annealing the bonded back-illuminated semiconductor structure.

[0063] In some embodiments, the bonded back-illuminated semiconductor structure is annealed, and the annealing temperature may be 300°C-400°C, for example, 300°C, 320°C, 340°C, 360°C, 380°C or 40°C, etc.; the annealing time may be 40min-90min, for example, 40 min, 45 min, 50 min, 55 min, 60 min, 65 min, 70 min, 75 min, 80 min, 85min, or 90 min, etc.

[0064] In some embodiments, the target value is 0-10 nm, such as 0 nm, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm or 10 nm, etc.

[0065] Specifically, the first dielectric layer and the second dielectric layer can be deposited by high-density plasma enhanced chemical vapor deposition (HDP-CVD) process, which is a special form of plasma deposition (PECVD) process. In high-density plasma, ionized atoms or molecules have higher energy and have stronger bombardment when moving toward the substrate, and film deposition and sputtering occur simultaneously. This sputtering process can effectively eliminate the overhanging structure formed during the film deposition process, and can achieve bottom-up filling of grooves and pores. The film deposited by HDP-CVD has higher density and lower impurity content. The second dielectric layer with compressive stress deposited by HDP-CVD process can effectively reduce the wafer warpage; Tetraethoxysilane (TEOS) can be used as a deposition source when depositing the third dielectric layer, and the reaction conditions can be adjusted according to actual needs to control the thickness and quality of the film, reduce the height difference between the middle and edge parts of the wafer, and reduce the number of bubbles at the bonding interface.

[0066] In some embodiments, a high-density plasma chemical vapor deposition process is used to form the fourth dielectric layer. Since the density of the fourth dielectric layer is greater than that of the third dielectric layer, under the same removal conditions, the removal rate of the fourth dielectric layer is greater than that of the third dielectric layer, thereby reducing the number of bubbles at the bonding interface while minimizing the damage that may be caused to the bonding surface during the bonding process. In addition, the fourth dielectric layer can provide compressive stress to the device wafer, further reducing the warpage of the device wafer.

[0067] As an example, see Figure 4-Figure 8 , provides a back-illuminated image sensor, which is prepared by the back-illuminated semiconductor structure bonding method in any of the above embodiments, and the method comprises the following steps:

[0068] Step S110: providing a device wafer 110 and a carrier wafer 120; the device wafer 110 includes a device layer 111 and an epitaxial layer 113 located between the device layer 111 and a substrate 112; the device layer 111 includes a photodiode array.

[0069] Step S120: depositing a first dielectric layer 114 on the top surface of the device layer 111, planarizing the top surface of the first dielectric layer 114, and obtaining a height difference between a middle region (not shown) of the top surface of the planarized first dielectric layer 114 and a peripheral region (not shown) surrounding the middle region;

[0070] Step S130: after depositing the second dielectric layer 115 on the top surface of the planarized first dielectric layer 114, a third dielectric layer 116 with a preset thickness is formed on the top surface of the second dielectric layer 115; wherein, under the same polishing conditions, the removal rate of the third dielectric layer 116 is greater than the removal rate of the second dielectric layer 115;

[0071] Step S140: performing a chemical mechanical polishing process on the top surface of the third dielectric layer 116, so that the top surface step difference of the third dielectric layer 116 after polishing is less than a target value; the preset thickness is the sum of the height difference and the polishing removal amount of the third dielectric layer 116, and the polishing removal amount of the third dielectric layer 116 is related to the top surface step difference; the top surface step difference is the height difference between the highest point and the lowest point of the top surface of the third dielectric layer 116 after polishing;

[0072] Step S150: depositing a fourth dielectric layer 117 with a first thickness H1 on the top surface of the polished third dielectric layer 116; chemically mechanically polishing the fourth dielectric layer 117 to remove a second thickness H2 of the fourth dielectric layer 117, wherein the second thickness H2 is less than the first thickness H1;

[0073] Step S160: Bonding the top surface of the ground fourth dielectric layer 117 to the front surface of the carrier wafer 120 to obtain a back-illuminated semiconductor structure 100. The back-illuminated semiconductor structure bonding method and back-illuminated image sensor disclosed in the present invention have the following unexpected beneficial effects:

[0074] In the back-illuminated semiconductor structure bonding method and the back-illuminated image sensor disclosed in the present invention, a device wafer and a carrier wafer are first provided; the device wafer includes a device layer and an epitaxial layer located between the device layer and the substrate; the device layer includes a photodiode array, and then a first dielectric layer is deposited on the top surface of the device layer, and after the top surface of the first dielectric layer is planarized, a height difference between a middle area of ​​the top surface of the planarized first dielectric layer and a peripheral area surrounding the middle area is obtained, and after a second dielectric layer is deposited on the top surface of the planarized first dielectric layer, a third dielectric layer of a preset thickness is formed on the top surface of the second dielectric layer; wherein, on the same grinding strip, Under the condition that the removal rate of the third dielectric layer is greater than the removal rate of the second dielectric layer, the grinding gap can be avoided and the edge height difference can be reduced. Then, the top surface of the third dielectric layer is subjected to a chemical mechanical grinding process, so that the top surface step difference of the third dielectric layer after grinding is less than the target value; the preset thickness is the sum of the height difference and the grinding removal amount of the third dielectric layer, and the grinding removal amount of the third dielectric layer is related to the top surface step difference; the top surface step difference is the height difference between the highest point and the lowest point of the top surface of the third dielectric layer after grinding, so as to avoid the problem of high wafer warpage caused by wafer stress, reduce the height difference of the wafer edge, and avoid wafer edge collapse. After depositing a fourth dielectric layer of a first thickness on the top surface of the ground third dielectric layer, the fourth dielectric layer is subjected to chemical mechanical grinding to remove a second thickness of the fourth dielectric layer, the second thickness is less than the first thickness, and the top surface of the ground fourth dielectric layer whose top surface flatness reaches the target value is further obtained. Finally, the top surface of the ground fourth dielectric layer is bonded to the front side of the carrier wafer, so as to reduce the number of bubbles at the bonding interface and improve the device yield.

[0075] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0076] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0077] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A back-illuminated semiconductor structure bonding method, characterized in that: The method comprises: Providing a device wafer and a carrier wafer; the device wafer comprises a device layer and an epitaxial layer located between the device layer and a substrate; the device layer comprises a photodiode array; Depositing a first dielectric layer on the top surface of the device layer, and after planarizing the top surface of the first dielectric layer, obtaining a height difference between a middle area of ​​the top surface of the planarized first dielectric layer and a peripheral area surrounding the middle area; After depositing a second dielectric layer on the top surface of the planarized first dielectric layer, a third dielectric layer of a preset thickness is formed on the top surface of the second dielectric layer; wherein, under the same polishing conditions, the removal rate of the third dielectric layer is greater than the removal rate of the second dielectric layer; A chemical mechanical polishing process is performed on the top surface of the third dielectric layer, so that the step difference of the top surface of the third dielectric layer after polishing is less than a target value; the preset thickness is the sum of the height difference and the polishing removal amount of the third dielectric layer, and the polishing removal amount of the third dielectric layer is related to the top surface step difference; the top surface step difference is the height difference between the highest point and the lowest point of the top surface of the third dielectric layer after polishing; Depositing a fourth dielectric layer with a first thickness on the top surface of the polished third dielectric layer; Chemical mechanical polishing is performed on the fourth dielectric layer to remove a second thickness of the fourth dielectric layer, wherein the second thickness is less than the first thickness; The top surface of the ground fourth dielectric layer is bonded to the front surface of the carrier wafer.

2. The back-illuminated semiconductor structure bonding method according to claim 1, characterized in that: The logarithmic value lg(q) of the top surface step difference q is negatively correlated with the polishing removal amount of the third dielectric layer.

3. The back-illuminated semiconductor structure bonding method according to claim 1, characterized in that: Before forming a third dielectric layer of a preset thickness, a data fitting algorithm is used to obtain a functional relationship between a logarithmic value lg(q) of a step difference q on a top surface of the third dielectric layer and a grinding removal amount of the third dielectric layer; The minimum value of the preset thickness is determined according to the functional relationship and the target value.

4. The back-illuminated semiconductor structure bonding method according to claim 3, characterized in that: The functional relationship between the logarithm lg(q) of the top surface step difference q of the third dielectric layer obtained by using a data fitting algorithm and the grinding removal amount x of the third dielectric layer is: lg(q)=kx+b; In the above formula, k and b are both constants, and k<0.

5. The back-illuminated semiconductor structure bonding method according to any one of claims 1 to 4, characterized in that: Performing a chemical mechanical polishing process on the top surface of the third dielectric layer includes: After performing a first chemical mechanical polishing process on the top surface of the third dielectric layer using a first polishing pad, a second chemical mechanical polishing process is continued to be performed on the top surface of the third dielectric layer using a second polishing pad; the compression coefficient of the first polishing pad is different from the compression coefficient of the second polishing pad and both are greater than a preset compression coefficient threshold.

6. The back-illuminated semiconductor structure bonding method according to any one of claims 1 to 4, characterized in that: After bonding the top surface of the ground fourth dielectric layer to the front surface of the carrier wafer, the method further includes: Annealing the bonded back-illuminated semiconductor structure.

7. The back-illuminated semiconductor structure bonding method according to any one of claims 1 to 4, characterized in that: The target value is 0-10 nm.

8. The back-illuminated semiconductor structure bonding method according to any one of claims 1 to 4, characterized in that: The second dielectric layer is deposited on the top surface of the planarized first dielectric layer by using a high-density plasma chemical vapor deposition process, and the second dielectric layer is used to provide compressive stress to the device wafer.

9. The back-illuminated semiconductor structure bonding method according to any one of claims 1 to 4, characterized in that: The first dielectric layer and the second dielectric layer are made of the same material, and the first dielectric layer and the third dielectric layer are made of different materials.

10. A back-illuminated image sensor, characterized in that: It is prepared by the back-illuminated semiconductor structure bonding method described in any one of claims 1 to 9.

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