A semiconductor device with a gas guide groove structure and a method for manufacturing the same

Abstract

A semiconductor device with an air guide groove structure and a preparation method thereof belong to the technical field of semiconductor devices and their processing technology. The present invention is to deposit a first metal layer on the surface of a silicon-based CMOS with a reserved cutting path, then evaporate an ITO film on the surface of a GaN epitaxial wafer of a sapphire / silicon substrate and perform annealing treatment, and after depositing the second metal layer, use an IBE process to etch or a metal stripping process to obtain a grid-like air guide groove structure; after aligning the air guide groove with the reserved cutting path, ultrasonic eutectic bonding is performed, and finally, the substrate, N‑GaN layer and quantum well layer are cut through along the air guide groove structure on the back side of the substrate, so that the air guide groove is connected to the air; then the sapphire substrate is peeled off by laser or the silicon substrate is ground off, and then the N‑GaN layer is thinned, so as to prepare a semiconductor device with an air guide groove structure. The method described in the present invention does not require the use of high-precision bonding equipment, thereby reducing equipment investment and having good technical effects.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor devices and processing techniques thereof, and in particular relates to a semiconductor device with an air guide groove structure and a preparation method thereof. Background Art

[0002] Currently in the field of silicon-based Micro LED, the bonding process is mainly divided into direct bonding and wafer bonding with intermediate material.

[0003] As one of the wafer bonding methods, eutectic bonding (wafer to wafer) refers to the process of coating the entire surface of GaN epitaxial wafers on sapphire / silicon substrates (i.e., growing N-GaN / quantum well / P-GaN structures on sapphire / silicon, which is the current mainstream LED epitaxial structure) and silicon-based CMOS with metal, heating two or more materials to a molten state at high temperature, so that their surfaces fuse with each other and form a strong connection during the cooling process. It has low bonding accuracy requirements and is mainly used in MEMS, CMOS Image Sensor (CIS) and other fields. Eutectic bonding can achieve high-resolution, high-brightness and low-energy display effects, so it has broad application prospects in display panels, virtual reality, augmented reality and other fields.

[0004] Fusion Bonding is a type of direct bonding. It activates the surface of the wafer and uses van der Waals force to pre-bond two wafers in the bonding machine. After high-temperature annealing, the bonding energy can be improved so that the wafer can be processed and produced later. Hybrid Bonding is an improvement on Fusion Bonding. It can perform point-to-point bonding or mixed bonding of metal and non-metal. Therefore, it has extremely high requirements for bonding accuracy. It is currently mainly used in fields such as 3D stacking. Hybrid bonding technology can achieve high bonding strength and excellent electrical performance at the same time, which helps to improve the overall performance of Micro LED display chips.

[0005] The two mainstream bonding technologies currently have their own problems: eutectic bonding (wafer to wafer) has low precision requirements, but a large number of bubbles will be generated during bonding, thus forming voids in the bonding layer, which in turn affects the quality of the product. Hybrid bonding has extremely high precision requirements, is difficult to align, requires high precision equipment, and has high and complex process parameters, so the product quality is good. Both technologies have significant advantages and disadvantages, so neither is perfect.

[0006] The mainstream technology at present is eutectic bonding (wafer to wafer), and the solder used is an alloy of gold and tin. However, there is a void problem during gold-tin bonding. The main reasons for the voids are: welding surface conditions (such as surface dirt), improper welding process parameters (temperature, pressure, time, etc.), material properties of gold-tin alloy, Kirkendall effect, etc. The void rate will affect the thermal resistance and electrical resistance, and thus affect the electrical and thermal performance of the Micro LED screen and each sub-pixel. Summary of the invention

[0007] The purpose of the present invention is to provide a semiconductor device with an air guide groove structure and a preparation method thereof. The present invention can effectively remove bubbles in the metal bonding process by introducing the air guide groove structure in the semiconductor device, thereby solving the problem of bubble generation in the MicroLED bonding process.

[0008] The semiconductor device with an air guide groove structure described in the present invention consists of a silicon-based CMOS with a reserved cutting path, a first metal layer, a second metal layer, an ITO film, a P-GaN layer, a quantum well layer, and an N-GaN layer from bottom to top. An air guide groove structure connected to the air is provided in the second metal layer, the ITO film, the P-GaN layer, the quantum well layer, and the N-GaN layer. The symmetry center line of the air guide groove coincides with the symmetry center line of the reserved cutting path of the silicon-based CMOS, and the width of the air guide groove is smaller than the width of the reserved cutting path.

[0009] The method for preparing a semiconductor device with a gas-conducting groove structure according to the present invention comprises the following steps:

[0010] A. Prepare the first metal layer on the silicon-based CMOS surface with reserved cutting paths:

[0011] (1) Using evaporation, magnetron sputtering or electroplating process to deposit a single-layer structure or a multi-layer structure with "titanium layer-platinum layer" as a stacking repeating unit on a silicon-based CMOS surface with a reserved cutting path, the platinum layer is used as a protective metal, the titanium layer is used as a link metal, the thickness of the titanium layer is 15~50nm, and the thickness of the platinum layer is 15~50nm;

[0012] (2) depositing a single-layer structure or a multi-layer structure with a "gold layer-tin layer" as a stacking repeating unit on the surface of the outermost platinum layer in step (1) by evaporation, magnetron sputtering or electroplating, wherein the thickness of the gold layer is 15 to 50 nm and the thickness of the tin layer is 15 to 50 nm;

[0013] (3) depositing a single gold layer with a thickness of 80 to 120 nm on the surface of the outermost tin layer in step (2) by evaporation, magnetron sputtering or electroplating, thereby preparing a first metal layer consisting of a "titanium layer-platinum layer" stacked structure, a "gold layer-tin layer" stacked structure and a single gold layer on the surface of the silicon-based CMOS with a reserved cutting path;

[0014] Furthermore, a chromium layer with a thickness of 80 to 120 nm is deposited between the silicon-based CMOS surface and the first titanium layer of the "titanium layer-platinum layer" stacked structure; thereby, a first metal layer consisting of the chromium layer, the "titanium layer-platinum layer" stacked structure, the "gold layer-tin layer" stacked structure and a single gold layer is prepared on the silicon-based CMOS surface with a reserved cutting path;

[0015] Silicon-based CMOS is a silicon wafer with CMOS circuits on its surface, including pixel drive circuits, timing circuits, interface circuits, etc. of each display module (panel); many grid-shaped display panel backplanes (Back Plane) are arranged on the surface of silicon-based CMOS, and a certain width is reserved between each two panels as a reserved cutting path when cutting, such as Figure 7 As shown;

[0016] B. Prepare an ITO film and a second metal layer on the surface of the cleaned GaN epitaxial wafer of the sapphire / silicon substrate:

[0017] (1) Using electron beam evaporation technology, a 150-250 nm thick ITO film is deposited on the surface of the cleaned GaN epitaxial wafer on the sapphire / silicon substrate, and then annealed;

[0018] (2) depositing a chromium layer with a thickness of 80 to 120 nm as a barrier protective layer on the surface of the ITO film in step (1) by evaporation, magnetron sputtering or electroplating;

[0019] (3) depositing a single-layer structure or a multi-layer structure with "titanium layer-platinum layer" as a stacking repeating unit on the surface of the chromium layer in step (2) by evaporation, magnetron sputtering or electroplating, wherein the thickness of the titanium layer is 15 to 50 nm and the thickness of the platinum layer is 15 to 50 nm;

[0020] (4) Depositing a single-layer structure or a multi-layer structure with "tin layer-gold layer" as a stacking repeating unit on the surface of the outermost platinum layer in step (3) by evaporation, magnetron sputtering or electroplating, wherein the thickness of the tin layer is 30-50 nm and the thickness of the gold layer is 15-50 nm; thereby preparing an ITO thin film and a second metal layer consisting of a chromium layer, a "titanium layer-platinum layer" stacking structure and a "tin layer-gold layer" stacking structure on the surface of the GaN epitaxial wafer on the sapphire / silicon substrate;

[0021] The thickness of the first metal layer obtained in step B is different from the thickness of the second metal layer obtained in step A, including the total thickness and the thickness of a single metal layer. The specific thickness needs to be determined by subsequent process conditions such as bonding time and IBE etching depth.

[0022] The GaN epitaxial wafer on sapphire / silicon substrate has a substrate / N-GaN / quantum well / P-GaN structure, and the substrate is a sapphire substrate or a silicon substrate;

[0023] The cleaning is to use concentrated sulfuric acid and hydrogen peroxide solution with a molar concentration ratio of 6 to 8:1 to remove organic matter on the surface of the GaN epitaxial wafer, and then use acetone and isopropanol to remove inorganic matter on the surface of the GaN epitaxial wafer, and then soak and wash with pure water, rinse with pure water, and then dry;

[0024] C. The surface of the GaN epitaxial wafer on the sapphire / silicon substrate obtained in step B is etched by IBE process or metal stripping process to obtain a grid-like gas guide groove structure. The width of the gas guide groove is smaller than the width of the reserved cutting road on the silicon-based CMOS surface; the depth of the gas guide groove needs to be etched through the second metal layer, the ITO film and a part of the P-GaN layer, and the complete quantum well layer and the N-GaN layer are retained, such as Figure 3 As shown in (b);

[0025] D. Surface-bonding the second metal layer surface of the GaN epitaxial wafer obtained in step C with the first metal layer surface of the silicon-based CMOS obtained in step A in a manner that the GaN epitaxial wafer is on top and the silicon-based CMOS is on the bottom, and aligning the gas guide groove on the surface of the GaN epitaxial wafer with the reserved cutting path of the silicon-based CMOS, such as Figure 4 As shown in (a), alignment is to make the symmetric center line of the gas guide groove coincide with the symmetric center line of the reserved cutting path of the silicon-based CMOS; then ultrasonic eutectic bonding is performed, that is, heating to 200-300 degrees Celsius at a heating rate of 8-10 degrees Celsius / minute under vacuum conditions, then applying a pressure of 25-35 KN and maintaining it for 8-15 minutes, then ultrasonically treating it at a frequency of 60-80 kHz for 8-15 minutes, and finally gradually cooling it to room temperature;

[0026] E. Use a cutting wheel to cut through the substrate, N-GaN layer and quantum well layer along the gas guide groove structure on one side of the sapphire / silicon substrate, so that the gas guide groove structure is connected to the air; then the sapphire substrate is peeled off by laser or the silicon substrate is ground off, and then the N-GaN layer is thinned to prepare a semiconductor device with a gas guide groove structure.

[0027] Another semiconductor device with an air guide groove structure described in the present invention is composed of an N-GaN layer, a quantum well layer, a P-GaN layer, an ITO film, a second metal layer, a first metal layer and a silicon-based CMOS with a reserved cutting path from bottom to top. The first metal layer has an air guide groove structure, the symmetry center line of the air guide groove coincides with the symmetry center line of the reserved cutting path of the silicon-based CMOS, and the width of the air guide groove is smaller than the width of the reserved cutting path, and the depth of the air guide groove is engraved through the first metal layer.

[0028] Another method for preparing a semiconductor device with an air guide groove structure according to the present invention comprises the following specific steps:

[0029] A. Prepare the first metal layer on the silicon-based CMOS surface with reserved cutting paths:

[0030] (1) preparing a photoresist grid structure having an inverted trapezoidal shape on a surface of a silicon-based CMOS with a reserved cutting path, wherein the position of the photoresist grid structure is aligned with the reserved cutting path of the silicon-based CMOS;

[0031] (2) using evaporation, magnetron sputtering or electroplating technology to deposit a single-layer structure or a multi-layer structure with "titanium layer-platinum layer" as a stacking repeating unit on the photoresist grid structure in step (1) and the surface of the silicon-based CMOS, wherein the platinum layer serves as a protective metal and the titanium layer serves as a linking metal, the thickness of the titanium layer is 15 to 50 nm, and the thickness of the platinum layer is 15 to 50 nm;

[0032] (3) using evaporation, magnetron sputtering or electroplating technology to deposit a single-layer structure or a multi-layer structure with a "gold layer-tin layer" as a stacking repeating unit on the surface of the outermost platinum layer in step (2), wherein the thickness of the gold layer is 15 to 50 nm and the thickness of the tin layer is 30 to 50 nm;

[0033] (4) depositing a single gold layer with a thickness of 80 to 120 nm on the surface of the outermost tin layer in step (3) by evaporation, magnetron sputtering or electroplating, thereby preparing a first metal layer consisting of a "titanium layer-platinum layer" stacked structure, a "gold layer-tin layer" stacked structure and a single gold layer on the surface of the silicon-based CMOS with a reserved cutting path;

[0034] Furthermore, a chromium layer with a thickness of 80 to 120 nm is deposited between the photoresist grid structure and the silicon-based CMOS surface and the first titanium layer of the "titanium layer-platinum layer" stacked structure; thereby, a first metal layer consisting of the chromium layer, the "titanium layer-platinum layer" stacked structure, the "gold layer-tin layer" stacked structure and a single gold layer is prepared on the silicon-based CMOS surface with a reserved cutting path;

[0035] B. removing the photoresist from the silicon-based CMOS obtained in step A through a metal stripping process, thereby stripping the photoresist and the first metal layer thereon, and obtaining an air guide groove structure that is connected to the air and penetrates the first metal layer; the width of the air guide groove is smaller than the width of the reserved cutting road on the surface of the silicon-based CMOS, and the symmetry center line of the air guide groove coincides with the symmetry center line of the reserved cutting road of the silicon-based CMOS;

[0036] C. Preparing an ITO film and a second metal layer on the surface of the GaN epitaxial wafer of the cleaned sapphire / silicon substrate:

[0037] (1) Using electron beam evaporation technology, a 150-250 nm thick ITO film is deposited on the surface of the cleaned GaN epitaxial wafer on the sapphire / silicon substrate, and then annealed;

[0038] (2) depositing a chromium layer with a thickness of 80 to 120 nm as a barrier protective layer on the surface of the ITO film in step (1) by evaporation, magnetron sputtering or electroplating;

[0039] (3) depositing a single-layer structure or a multi-layer structure with "titanium layer-platinum layer" as a stacking repeating unit on the surface of the chromium layer in step (2) by evaporation, magnetron sputtering or electroplating, wherein the thickness of the titanium layer is 15 to 50 nm and the thickness of the platinum layer is 15 to 50 nm;

[0040] (4) Depositing a single-layer structure or a multi-layer structure with "tin layer-gold layer" as a stacking repeating unit on the surface of the outermost platinum layer in step (3) by evaporation, magnetron sputtering or electroplating; the thickness of the tin layer is 30-50 nm, and the thickness of the gold layer is 15-50 nm; thereby preparing an ITO thin film and a second metal layer consisting of a chromium layer, a "titanium layer-platinum layer" stacking structure and a "tin layer-gold layer" stacking structure on the surface of the GaN epitaxial wafer on the sapphire / silicon substrate;

[0041] The cleaning is to use concentrated sulfuric acid and hydrogen peroxide solution with a molar concentration ratio of 6 to 8:1 to remove organic matter on the surface of the GaN epitaxial wafer, and then use acetone and isopropanol to remove inorganic matter on the surface of the GaN epitaxial wafer, and then soak and wash with pure water, rinse with pure water, and then dry;

[0042] D. Surface bonding the second metal layer surface of the GaN epitaxial wafer obtained in step C to the first metal layer surface of the silicon-based CMOS obtained in step B in a manner that the GaN epitaxial wafer is at the bottom and the silicon-based CMOS is at the top. Figure 4 As shown in (c), ultrasonic eutectic bonding is then performed, that is, the temperature is raised to 200-300 degrees Celsius at a heating rate of 8-10 degrees Celsius / minute under vacuum conditions, and then a pressure of 25-35 KN is applied and maintained for 8-15 minutes, and then ultrasonic treatment is performed at a frequency of 60-80 kHz for 8-15 minutes, and finally the temperature is gradually cooled to room temperature;

[0043] E. The sapphire substrate is peeled off by laser or the silicon substrate is ground off, and then the N-GaN layer is thinned to prepare a semiconductor device with a gas guide groove structure.

[0044] The semiconductor device with the air guide groove structure of the present invention is prepared by the above method. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 : A front cross-sectional view of a semiconductor device with an air guide groove structure according to the present invention;

[0046] Figure 2 : A front cross-sectional view of the metal layer structure of the present invention;

[0047] Figure 3 : Schematic diagram of the gas-conducting groove structure on the surface of the GaN epitaxial wafer and the surface of the silicon-based CMOS according to the present invention;

[0048] Figure 4 : Schematic diagram of the device structure after the ultrasonic bonding process of the present invention is completed;

[0049] Figure 5 :Process flow chart for preparing gas-conducting groove structure on GaN epitaxial wafer on sapphire / Si substrate;

[0050] Figure 6 : Process flow chart for bonding, cutting and thinning a GaN epitaxial wafer with a gas-conducting groove structure and a silicon-based CMOS with a reserved cutting path structure;

[0051] Figure 7 :Schematic diagram of silicon-based CMOS surface structure;

[0052] Figure 8 : Top view of air guide groove structures with various densities. DETAILED DESCRIPTION Embodiment 1:

[0053] A. Prepare the first metal layer on the silicon-based CMOS surface with reserved cutting paths:

[0054] (1) Using evaporation, magnetron sputtering or electroplating process to deposit a double-layer structure with "titanium layer-platinum layer" as a stacking repeating unit on the surface of a silicon-based CMOS with a reserved cutting path, the platinum layer is used as a protective metal and the titanium layer is used as a link metal. The thickness of the titanium layer is 20nm and the thickness of the platinum layer is 20nm;

[0055] (2) depositing a double-layer structure of "gold layer-tin layer" as a stacking repeating unit on the surface of the outermost platinum layer in step (1) by evaporation, magnetron sputtering or electroplating, wherein the thickness of the gold layer is 20 nm and the thickness of the tin layer is 20 nm;

[0056] (3) A single gold layer with a thickness of 100 nm is deposited on the surface of the outermost tin layer in step (2) by evaporation, magnetron sputtering or electroplating process, thereby preparing a first metal layer consisting of a "titanium layer-platinum layer" double-layer structure, a "gold layer-tin layer" double-layer structure and a single gold layer on the surface of the silicon-based CMOS with a reserved cutting path; that is, Ti 20nm+Pt 20nm+Ti20nm+Pt 20nm+Au 20nm+Sn 20nm+ Au 20nm +Sn 20nm+Au 100 nm;

[0057] B. Clean the surface of the GaN epitaxial wafer, i.e., use a concentrated sulfuric acid and hydrogen peroxide solution with a molar concentration ratio of 7:1 to remove organic matter on the surface of the GaN epitaxial wafer, then use acetone and isopropanol to remove inorganic matter on the surface of the GaN epitaxial wafer, then soak and wash with pure water, rinse with pure water, and then spin dry;

[0058] C. Prepare an ITO film and a second metal layer on the surface of the cleaned GaN epitaxial wafer of the sapphire / silicon substrate:

[0059] (1) A 200 nm thick ITO film is deposited on the surface of the cleaned GaN epitaxial wafer on the sapphire / silicon substrate using an electron beam evaporation process, and then annealed; the annealing temperature is 475 degrees Celsius, the annealing time is 3 minutes, and the annealing atmosphere is an oxygen atmosphere;

[0060] (2) depositing a chromium layer with a thickness of 100 nm as a barrier protective layer on the surface of the ITO film in step (1) by evaporation, magnetron sputtering or electroplating;

[0061] (3) depositing a double-layer structure of "titanium layer-platinum layer" as a stacking repeating unit on the surface of the chromium layer in step (2) by evaporation, magnetron sputtering or electroplating, wherein the thickness of the titanium layer is 20 nm and the thickness of the platinum layer is 20 nm;

[0062] (4) On the surface of the outermost platinum layer in step (3), a four-layer structure with "tin layer-gold layer" as a stacking repeating unit is deposited by evaporation, magnetron sputtering or electroplating process, the thickness of the tin layer is 40nm, and the thickness of the gold layer is 20nm; thereby, an ITO film and a second metal layer consisting of a chromium layer, a "titanium layer-platinum layer" double-layer structure, and a "tin layer-gold layer" four-layer structure are prepared on the surface of the GaN epitaxial wafer on the sapphire / silicon substrate, that is, Cr 100nm+ Ti 20nm+Pt 20nm+Ti 20nm+Pt 20nm+Sn40nm+Au 20nm+ Sn 40nm+Au 20nm+Sn 40nm+Au 20nm+Sn 40nm+Au 20nm;

[0063] D. Using a CVD process to evaporate 0.7 μm thick SiO2 as a hard mask layer on the surface of the second metal layer obtained in step C, and then spin-coating a photoresist (photoresist 7500, positive photoresist) on the SiO2 at a rotation speed of 1000 R / s, and baking at 120° C. for 120 seconds for curing, the prepared photoresist film has a thickness of 1 μm; using a mask plate complementary to the gas guide groove structure to perform mask photolithography, so that the photoresist at the position of the gas guide groove structure not blocked by the mask plate is exposed; the exposure energy during exposure is 80 mj, and after exposure, the mask plate is removed, and then a 2.38% by mass tetramethylammonium hydroxide aqueous solution is used as a developer to decompose the exposed photoresist at the position corresponding to the gas guide groove structure, thereby exposing the SiO2 at the position corresponding to the gas guide groove structure, and then using an ICP etching process to remove the SiO2 hard mask layer without the photoresist film blocking it, thereby exposing the second metal layer thereunder, and finally washing away the remaining photoresist;

[0064] E. Use the IBE process to etch the second metal layer, the ITO film and a portion of the P-GaN layer using the remaining SiO2 hard mask layer outside the gas guide groove structure as a mask, thereby producing a non-through gas guide groove structure; the width of the gas guide groove (45μm) is smaller than the width of the reserved cutting road of the silicon-based CMOS (55μm), and then use wet etching to remove the SiO2 hard mask layer; the etching angle of the IBE process is 15°, and the applied voltage is 400V;

[0065] F. Surface bonding is performed on the second metal layer surface of the GaN epitaxial wafer obtained in step E and the first metal layer surface of the silicon-based CMOS obtained in step A in the manner of the GaN epitaxial wafer on top and the silicon-based CMOS on the bottom, and the gas guide groove on the surface of the GaN epitaxial wafer is aligned with the reserved cutting path of the silicon-based CMOS, that is, the symmetric center line of the gas guide groove coincides with the symmetric center line of the reserved cutting path of the silicon-based CMOS, and then ultrasonic eutectic bonding is performed. The bonding steps are: first vacuumize, then slowly heat up (heat at a rate of 10°C / min), and after the temperature reaches 280°C, pressure (30 KN) is applied and maintained for 10 minutes. After the bonding metal is fully melted and gold and tin enter each other, ultrasonic (frequency 65 kHz) is applied for 10 minutes, and finally the temperature is gradually cooled to room temperature. Due to the existence of the gas guide groove structure, the gas generated during bonding is discharged from the inside of the bonding position through the gas guide groove, and the situation in which there is no bubbling in the peripheral area of ​​the bonding position and the bubbles in the central area are not removed cleanly in the existing process will not occur; in addition, due to the application of the ultrasonic process, the effect of removing bubbles can be better enhanced;

[0066] G. Use a cutting wheel to cut through the substrate, N-GaN layer and quantum well layer along the gas groove structure on the back of the sapphire / silicon substrate, so that the gas groove structure is connected to the air; then remove the sapphire substrate by laser or grind off the silicon substrate, and then thin the N-GaN layer to prepare a semiconductor device with a gas groove structure, thereby achieving the purpose of removing bubbles in the Micro LED metal bonding process. The sapphire substrate is laser-stripped, the laser wavelength is 266nm, the laser irradiation point distance is 30μm, the irradiation frequency is 1000Hz, the bonding wafer carrier temperature is 30 degrees Celsius, and the ring scheme is used to irradiate and peel from the outside to the inside;

[0067] H. Use dry etching to make Micro LED countertops (countertop width 3.75μm, height 2μm), and then carry out other Micro LED processes. You can refer to Monochromatic Active Matrix Micro-LED Micro-Displays with >5,000 dpi Pixel Density Fabricated using Monolithic Hybrid Integration Process, SID 2018 DIGEST P-125 to obtain a Micro LED display panel.

[0068] Embodiment 2:

[0069] A. Prepare the first metal layer on the silicon-based CMOS surface with reserved cutting paths:

[0070] (1) Spin-coating a 3 μm photoresist (negative photoresist, model Az2020) on the surface of a silicon-based CMOS with a reserved cutting path (width of 55 μm) at a rotation speed of 1000 rpm, a curing baking temperature of 100°C, and a baking time of 90 seconds; then using a mask plate complementary to the gas guide groove structure to perform mask lithography, so that the photoresist at the position of the gas guide groove structure not blocked by the mask plate is exposed, and after removing the mask plate, using a developer (using a tetramethylammonium hydroxide aqueous solution with a mass fraction of 2.38% as the developer, the same developer as in Example 1, but with a different doping formula; the developer of the negative photoresist is doped with a surfactant, which is mainly alcohol ether carboxylate, with a molar concentration ratio of 5% to 10%) to remove the unexposed photoresist, and obtain a photoresist grid structure with an inverted trapezoidal groove (grid width of 45 μm), the symmetry center line of the photoresist grid structure coincides with the symmetry center line of the reserved cutting path of the silicon-based CMOS;

[0071] (2) using evaporation, magnetron sputtering or electroplating technology to deposit a three-layer structure with "titanium layer-platinum layer" as a stacking repeating unit on the photoresist grid structure in step (1) and the surface of the silicon-based CMOS, wherein the platinum layer serves as a protective metal and the titanium layer serves as a linking metal, the thickness of the titanium layer is 30 nm, and the thickness of the platinum layer is 30 nm;

[0072] (3) using evaporation, magnetron sputtering or electroplating technology to deposit a single stacked structure of "gold layer-tin layer" as a stacking repeating unit on the surface of the outermost platinum layer in step (2), wherein the thickness of the gold layer is 20 nm and the thickness of the tin layer is 40 nm;

[0073] (4) using evaporation, magnetron sputtering or electroplating to deposit a single gold layer with a thickness of 100 nm on the surface of the outermost tin layer in step (3), thereby preparing a first metal layer consisting of a "titanium layer-platinum layer" triple-layer structure, a "gold layer-tin layer" single-layer structure and a single gold layer on the surface of the silicon-based CMOS with a reserved cutting path; that is, Ti 30nm+Pt 30nm+Ti30nm+Pt 30nm+Ti 30nm+Pt 30nm+Au 20nm+Sn 40nm+Au 100 nm;

[0074] B. removing the photoresist from the silicon-based CMOS obtained in step A through a metal stripping process, thereby stripping the photoresist and the first metal layer thereon to obtain a gas guide groove structure penetrating the first metal layer; the width of the gas guide groove is smaller than the width of the reserved cutting road on the surface of the silicon-based CMOS, and the symmetry center line of the gas guide groove coincides with the symmetry center line of the reserved cutting road of the silicon-based CMOS;

[0075] C. Clean the GaN epitaxial wafer on the sapphire / silicon substrate, use a concentrated sulfuric acid and hydrogen peroxide solution with a molar concentration ratio of 7:1 to remove organic matter on the surface of the GaN epitaxial wafer, then use acetone and isopropanol to remove inorganic matter on the surface of the GaN epitaxial wafer, then soak and wash with pure water, then rinse with pure water, and then spin dry;

[0076] D. Prepare an ITO film and a second metal layer on the surface of the cleaned GaN epitaxial wafer of the sapphire / silicon substrate:

[0077] (1) A 200 nm thick ITO film is deposited on the surface of the cleaned GaN epitaxial wafer on the sapphire / silicon substrate using an electron beam evaporation process, and then annealed; the annealing temperature is 475 degrees Celsius, the annealing time is 3 minutes, and the annealing atmosphere is an oxygen atmosphere;

[0078] (2) depositing a chromium layer with a thickness of 100 nm as a barrier protective layer on the surface of the ITO film in step (1) by evaporation, magnetron sputtering or electroplating;

[0079] (3) depositing a double-layer structure of "titanium layer-platinum layer" as a stacking repeating unit on the surface of the chromium layer in step (2) by evaporation, magnetron sputtering or electroplating, wherein the thickness of the titanium layer is 20 nm and the thickness of the platinum layer is 20 nm;

[0080] (4) On the surface of the outermost platinum layer in step (3), a four-layer structure with "tin layer-gold layer" as a stacking repeating unit is deposited by evaporation, magnetron sputtering or electroplating process; the thickness of the tin layer is 40nm, and the thickness of the gold layer is 20nm; thereby, an ITO film and a first metal layer composed of a chromium layer, a "titanium layer-platinum layer" double-layer structure and a "tin layer-gold layer" four-layer structure are prepared on the surface of the GaN epitaxial wafer on the sapphire / silicon substrate; that is, Cr 100nm+ Ti 20nm+Pt 20nm+Ti 20nm+Pt20nm+Sn 40nm+Au 20nm+ Sn 40nm+Au 20nm+Sn 40nm+Au 20nm+Sn 40nm+Au 20nm;

[0081] E. Surface-bond the second metal layer surface of the GaN epitaxial wafer obtained in step D with the first metal layer surface of the silicon-based CMOS obtained in step B in a manner of GaN epitaxial wafer at the bottom and silicon-based CMOS at the top, and then perform ultrasonic eutectic bonding. The bonding steps are: first evacuate the vacuum, then slowly heat up (preferably at a rate of 10°C / min), and after the temperature reaches 280°C, begin to apply pressure (30 KN) and maintain for 10 minutes, and after the bonding metal is fully melted and gold and tin enter each other, apply ultrasound (frequency 65 kHz) for 10 minutes. Due to the presence of the gas guide groove, the gas is discharged from the inside of the bonding position through the gas guide groove during bonding, and the situation in the existing process where there is no bubbling in the surrounding area of ​​the bonding position but the bubbles in the central area cannot be completely discharged will not occur; in addition, due to the application of the ultrasonic process, the effect of removing bubbles can be better enhanced;

[0082] F. Remove the sapphire substrate by laser stripping or grind the silicon substrate, then thin the N-GaN layer to prepare a semiconductor device with a gas-conducting groove structure, thereby achieving the purpose of removing bubbles in the Micro LED metal bonding process. The sapphire substrate is laser stripped, the laser wavelength is 266nm, the laser irradiation point distance is 30μm, the irradiation frequency is 1000Hz, the bonding wafer carrier temperature is 30 degrees Celsius, and the ring scheme is used to irradiate and strip from the outside to the inside;

[0083] G. Use dry etching to make Micro LED countertops (countertop width 3.75μm, height 2μm), and then carry out other Micro LED processes. You can refer to Monochromatic Active Matrix Micro-LED Micro-Displays with >5,000 dpi Pixel Density Fabricated using Monolithic Hybrid Integration Process, SID 2018 DIGEST P-125 to obtain a Micro LED display panel.

[0084] like Figure 1 , which is a front cross-sectional view of a semiconductor device with an air guide groove structure according to the present invention; wherein, Figure 1 (a) is a front cross-sectional view of a semiconductor device having an air-conducting groove structure connected to air prepared in a GaN epitaxial wafer; Figure 1 (b) is a front cross-sectional view of a semiconductor device having an air-conducting groove structure connected to air in a silicon-based CMOS. Figure 1 As can be seen in (a), the device consists of a silicon-based CMOS with a reserved cutting path, a first metal layer, a second metal layer, an ITO film, a P-GaN layer, a quantum well layer, and an N-GaN layer from bottom to top. There is a gas-conducting groove structure connected to the air in the second metal layer, the ITO film, the P-GaN layer, the quantum well layer, and the N-GaN layer. The symmetry center line of the gas-conducting groove coincides with the symmetry center line of the reserved cutting path of the silicon-based CMOS, and the width of the gas-conducting groove is smaller than the width of the reserved cutting path. The depth of the gas-conducting groove is engraved through the second metal layer, the ITO film, the P-GaN layer, the quantum well layer, and the N-GaN layer; Figure 1 As can be seen in (b), the device consists of an N-GaN layer, a quantum well layer, a P-GaN layer, an ITO film, a second metal layer, a first metal layer and a silicon-based CMOS with a reserved cutting path from bottom to top. In the first metal layer, there is a gas guide groove structure connected to the air. The symmetry center line of the gas guide groove coincides with the symmetry center line of the reserved cutting path of the silicon-based CMOS, and the width of the gas guide groove is smaller than the width of the reserved cutting path. The depth of the gas guide groove is engraved through the first metal layer.

[0085] like Figure 2 , which is a front cross-sectional view of the metal layer structure of the present invention; wherein, Figure 2 (a) is a front cross-sectional view of the first metal layer structure prepared on the surface of silicon-based CMOS. Figure 2 (b) is a front cross-sectional view of the second metal layer structure prepared on the surface of the GaN epitaxial wafer; Figure 2As shown in (a), a first metal layer consisting of a chromium layer (optional structure), a "titanium layer-platinum layer" stacked structure, a "gold layer-tin layer" stacked structure and a single gold layer is prepared on the surface of the silicon-based CMOS; Figure 2 As can be seen in (b), a second metal layer consisting of a chromium layer, a "titanium layer-platinum layer" stacked structure and a "tin layer-gold layer" stacked structure is prepared on the surface of the GaN epitaxial wafer.

[0086] like Figure 3 FIG. 1 is a schematic diagram of the gas-conducting groove structure on the surface of the GaN epitaxial wafer and the surface of the silicon-based CMOS according to the present invention, wherein Figure 3 (a) is a top view of the gas-guiding groove structure on the surface of the GaN epitaxial wafer. Figure 3 (b) is a front cross-sectional view of the gas guide groove structure of the GaN epitaxial wafer; Figure 3 As can be seen in (a), the horizontal and vertical cross-shaped gas guide grooves form a grid structure on the surface of the epitaxial wafer. The gas guide grooves surround a P-GaN area, which can be the size of a panel. Figure 3 (b) is acceptable. The depth of the gas-conducting groove needs to penetrate the second metal layer and the ITO film, reach the P-GaN layer and be higher than the quantum well layer in the active region. Figure 3 (c) is a top view of the gas-guiding groove structure on the surface of silicon-based CMOS. Figure 3 (d) is a front cross-sectional view of the silicon-based CMOS gas-conducting groove structure; Figure 3 As can be seen in (c), the horizontal and vertical cross-shaped gas guide grooves form a grid structure on the surface of the silicon-based CMOS, and the gas guide grooves surround a display backplane (CMOS Panel); Figure 3 As can be seen in (d), the depth of the gas guide groove needs to be engraved through the first metal layer to reach the surface of the silicon-based CMOS, and the width of the gas guide groove must be smaller than the width of the reserved cutting road, and the gas guide groove and the reserved cutting road are aligned.

[0087] like Figure 4 FIG. 1 is a schematic diagram of the device structure after the ultrasonic bonding process of the present invention is completed; wherein Figure 4 (a) is the main cross-sectional view of the device structure after the gas-guiding groove structure on the surface of the GaN epitaxial wafer is aligned and bonded with the reserved cutting path of the silicon-based CMOS. Figure 4 (b) is a schematic diagram of the alignment of the gas-guiding groove structure on the surface of the GaN epitaxial wafer with the reserved cutting path of the silicon-based CMOS. Figure 4 (c) is a front cross-sectional view of the device structure after the GaN epitaxial wafer and the gas guide groove structure on the surface of the reserved cutting path of the silicon-based CMOS are aligned and bonded; Figure 4 As shown, the gas guide groove has the same period as the pre-stored cutting road of the silicon-based CMOS, the horizontal gas guide groove coincides with the horizontal cutting road, the vertical gas guide groove coincides with the vertical cutting road, the gas guide groove and the cutting road surround a display back panel, and the width of the gas guide groove is smaller than the width of the reserved cutting road.

[0088] like Figure 5 As shown, it is a process flow chart for preparing a gas guide groove structure on a GaN epitaxial wafer of a sapphire / Si substrate; wherein step (a) is to clean the surface of the sapphire / Si substrate, and step (b) is to epitaxially grow an N-GaN / quantum well / P-GaN structure on the cleaned sapphire / Si substrate to obtain a GaN epitaxial wafer with an LED light-emitting layer; the quantum well is AlGaN doped with Al as the LED light-emitting layer, and the doping ratio of aluminum determines the light-emitting wavelength; step (c) is to evaporate an ITO film on the P-GaN layer, and then deposit a second metal layer on the surface of the ITO film; step (d) is to prepare a grid-structured gas guide groove structure by a semiconductor process, preferably using an IBE process; the width of the gas guide groove is smaller than the width of the reserved cutting path on the surface of the silicon-based CMOS; the depth of the gas guide groove needs to be engraved through the second metal layer, the ITO film and a part of the P-GaN layer, retaining a complete quantum well layer and N-GaN layer.

[0089] like Figure 6 As shown, it is a process flow chart for bonding, cutting and thinning a GaN epitaxial wafer with an air guide groove structure and a silicon-based CMOS with a reserved cutting path structure; wherein step (a) is to evaporate a first metal layer on the surface of the silicon-based CMOS, step (b) is to ultrasonically bond the GaN epitaxial wafer with the air guide groove structure and the silicon-based CMOS with the reserved cutting path structure, and the second metal layer of the GaN epitaxial wafer is surface-bonded with the first metal layer of the silicon-based CMOS; step (c) is to cut through the sapphire / Si substrate, the N-GaN layer and the quantum well layer along the direction of the air guide groove structure, so that the air guide groove structure runs through the entire GaN epitaxial wafer and is connected to the air; step (d) is to remove the sapphire substrate by laser stripping or remove the silicon substrate by grinding, and then thin the N-GaN layer, so as to obtain a device with an air guide groove structure.

[0090] like Figure 7 , which is a schematic diagram of the surface structure of a silicon-based CMOS; wherein the distance between every two panels is equivalent to the width of the reserved cutting path.

[0091] Embodiment 3:

[0092] In Example 1 and Example 2, the air guide grooves and the cutting paths exist in a one-to-one relationship. However, in the actual production process, technicians can achieve similar effects to those in Example 1 and Example 2 by reducing the density of the air guide grooves (only transverse air guide grooves, or only longitudinal air guide grooves, or increasing the spacing between adjacent transverse and longitudinal air guide grooves at the same time, or only increasing the spacing between transverse air guide grooves, or only increasing the spacing between longitudinal air guide grooves, etc.).

[0093] like Figure 8As shown in (a), it is a top view of the gas guide groove structure in Example 1 and Example 2, which corresponds one-to-one with the reserved cutting road of the silicon-based CMOS; Figure 8 As shown in (b), it is a top view of the air guide groove structure with only the longitudinal air guide groove; Figure 8 (c) is a top view of the air guide groove structure in which the spacing between adjacent transverse and longitudinal air guide grooves is increased at the same time; Figure 8 (d) is a top view of the air guide groove structure in which only the longitudinal air guide groove spacing is increased.

[0094] Effects and benefits of the present invention:

[0095] Compared with the wafer to wafer gold-tin bonding solution, the semiconductor device described in the present invention introduces a gas guide groove structure to ensure the discharge of bubbles generated during the bonding process; compared with the hybrid bonding solution, the solution described in the present invention does not require the use of high-precision bonding equipment, thereby reducing equipment investment. The solution described in the present invention combines the advantages of the two mainstream bonding solutions and avoids the disadvantages of the two solutions. In addition, the introduction of the ultrasonic eutectic bonding process can disperse the bubbles to the greatest extent and avoid the occurrence of large bubbles that affect the electrical and thermal properties of the Micro LED pixels. Taking a single Micro LED pixel as an example, if bubbles are generated during the wafer bonding process, the connection between the GaN epitaxial of the Micro LED and the silicon-based CMOS circuit will cause a cold solder joint or a broken circuit, which will cause the lighting voltage of a single Micro LED pixel to increase or fail to light up; at the same time, in terms of thermal performance, due to the existence of cold solder joints or broken circuits, uneven heat dissipation will occur, and the pixels in the Micro LED area will overheat and cause wavelength drift.

Claims

1. A method for preparing a semiconductor device with a gas-conducting groove structure, characterized in that: The steps are as follows: A. Prepare the first metal layer on the silicon-based CMOS surface with reserved cutting paths: (1) Depositing a single-layer structure or a multi-layer structure with "titanium layer-platinum layer" as a stacking repeating unit on a silicon-based CMOS surface with a reserved cutting path by evaporation, magnetron sputtering or electroplating, wherein the thickness of the titanium layer is 15~50nm and the thickness of the platinum layer is 15~50nm; (2) depositing a single-layer structure or a multi-layer structure with a "gold layer-tin layer" as a stacking repeating unit on the surface of the outermost platinum layer in step (1) by evaporation, magnetron sputtering or electroplating, wherein the thickness of the gold layer is 15 to 50 nm and the thickness of the tin layer is 15 to 50 nm; (3) depositing a single gold layer with a thickness of 80 to 120 nm on the surface of the outermost tin layer in step (2) by evaporation, magnetron sputtering or electroplating, thereby preparing a first metal layer consisting of a "titanium layer-platinum layer" stacked structure, a "gold layer-tin layer" stacked structure and a single gold layer on the surface of the silicon-based CMOS with a reserved cutting path; B. Prepare an ITO film and a second metal layer on the surface of the cleaned GaN epitaxial wafer of the sapphire / silicon substrate: (1) Using electron beam evaporation technology, a 150-250 nm thick ITO film is deposited on the surface of the cleaned GaN epitaxial wafer on the sapphire / silicon substrate, and then annealed; (2) depositing a chromium layer with a thickness of 80 to 120 nm as a barrier protective layer on the surface of the ITO film in step (1) by evaporation, magnetron sputtering or electroplating; (3) depositing a single-layer structure or a multi-layer structure with "titanium layer-platinum layer" as a stacking repeating unit on the surface of the chromium layer in step (2) by evaporation, magnetron sputtering or electroplating, wherein the thickness of the titanium layer is 15 to 50 nm and the thickness of the platinum layer is 15 to 50 nm; (4) Depositing a single-layer structure or a multi-layer structure with "tin layer-gold layer" as a stacking repeating unit on the surface of the outermost platinum layer in step (3) by evaporation, magnetron sputtering or electroplating, wherein the thickness of the tin layer is 30-50 nm and the thickness of the gold layer is 15-50 nm; thereby preparing an ITO thin film and a second metal layer consisting of a chromium layer, a "titanium layer-platinum layer" stacking structure, and a "tin layer-gold layer" stacking structure on the surface of the GaN epitaxial wafer on the sapphire / silicon substrate; The GaN epitaxial wafer on sapphire / silicon substrate has a substrate / N-GaN / quantum well / P-GaN structure, and the substrate is a sapphire substrate or a silicon substrate; C. The surface of the GaN epitaxial wafer on the sapphire / silicon substrate obtained in step B is etched by an IBE process or a metal stripping process to obtain a grid-shaped gas-conducting groove, wherein the width of the gas-conducting groove is smaller than the width of the reserved cutting path on the surface of the silicon-based CMOS; the depth of the gas-conducting groove needs to be etched through the second metal layer, the ITO film and a part of the P-GaN layer, and the complete quantum well layer and the N-GaN layer are retained; D. Surface bonding the second metal layer surface of the GaN epitaxial wafer obtained in step C and the first metal layer surface of the silicon-based CMOS obtained in step A in a manner that the GaN epitaxial wafer is on top and the silicon-based CMOS is on the bottom, and the air guide groove on the surface of the GaN epitaxial wafer is aligned with the reserved cutting path of the silicon-based CMOS, wherein the alignment is to make the symmetric center line of the air guide groove coincide with the symmetric center line of the reserved cutting path of the silicon-based CMOS; then ultrasonic eutectic bonding is performed, and finally the temperature is gradually lowered to room temperature; E. Use a cutting wheel to cut through the substrate, N-GaN layer and quantum well layer along the gas guide groove structure on one side of the sapphire / silicon substrate, so that the gas guide groove structure is connected to the air; then the sapphire substrate is peeled off by laser or the silicon substrate is ground off, and then the N-GaN layer is thinned to prepare a semiconductor device with a gas guide groove structure.

2. The method for preparing a semiconductor device with a gas-conducting groove structure according to claim 1, characterized in that: A chromium layer with a thickness of 80 to 120 nm is deposited between the silicon-based CMOS surface and the first titanium layer of the "titanium layer-platinum layer" stacked structure; thereby, a first metal layer consisting of a chromium layer, a "titanium layer-platinum layer" stacked structure, a "gold layer-tin layer" stacked structure and a single gold layer is prepared on the silicon-based CMOS surface with a reserved cutting path.

3. A method for preparing a semiconductor device with a gas-conducting groove structure, characterized in that: The steps are as follows: A. Prepare the first metal layer on the silicon-based CMOS surface with reserved cutting paths: (1) preparing a photoresist grid structure having an inverted trapezoidal shape on a surface of a silicon-based CMOS with a reserved cutting path, wherein the position of the photoresist grid structure is aligned with the reserved cutting path of the silicon-based CMOS; (2) using evaporation, magnetron sputtering or electroplating technology to deposit a single-layer structure or a multi-layer structure with "titanium layer-platinum layer" as a stacking repeating unit on the photoresist grid structure and the silicon-based CMOS surface in step (1), wherein the thickness of the titanium layer is 15 to 50 nm and the thickness of the platinum layer is 15 to 50 nm; (3) using evaporation, magnetron sputtering or electroplating technology to deposit a single-layer structure or a multi-layer structure with "gold layer-tin layer" as a stacking repeating unit on the surface of the outermost platinum layer in step (2), wherein the thickness of the gold layer is 15 to 50 nm and the thickness of the tin layer is 30 to 50 nm; (4) depositing a single gold layer with a thickness of 80 to 120 nm on the surface of the outermost tin layer in step (3) by evaporation, magnetron sputtering or electroplating, thereby preparing a first metal layer consisting of a "titanium layer-platinum layer" stacked structure, a "gold layer-tin layer" stacked structure and a single gold layer on the surface of the silicon-based CMOS with a reserved cutting path; B. removing the photoresist from the silicon-based CMOS obtained in step A through a metal stripping process, thereby stripping the photoresist and the first metal layer thereon to obtain a gas guide groove structure penetrating the first metal layer; the width of the gas guide groove is smaller than the width of the reserved cutting road on the surface of the silicon-based CMOS, and the symmetry center line of the gas guide groove coincides with the symmetry center line of the reserved cutting road of the silicon-based CMOS; C. Prepare an ITO film and a second metal layer on the surface of the cleaned GaN epitaxial wafer of the sapphire / silicon substrate: (1) Using electron beam evaporation technology, a 150-250 nm thick ITO film is deposited on the surface of the cleaned GaN epitaxial wafer on the sapphire / silicon substrate, and then annealed; (2) depositing a chromium layer with a thickness of 80 to 120 nm as a barrier protective layer on the surface of the ITO film in step (1) by evaporation, magnetron sputtering or electroplating; (3) depositing a single-layer structure or a multi-layer structure with "titanium layer-platinum layer" as a stacking repeating unit on the surface of the chromium layer in step (2) by evaporation, magnetron sputtering or electroplating, wherein the thickness of the titanium layer is 15 to 50 nm and the thickness of the platinum layer is 15 to 50 nm; (4) Depositing a single-layer structure or a multi-layer structure with "tin layer-gold layer" as a stacking repeating unit on the surface of the outermost platinum layer in step (3) by evaporation, magnetron sputtering or electroplating; the thickness of the tin layer is 30-50 nm, and the thickness of the gold layer is 15-50 nm; thereby preparing an ITO thin film and a second metal layer consisting of a chromium layer, a "titanium layer-platinum layer" stacking structure, and a "tin layer-gold layer" stacking structure on the surface of the GaN epitaxial wafer on the sapphire / silicon substrate; D. Surface-bonding the second metal layer surface of the GaN epitaxial wafer obtained in step C and the first metal layer surface of the silicon-based CMOS obtained in step B in a manner of the GaN epitaxial wafer being at the bottom and the silicon-based CMOS being at the top, and then ultrasonic eutectic bonding is performed, and finally the temperature is gradually lowered to room temperature; E. The sapphire substrate is peeled off by laser or the silicon substrate is ground off, and then the N-GaN layer is thinned to prepare a semiconductor device with a gas guide groove structure.

4. The method for preparing a semiconductor device with a gas-conducting groove structure according to claim 3, characterized in that: A chromium layer with a thickness of 80 to 120 nm is deposited between the photoresist grid structure, the silicon-based CMOS surface and the first titanium layer of the "titanium layer-platinum layer" stacked structure; thereby, a first metal layer consisting of the chromium layer, the "titanium layer-platinum layer" stacked structure, the "gold layer-tin layer" stacked structure and a single gold layer is prepared on the silicon-based CMOS surface with a reserved cutting path.

5. A method for preparing a semiconductor device with a gas-conducting groove structure according to claim 1 or 3, characterized in that: The annealing temperature is 450~500 degrees Celsius, the annealing time is 3~8 minutes, and the annealing atmosphere is an oxygen atmosphere.

6. A method for preparing a semiconductor device with a gas-conducting groove structure according to claim 1 or 3, characterized in that: Ultrasonic eutectic bonding is to heat the material to 200-300 degrees Celsius at a rate of 8-10 degrees Celsius / minute under vacuum conditions, then apply a pressure of 25-35 KN and maintain for 8-15 minutes, then ultrasonically treat at a frequency of 60-80 kHz for 8-15 minutes, and finally gradually cool down to room temperature.

7. A method for preparing a semiconductor device with a gas-conducting groove structure according to claim 1 or 3, characterized in that: The gas guide grooves correspond to the reserved cutting paths of the silicon-based CMOS one by one, or the density of the gas guide grooves is less than the density of the reserved cutting paths of the silicon-based CMOS.

8. A semiconductor device with an air guide groove structure, characterized in that: The compound is prepared by the preparation method according to any one of claims 1 to 7.

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