An inverted light-emitting diode chip and a preparation method thereof

Abstract

The present invention provides an inverted light-emitting diode chip and a method for manufacturing the same. The method for manufacturing the inverted light-emitting diode chip includes: providing a substrate required for growth, and sequentially depositing an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer on the substrate; fabricating an N-type conductive via hole in the P-type semiconductor; fabricating a current spreading layer on the P-type semiconductor layer and the N-type conductive via hole; fabricating an isolation groove on the N-type conductive via hole and the current spreading layer; fabricating a first semiconductor layer on the P-type semiconductor layer, the N-type conductive via hole, the current spreading layer, and the isolation groove; fabricating a third insulating layer on the first semiconductor layer; fabricating a heat-conducting metal layer on the third insulating layer; fabricating a fourth insulating layer on the heat-conducting metal layer; fabricating a pad layer on the fourth insulating layer; and using an eutectic soldering process to solder the semi-finished product after completing step S9 onto a bracket.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly relates to a flip-chip light-emitting diode chip and a preparation method thereof. Background Art

[0002] In recent years, the technology of light-emitting diode chips has developed rapidly under the competition of major manufacturers and has been widely used in various fields such as general lighting, special lighting, direct display screens, backlight display screens, vehicle lamps, etc.

[0003] In the prior art, the existing flip-chip light-emitting diode chips have a high working temperature. When multiple flip-chip light-emitting diode chips are connected in series, such as in vehicle lamps, the working temperature of the entire lamp bead will increase sharply, seriously affecting the service life of the flip-chip light-emitting diode chips. Summary of the Invention

[0004] Based on this, the object of the present invention is to provide a flip-chip light-emitting diode chip and a preparation method thereof, which can effectively solve the deficiencies in the above-mentioned prior art.

[0005] A preparation method of a flip-chip light-emitting diode chip, the preparation method comprising:

[0006] S1, providing a substrate required for growth, and sequentially depositing an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer on the substrate;

[0007] S2, preparing an N-type conductive through-hole on the P-type semiconductor;

[0008] S3, preparing a current spreading layer on the P-type semiconductor layer and the N-type conductive through-hole;

[0009] S4, preparing an isolation groove on the N-type conductive through-hole and the current spreading layer;

[0010] S5, preparing a first semiconductor layer on the P-type semiconductor layer, the N-type conductive through-hole, the current spreading layer, and the isolation groove;

[0011] S6, preparing a third insulating layer on the first semiconductor layer;

[0012] S7, preparing a heat-conducting metal layer on the third insulating layer, and then preparing an N-type heat-conducting metal layer through-hole and a P-type heat-conducting metal layer through-hole on the heat-conducting metal layer;

[0013] Wherein, the thickness of the heat-conducting metal layer is between 2000 Å and 20000 Å, and the area of the heat-conducting metal layer is larger than the area of the N-type semiconductor layer;

[0014] S8. Prepare a fourth insulating layer on the heat-conducting metal layer, the N-type heat-conducting metal layer through-hole, and the P-type heat-conducting metal layer through-hole. Then, prepare an N-type fourth insulating layer through-hole, a P-type fourth insulating layer through-hole, and a fourth insulating layer connection through-hole disposed between the N-type fourth insulating layer through-hole and the P-type fourth insulating layer through-hole on the fourth insulating layer;

[0015] S9. Prepare a pad layer on the fourth insulating layer, the N-type fourth insulating layer through-hole, the P-type fourth insulating layer through-hole, and the fourth insulating layer connection through-hole. The pad layer includes an N-type pad, a P-type pad, and a heat-conducting pad located between the P-type pad and the N-type pad;

[0016] Among them, the fourth insulating layer connection through-hole is used to connect the heat-conducting pad and the heat-conducting metal layer. The area of the fourth insulating layer connection through-hole is larger than the area of the heat-conducting pad. The area of the heat-conducting pad is larger than the sum of the areas of the N-type pad and the P-type pad, and the area of the heat-conducting pad is larger than half of the area of the heat-conducting metal layer;

[0017] S10. Use the eutectic soldering process to solder the semi-finished product after completing step S9 on the bracket;

[0018] Among them, the area of the bracket is larger than that of the semi-finished product. A heat-dissipating pad and a heat-dissipating metal are provided on the bracket. The heat-conducting pad is connected to the heat-dissipating pad, and the heat-dissipating pad is connected to the heat-dissipating metal.

[0019] Further, the first semiconductor layer includes a first insulating layer, a Bragg reflection layer, a Bragg reflection layer through-hole, a first insulating layer through-hole, a metal reflection layer, a second insulating layer, a second insulating layer through-hole, and a metal connection layer that are sequentially disposed on the P-type semiconductor layer.

[0020] Further, the specific process for preparing the first insulating layer is:

[0021] Deposit SiO on the surfaces of the P-type semiconductor layer, the N-type conductive through-hole, the current spreading layer, and the isolation groove by PECVD process 2 as the first insulating layer, wherein the thickness of the first insulating layer is greater than 5000 Å.

[0022] Further, the specific process for preparing the Bragg reflection layer and the Bragg reflection layer through-hole is:

[0023] Evaporate 2 - 10 groups of TiO on the surface of the first insulating layer by electron beam evaporation process 2 and SiO 2The stacked layers are used as a Bragg reflection layer, and then a photoresist is coated on the surface of the Bragg reflection layer, and then the photoresist on the Bragg reflection layer is removed by exposure and development, and then the exposed Bragg reflection layer is removed by an inductively coupled plasma etching process to form a Bragg reflection layer through hole, and then the photoresist is removed;

[0024] Wherein, the Bragg reflection layer through hole includes an N-type Bragg reflection layer through hole and a P-type Bragg reflection layer through hole.

[0025] Furthermore, the specific process for preparing the first insulating layer through hole is:

[0026] Applying photoresist on the surface of the Bragg reflective layer and the through hole of the Bragg reflective layer, then removing part of the photoresist in the through hole of the Bragg reflective layer by exposure and development to expose the first insulating layer under the through hole of the Bragg reflective layer, then removing the exposed first insulating layer by BOE etching solution to form the through hole of the first insulating layer, and then removing the photoresist;

[0027] The first insulating layer through-holes include N-type first insulating layer through-holes and P-type first insulating layer through-holes.

[0028] Furthermore, the specific process for preparing the metal reflective layer is:

[0029] A negative photoresist is coated on the P-type first insulating layer through hole, the P-type Bragg reflective layer through hole and the Bragg reflective layer, and then part of the photoresist is removed by exposure and development, and then Ag metal, Ni metal, Ti metal, Ni metal and Ti metal are sequentially evaporated by electron beam evaporation process as the metal reflective layer, and then the metal layer located above the photoresist is removed by lift-off process, and then the photoresist is removed.

[0030] Furthermore, the specific process for preparing the second insulating layer and the through hole of the second insulating layer is:

[0031] Al2O3 is deposited on the metal reflective layer and in the area not covered by the metal reflective layer by using an ALD process. 3 , then deposited Al2O 3 SiO is deposited by PECVD process. 2 , as the second insulating layer, then coating the surface of the second insulating layer with photoresist, then exposing and developing to remove part of the photoresist, exposing the second insulating layer under the part of the photoresist, then removing the exposed second insulating layer with an inductively coupled plasma etching process to form a through hole in the second insulating layer, and then removing the photoresist;

[0032] Among them, the second insulating layer vias include N-type second insulating layer vias and P-type second insulating layer vias.

[0033] Furthermore, the specific process for preparing the metal connection layer is as follows:

[0034] Apply negative photoresist on the surface of the second insulating layer and the second insulating layer vias, then expose and develop to remove part of the photoresist, and then use electron beam evaporation to sequentially deposit Cr metal, Al metal, Ti metal, Cu metal, Ti metal, Ni metal, Ti metal, Ni metal, and Ti metal as the metal connection layer;

[0035] Among them, the metal connection layer includes an N-type metal connection layer and a P-type metal connection layer.

[0036] Furthermore, the specific process for preparing the third insulating layer is as follows:

[0037] Deposit a layer of ALN film by CVD process on the metal connection layer and the places not covered by the metal connection layer as the third insulating layer.

[0038] The present invention also provides a flip-chip light-emitting diode chip, which is prepared by using the preparation method of the flip-chip light-emitting diode chip as described above.

[0039] Compared with the prior art, the beneficial effects of the present invention are as follows: By preparing a third insulating layer on the first semiconductor layer, by preparing a heat-conducting metal layer with an area larger than that of the N-type semiconductor layer on the third insulating layer, and by preparing a fourth insulating layer on the heat-conducting metal layer, the N-type heat-conducting metal layer vias, and the P-type heat-conducting metal layer vias, so that the third insulating layer, the fourth insulating layer, and the heat-conducting metal layer disposed between the third insulating layer and the fourth insulating layer together form a heat sink structure, and then evenly distribute the heat of the flip-chip light-emitting diode chip on this heat sink structure; By setting the area of the heat-conducting pad to be larger than the sum of the areas of the N-type pad and the P-type pad, and the area of the heat-conducting pad is larger than half of the area of the heat-conducting metal layer, thereby increasing the area of the heat-conducting pad. The larger the area, the better the heat-conducting effect, and the lower the working temperature of the flip-chip light-emitting diode chip; By welding the semi-finished product after completing step S9 on the bracket, so that part of the heat of the flip-chip light-emitting diode chip can be transferred from the heat-conducting metal layer through the heat-conducting pad to the bracket with an area larger than the chip area and then to the heat-dissipating metal of the bracket. Such a setting can further reduce the working temperature of the flip-chip light-emitting diode chip, reduce the thermal resistance of the flip-chip light-emitting diode chip, and increase the service life of the flip-chip light-emitting diode chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is a flowchart of the preparation method of the flip-chip light-emitting diode chip in Embodiment 1 of the present invention;

[0041] Figure 2 It is a schematic cross-sectional view of the semi-finished product formed after step S9 in Embodiment 1 of the present invention;

[0042] Figure 3 It is a schematic cross-sectional view of the flip-chip light-emitting diode chip in Embodiment 1 of the present invention;

[0043] Description of main component symbols:

[0044]

[0045] The following specific embodiments will further illustrate the present invention in conjunction with the above-mentioned drawings. Specific Embodiments

[0046] To facilitate the understanding of the present invention, the present invention will be described more comprehensively below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present invention more thorough and comprehensive.

[0047] It should be noted that when an element is referred to as being "fixed on" another element, it can be directly on the other element or there may also be an intermediate element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intermediate element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs. The terms used herein in the description of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0049] Embodiment 1

[0050] Please refer to Figures 1 to 3 , the preparation method of the flip-chip light-emitting diode chip in the embodiment of the present invention includes:

[0051] S1, providing a substrate 10 required for growth, and sequentially depositing an N-type semiconductor layer 111, an active light-emitting layer 112, and a P-type semiconductor layer 113 on the substrate 10;

[0052] Furthermore, the substrate 10 can be a GaN substrate or an Al 2 O 3 substrate or a Si substrate.

[0053] S2. Prepare an N-type conductive via 114 on the P-type semiconductor layer 113;

[0054] Specifically, in this embodiment, the specific process for preparing the N-type conductive via 114 is as follows:

[0055] Coat photoresist on the surface of the P-type semiconductor layer 113, then use the exposure and development processes to remove part of the photoresist, exposing part of the P-type semiconductor layer. Then use inductively coupled plasma etching to remove the exposed P-type semiconductor layer and the active light-emitting layer below this part of the P-type semiconductor, forming the N-type conductive via 114. Then remove the photoresist.

[0056] S3. Prepare a current spreading layer 12 on the P-type semiconductor layer 113 and the N-type conductive via 114;

[0057] Specifically, in this embodiment, the specific process for preparing the current spreading layer 12 is as follows:

[0058] Deposit indium tin oxide on the surfaces of the P-type semiconductor layer 113 and the N-type conductive via 114 by magnetron sputtering. Then coat photoresist on the indium tin oxide surface, and then use exposure and development to remove part of the photoresist, exposing part of the indium tin oxide. Then use indium tin oxide etchant to remove the exposed indium tin oxide, and then remove the photoresist to form the current spreading layer 12.

[0059] S4. Prepare an isolation groove 115 on the N-type conductive via 114 and the current spreading layer 12;

[0060] Specifically, in this embodiment, the specific process for preparing the isolation groove 115 is as follows:

[0061] Coat photoresist on the surfaces of the N-type conductive via 114 and the current spreading layer 12, then use exposure and development to remove part of the photoresist, exposing the N-type conductive vias around. Then use ICP etching to remove the exposed N-type conductive vias to form the isolation groove 115, and then remove the photoresist.

[0062] S5. Prepare a first semiconductor layer on the P-type semiconductor layer 113, the N-type conductive via 114, the current spreading layer 12, and the isolation groove 115;

[0063] Furthermore, the first semiconductor layer includes a first insulating layer 13, a Bragg reflector 14, a Bragg reflector via hole, a first insulating layer via hole, a metal reflector 15, a second insulating layer 16, a second insulating layer via hole, and a metal connection layer, which are sequentially arranged on the P-type semiconductor layer 113.

[0064] Further, the specific process for preparing the first insulating layer 13 is as follows:

[0065] Deposit SiO on the surfaces of the P-type semiconductor layer 113, the N-type conductive via 114, the current spreading layer 12, and the isolation groove 115 by using PECVD process 2 as the first insulating layer, wherein the thickness of the first insulating layer is greater than 5000 Å.

[0066] Further, the specific process for preparing the Bragg reflection layer 14 and the Bragg reflection layer via holes is as follows:

[0067] Evaporate 2 - 10 groups of TiO 2 and SiO 2 stacked layers on the surface of the first insulating layer 13 as the Bragg reflection layer 14. Then, coat photoresist on the surface of the Bragg reflection layer 14, and then use exposure and development to remove the photoresist on top of part of the Bragg reflection layer. Then, use inductively coupled plasma etching process to remove the exposed Bragg reflection layer to form the Bragg reflection layer via holes, and then remove the photoresist;

[0068] Among them, the Bragg reflection layer via holes include N-type Bragg reflection layer via holes 141 and P-type Bragg reflection layer via holes 142.

[0069] Further, the specific process for preparing the first insulating layer via holes is as follows:

[0070] Coat photoresist on the surfaces of the Bragg reflection layer 14 and the Bragg reflection layer via holes, and then use exposure and development to remove the photoresist inside part of the Bragg reflection layer via holes, exposing the first insulating layer below the Bragg reflection layer via holes. Then, use BOE etching solution to remove the exposed first insulating layer to form the first insulating layer via holes, and then remove the photoresist;

[0071] Among them, the first insulating layer via holes include N-type first insulating layer via holes 131 and P-type first insulating layer via holes 132.

[0072] Further, the specific process for preparing the metal reflection layer 15 is as follows:

[0073] Coat negative photoresist on the P-type first insulating layer via holes 132, the P-type Bragg reflection layer via holes 142, and the Bragg reflection layer 14, and then use exposure and development to remove part of the photoresist. Then, use electron beam evaporation process to evaporate Ag metal, Ni metal, Ti metal, Ni metal, and Ti metal in sequence as the metal reflection layer 15. Then, use lift-off process to remove the metal layer on top of the photoresist, and then remove the photoresist.

[0074] Furthermore, the specific process for preparing the second insulating layer 16 and the through hole of the second insulating layer is:

[0075] Al2O is deposited on the metal reflective layer 15 and the area not covered by the metal reflective layer 15 by using the ALD process. 3 , then deposited Al2O 3 SiO is deposited by PECVD process. 2 , as the second insulating layer 16, then coating the second insulating layer 16 with photoresist, then exposing and developing to remove part of the photoresist, exposing the second insulating layer under the part of the photoresist, then removing the exposed second insulating layer by inductively coupled plasma etching process, forming the second insulating layer through hole, and then removing the photoresist;

[0076] The second insulating layer through holes include an N-type second insulating layer through hole 161 and a P-type second insulating layer through hole 162 .

[0077] Furthermore, the specific process for preparing the metal connection layer is:

[0078] A negative photoresist is coated on the surface of the second insulating layer 16 and the through hole of the second insulating layer, and then a part of the photoresist is removed by exposure and development, and then Cr metal, Al metal, Ti metal, Cu metal, Ti metal, Ni metal, Ti metal, Ni metal and Ti metal are sequentially evaporated by electron beam evaporation process as the metal connection layer;

[0079] The metal connection layer includes an N-type metal connection layer 171 and a P-type metal connection layer 172 .

[0080] S6, preparing a third insulating layer 18 on the first semiconductor layer;

[0081] Furthermore, the specific process for preparing the third insulating layer 18 is as follows:

[0082] A layer of AlN film is deposited on the metal connection layer and the area not covered by the metal connection layer by using a CVD process to serve as the third insulating layer 18 .

[0083] S7, forming a heat-conducting metal layer 19 on the third insulating layer 18, and then forming an N-type heat-conducting metal layer through hole 191 and a P-type heat-conducting metal layer through hole 192 on the heat-conducting metal layer 19;

[0084] Specifically in this embodiment, the specific process for preparing the thermally conductive metal layer 19 is:

[0085] Apply negative photoresist on the surface of the third insulating layer 18, then expose and develop to remove part of the photoresist, and then deposit a layer of Cu metal by electron beam evaporation as the heat-conducting metal layer 19.

[0086] Among them, the thickness of the heat-conducting metal layer 19 is between 2000 Å and 20000 Å, and the area of the heat-conducting metal layer 19 is larger than the area of the N-type semiconductor layer 111;

[0087] Specifically in this embodiment, the specific process for preparing the N-type heat-conducting metal layer through hole 191 and the P-type heat-conducting metal layer through hole 192 is as follows:

[0088] Apply photoresist on the surface of the heat-conducting metal layer 19, then expose and develop to remove part of the photoresist, expose the heat-conducting metal layer under this part of the photoresist, and then use inductively coupled plasma etching process to remove the exposed heat-conducting metal layer to form the N-type heat-conducting metal layer through hole 191 and the P-type heat-conducting metal layer through hole 192, and then remove the photoresist.

[0089] S8, prepare a fourth insulating layer 20 on the heat-conducting metal layer 19, the N-type heat-conducting metal layer through hole 191 and the P-type heat-conducting metal layer through hole 192, and then prepare an N-type fourth insulating layer through hole 201, a P-type fourth insulating layer through hole 202 and a fourth insulating layer connection through hole 203 arranged between the N-type fourth insulating layer through hole 201 and the P-type fourth insulating layer through hole 202 on the fourth insulating layer 20;

[0090] Specifically in this embodiment, the specific process for preparing the fourth insulating layer is as follows:

[0091] Deposit an ALN thin film on the heat-conducting metal layer 19, the N-type heat-conducting metal layer through hole 191 and the P-type heat-conducting metal layer through hole 192 by CVD process as the fourth insulating layer 20.

[0092] Specifically in this embodiment, the specific process for preparing the N-type fourth insulating layer through hole 201, the P-type fourth insulating layer through hole 202 and the fourth insulating layer connection through hole 203 is as follows:

[0093] Apply photoresist on the surface of the fourth insulating layer 20, then expose and develop to remove part of the photoresist, expose the fourth insulating layer under this part of the photoresist, and then use inductively coupled plasma etching process to remove the exposed fourth insulating layer, and then remove the remaining photoresist to form the N-type fourth insulating layer through hole 201, the P-type fourth insulating layer through hole 202 and the fourth insulating layer connection through hole 203 arranged between the N-type fourth insulating layer through hole 201 and the P-type fourth insulating layer through hole 202.

[0094] S9. Prepare a pad layer on the fourth insulating layer 20, the N-type fourth insulating layer through hole 201, the P-type fourth insulating layer through hole 202, and the fourth insulating layer connection through hole 203. The pad layer includes an N-type pad 211, a P-type pad 212, and a heat-conducting pad 213 located between the P-type pad 212 and the N-type pad 211.

[0095] Specifically in this embodiment, the specific process for preparing the pad layer is as follows:

[0096] Coat a negative photoresist on the surfaces of the fourth insulating layer 20, the N-type fourth insulating layer through hole 201, the P-type fourth insulating layer through hole 202, and the fourth insulating layer connection through hole 203. Then, expose and develop to remove part of the photoresist. Then, use the electron beam evaporation process to sequentially evaporate Ti metal, Ni metal, Ti metal, Ni metal, and AuSn metal. Then, use the blue film stripping process to remove part of the metal to form the pad layer.

[0097] Among them, the fourth insulating layer connection through hole 203 is used to connect the heat-conducting pad 213 and the heat-conducting metal layer 19. The area of the fourth insulating layer connection through hole 203 is larger than the area of the heat-conducting pad 213. The area of the heat-conducting pad 213 is larger than the sum of the areas of the N-type pad 211 and the P-type pad 212, and the area of the heat-conducting pad 213 is larger than half of the area of the heat-conducting metal layer 19.

[0098] Specifically in this embodiment, the area of the heat-conducting pad 213 is 70% of the area of the heat-conducting metal layer 19, and the area of the heat-conducting pad 213 is six times the sum of the areas of the N-type pad 211 and the P-type pad 212.

[0099] S10. Use the eutectic soldering process to solder the semi-finished product after completing step S9 on the bracket 22.

[0100] Among them, the area of the bracket 22 is larger than that of the semi-finished product. A heat-dissipating pad 221 and a heat-dissipating metal 222 are provided on the bracket 22. The heat-conducting pad 213 is connected to the heat-dissipating pad 221, and the heat-dissipating pad 221 is connected to the heat-dissipating metal 222.

[0101] It can be understood that by depositing an ALN thin film as the third insulating layer 18 on the metal connection layer and the places not covered by the metal connection layer using the CVD process, by preparing a heat-conducting metal layer with an area larger than that of the N-type semiconductor layer on the third insulating layer, and by depositing an ALN thin film on the heat-conducting metal layer 19, the N-type heat-conducting metal layer through-hole 191 and the P-type heat-conducting metal layer through-hole 192 using the CVD process as the fourth insulating layer 20, so that the third insulating layer 18, the fourth insulating layer 20 and the heat-conducting metal layer 19 disposed between the third insulating layer 18 and the fourth insulating layer 20 together form a heat sink structure, and then the heat of the flip-chip light-emitting diode chip is evenly distributed on this heat sink structure; by setting the area of the heat-conducting pad 213 to be larger than the sum of the areas of the N-type pad 211 and the P-type pad 212, and the area of the heat-conducting pad 213 is larger than half of the area of the heat-conducting metal layer 19, thereby increasing the area of the heat-conducting pad 213. The larger its area, the better the heat-conducting effect, and the lower the working temperature of the flip-chip light-emitting diode chip; by welding the semi-finished product after completing step S9 on the bracket 22, so that part of the heat of the flip-chip light-emitting diode chip can be transferred from the heat-conducting metal layer 19 through the heat-conducting pad 213 to the bracket 22 with an area larger than the chip area and then to the heat-dissipating metal 222 of the bracket 22. Such a setting can further reduce the working temperature of the flip-chip light-emitting diode chip, reduce the thermal resistance of the flip-chip light-emitting diode chip, and increase the service life of the flip-chip light-emitting diode chip.

[0102] Please refer to Figure 3 , which shows a cross-sectional schematic diagram of the flip-chip light-emitting diode chip prepared by the preparation method of the flip-chip light-emitting diode chip in the embodiment of the present invention.

[0103] Embodiment 2

[0104] A flip-chip light-emitting diode chip, which is different from the flip-chip light-emitting diode chip prepared in Embodiment 1 in that:

[0105] Specifically in this embodiment, the specific process for preparing the heat-conducting metal layer is:

[0106] Coat a negative photoresist on the surface of the third insulating layer, then expose and develop to remove part of the photoresist, and then deposit a layer of AL metal as the heat-conducting metal layer using the electron beam evaporation process.

[0107] Embodiment 3

[0108] A flip-chip light-emitting diode chip, which is different from the flip-chip light-emitting diode chip prepared in Embodiment 1 in that:

[0109] Specifically in this embodiment, the area of the heat-conducting pad is 52% of the area of the heat-conducting metal layer, and the area of the heat-conducting pad is twice the sum of the areas of the N-type pad and the P-type pad.

[0110] Comparative Example 1

[0111] A flip-chip light-emitting diode chip, which is different from the flip-chip light-emitting diode chip prepared in Example 1 in that:

[0112] The flip-chip light-emitting diode chip in Comparative Example 1 does not include the third insulating layer, the heat-conducting metal layer, and the heat-conducting pad.

[0113] Specifically in this comparative example, the specific process for preparing the fourth insulating layer is as follows:

[0114] Deposit a layer of SiO 2 thin film by CVD process on the metal connection layer and the places not covered by the metal connection layer as the third insulating layer.

[0115] Based on the flip-chip light-emitting diode chips prepared in the above-mentioned Example 1, Example 2, and Example 3 and the flip-chip light-emitting diode chip in Comparative Example 1, a rapid deterioration test is carried out on the flip-chip light-emitting diode chips prepared in Example 1, Example 2, and Example 3 and the flip-chip light-emitting diode chip in Comparative Example 1. First, the chips are encapsulated on the bracket, and then placed in a closed space at 150 °C, and the chips are powered on, and the current passed is 1.5 times the rated working current of the chips. Thereafter, the chip brightness is measured every 12 hours, and the chip brightness attenuation is recorded (the brightness before the start of the deterioration test is 100%, until the brightness is lower than 90%). The longer the time, the better the heat conduction ability of the chip. The corresponding test results are shown in the following table:

[0116] It should be noted that the area of the chips in this test is 1300um * 1300um.

[0117]

[0118] In summary, for the flip-chip light-emitting diode chip and its manufacturing method in the above embodiments of the present invention, a third insulating layer is prepared on the first semiconductor layer, a heat-conducting metal layer with an area larger than that of the N-type semiconductor layer is prepared on the third insulating layer, and a fourth insulating layer is prepared on the heat-conducting metal layer, the N-type heat-conducting metal layer through hole, and the P-type heat-conducting metal layer through hole, so that the third insulating layer, the fourth insulating layer, and the heat-conducting metal layer disposed between the third insulating layer and the fourth insulating layer together form a heat sink structure, and then the heat of the flip-chip light-emitting diode chip is evenly distributed on this heat sink structure; by setting the area of the heat-conducting pad to be larger than the sum of the areas of the N-type pad and the P-type pad, and the area of the heat-conducting pad is larger than half of the area of the heat-conducting metal layer, thereby increasing the area of the heat-conducting pad, the larger its area, the better the heat-conducting effect, and the lower the operating temperature of the flip-chip light-emitting diode chip; by welding the semi-finished product after completing step S9 on the bracket, so that part of the heat of the flip-chip light-emitting diode chip can be transferred from the heat-conducting metal layer through the heat-conducting pad to the bracket with an area larger than the chip area and then to the heat-dissipating metal of the bracket. Such a setting can further reduce the operating temperature of the flip-chip light-emitting diode chip, reduce the thermal resistance of the flip-chip light-emitting diode chip, and increase the service life of the flip-chip light-emitting diode chip.

[0119] In the description of this specification, the descriptions referring to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0120] The above-described embodiments merely represent several implementation manners of the present invention. The descriptions are relatively specific and detailed, but should not be construed as limiting the scope of the patent of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention should be subject to the appended claims.

Claims

1. A method for preparing a flip-chip light-emitting diode chip, characterized in that: The preparation method comprises: S1, providing a substrate required for growth, and sequentially depositing an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer on the substrate; S2, preparing an N-type conductive through hole on the P-type semiconductor; S3, preparing a current spreading layer on the P-type semiconductor layer and the N-type conductive through hole; S4, preparing an isolation groove on the N-type conductive through hole and the current spreading layer; S5, preparing a first semiconductor layer on the P-type semiconductor layer, the N-type conductive via, the current spreading layer and the isolation trench; S6, preparing a third insulating layer on the first semiconductor layer; S7, preparing a thermally conductive metal layer on the third insulating layer, and then preparing an N-type thermally conductive metal layer through hole and a P-type thermally conductive metal layer through hole on the thermally conductive metal layer; Wherein, the thickness of the thermally conductive metal layer is between 2000Å and 20000Å, and the area of ​​the thermally conductive metal layer is larger than the area of ​​the N-type semiconductor layer; S8, preparing a fourth insulating layer on the thermally conductive metal layer, the N-type thermally conductive metal layer through hole, and the P-type thermally conductive metal layer through hole, and then preparing an N-type fourth insulating layer through hole, a P-type fourth insulating layer through hole, and a fourth insulating layer connecting through hole disposed between the N-type fourth insulating layer through hole and the P-type fourth insulating layer through hole on the fourth insulating layer; S9, preparing a pad layer on the fourth insulating layer, the N-type fourth insulating layer through hole, the P-type fourth insulating layer through hole, and the fourth insulating layer connecting through hole, the pad layer comprising an N-type pad, a P-type pad, and a thermally conductive pad located between the P-type pad and the N-type pad; The fourth insulating layer connecting through hole is used to connect the thermally conductive pad and the thermally conductive metal layer, the area of ​​the fourth insulating layer connecting through hole is larger than the area of ​​the thermally conductive pad, the area of ​​the thermally conductive pad is larger than the sum of the areas of the N-type pad and the P-type pad, and the area of ​​the thermally conductive pad is larger than half the area of ​​the thermally conductive metal layer; S10, welding the semi-finished product after step S9 onto the bracket using a eutectic welding process; The support has an area larger than that of the semi-finished product, a heat dissipation pad and a heat dissipation metal are arranged on the support, the thermal conductive pad is connected to the heat dissipation pad, and the heat dissipation pad is connected to the heat dissipation metal.

2. The method for preparing a flip-chip light-emitting diode chip according to claim 1, characterized in that: The first semiconductor layer includes a first insulating layer, a Bragg reflection layer, a Bragg reflection layer through hole, a first insulating layer through hole, a metal reflection layer, a second insulating layer, a second insulating layer through hole, and a metal connection layer which are sequentially arranged on the P-type semiconductor layer.

3. The method for preparing a flip-chip light emitting diode chip according to claim 2, characterized in that: The specific process for preparing the first insulating layer is: SiO2 is deposited as a first insulating layer on the surface of the P-type semiconductor layer, the N-type conductive via, the current spreading layer and the isolation groove using a PECVD process, wherein the thickness of the first insulating layer is greater than 5000Å.

4. The method for preparing a flip-chip light emitting diode chip according to claim 3, characterized in that: The specific process of preparing the Bragg reflection layer and the Bragg reflection layer through hole is as follows: 2-10 groups of TiO2 and SiO2 stacks are deposited on the surface of the first insulating layer by electron beam evaporation process as a Bragg reflection layer, then photoresist is coated on the surface of the Bragg reflection layer, and then the photoresist on a part of the Bragg reflection layer is removed by exposure and development, and then the exposed Bragg reflection layer is removed by inductively coupled plasma etching process to form a Bragg reflection layer through hole, and then the photoresist is removed; Wherein, the Bragg reflection layer through hole includes an N-type Bragg reflection layer through hole and a P-type Bragg reflection layer through hole.

5. The method for preparing a flip-chip light emitting diode chip according to claim 3, characterized in that: The specific process of preparing the first insulating layer through hole is: Applying photoresist on the surface of the Bragg reflective layer and the through hole of the Bragg reflective layer, then removing part of the photoresist in the through hole of the Bragg reflective layer by exposure and development to expose the first insulating layer under the through hole of the Bragg reflective layer, then removing the exposed first insulating layer by BOE etching solution to form the through hole of the first insulating layer, and then removing the photoresist; The first insulating layer through-holes include N-type first insulating layer through-holes and P-type first insulating layer through-holes.

6. The method for preparing a flip-chip light emitting diode chip according to claim 5, characterized in that: The specific process for preparing the metal reflective layer is: A negative photoresist is coated on the P-type first insulating layer through hole, the P-type Bragg reflective layer through hole and the Bragg reflective layer, and then part of the photoresist is removed by exposure and development, and then Ag metal, Ni metal, Ti metal, Ni metal and Ti metal are sequentially evaporated by electron beam evaporation process as the metal reflective layer, and then the metal layer located above the photoresist is removed by lift-off process, and then the photoresist is removed.

7. The method for preparing a flip-chip light emitting diode chip according to claim 6, characterized in that: The specific process of preparing the second insulating layer and the through hole of the second insulating layer is: Depositing Al2O3 on the metal reflective layer and the area not covered by the metal reflective layer by using an ALD process, then depositing SiO2 on the deposited Al2O3 by using a PECVD process as the second insulating layer, then coating the surface of the second insulating layer with a photoresist, then removing part of the photoresist by exposing and developing, exposing the second insulating layer under the part of the photoresist, then removing the exposed second insulating layer by using an inductively coupled plasma etching process, forming a through hole in the second insulating layer, and then removing the photoresist; The second insulating layer through-holes include N-type second insulating layer through-holes and P-type second insulating layer through-holes.

8. The method for preparing a flip-chip light emitting diode chip according to claim 7, characterized in that: The specific process for preparing the metal connection layer is: A negative photoresist is coated on the second insulating layer and the surface of the through hole of the second insulating layer, and then a part of the photoresist is removed by exposure and development, and then Cr metal, Al metal, Ti metal, Cu metal, Ti metal, Ni metal, Ti metal, Ni metal and Ti metal are sequentially evaporated by an electron beam evaporation process as the metal connection layer; Wherein, the metal connection layer includes an N-type metal connection layer and a P-type metal connection layer.

9. The method for preparing a flip-chip light emitting diode chip according to claim 8, characterized in that: The specific process for preparing the third insulating layer is: A layer of AlN film is deposited on the metal connection layer and the area not covered by the metal connection layer by using a CVD process to serve as the third insulating layer.

10. A flip-chip light emitting diode chip, characterized in that: The flip-chip light-emitting diode chip is prepared by the method for preparing the flip-chip light-emitting diode chip according to any one of claims 1 to 9.

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