Pixel circuit, display panel and display device

Abstract

The present disclosure relates to a pixel circuit, a display panel and a display device. The pixel circuit comprises a driving transistor T1, a double-gate transistor T3 comprising a first transistor T3-2 and a second transistor T3-1, the first transistor T3-2 and the second transistor T3-1 being electrically connected between the gate and the drain of the driving transistor T1, and an adjusting unit X connected to a first node A between the first transistor T3-2 and the second transistor T3-1, for writing an adjusting signal to the first node A to adjust the potential of the first node A. The pixel circuit provided by the present disclosure can adjust the potential of the first node A in the light-emitting stage, so as to reduce the leakage current of the double-gate transistor T3 caused by the large voltage difference, further stabilize the gate potential of the driving transistor T1, and make the display brightness of the display panel where the pixel circuit is located more uniform.

Description

Technical Field

[0001] This disclosure relates to the field of screen display, and more particularly to a pixel circuit, display panel, and display device. Background Technology

[0002] With the rapid development of technology, Active Matrix Organic Light Emitting Diode (AMOLED), as a current-driven light-emitting device, is increasingly being used in the field of high-performance displays due to its characteristics such as self-emission, fast response, wide viewing angle, and ability to be fabricated on flexible substrates.

[0003] AMOLED display panels include multiple pixel circuits arranged in a matrix. Each pixel circuit contains multiple transistors, which work together to drive the light-emitting elements to emit light.

[0004] However, when the display panel is displayed at low frequency, there is a leakage current problem in the transistor connected between the gate and drain of the driving transistor in the pixel circuit. This causes fluctuations in the gate potential of the driving transistor during the light-emitting stage, resulting in unstable driving current transmitted by the pixel circuit, causing uneven brightness of the display panel and affecting the display effect. Summary of the Invention

[0005] To overcome the problems existing in related technologies, this disclosure provides a pixel circuit, a display panel, and a display device. The pixel circuit proposed in this disclosure enables the adjustment of the potential of the first node during the light-emitting stage, thereby reducing leakage current in the dual-gate transistor caused by large voltage differences, further stabilizing the gate potential of the driving transistor, and making the display panel containing the pixel circuit exhibit more uniform display brightness.

[0006] This disclosure provides a pixel circuit, including:

[0007] Drive transistors;

[0008] A dual-gate transistor includes a first transistor and a second transistor, wherein the first transistor and the second transistor are electrically connected between the gate and the drain of the driving transistor;

[0009] An adjustment unit, connected to a first node between the first transistor and the second transistor, is used to write an adjustment signal to the first node to adjust the potential of the first node.

[0010] In some embodiments, the adjustment unit includes:

[0011] The third transistor is connected to the first node;

[0012] When the third transistor is turned on, the third transistor outputs the adjustment signal.

[0013] In some embodiments, the pixel circuit further includes: an adjustment voltage terminal and a first scan signal terminal;

[0014] The gate of the third transistor is connected to the first scan signal terminal, the source of the third transistor is connected to the adjustment voltage terminal, and the drain of the third transistor is connected to the first node.

[0015] Specifically, when the first pulse signal is output at the first scan signal terminal, the third transistor is turned on;

[0016] When the second pulse signal is output at the first scan signal terminal, the third transistor is turned off, and the level of the first pulse signal is less than the level of the second pulse signal.

[0017] In some embodiments, the voltage adjustment terminal is connected to an AC signal source;

[0018] When the first scanning signal terminal switches to outputting the first pulse signal, the third transistor outputs a high-level AC signal.

[0019] Before the first scanning signal terminal switches from outputting the first pulse signal to outputting the second pulse signal, the third transistor switches to outputting a low-level AC signal.

[0020] In some embodiments, the source of the first transistor is connected to the drain of the driving transistor, the drain of the first transistor is connected to the source of the second transistor, and the drain of the second transistor is connected to the gate of the driving transistor.

[0021] The first node is located between the drain of the first transistor and the source of the second transistor.

[0022] In some embodiments, the pixel circuit further includes a fourth transistor;

[0023] The fourth transistor is connected at a second node between the gate of the second transistor and the gate of the driving transistor;

[0024] When the fourth transistor is turned on, the drain of the fourth transistor outputs a first reset signal and writes the first reset signal into the second node.

[0025] In some embodiments, the fourth transistor and the adjustment unit are connected to the same AC signal source;

[0026] When the fourth transistor is turned on, the first reset signal and the adjustment signal are the same low-level signal.

[0027] In some embodiments, the pixel circuit further includes: a light-emitting element and a fifth transistor;

[0028] The anode of the light-emitting element is connected to a third node between the drain of the dual-gate transistor and the drain of the driving transistor;

[0029] The drain of the fifth transistor is connected between the third node and the anode of the light-emitting element;

[0030] When the fifth transistor is turned on, the drain of the fifth transistor outputs a second reset signal and writes the second reset signal into the anode of the light-emitting element.

[0031] In some embodiments, the pixel circuit further includes: a driving signal source, a sixth transistor, and a seventh transistor;

[0032] The sixth transistor is connected between the driving signal source and the source of the driving transistor;

[0033] The seventh transistor is connected between the fifth transistor and the third node;

[0034] The sixth transistor, the seventh transistor, and the adjustment unit are all connected to the first scan signal terminal of the pixel circuit;

[0035] When the driving transistor, the sixth transistor, and the seventh transistor are all turned on, the driving signal output by the driving signal source is input to the light-emitting element through the sixth transistor, the driving transistor, and the seventh transistor to drive the light-emitting element to emit light.

[0036] In some embodiments, the pixel circuit further includes: a data signal terminal, an eighth transistor, a second scan signal terminal, and a capacitor element;

[0037] The source of the eighth transistor is connected to the data signal terminal, and the drain of the eighth transistor is connected to the source of the driving transistor.

[0038] The gate of the eighth transistor, the gate of the first transistor, and the gate of the second transistor are all connected to the second scan signal terminal;

[0039] The capacitor element is connected to a second node between the gate of the second transistor and the gate of the driving transistor;

[0040] When the driving transistor, the first transistor, and the second transistor are all turned on, the data signal output from the data signal terminal is written to the capacitor element through the driving transistor, the first transistor, and the second transistor in sequence.

[0041] This disclosure also provides a display panel including the pixel circuit proposed in the above embodiments.

[0042] This disclosure also provides a display device, including the display panel proposed in the above embodiments.

[0043] The technical solutions provided by the embodiments of this disclosure may include the following beneficial effects:

[0044] The pixel circuit proposed in this embodiment includes a driving transistor, a dual-gate transistor, and an adjustment unit. The adjustment unit is disposed at a first node between the first transistor and the second transistor in the dual-gate transistor. Thus, when the pixel circuit is operating in the light-emitting stage, the potential of the first node can be adjusted by adjusting the signal to reduce the voltage difference between the two electrodes of the first transistor and the two electrodes of the second transistor. This further reduces the leakage current of the dual-gate transistor caused by the large voltage difference, thereby stabilizing the gate potential of the driving transistor, improving the stability of the driving current in the pixel circuit, making the display brightness of the display panel where the pixel circuit is located more uniform, and improving the display effect of the display panel.

[0045] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0046] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0047] Figure 1 This is a simplified structural diagram of a pixel circuit according to an exemplary embodiment;

[0048] Figure 2 This is a schematic diagram of the pixel circuit structure according to an exemplary embodiment. Figure 1 ;

[0049] Figure 3 This is a schematic diagram of the structure of an adjustment unit according to an exemplary embodiment;

[0050] Figure 4 This is a schematic diagram of the pixel circuit structure according to an exemplary embodiment. Figure 2 ;

[0051] Figure 5 This is a driving timing diagram of a pixel circuit according to an exemplary embodiment;

[0052] Figure 6 This is a schematic diagram of a conventional pixel circuit according to an exemplary embodiment;

[0053] Figure 7 This is a driving timing diagram of a conventional pixel circuit according to an exemplary embodiment;

[0054] Figure 8 This is a schematic diagram of the leakage path of a conventional pixel circuit according to an exemplary embodiment.

[0055] Figure 9 This is a structural block diagram of a display device according to an exemplary embodiment. Detailed Implementation

[0056] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0057] See Figure 1 , Figure 1 This is a simplified structural diagram of a pixel circuit according to an exemplary embodiment; as shown below. Figure 1 As shown, the pixel circuit of the display panel includes: a data writing unit a, a threshold compensation unit b, a reset unit c, and a light-emitting unit d. It also includes a driving transistor T1 and a capacitor C0. Here, when the pixel circuit is in the light-emitting stage, the brightness of the light-emitting unit d is determined by the magnitude of the driving current flowing to the light-emitting unit d. However, when the power supply to the pixel circuit is a constant voltage power supply, the gate potential of the driving transistor T1 affects the magnitude of the driving current.

[0058] In some actual light-emitting processes of pixel circuits, such as when the display panel is displaying low-frequency images, due to the long duration t of the low-frequency display, according to the charge formula CV=It, under the condition that the leakage current in the transistor in the threshold compensation unit b is the same, the gate potential V of the driving transistor T1 increases, which further aggravates the leakage current problem of the transistor in the threshold compensation unit b and affects the magnitude of the driving current, thereby causing the low-frequency flickering problem of the display panel.

[0059] To overcome the low-frequency flicker problem of the display panel mentioned above, embodiments of this disclosure provide a pixel circuit. See also... Figure 2 , Figure 2 This is a schematic diagram of the pixel circuit structure according to an exemplary embodiment. Figure 1 ;like Figure 2 As shown, the pixel circuit proposed in this disclosure includes at least:

[0060] Drive transistor T1;

[0061] The dual-gate transistor T3 includes a first transistor T3-2 and a second transistor T3-1, which are electrically connected between the gate and drain of the driving transistor T1.

[0062] The adjustment unit X is connected to the first node A between the first transistor T3-2 and the second transistor T3-1, and is used to write the adjustment signal to the first node A to adjust the potential of the first node A.

[0063] Here, the pixel circuit proposed in this disclosure can be applied in a display panel, for example, it can be applied in an organic light-emitting diode (OLED) display panel, where the OLED display panel includes a passive matrix organic light-emitting diode (PMOLED) display panel and an AMOLED display panel.

[0064] AMOLED display panels can be applied in the low-frequency display field. Currently, AMOLED display panels use a pixel design composed of hybrid transistors of low-temperature polycrystalline silicon (LTPS) and indium zinc oxide (IZO). LTPS is fabricated using PMOS transistor technology, and IZO is fabricated using NMOS transistor technology. Taking an AMOLED display panel as an example, the AMOLED display panel includes multiple pixel circuits as proposed in the embodiments of this disclosure. Pixel circuits are semiconductor-based circuits composed of multiple transistors arranged in a matrix on a plane. Each pixel circuit is used to realize the light emission display of one or more pixels. Here, when the pixel circuit is in the light-emitting stage, the adjustment unit proposed in this disclosure can adjust the potential of the first node through an adjustment signal to reduce the leakage current of the dual-gate transistor located in the threshold compensation unit due to the excessive voltage difference between the gate of the driving transistor and the anode of the light-emitting element, further stabilizing the gate potential of the driving transistor and making the display panel containing the pixel circuit more uniform in brightness.

[0065] In this disclosure, the driving transistor T1, the first transistor T3-2, and the second transistor T3-1 can all be field-effect transistors or other devices with the same characteristics. Depending on their function in the circuit, the driving transistor T1, the first transistor T3-2, and the second transistor T3-1 used in the embodiments of this disclosure can all be thin film transistors (TFTs) or metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0066] Taking the driving transistor T1, the first transistor T3-2, and the second transistor T3-1 as examples, all of which are MOSFETs (hereinafter referred to as MOS transistors), a MOS transistor has three electrodes, namely the gate (G), the drain (D), and the source (S). MOS transistors include P-channel MOS transistors (hereinafter referred to as PMOS transistors) and N-channel MOS transistors (hereinafter referred to as NMOS transistors). The driving transistor T1, the first transistor T3-2, and the second transistor T3-1 proposed in the embodiments of this disclosure can all be PMOS transistors or NMOS transistors, or they can be partially PMOS transistors and partially NMOS transistors. This disclosure does not limit them in this way.

[0067] Optionally, the driving transistor T1, the first transistor T3-2, and the second transistor T3-1 are all PMOS transistors.

[0068] It should be noted that the POMS transistor conducts when the gate potential is low (corresponding to a small gate-source voltage Vgs) and is cut off when the gate potential is high (corresponding to a large gate-source voltage Vgs). The NOMS transistor conducts when the gate potential is high (corresponding to a large gate-source voltage Vgs) and is cut off when the gate potential is low (corresponding to a small gate-source voltage Vgs).

[0069] For example, in combination Figure 2 The pixel circuit shown has a source of driving transistor T1 connected to data writing unit a; the gate and drain of driving transistor T1 are connected to the first transistor T3-2 and the second transistor T3-1, respectively; in addition, the gate of driving transistor T1 is also connected to reset unit c, and the drain of driving transistor T1 is also connected to light-emitting unit d; driving transistor T1 is a POMS transistor, which is turned on when the gate potential is low and turned off when the gate potential is high. When displaying different pixel frames, the pixel circuit operates in the corresponding working process; here, a working process has multiple working stages. In different working stages, reset unit c can reset the potential of the gate of driving transistor T1, data writing unit a can write data signals into the capacitor element inside the pixel circuit through driving transistor T1, and light-emitting unit d can emit light under the action of driving transistor T1.

[0070] In some examples, the first transistor T3-2 and the second transistor T3-1 proposed in this disclosure are both PMOS transistors.

[0071] It should be noted that the first transistor T3-2 and the second transistor T3-1 can be transistors of the same specification or transistors of different specifications. The positions of the first transistor T3-2 and the second transistor T3-1 can be interchanged. For example, the first transistor T3-2 can be set at the position connected to the drain of the driving transistor T1 or at the position connected to the gate of the driving transistor T1. This disclosure does not impose further restrictions in this regard.

[0072] In some embodiments, the source of the first transistor T3-2 is connected to the drain of the driving transistor T1, the drain of the first transistor T3-2 is connected to the source of the second transistor T3-1, and the drain of the second transistor T3-1 is connected to the gate of the driving transistor T1; the first node A is located between the drain of the first transistor T3-2 and the source of the second transistor T3-1.

[0073] Here, the gate and drain of the first transistor T3-2 and the second transistor T3-1 are interconnected, which makes the dual-gate transistor T3 have higher input impedance and lower output impedance. The insulating layer between the first transistor T3-2 and the second transistor T3-1 can reduce current leakage, making the dual-gate transistor T3 have higher reliability and longer life.

[0074] In other examples, the first transistor T3-2 and the second transistor T3-1 can also be a PMOS transistor and an NMOS transistor, respectively; in this case, the source of the first transistor T3-2 is connected to the drain of the driving transistor T1, the drain of the first transistor T3-2 is connected to the drain of the second transistor T3-1, and the source of the second transistor T3-1 is connected to the gate of the driving transistor T1; the first node A is located between the drain of the first transistor T3-2 and the drain of the second transistor T3-1.

[0075] In other examples, both the first transistor T3-2 and the second transistor T3-1 are NMOS transistors. Because NMOS transistors have low leakage current, low-frequency displays can be further implemented.

[0076] In this embodiment of the disclosure, taking the first transistor T3-2 and the second transistor T3-1 both as PMOS transistors as an example, combined with... Figure 2In the illustrated pixel circuit, when the pixel circuit is operating in the light-emitting stage, there is a large voltage difference between the gate of the driving transistor T1 and the second node B and the light-emitting unit d between the second transistor T3-1 and the light-emitting unit d. Therefore, in this embodiment of the present disclosure, the adjustment unit X outputs an adjustment signal during the light-emitting stage. This adjustment signal can be a high-level potential signal at this time to increase the potential of the first node A. Thus, since the voltage difference between the second node B and the first node A is less than the original voltage difference between the second node B and the light-emitting unit d, the leakage current of the second transistor T3-1 is further reduced. Furthermore, the voltage difference between the first node A and the light-emitting unit d is also less than the original voltage difference between the first node A and the light-emitting unit d, further reducing the leakage current of the first transistor T3-2.

[0077] It should be noted that during the light-emitting stage of the pixel circuit, the adjustment signal output by the adjustment unit X can be a constant voltage signal or a dynamic signal, which is dynamically adjusted according to the potential of the second node B. At this time, the constant voltage signal or the dynamic signal is a high-level signal, and the potential written to the first node A is less than the potential of the second node B during the actual light-emitting stage.

[0078] It should also be noted that before the light emission stage of the current pixel frame is about to end and all working stages of the next pixel frame begin, the potential of the adjustment signal needs to be changed and the first node A needs to be reset to a low level. This will enable the dual-gate transistor T3 to conduct the data signal and realize the threshold compensation work of the driving transistor T1 in the working stage of the next pixel frame.

[0079] In this embodiment of the disclosure, the adjustment unit X may include a switching element, which is closed during the light-emitting stage, so that the adjustment signal can be written to the first node A through the adjustment unit, and the switching element is open during other working stages; the adjustment unit X may also include a variable electronic element (e.g., a transformer resistor, a transformer capacitor, etc.), which can adjust the output impedance during the light-emitting stage, and change the voltage of the output adjustment signal by the voltage division of the variable electronic element, so as to further adjust the potential written to the first node A.

[0080] The pixel circuit proposed in this embodiment includes a driving transistor, a dual-gate transistor, and an adjustment unit. The adjustment unit is disposed at a first node between the first transistor and the second transistor in the dual-gate transistor. Thus, when the pixel circuit is operating in the light-emitting stage, the potential of the first node can be adjusted by adjusting the signal to reduce the voltage difference between the two electrodes of the first transistor and the two electrodes of the second transistor. This further reduces the leakage current of the dual-gate transistor caused by the large voltage difference, thereby stabilizing the gate potential of the driving transistor, improving the stability of the driving current in the pixel circuit, making the display brightness of the display panel where the pixel circuit is located more uniform, and improving the display effect of the display panel.

[0081] In some embodiments, see Figure 3 , Figure 3 This is a schematic diagram of the structure of an adjustment unit according to an exemplary embodiment; as shown below. Figure 3 As shown, the adjustment unit proposed in this embodiment includes:

[0082] The third transistor T8 is connected to the first node A;

[0083] When the third transistor T8 is turned on, the third transistor T8 outputs an adjustment signal.

[0084] Here, the third transistor T8 can be a separate field-effect transistor, such as the PMOS or NMOS transistor described above in this disclosure, or a thin-film transistor (TFT); the third transistor T8 can also be a dual-gate insulated transistor, and this disclosure does not impose further limitations on it.

[0085] Here, taking the third transistor T8 as an example, which is a PMOS transistor, the third transistor T8 has a gate, a source, and a drain. When the gate potential of the third transistor T8 is low, the third transistor T8 is turned on, and outputs the adjustment signal, which is written between the first transistor T3-2 and the second transistor T3-1 in the dual-gate transistor T3. For example, the third transistor T8 is connected between the drain of the first transistor T3-2 and the source of the second transistor T3-1.

[0086] It should be noted that when the pixel circuit is operating in the light-emitting stage, the third transistor T8 is turned on. During the conduction of the third transistor T8, the first transistor T3-2 and the second transistor T3-1 are both in the off state, so that the adjustment signal only adjusts the potential of the first node A (in the above example, that is, adjusts the drain potential of the first transistor T3-2 and the source potential of the second transistor T3-1), and cannot further affect the source potential of the first transistor T3-2 and the drain potential of the second transistor T3-1 through the first transistor T3-2 and the second transistor T3-1.

[0087] This embodiment of the present disclosure provides a third transistor and utilizes the unidirectional conduction performance of the third transistor to write the adjustment signal between the first transistor and the second transistor during the light-emitting stage of the pixel circuit, thereby reducing leakage current caused by voltage difference between the first transistor and the second transistor and further stabilizing the gate potential of the driving transistor.

[0088] In some embodiments, combined with Figure 3 As shown, the pixel circuit also includes: a voltage adjustment terminal VI-1 and a first scan signal terminal EM;

[0089] The gate of the third transistor T8 is connected to the first scan signal terminal EM, the source of the third transistor T8 is connected to the adjustment voltage terminal VI-1, and the drain of the third transistor T8 is connected to the first node A.

[0090] Specifically, when the first pulse signal is output at the first scan signal terminal EM, the third transistor T8 is turned on;

[0091] When the second pulse signal is output at the first scan signal terminal EM, the third transistor T8 is turned off, and the level of the first pulse signal is lower than the level of the second pulse signal.

[0092] It should be noted that the voltage adjustment terminal VI-1 is connected to at least one signal source, which can output an adjustment signal. When the third transistor T8 is turned on, the adjustment signal can be written to the first node A through the third transistor T8.

[0093] In this embodiment of the disclosure, the voltage adjustment terminal VI-1 can be connected to one signal source or multiple signal sources. During the process of the pixel circuit working in the light emission stage, the magnitude of the adjustment signal can be adjusted to further adjust the potential change of the first node A.

[0094] Here, the third transistor T8 is a PMOS transistor. When the pixel circuit is operating in the light-emitting stage, the first scan signal terminal EM outputs a first pulse signal, which is a low-level signal. At this time, the gate-source voltage Vgs of the third transistor T8 is less than zero, and the third transistor T8 is turned on. The adjustment signal output from the adjustment voltage terminal VI-1 passes through the third transistor T8 and is written to the first node A. When the pixel circuit is operating in the reset stage, data writing stage, and threshold compensation stage, the first scan signal terminal EM outputs a second pulse signal, which is a high-level signal. At this time, the gate-source voltage Vgs of the third transistor T8 is greater than zero, and the third transistor T8 is turned off. The adjustment signal output from the adjustment voltage terminal VI-1 cannot pass through the third transistor T8.

[0095] In this way, by setting the first scanning signal terminal and the adjustment voltage terminal to work in coordination with the conduction characteristics of the third transistor, the adjustment unit can output the corresponding adjustment signal at the appropriate time point, thereby further improving the light emission effect of the pixel circuit.

[0096] In some embodiments, the voltage adjustment terminal VI-1 is connected to an AC signal source;

[0097] When the first scan signal terminal EM switches to output the first pulse signal, the third transistor T8 outputs a high-level AC signal.

[0098] Before the first scan signal terminal EM switches from outputting the first pulse signal to outputting the second pulse signal, the third transistor T8 switches to outputting a low-level AC signal.

[0099] Here, the voltage adjustment terminal VI-1 is connected to an AC signal source, which generates the adjustment signal. The AC signal source can switch the level of the adjustment signal at any time according to the working stage of the pixel circuit, for example, switching from a low-level signal to a high-level signal, or switching from a high-level signal to a low-level signal.

[0100] It should be noted that when the display panel displays images, it plays different frames sequentially; the pixel circuit completes a light-emitting process sequentially, so that the corresponding pixel of each frame emits light in each light-emitting process. Here, a light-emitting process includes the following stages: reset stage, data writing and threshold compensation stage, and light-emitting stage (including the early light-emitting stage and the late light-emitting stage).

[0101] The third transistor T8 disclosed herein is turned on throughout the entire light-emitting phase. During the early light-emitting phase, the first scan signal terminal EM switches from the second pulse signal to outputting the first pulse signal. At this time, the AC signal source generates a high-level AC signal, the third transistor T8 is turned on and outputs a high-level AC signal, setting the first node A to a high potential. During the later light-emitting phase, the AC signal source switches to generating a low-level AC signal. The third transistor T8 remains on and switches from outputting a high-level AC signal to outputting a low-level AC signal, setting the first node A to a low potential to complete the reset process for the first node A.

[0102] Here, at the end of the late-stage emission phase of the current frame and before the start of the reset phase of the next frame, the first scan signal terminal EM switches from outputting the first pulse signal to outputting the second pulse signal. At this time, the third transistor T8 is turned off, and the adjustment signal cannot be written into the first node A again. Here, because the potential of the first node A is low at the end of the late-stage emission phase of the current frame, the data writing and threshold compensation phases in the emission process of the next frame can proceed smoothly.

[0103] In this embodiment of the disclosure, the voltage adjustment terminal is connected to an AC signal source. The AC signal source can switch the level of the adjustment signal at any time according to the working stage of the pixel circuit, making the adjustment signal output by the adjustment unit more flexible. Compared with the combination of connecting two DC signal sources and switches respectively, it is more convenient and improves the working efficiency and flexibility of the pixel circuit.

[0104] In some embodiments, see Figure 4 , Figure 4 This is a schematic diagram of the pixel circuit structure according to an exemplary embodiment. Figure 2 ; combination Figure 4 As shown, the pixel circuit also includes a fourth transistor T5;

[0105] The fourth transistor T5 is connected to the second node B between the gates of the second transistor T3-1 and the driving transistor T1;

[0106] When the fourth transistor T5 is turned on, the drain of the fourth transistor T5 outputs a first reset signal and writes the first reset signal into the second node.

[0107] The pixel circuit proposed in this embodiment further includes: a third scan signal terminal G1 and a first reset voltage terminal VI-2; the gate of the fourth transistor T5 is connected to the third scan signal terminal G1, and the source of the fourth transistor T5 is connected to the first reset voltage terminal VI-2.

[0108] It should be noted that the fourth transistor T5 is set in Figure 2 In the reset unit c shown.

[0109] Here, the fourth transistor T5 is a PMOS transistor. The third scan signal terminal G1 can output either a third pulse signal or a fourth pulse signal, and the first reset voltage terminal VI-2 outputs a first reset signal. When the third scan signal transistor G1 outputs the third pulse signal, the fourth transistor T5 is turned on; when the third scan signal transistor G1 outputs the fourth pulse signal, the fourth transistor T5 is turned off. Here, the level of the third pulse signal is lower than the level of the fourth pulse signal.

[0110] Specifically, as described above in this disclosure, during a light-emitting process, the first stage is the reset phase. At this time, the first scan signal terminal EM outputs a second pulse signal, and the third transistor T8 is turned off. The third scan signal terminal G1 outputs a third pulse signal, which is a low-level signal. At this time, the gate-source voltage Vgs of the fourth transistor T5 is less than zero, and the fourth transistor T5 is turned on. The first reset signal output from the first reset voltage terminal VI-2 passes through the fourth transistor T5 and is written to the second node B. When the pixel circuit is operating in the data writing and threshold compensation phase, or the light-emitting phase, the third scan signal terminal G1 outputs a fourth pulse signal, which is a high-level signal. At this time, the gate-source voltage Vgs of the fourth transistor T5 is greater than zero, and the fourth transistor T5 is turned off. The first reset signal output from the first reset voltage terminal VI-2 cannot pass through the fourth transistor T5.

[0111] It should be noted that, in order to ensure data writing and threshold compensation during the light-emitting process, the first reset signal is a low-level signal during the reset phase when the fourth transistor T5 is turned on, so that the data signal can sequentially drive transistor T1, dual-gate transistor T3 and the capacitor element in the pixel circuit.

[0112] The embodiments of this disclosure provide a fourth transistor capable of performing a low-potential reset process on the gate of the driving transistor in the pixel circuit, so that the data signal in the pixel circuit can be normally written into the pixel circuit, ensuring the orderly progress of the light emission process.

[0113] In this embodiment of the disclosure, combined with Figure 4 The first reset voltage terminal VI-2 and the adjustment voltage terminal VI-1 can be connected to the same signal source or to different signal sources, and this disclosure does not impose any restrictions on this.

[0114] In some embodiments, the fourth transistor T5 and the regulating unit X are connected to the same AC signal source;

[0115] When the fourth transistor T5 is turned on, the first reset signal and the adjustment signal are the same low-level signal.

[0116] In this disclosure, the adjustment unit includes a third transistor T8, so the fourth transistor T5 and the third transistor T8 can be connected to the same AC signal source. Specifically, both the first reset voltage terminal and the adjustment voltage terminal are connected to the AC signal source.

[0117] Here, during the reset phase, the fourth transistor T5 is turned on, and the first reset signal is written to the second node B through T5 (that is, the gate potential of the driving transistor T1 is pulled low for reset). At this time, the third transistor T8 is turned off, and the adjustment signal is also a low-level signal, but it cannot be written to the first node A.

[0118] During the data writing and threshold compensation stage, the first scan signal terminal EM outputs the second pulse signal, the third scan signal terminal G1 outputs the fourth pulse signal, the fourth transistor T5 and the third transistor T8 are both cut off, the first reset signal is a low level signal, but cannot pass through the fourth transistor T5, the adjustment signal is also the same low level signal, but cannot pass through the third transistor T8;

[0119] During the light emission stage, the first scan signal terminal EM outputs the first pulse signal, the third scan signal terminal G1 outputs the fourth pulse signal, the fourth transistor T5 is cut off, the first reset signal is a high-level signal, but it cannot pass through the fourth transistor T5. At this time, the third transistor T8 is turned on, and the adjustment signal is also a high-level signal, which can be written to the first node through the third transistor T8.

[0120] This disclosure reduces the number of signal sources required by connecting the fourth transistor and the adjustment unit to the same AC signal source, simplifies circuit design, and increases the convenience of pixel circuit control.

[0121] In other embodiments, the fourth transistor T5 is connected to the first DC signal source, and the adjustment unit X is connected to the AC signal source.

[0122] Here, the first reset voltage terminal VI-2 is connected to the first DC signal source, and the adjustment voltage terminal VI-1 is connected to the AC signal source.

[0123] The first reset signal generated by the first DC signal source is a low-level DC signal. During the reset phase, the fourth transistor T5 is turned on, and the low-level DC signal is written to the second node through the fourth transistor T5. During the data writing and threshold compensation phase and the light emission phase, the fourth transistor T5 is turned off, and the low-level DC signal cannot pass through the fourth transistor T5.

[0124] In some embodiments, combined with Figure 4 As shown, the pixel circuit proposed in this embodiment further includes: a light-emitting element EL and a fifth transistor T4;

[0125] The anode of the light-emitting element EL is connected to the third node D between the drain of the dual-gate transistor T3 and the drive transistor T1;

[0126] The drain of the fifth transistor T4 is connected between the third node D and the anode of the light-emitting element EL;

[0127] When the fifth transistor T4 is turned on, the drain of the fifth transistor T4 outputs a second reset signal and writes the second reset signal into the anode of the light-emitting element EL.

[0128] Here, the light-emitting element (EL) can emit light during the light-emitting phase, achieving effective brightness display of the pixel frame.

[0129] The pixel circuit proposed in this disclosure also includes a second reset voltage terminal VI-3; the gate of the fifth transistor T4 is connected to the third scan signal terminal G1, and the source of the fifth transistor T4 is connected to the second reset voltage terminal VI-3.

[0130] It should be noted that the fifth transistor T4 and the light-emitting element EL are both located in... Figure 2 In the light-emitting unit d shown.

[0131] Here, the fifth transistor T4 is a PMOS transistor, and the second reset voltage terminal VI-3 outputs the second reset signal. When the third scan signal terminal G1 outputs the third pulse signal, the fifth transistor T4 is turned on; when the third scan signal terminal G1 outputs the fourth pulse signal, the fifth transistor T4 is turned off.

[0132] Specifically, referring to the above disclosure, during the reset phase of a light-emitting process, the first scan signal terminal EM outputs a second pulse signal, and the third transistor T8 is turned off; the second scan signal terminal G1 outputs a third pulse signal. At this time, the gate-source voltage Vgs of the fifth transistor T4 is less than zero, and the fifth transistor T4 is turned on. The second reset signal output by the second reset voltage terminal VI-3 passes through the fifth transistor T4 and is written to the fourth node C (the anode of the light-emitting element EL). When the pixel circuit is operating in the data writing and threshold compensation phase and the light-emitting phase, the second scan signal terminal G1 outputs a fourth pulse signal, which is a high-level signal. At this time, the gate-source voltage Vgs of the fifth transistor T4 is greater than zero, and the fifth transistor T4 is turned off. The second reset signal output by the second reset voltage terminal VI-3 cannot pass through the fifth transistor T4.

[0133] It should be noted that, in order to ensure data writing and threshold compensation during the light-emitting process, the second reset signal is a low-level signal during the reset phase when the fifth transistor T4 is turned on, so that the subsequent drive current can be input to the light-emitting element.

[0134] It should also be noted that the second reset voltage terminal VI-3 is connected to the second DC signal source, and the second reset signal generated by the second DC signal source is a low-level DC signal. In this disclosure, both the first reset signal and the second reset signal are low-level signals, but their voltage values ​​can be the same or different.

[0135] In some examples, when the pixel circuit is operating in the reset phase, the voltage value of the first reset signal written to the second node B is the same as the voltage value of the second reset signal written to the fourth node C. At this time, the gate potential of the driving transistor T1 and the anode potential of the light-emitting element EL are the same. In other examples, the voltage value of the first reset signal written to the second node B is less than the voltage value of the second reset signal written to the fourth node C. At this time, the gate potential of the driving transistor T1 is less than the anode potential of the light-emitting element EL.

[0136] Here, the pixel circuit also includes a ground terminal VSS, and the cathode of the light-emitting element EL is connected to the ground terminal VSS to ensure the potential balance of the pixel circuit.

[0137] The embodiments of this disclosure provide a fifth transistor capable of performing a low-potential reset process on the anode of the light-emitting element in the pixel circuit, so that the driving current in the pixel circuit can be input to the light-emitting element, ensuring the orderly progress of the light-emitting process.

[0138] In some embodiments, the pixel circuit further includes: a drive signal source VDD, a sixth transistor T6, and a seventh transistor T7;

[0139] The sixth transistor T6 is connected between the drive signal source VDD and the source of the drive transistor T1;

[0140] The seventh transistor T7 is connected between the fifth transistor T4 and the third node D;

[0141] The sixth transistor T6, the seventh transistor T7, and the adjustment unit are all connected to the first scan signal terminal EM of the pixel circuit;

[0142] When the driving transistor T1, the sixth transistor T6, and the seventh transistor T7 are all turned on, the driving signal output by the driving signal source VDD is sequentially input to the light-emitting element EL through the sixth transistor T6, the driving transistor T1, and the seventh transistor T7 to drive the light-emitting element EL to emit light.

[0143] Here, the driving signal source VDD is a constant voltage signal source in the pixel circuit, used to output a driving signal, which is used to control the brightness of the light-emitting element EL.

[0144] In this embodiment of the present disclosure, the gate of the sixth transistor T6 is connected to the first scan signal terminal EM, the source of the sixth transistor T6 is connected to the driving signal source VDD, and the drain of the sixth transistor T6 is connected to the source of the driving transistor T1; the gate of the seventh transistor T7 is connected to the first scan signal terminal EM, the source of the seventh transistor T7 is connected to the third node D, and the drain of the seventh transistor T7 is connected to the anode of the light-emitting element EL.

[0145] It should be noted that the seventh transistor T7 is set in Figure 2 In the light-emitting unit d shown.

[0146] Here, the sixth transistor and the seventh transistor T7 are both PMOS transistors. When the first scan signal terminal EM outputs the first pulse signal, the driving transistor T1, the sixth transistor T6, and the seventh transistor T7 are all turned on; when the first scan signal terminal EM outputs the second pulse signal, the sixth transistor T6 and the seventh transistor T7 are all turned off.

[0147] When the pixel circuit is operating in the light-emitting stage of a light-emitting process, the third scan signal terminal G1 outputs the fourth pulse signal, and the fourth transistor T5 and the fifth transistor T4 are both in the off state; the first scan signal terminal EM outputs the first pulse signal, which is a low-level signal. The gate-source voltage Vgs of the sixth transistor T6 is less than zero, and the gate-source voltage Vgs of the seventh transistor T7 is less than zero. At this time, the sixth transistor T6, the seventh transistor T7, and the driving transistor T1 are all turned on. The driving signal output by the driving signal source VDD is input to the light-emitting element EL through the sixth transistor T6, the driving transistor T1, and the seventh transistor T7 to drive the light-emitting element EL to emit light. When the pixel circuit is operating in the reset stage, data writing stage, and threshold compensation stage, when the first scan signal terminal EM outputs the second pulse signal, the gate-source voltage Vgs of the sixth transistor T6 is greater than zero, and the gate-source voltage of the seventh transistor T7 is greater than zero. The sixth transistor T6 and the seventh transistor T7 are both turned off, and the driving signal cannot pass through the sixth transistor T6 and the seventh transistor T7.

[0148] The embodiments disclosed herein enable the light-emitting elements of the pixel circuit to emit light during appropriate operating phases by configuring a sixth transistor, a seventh transistor, and a driving transistor to work together.

[0149] In some embodiments, the pixel circuit further includes: a data signal terminal SD, an eighth transistor T2, a second scan signal terminal G2, and a capacitor element C1;

[0150] The source of the eighth transistor T2 is connected to the data signal terminal SD, and the drain of the eighth transistor T2 is connected to the source of the driving transistor T1.

[0151] The gates of the eighth transistor T2, the first transistor T3-2, and the second transistor T3-1 are all connected to the second scan signal terminal G2;

[0152] Capacitor C1 is connected to the second node B between the gate of the second transistor T3-1 and the gate of the driving transistor T1;

[0153] When the driving transistor T1, the first transistor T3-2, and the second transistor T3-1 are all turned on, the data signal output from the data signal terminal SD is written to the capacitor element C1 through the driving transistor T1, the first transistor T3-2, and the second transistor T3-1 in sequence.

[0154] Here, the capacitor C1 can store charge, and the data signal in this disclosure can be written into the capacitor C1 to store charge, thus completing the charging process of the capacitor C1.

[0155] The data signal terminal SD is connected to the data signal source and is used to output the data signal generated by the data signal source. Here, the data signal source can be located in the control module of the display device, such as in the system-on-a-chip on the motherboard.

[0156] It should be noted that the eighth transistor T2 is set at... Figure 2 The data shown is written into unit a.

[0157] Here, the eighth transistor T2 is a PMOS transistor, and the first transistor T3-2 and the second transistor T3-1 are also PMOS transistors. The source of the first transistor T3-2 is connected to the drain of the driving transistor T1, the drain of the first transistor T3-2 is connected to the source of the second transistor T3-1, and the drain of the second transistor T3-1 is connected to the gate of the driving transistor T1. When the fifth pulse signal is output at the second scan signal terminal G2, the eighth transistor T2, the first transistor T3-2, and the second transistor T3-1 are turned on. When the sixth pulse signal is output at the second scan signal terminal G2, the eighth transistor T2, the first transistor T3-2, and the second transistor T3-1 are turned off. Here, the level of the fifth pulse signal is lower than the level of the sixth pulse signal.

[0158] Specifically, in conjunction with the above disclosure, during the data writing and threshold compensation stage of a light-emitting process, the third scan signal terminal G1 outputs a fourth pulse signal, and both the fourth transistor T5 and the fifth transistor T4 are cut off; the first scan signal terminal EM outputs a second pulse signal, and the third transistor T8, the sixth transistor T6, and the first transistor T7 are all cut off; at this time, the second scan signal terminal G2 outputs a fifth pulse signal, which is a low-level signal. At this time, the gate-source voltage Vgs corresponding to the eighth transistor T2, the first transistor T3-2, and the second transistor T3-1 are all less than zero, and both the eighth transistor T2, the first transistor T3-2, and the second transistor T3-1 are turned on. The data signal output from the data signal terminal SD passes through the source and drain of the eighth transistor T2 and the driving transistor T1, and the sixth transistor... T6 and the first transistor T7 are written to the second node B (i.e., the gate of the driving transistor) and compensate the threshold voltage Vth of the driving transistor T1, so that node B simultaneously has SD data information and threshold compensation information of the driving transistor T1, and simultaneously writes SD data information into capacitor C1 to charge capacitor C1; when the pixel circuit is working in the reset stage and the light emission stage, the second scan signal terminal G2 outputs the sixth pulse signal, which is a high-level signal. At this time, the gate-source voltage Vgs corresponding to the eighth transistor T2, the first transistor T3-2 and the second transistor T3-1 are all greater than zero, the eighth transistor T2, the first transistor T3-2 and the second transistor T3-1 are all cut off, and the data signal output by the data signal terminal SD cannot pass through the fourth transistor T5.

[0159] The embodiments disclosed herein provide a second transistor and a driving transistor, a dual-gate transistor working together to enable the data signal corresponding to the pixel circuit to be written into the capacitor element and to complete the threshold compensation of the driving transistor.

[0160] Based on the pixel circuit proposed in the above embodiments of this disclosure, the specific light-emitting process of the pixel circuit in the actual pixel frame display stage is described. See also Figure 5 , Figure 5 This is a driving timing diagram of a pixel circuit according to an exemplary embodiment; combined with Figure 5 As shown, the working stages of the pixel circuit include: the late emission stage (t1) corresponding to the previous pixel frame, the reset stage (t2) of the current pixel frame, the data writing and threshold compensation stage of the current pixel frame (t3), and the early emission stage (t4) of the current pixel frame.

[0161] First, it should be noted that the light emission process for each pixel frame is sequentially the reset stage, the data writing and threshold compensation stage, the pre-light emission stage, and the post-light emission stage. The driving timing diagram shown in this disclosure captures a portion of the working stages from the previous pixel frame and the current pixel frame.

[0162] Here, the pixel circuit proposed in the above embodiments of this disclosure and Figures 2 to 4 The pixel circuit shown illustrates... Figure 5 The operating status of each device in the pixel circuit during each working stage.

[0163] In the late-stage of illumination (t1 stage) corresponding to the previous pixel frame:

[0164] The first scan signal terminal EM outputs the first pulse signal and is in a low-voltage on state; at this time, the third transistor T8, the sixth transistor T6, and the seventh transistor T7 are all turned on.

[0165] The second scan signal terminal G2 outputs the sixth pulse signal and is in a high-voltage cutoff state; at this time, the eighth transistor T2, the first transistor T3-2, and the second transistor T3-1 are all cut off.

[0166] The third scan signal terminal G1 outputs the fourth pulse signal and is in a high-voltage cutoff state; at this time, the fifth transistor T4 and the fourth transistor T5 are both cut off.

[0167] Here, in the pre-emission stage corresponding to the previous pixel frame (i.e., before stage t1), the adjustment signal output by the adjustment voltage terminal VI-1 is a high-level AC signal. The first node A of the pixel circuit is at a relatively high potential, reducing the voltage difference between the second node B and the first node A. At this time, the leakage current of the second transistor T3-1 decreases, making the potential of the second node B relatively stable. In stage t1, the adjustment voltage terminal VI-1 switches from outputting an adjustment signal to outputting a low-level AC signal, and the first node A of the pixel circuit becomes low, performing a low-level reset process for the first node A. This prepares for subsequent data writing and threshold compensation operations.

[0168] During the reset phase (t2 phase) of the current pixel frame:

[0169] The first scan signal terminal EM outputs the second pulse signal and is in a high voltage cutoff state; at this time, the third transistor T8, the sixth transistor T6, and the seventh transistor T7 are all cut off.

[0170] The second scan signal terminal G2 outputs the sixth pulse signal and is in a high-voltage cutoff state; at this time, the eighth transistor T2, the first transistor T3-2, and the second transistor T3-1 are all cut off.

[0171] The third scan signal terminal G1 outputs the third pulse signal and is in a low-voltage on state; at this time, both the fifth transistor T4 and the fourth transistor T5 are turned on.

[0172] It should be noted that, from the end of the late emission stage (t1 stage) corresponding to the previous pixel frame to the start of the reset stage (t2 stage) of the current pixel frame, the first scanning signal terminal EM switches from outputting the first pulse signal to outputting the second pulse signal.

[0173] Here, the first reset voltage terminal VI-2 outputs a first reset signal, which is a low-level signal. The first reset signal is pulled low to reset the second node B through the fourth transistor T5. The second reset voltage terminal VI-3 outputs a second reset signal, which is a low-level signal. The second reset signal is pulled low to reset the fourth node C through the fifth transistor T4.

[0174] During the data writing and threshold compensation phase of the current pixel frame (phase t3):

[0175] The first scan signal terminal EM outputs the second pulse signal and is in a high voltage cutoff state; at this time, the third transistor T8, the sixth transistor T6, and the seventh transistor T7 are all cut off.

[0176] The second scan signal terminal G2 outputs the fifth pulse signal and is in a low-voltage turn-on state; at this time, the eighth transistor T2, the first transistor T3-2, and the second transistor T3-1 are all turned on.

[0177] The third scan signal terminal G1 outputs the fourth pulse signal and is in a high-voltage cutoff state; at this time, the fifth transistor T4 and the fourth transistor T5 are both cut off.

[0178] It should be noted that, after the reset phase (t2 phase) of the current pixel frame ends and before the data writing and threshold compensation phase (t3 phase) of the current pixel frame begins, the third scan signal terminal G1 switches from outputting the third pulse signal to outputting the fourth pulse signal.

[0179] Here, the data signal output from the data signal terminal SD passes through the source and drain of the eighth transistor T2 and the driving transistor T1, the sixth transistor T6 and the first transistor T7, and is written to the second node B (i.e., the gate of the driving transistor T1). The threshold voltage Vth of the driving transistor T1 is compensated, so that node B simultaneously has SD data information and threshold compensation information of the driving transistor T1. At the same time, the SD data information is written into the capacitor element C1 to charge the capacitor element C1.

[0180] In the early emission stage (t4 stage) of the current pixel frame:

[0181] The first scan signal terminal EM outputs the first pulse signal and is in a low-voltage on state; at this time, the third transistor T8, the sixth transistor T6, and the seventh transistor T7 are all turned on.

[0182] The second scan signal terminal G2 outputs the sixth pulse signal and is in a high-voltage cutoff state; at this time, the eighth transistor T2, the first transistor T3-2, and the second transistor T3-1 are all cut off.

[0183] The third scan signal terminal G1 outputs the fourth pulse signal and is in a high-voltage cutoff state; at this time, the fifth transistor T4 and the fourth transistor T5 are both cut off.

[0184] It should be noted that after the data writing and threshold compensation stage (t3 stage) of the current pixel frame ends and before the pre-luminescence stage (t4 stage) of the current pixel frame begins, the output of the fifth pulse signal of the second scan signal terminal G2 switches to the output of the sixth pulse signal. In addition, the adjustment signal output of the adjustment voltage terminal VI-1 switches from a low-level AC signal to a high-level AC signal, so that the first node A of the pixel circuit is at a relatively high potential in the pre-luminescence stage (t4 stage) of the current pixel frame.

[0185] Here, the drive signal output from the drive signal source VDD is input to the light-emitting element EL through the sixth transistor T6, the drive transistor T1, and the seventh transistor T7, forming a current loop from VDD-T6-T1-T7-EL-VSS to drive the light-emitting element EL to emit light. Here, the gate potential of the drive transistor T1 (the potential of the second node B) affects the magnitude of the drive current and determines the brightness of the light-emitting element.

[0186] With the pixel circuit proposed in this disclosure, when the pixel circuit displays a low grayscale image, the first node A is at a high potential corresponding to the adjustment voltage terminal VI-1. The voltage difference between this potential and the second node B is small, less than... Figure 1 The pixel circuit shown reduces the leakage current of the second transistor T3-1 by adjusting the gate potential of the driving transistor T1 and the voltage difference between the light-emitting unit d. Simultaneously, the voltage difference between the first node A and the fourth node C is also less than the original voltage difference between the first node A and the light-emitting unit d, further reducing the leakage current of the first transistor T3-2. Furthermore, the leakage path of the first transistor T3-2 is node C-T7-T3-2-T8-VI-1, reducing its impact on the second node B and stabilizing the potential of the second node B. Therefore, the adjustment unit in the pixel circuit proposed in this disclosure can stabilize the potential of the second node B during the early stage of light emission, improving the stability of the driving current in the pixel circuit. This results in more uniform brightness on the display panel where the pixel circuit is located, improves low-grayscale flickering, enhances the display effect of the display panel, and makes it more suitable for use in ultra-low frequency display devices.

[0187] See Figure 6 , Figure 7 and Figure 8 , Figure 6 This is a schematic diagram of a conventional pixel circuit according to an exemplary embodiment; Figure 7 This is a driving timing diagram of a conventional pixel circuit according to an exemplary embodiment; Figure 8 This is a schematic diagram of the leakage path of a conventional pixel circuit according to an exemplary embodiment.

[0188] like Figure 6 As shown, the traditional pixel circuit is a 7T1C pixel compensation circuit, a high-precision, low-power memory circuit. Each memory cell consists of seven MOSFETs (here, a dual-gate transistor is understood as one transistor, and the same applies below) and one capacitor (capacitor element C0). Combined with... Figure 6 and Figure 7In a traditional pixel circuit, the traditional data input terminal SD-0, the first traditional scan signal terminal EM-0, the second traditional scan signal input terminal G2-0, and the third traditional scan signal input terminal G1-0 input corresponding signals at different operating stages to control the conduction or cutoff of each transistor; the traditional reset voltage terminal VI-0 outputs a reset signal at the corresponding operating stage to control the reset of the corresponding node in the pixel circuit. The working process of a traditional pixel circuit can include the following stages:

[0189] Reset phase (t1′ phase): The third traditional scan signal input terminal G1-0 is in a low-voltage on state. Under the action of the third traditional scan signal input terminal G1-0, transistors T4 and T5 are turned on. The traditional reset voltage terminal VI-0 outputs a low-level DC signal and writes it to the second node B and the fourth node C, resetting the capacitor C0 and the anode EL of the light-emitting element.

[0190] Data writing and threshold compensation stage (t2′ stage): The second conventional scan signal input terminal G2 is in the low-voltage turn-on stage. Under the action of the second conventional scan signal input terminal G2-0, transistors T2 and T3 are turned on; thus, the data signal is written to node B sequentially through transistors T2, T1, and T3, charging capacitor C0. At this time, the gate and drain of transistor T1 are connected, forming a diode configuration. The gate potential of transistor T1 contains the threshold voltage signal of transistor T1, performing threshold voltage compensation.

[0191] Light-emitting stage (t3′ stage): The first conventional scan signal terminal EM-0 is in a low-voltage on-state. Under the action of the first conventional scan signal terminal EM-0, transistors T6 and T7 are turned on, forming a light-emitting current in the VDD-T6-T1-T7-EL-VSS loop. The magnitude of the light-emitting current is determined by the gate potential of transistor T1. This light-emitting stage continues until the t1 stage of the next frame, thereby realizing the light-emitting display of the display panel.

[0192] Combination Figure 8 When a low grayscale image is displayed on the display panel containing the pixel circuit, because the potential of the second node B is greater than the potential of the third node C, and the voltage difference is large, leakage current is generated in the dual-gate transistor T3 (including T3-2 and T3-1). The leakage current path caused by the leakage current of the dual-gate transistor T3 is: second node B-T3-1-A-T3-2-T7-fourth node C-EL-VSS, that is... Figure 8 The leakage path I_1 is shown. When a high grayscale image is displayed on the display panel where the pixel circuit is located, the potential of the fourth node C is higher than that of the first node A. The leakage path caused by the leakage of the dual-gate transistor T3 is the fourth node C-T7-T3-2-A-T3-1-B, that is... Figure 8The leakage path I_2 is shown. In the above situation, the leakage action of the leakage path I_1 increases the current flowing through the light-emitting element EL, making the light-emitting element EL bright; the path I_2 increases the potential of the second node B, making the drive current output by the transistor T1 lower, and thus reducing the brightness of the light-emitting element EL; all of the above situations cause the problem of unstable light emission brightness of the light-emitting element EL.

[0193] To alleviate leakage current issues and reduce flickering in traditional pixel compensation circuits, this disclosure proposes an 8T1C pixel compensation circuit, which adds a third transistor T8. Combined with... Figure 4 The pixel circuit structure diagram shown, and Figure 5 The driving timing diagram shown indicates that the 8T1C pixel compensation circuit proposed in this disclosure includes a third transistor T8, which can output an adjustment signal. Compared with the traditional pixel compensation circuit, the light emission stage in this disclosure includes an early stage and a late stage. In the early stage, the adjustment signal is a high-level signal, which raises the potential of the first node A. In the late stage, the adjustment signal is a low-level signal, which lowers the potential of the first node A, thus resetting it.

[0194] Thus, when the display panel containing the pixel circuit displays a low grayscale image, the first node A is at a high potential corresponding to the adjustment voltage terminal VI-1. The voltage difference between this potential and the second node B is small, less than... Figure 1 The pixel circuit shown illustrates the voltage difference between the gate potential of driving transistor T1 and the voltage difference between the light-emitting unit d, which reduces the leakage current of the second transistor T3-1. Simultaneously, the voltage difference between the first node A and the fourth node C is also less than the original voltage difference between the first node A and the light-emitting unit d, further reducing the leakage current of the first transistor T3-2. Meanwhile, the leakage path of the first transistor T3-2 is node C-T7-T3-2-T8-VI-1, reducing its impact on the second node B and stabilizing the potential of the second node B. When the pixel circuit displays a high grayscale image, the leakage path of the first transistor T3-2 is node C-T7-T3-2-T8-VI-1, further reducing its impact on the second node B. Therefore, the pixel circuit proposed in this disclosure can effectively adjust the potential of the first node through the third transistor and the adjustment signal, reduce the voltage difference between the source and drain of the first transistor and the voltage difference between the source and drain of the second transistor when the pixel circuit is working in the light-emitting stage, so as to further reduce the leakage current of the dual-gate transistor due to the large voltage difference, thereby stabilizing the gate potential of the driving transistor, improving the stability of the driving current in the pixel circuit, making the display brightness of the display panel where the pixel circuit is located more uniform, improving the low grayscale flicker problem, improving the display effect of the display panel, and making it more suitable for use in ultra-low frequency display devices.

[0195] It should be noted that the driving transistor and the first to eighth transistors in the above embodiments of this disclosure are all PMOS transistors for discussion. In some other examples, the driving transistor and the first to eighth transistors can all be NMOS transistors, or some can be PMOS transistors and some can be NMOS transistors. Since PMOS transistors are turned on when the gate is at a low potential and NMOS transistors are turned on when the gate is at a high potential, this disclosure only needs to ensure that the conduction state of the driving transistor and the first to eighth transistors is the same as in the example described above, and that the signals output by the adjustment voltage terminal, the first reset voltage signal terminal and the second reset voltage signal terminal are the same as in the example described above. The pulse signals output by the corresponding first scan signal terminal EM, the second scan signal terminal G2, and the third scan signal segment G1 can be adjusted accordingly, or other scan signal terminals can be connected. This disclosure will not elaborate further on this.

[0196] This disclosure also provides a display panel including the pixel circuit proposed in the above embodiments.

[0197] Here, the display panel includes organic light-emitting diode (OLED) display panels, which include passive matrix organic light-emitting diode (PMOLED) display panels and AMOLED display panels.

[0198] In this disclosure, the display panel includes multiple pixel circuits, each pixel circuit being used to individually control the brightness display of one or more pixels. Here, each pixel circuit includes at least multiple functional elements proposed in the above embodiments of this disclosure. The multiple functional elements include at least driving transistors, dual-gate transistors, adjustment units, third transistors, fourth transistors, fifth transistors, sixth transistors, seventh transistors, eighth transistors, light-emitting elements, capacitor elements, and other devices.

[0199] By using the pixel circuit proposed in this disclosure, when pixel light emission display is performed in the display panel, the potential of the first node in the middle of the dual gate transistor can be adjusted during the light emission stage to reduce the leakage current of the dual gate transistor caused by the large voltage difference, further stabilizing the gate potential of the driving transistor, and making the display brightness of the display panel more uniform.

[0200] This disclosure also provides a display device, including the display panel proposed in the above embodiments.

[0201] Here, the display device includes an electronic device with display function, including but not limited to a computer, a mobile terminal, and a portable electronic device. The mobile terminal includes but is not limited to a mobile phone and a tablet computer; the portable electronic device includes but is not limited to a smartwatch. Here, the embodiments of this disclosure do not further limit the type of display device.

[0202] In this disclosure, the display device includes a display panel, a motherboard, a battery, etc. The battery is used to provide power to the display panel, and a system-on-a-chip is provided on the motherboard. The system-on-a-chip is connected to the display panel and is used to control the pixel display on the display panel.

[0203] Figure 9 This is a structural block diagram illustrating a display device according to an exemplary embodiment. For example, the display device 900 may be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0204] Reference Figure 9 The display device 900 may include one or more of the following components: a processing component 902, a memory 904, a power supply component 906, a multimedia component 908, an audio component 910, an input / output (I / O) interface 912, a sensor component 914, and a communication component 916.

[0205] Processing component 902 typically controls the overall operation of display device 900, such as operations associated with display, telephone calls, data communication, camera operation, and recording. Processing component 902 may include one or more processors 920 to execute instructions to perform all or part of the steps of the methods described above. Furthermore, processing component 902 may include one or more modules to facilitate interaction between processing component 902 and other components. For example, processing component 902 may include a multimedia module to facilitate interaction between multimedia component 908 and processing component 902.

[0206] Memory 904 is configured to store various types of data to support the operation of display device 900. Examples of this data include instructions for any application or method operating on display device 900, contact data, phonebook data, messages, pictures, videos, etc. Memory 904 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0207] Power supply component 906 provides power to various components of display device 900. Power supply component 906 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to display device 900.

[0208] Multimedia component 908 includes a screen that provides an output interface between the display device 900 and the user. The pixel circuitry proposed in this disclosure is applied to the screen. In some embodiments, the screen may include an OLED display panel, such as an AMOLED display panel, or a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen can be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors can sense not only the boundaries of the touch or swipe action but also the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 908 includes a front-facing camera and / or a rear-facing camera. When the display device 900 is in an operating mode, such as a shooting mode or a video mode, the front-facing camera and / or the rear-facing camera can receive external multimedia data. Each front-facing camera and rear-facing camera can be a fixed optical lens system or have focal length and optical zoom capabilities.

[0209] Audio component 910 is configured to output and / or input audio signals. For example, audio component 910 includes a microphone (MIC) configured to receive external audio signals when display device 900 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 904 or transmitted via communication component 916. In some embodiments, audio component 910 also includes a speaker for outputting audio signals.

[0210] I / O interface 912 provides an interface between processing component 902 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0211] Sensor assembly 914 includes one or more sensors for providing status assessments of various aspects of display device 900. For example, sensor assembly 914 may detect the on / off state of display device 900, the relative positioning of components such as the display and keypad of display device 900, changes in position of display device 900 or a component of display device 900, the presence or absence of user contact with display device 900, orientation or acceleration / deceleration of display device 900, and temperature changes of display device 900. Sensor assembly 914 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 914 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 914 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0212] Communication component 916 is configured to facilitate wired or wireless communication between display device 900 and other devices. Device 900 can access wireless networks based on communication standards, such as WiFi, 2G, or 3G, or combinations thereof. In one exemplary embodiment, communication component 916 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 916 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0213] In an exemplary embodiment, the display device 900 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components.

[0214] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 904 including instructions that can be executed by a processor 920 of a display device 900. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, or optical data storage device, etc.

[0215] The pixel circuit proposed in this disclosure is applied in the display panel of a display device. It can adjust the potential of the first node A during the light-emitting stage to reduce leakage current caused by the large voltage difference of the dual-gate transistor, further stabilize the gate potential of the driving transistor, and make the display brightness of the display panel where the pixel circuit is located more uniform.

[0216] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0217] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A pixel circuit, characterized in that, include: Drive transistors; A dual-gate transistor includes a first transistor and a second transistor, the first transistor and the second transistor being electrically connected between the gate and drain of the driving transistor, and both being in the off state when the pixel circuit is operating in the light-emitting stage; An adjustment unit, connected to a first node between the first transistor and the second transistor, is used to write an adjustment signal to the first node to adjust the potential of the first node; The voltage adjustment terminal is connected to an AC signal source to output the adjustment signal; The adjustment unit includes: a third transistor, the source of which is connected to the adjustment voltage terminal, and the drain of which is connected to the first node; During the early stage of light emission in the light emission stage, the AC signal source generates a high-level AC signal, the third transistor is turned on, and the high-level AC signal is output to write the first node as a high potential. When entering the later stage of the light emission stage, the AC signal source switches to generate a low-level AC signal, the third transistor turns on, and outputs the low-level AC signal to write the first node to a low potential.

2. The pixel circuit according to claim 1, characterized in that, The pixel circuit further includes: a first scanning signal terminal; The gate of the third transistor is connected to the first scan signal terminal; Specifically, when the first pulse signal is output at the first scan signal terminal, the third transistor is turned on; When the second pulse signal is output at the first scan signal terminal, the third transistor is turned off, and the level of the first pulse signal is less than the level of the second pulse signal.

3. The pixel circuit according to claim 2, characterized in that, When the first scan signal terminal switches to outputting the first pulse signal, the third transistor outputs the high-level AC signal; Before the first scanning signal terminal switches from outputting the first pulse signal to outputting the second pulse signal, the third transistor switches to outputting the low-level AC signal.

4. The pixel circuit according to claim 1, characterized in that, The source of the first transistor is connected to the drain of the driving transistor, the drain of the first transistor is connected to the source of the second transistor, and the drain of the second transistor is connected to the gate of the driving transistor. The first node is located between the drain of the first transistor and the source of the second transistor.

5. The pixel circuit according to any one of claims 1 to 4, characterized in that, The pixel circuit also includes a fourth transistor; The fourth transistor is connected at a second node between the gate of the second transistor and the gate of the driving transistor; When the fourth transistor is turned on, the drain of the fourth transistor outputs a first reset signal and writes the first reset signal into the second node.

6. The pixel circuit according to claim 5, characterized in that, The fourth transistor and the adjustment unit are connected to the same AC signal source; When the fourth transistor is turned on, the first reset signal and the adjustment signal are the same low-level signal.

7. The pixel circuit according to any one of claims 1 to 4, characterized in that, The pixel circuit also includes: a light-emitting element and a fifth transistor; The anode of the light-emitting element is connected to a third node between the drain of the dual-gate transistor and the drain of the driving transistor; The drain of the fifth transistor is connected between the third node and the anode of the light-emitting element; When the fifth transistor is turned on, the drain of the fifth transistor outputs a second reset signal and writes the second reset signal into the anode of the light-emitting element.

8. The pixel circuit according to claim 7, characterized in that, The pixel circuit also includes: a driving signal source, a sixth transistor, and a seventh transistor; The sixth transistor is connected between the driving signal source and the source of the driving transistor; The seventh transistor is connected between the fifth transistor and the third node; The sixth transistor, the seventh transistor, and the adjustment unit are all connected to the first scan signal terminal of the pixel circuit; When the driving transistor, the sixth transistor, and the seventh transistor are all turned on, the driving signal output by the driving signal source is input to the light-emitting element through the sixth transistor, the driving transistor, and the seventh transistor to drive the light-emitting element to emit light.

9. The pixel circuit according to any one of claims 1 to 4, characterized in that, The pixel circuit also includes: a data signal terminal, an eighth transistor, a second scan signal terminal, and a capacitor element; The source of the eighth transistor is connected to the data signal terminal, and the drain of the eighth transistor is connected to the source of the driving transistor. The gate of the eighth transistor, the gate of the first transistor, and the gate of the second transistor are all connected to the second scan signal terminal; The capacitor element is connected to a second node between the gate of the second transistor and the gate of the driving transistor; When the driving transistor, the first transistor, and the second transistor are all turned on, the data signal output from the data signal terminal is written to the capacitor element through the driving transistor, the first transistor, and the second transistor in sequence.

10. A display panel, characterized in that, Includes the pixel circuit as described in any one of claims 1 to 9.

11. A display device, characterized in that, Includes the display panel as described in claim 10.

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