Insulated gate MIS HEMT device, preparation method, chip and electronic device

Abstract

The present application discloses an insulated gate MIS HEMT device, a preparation method, a chip and an electronic device, wherein the device structure comprises: a substrate layer, a nucleation layer, a transition layer, a buffer layer, a channel layer, an insertion layer, a barrier layer and a C-doped C:GaN insulating layer sequentially located on the substrate layer; a metal layer located on the insulating layer; an isolation structure located on the side wall of the HEMT device, wherein the isolation structure penetrates the barrier layer, the insertion layer and the channel layer, and is located on the buffer layer; a passivation layer located on the upper surface of the metal layer and the barrier layer, and the side wall of the insulating layer and the metal layer; a gate located in the gate opening area, and penetrates the passivation layer to the upper surface of the metal layer; a source and a drain, respectively located on different sides of the gate, wherein the source and the drain penetrate the passivation layer, the barrier layer, the insertion layer and part of the channel layer. The present application provides a C:GaN insulating layer and a high-resistance buffer layer, so that the device has a relatively positive threshold voltage, reduces the gate leakage of the device, and improves the gate withstand voltage characteristics of the device.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to an insulated gate MIS HEMT device, a preparation method, a chip and an electronic device. Background Art

[0002] High electron mobility transistor (HEMT) has great prospects in power converter and power switch applications due to its many advantages such as high switching speed efficiency and high current density.

[0003] At present, a large number of HEMT devices have been studied and prepared in the prior art. In particular, compared with traditional Schottky structure HEMT devices, HEMT devices with metal-insulator-semiconductor (MIS) gate structure have higher gate withstand voltage and lower gate leakage, effectively improving the gate voltage swing.

[0004] Insulated gate MIS HEMT devices are often used in cascode systems. To ensure the reliability of the gate of the HEMT device, a thicker dielectric layer is generally used under the gate of the depletion-mode HEMT device. The depletion-mode device has a more negative threshold voltage. In order to match it, the MIS enhancement-mode HEMT device needs to have a higher withstand voltage. The higher withstand voltage of the traditional MIS enhancement-mode HEMT device often leads to excessively high on-resistance and power consumption of the entire system. Summary of the invention

[0005] The purpose of the present application is to provide an insulated gate MIS HEMT device, a preparation method, a chip and an electronic device to solve the problem in the related art that when the gate of a conventional insulated gate MIS HEMT device improves the withstand voltage characteristics, the on-resistance and power consumption of the entire system will be too high.

[0006] In order to achieve the above objectives, this application provides the following technical solutions:

[0007] In a first aspect, the present application provides an insulated gate MIS HEMT device, comprising:

[0008] A substrate layer, a nucleation layer, a transition layer, a buffer layer, a channel layer, an insertion layer and a barrier layer sequentially disposed on the substrate layer; an insulating layer, disposed on the barrier layer, wherein the material of the insulating layer is: C-doped C:GaN; a metal layer, disposed on the insulating layer; an isolation structure, disposed on the side wall of the HEMT device, wherein the isolation structure penetrates the barrier layer, the insertion layer and the channel layer, and is disposed on the buffer layer; a passivation layer, disposed on the upper surface of the metal layer and the upper surface of the barrier layer, the side wall of the insulating layer and the side wall of the metal layer; a gate, disposed on the gate opening region, and penetrating the passivation layer to the upper surface of the metal layer; a source electrode, disposed on one side of the gate electrode, wherein the source electrode penetrates the passivation layer, the barrier layer, the insertion layer and a part of the channel layer; a drain electrode, disposed on the other side of the gate electrode, wherein the drain electrode penetrates the barrier layer, the insertion layer and a part of the channel layer.

[0009] Furthermore, the thickness of the nucleation layer is in the range of 20 nm-500 nm, and the material of the nucleation layer includes: at least one of AlGaN and AlN; the thickness of the transition layer is in the range of 300 nm-400 nm, and the material of the transition layer includes: at least one of AlN, AlGaN and GaN; the thickness of the buffer layer is in the range of 1200 nm-6000 nm, and the material of the buffer layer includes: C-doped high-resistance GaN; the thickness of the channel layer is in the range of 200 nm-300 nm, and the material of the channel layer includes: unintentionally doped GaN; the thickness of the insertion layer is in the range of 0.5 nm-2 nm, and the material of the insertion layer includes: AlN; the thickness of the barrier layer is in the range of 10 nm-50 nm, and the Al component in the material of the barrier layer is 10%-30%.

[0010] Furthermore, the thickness of the insulating layer is in the range of 50 nm to 90 nm, and the C element doping concentration in the insulating layer is 10 18 cm -3 -10 20 cm -3 .

[0011] Furthermore, the thickness of the metal layer is in the range of 5 nm-300 nm, and the material of the metal layer includes: at least one of TiN, Cu and Al.

[0012] Furthermore, the thickness of the passivation layer ranges from 50 nm to 400 nm, and the materials of the passivation layer include: SiO2, SiN x , AlON and Al2O3.

[0013] Furthermore, the isolation structure includes: any one of a mesa isolation structure and an ion implantation structure.

[0014] In a second aspect, the present application also provides a method for preparing an insulated gate MIS HEMT device, comprising:

[0015] providing a substrate layer;

[0016] A nucleation layer, a transition layer, a buffer layer, a channel layer, an insertion layer, a barrier layer and an insulating layer are sequentially grown on the substrate layer, wherein the material of the insulating layer is: C-doped C:GaN;

[0017] Depositing a thin layer of metal on the upper surface of the insulating layer to form a metal layer;

[0018] forming an isolation structure on the upper surface of the metal layer and outside the active region of the HEMT device, wherein the isolation structure penetrates the metal layer, the insulating layer, the barrier layer, the insertion layer and the channel layer;

[0019] forming a gate region on the upper surface of the metal layer, and etching the metal layer and the insulating layer outside the gate region to a depth reaching the upper surface of the barrier layer;

[0020] Depositing a dielectric material on the upper surface of the barrier layer, the upper surface of the metal layer, the sidewall of the metal layer and the sidewall of the insulating layer to form a passivation layer;

[0021] Forming a gate opening region on the upper surface of the passivation layer in the gate region, etching away the dielectric layer in the gate opening region until reaching the upper surface of the metal layer, and depositing a metal material in the gate opening region to form a gate;

[0022] A source region and a drain region are respectively formed on the upper surface of the passivation layer, and the passivation layers of the source region and the drain region are etched, and the etching depth includes: the passivation layer, the barrier layer, the insertion layer and a part of the channel layer, to form a source etching region and a drain etching region, and metal materials are deposited in the source etching region and the drain etching region to form a source and a drain.

[0023] Furthermore, the step of sequentially growing a nucleation layer, a transition layer, a buffer layer, a channel layer, an insertion layer, a barrier layer and a C-doped insulating layer on the substrate layer comprises:

[0024] A metal organic chemical vapor deposition process is adopted to sequentially grow a nucleation layer, a transition layer, a buffer layer, a channel layer, an insertion layer, a barrier layer and a C-doped insulating layer on the substrate layer.

[0025] Furthermore, depositing a thin layer of metal on the upper surface of the insulating layer to form a metal layer includes:

[0026] A metal material is deposited on the upper surface of the insulating layer by a physical vapor deposition process to form a metal layer.

[0027] In a third aspect, the present application further provides a chip, wherein the chip comprises: an insulated gate MIS HEMT device as described in any one of the above.

[0028] In a fourth aspect, the present application also provides an electronic device, which includes: the chip as described above.

[0029] The present application provides an insulated gate MIS HEMT device, a preparation method, a chip, and an electronic device, which have the following beneficial effects:

[0030] 1. The present application provides a method for preparing an insulated gate MIS HEMT device, which comprises epitaxially growing a C:GaN insulating layer on a channel layer using a metal organic chemical vapor deposition process (MOCVD), and etching the C:GaN insulating layer using a selective self-stop etching technique to form a gate dielectric layer under the insulated gate MIS HEMT device. The preparation method effectively reduces the gate leakage of the insulated gate MIS HEMT device and improves the gate withstand voltage;

[0031] 2. The present application provides a C:GaN insulating layer and a carbon-doped high-resistance GaN buffer layer, and can realize a HEMT with a relatively positive threshold voltage by regulating the thickness of the C:GaN layer and the doping concentration of the C element. The conductivity of the GaN buffer layer is compensated by carbon to realize the control of the short channel effect and the reduction of the leakage current, thereby effectively improving the breakdown voltage of the device. The relatively positive threshold voltage effectively reduces the overall area, RON and power consumption of the entire cascode system. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic structural diagram of an insulated gate MIS HEMT device according to an embodiment of the present application;

[0033] Figure 2a-2g It is a detailed schematic diagram of a preparation process of an insulated gate MIS HEMT device according to an embodiment of the present application;

[0034] Figure 3 It is a schematic flow chart of a method for preparing an insulated gate MIS HEMT device according to an embodiment of the present application;

[0035] Figure 4 is a transfer characteristic curve diagram of an insulated gate MIS HEMT device provided in an embodiment of the present application;

[0036] Figure 5It is an output characteristic curve diagram of an insulated gate MIS HEMT device provided in an embodiment of the present application;

[0037] Figure 6 This is a graph showing a gate forward leakage characteristic curve of an insulated gate MIS HEMT device provided in an embodiment of the present application.

[0038] Figure numerals: 1. substrate layer; 2. nucleation layer; 3. transition layer; 4. buffer layer; 5. channel layer; 6. insertion layer; 7. barrier layer; 8. insulating layer; 9. metal layer; 10 isolation structure; 11. passivation layer; 12. gate; 13. source; 14. drain. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0040] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. In contrast, when an element is referred to as being "directly on" another element, there is no intermediate element. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0041] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0042] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include: one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0043] The terms used in one or more embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit one or more embodiments of the present application. The singular forms "a", "said" and "the" used in one or more embodiments of the present application are also intended to include: plural forms, unless the context clearly indicates other meanings.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of the template are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0045] It should be understood that, although the terms first, second, etc. may be used to describe various information in one or more embodiments of the present application, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of one or more embodiments of the present application, the first may also be referred to as the second, and similarly, the second may also be referred to as the first. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when the time of".

[0046] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes are not repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0047] Please refer to Figure 1 , an insulated gate MIS HEMT device provided in an embodiment of the present application includes:

[0048] A substrate layer 1, a nucleation layer 2, a transition layer 3, a buffer layer 4, a channel layer 5, an insertion layer 6 and a barrier layer 7 are sequentially arranged on the substrate layer; an insulating layer 8 is arranged on the barrier layer 7, wherein the material of the insulating layer is: C-doped C:GaN; a metal layer 9 is arranged on the insulating layer 8; an isolation structure 10 is arranged on the side wall of the HEMT device, wherein the isolation structure 10 runs through the barrier layer 7, the insertion layer 6 and the channel layer 5, and is arranged on the buffer layer 4; a passivation layer 11 is arranged on the metal layer 9 surface and the upper surface of the barrier layer 7, the side walls of the insulating layer 8 and the side walls of the metal layer 9; a gate 12, located in the gate opening area, and penetrating the passivation layer 11 to the upper surface of the metal layer 9; a source 13, located on one side of the gate 12, wherein the source 13 penetrates the passivation layer 11, the barrier layer 7, the insertion layer 6 and a portion of the channel layer 5; a drain 14, located on the other side of the gate 12, wherein the drain 14 penetrates the barrier layer 7, the insertion layer 6 and a portion of the channel layer 5.

[0049] In the above scheme, the insulated gate MIS HEMT device is provided with a C-doped C:GaN insulating layer 8 and a carbon-doped high-resistance GaN buffer layer 4, and then a HEMT device with a relatively positive threshold voltage can be realized by regulating the thickness of the C:GaN insulating layer 8 and the C element doping concentration, and the conductivity of the GaN buffer layer 4 is compensated by carbon to realize the control of the short channel effect and the reduction of the leakage current, which effectively improves the breakdown voltage of the device gate, and the relatively positive threshold voltage effectively reduces the overall area, RON and power consumption of the entire cascode system.

[0050] The above structures are described in detail below with reference to the accompanying drawings.

[0051] See also Figure 1 , providing a substrate layer 1, which can specifically be any one of a sapphire substrate, a Si substrate, a SiC substrate, a diamond substrate, a glass substrate, a ceramic substrate and a polymer substrate, as a supporting structure and a carrier structure of the HEMT device.

[0052] Please continue reading Figure 1 A nucleation layer 2 is formed on the substrate layer 1; in this embodiment, the material of the nucleation layer 2 can be at least one of AlGaN and AlN, and the thickness of the nucleation layer 2 can be controlled in the range of 20 nm-500 nm.

[0053] Please continue reading Figure 1There is also a transition layer 3 above the nucleation layer 2. In this embodiment, the material of the transition layer 3 can be at least one of AlN, AlGaN and GaN. It should be noted that the thickness of the transition layer 3 can range from 300 nm to 400 nm to ensure that the stress between the nucleation layer 2 and the buffer layer 4 is well regulated.

[0054] Please continue reading Figure 1 A buffer layer 4 is also formed on the transition layer 3. In this example, the material of the buffer layer 4 can be at least one of high-resistance GaN and high-resistance AlGaN, and the thickness of the buffer layer 4 can be controlled in the range of 1200 nm-6000 nm, so that the buffer layer 4 can grow normally and will not be longitudinally broken down.

[0055] Please continue reading Figure 1 A channel layer 5, an insertion layer 6 and a barrier layer 7 are also formed on the buffer layer 4. In the present embodiment, the material of the channel layer 5 may be unintentionally doped GaN, and the thickness of the channel layer 5 may be controlled within a range of 200 nm-300 nm. The material of the insertion layer 6 may be AlN, and the thickness of the insertion layer 6 may be controlled within a range of 0.5 nm-2 nm. The thickness of the barrier layer 7 may be in a range of 10 nm-50 nm, and the Al component in the material of the barrier layer 7 may be between 10% and 30%.

[0056] Please continue reading Figure 1 An insulating layer 8 is also formed on the barrier layer 7. In this embodiment, the thickness of the insulating layer 8 can be controlled in the range of 50 nm to 90 nm, and the C element doping concentration in the insulating layer 8 can be 10 18 cm -3 -10 20 cm -3 .

[0057] Please continue reading Figure 1 A metal layer 9 is also formed on the insulating layer 8. In this example, the thickness of the metal layer 9 can be controlled to be in the range of 5 nm-300 nm. The material of the metal layer 9 includes at least one of TiN, Cu and Al.

[0058] Please continue reading Figure 1 , on the sidewall of the HEMT device, further comprising: an isolation structure 10, wherein the isolation structure 10 penetrates the barrier layer 7, the insertion layer 6 and the channel layer 5, and is located on the buffer layer 4. It can be understood that by providing the isolation structure 10 on the sidewall of the HEMT device, an isolation region can be formed and parasitic effects can be reduced.

[0059] In a specific embodiment, the isolation structure 10 includes: any one of a mesa isolation structure and an ion implantation structure.

[0060] Specifically, the mesa isolation structure refers to an isolation structure formed in the mesa area of ​​the device through etching and other processes during the manufacturing process of semiconductor devices. It is used to achieve electrical isolation between different device areas, reduce leakage, crosstalk and other problems, and improve device performance and reliability.

[0061] Ion implantation structure refers to a doping structure that uses an ion implanter to accelerate and implant impurity ions into semiconductor materials. By controlling the type, energy, dose, angle and other parameters of the implanted ions, the electrical properties of semiconductor materials, such as carrier concentration, conductivity type, etc., can be precisely changed, thereby achieving regulation of semiconductor device performance.

[0062] Please continue reading Figure 1 A passivation layer 11 is also grown on the upper surface of the metal layer 9 and the upper surface of the barrier layer 7, the side wall of the insulating layer 8 and the side wall of the metal layer 9. It can be understood that the passivation layer 11 can improve the electrical performance of the HEMT device and protect the surface of the device.

[0063] Specifically, in HEMT devices, the density of states at the semiconductor surface and interface has a significant impact on the electrical properties of the device. The passivation layer 11 can reduce the density of surface states and interface states. When there is no passivation layer, the surface states and interface states will capture or release carriers (electrons or holes), resulting in increased carrier scattering and decreased mobility, which seriously affects the dynamic characteristics of the device. For example, in AlGaN / GaN HEMT devices, the passivation layer 11 can fill the defects on the surface and interface, reduce the unintended capture and scattering of carriers at these locations, thereby improving electron mobility and improving the performance of the device such as transconductance and output current.

[0064] In a specific embodiment, the thickness of the passivation layer 11 can be controlled in the range of 50 nm-400 nm, and the material of the passivation layer can be: SiO2, SiN x , AlON and Al2O3.

[0065] See also Figure 4 and Figure 5 According to the transfer characteristic curve and output characteristic curve of the HEMT device, it can be seen that the threshold voltage of the insulated gate MIS HEMT device provided in the present application is -2.5V, and the current density characteristics are good, and the on-resistance is small.

[0066] See also Figure 6 According to the gate forward leakage characteristic curve of the HEMT device, it can be seen that the gate leakage of the insulated gate MIS HEMT device provided by the present application is small, and the gate forward withstand voltage can reach 18V.

[0067] See also Figure 2a-2g as well as Figure 3 The present application also provides a method for preparing an insulated gate MIS HEMT device, which is applied to prepare the above-mentioned tunnel gate HEMT device, and at least comprises the following steps:

[0068] S10, providing a substrate layer 1.

[0069] Specifically, the substrate layer 1 may be any one of a sapphire substrate, a Si substrate, a SiC substrate, a diamond substrate, a glass substrate, a ceramic substrate, and a polymer substrate.

[0070] S20, sequentially growing a nucleation layer 2, a transition layer 3, a buffer layer 4, a channel layer 5, an insertion layer 6, a barrier layer 7 and an insulating layer 8 on the substrate layer 1, wherein the material of the insulating layer 8 is: C-doped C:GaN.

[0071] Specifically, see Figure 2a In this embodiment, a metal organic chemical vapor deposition process is adopted to sequentially grow a nucleation layer 2, a transition layer 3, a buffer layer 4, a channel layer 5, an insertion layer 6, a barrier layer 7 and an insulating layer 8 on the substrate layer 1.

[0072] In a specific embodiment, the thickness of the nucleation layer 2 is in the range of 20 nm-500 nm, and the material of the nucleation layer 2 includes: at least one of AlGaN and AlN; the thickness of the transition layer 3 is in the range of 300 nm-400 nm, and the material of the transition layer 3 includes: at least one of AlN, AlGaN and GaN; the thickness of the buffer layer 4 is in the range of 1200 nm-6000 nm, and the material of the buffer layer 4 includes: C-doped high-resistance GaN; the thickness of the channel layer 5 is in the range of 200 nm-300 nm, and the material of the channel layer 5 includes: unintentionally doped GaN; the thickness of the insertion layer 6 is in the range of 0.5 nm-2 nm, and the material of the insertion layer 6 includes: AlN; the thickness of the barrier layer 7 is in the range of 10 nm-50 nm, and the Al component in the material of the barrier layer 7 is 10%-30%; the thickness of the insulating layer 8 is in the range of 50 nm-90 nm, and the C element doping concentration in the insulating layer 8 is 10%-20%. 18 cm -3 -10 20 cm -3 .

[0073] S30 , depositing a thin layer of metal on the upper surface of the insulating layer to form a metal layer 9 .

[0074] Specifically, see Figure 2b In this embodiment, a physical vapor deposition process is used to deposit a metal material on the upper surface of the insulating layer to form a metal layer 9.

[0075] In a specific embodiment, the thickness of the metal layer 9 is in the range of 5 nm-300 nm, and the material of the metal layer 9 includes at least one of TiN, Cu and Al.

[0076] S40, forming an isolation structure 10 on the upper surface of the metal layer 9 and outside the active area of ​​the HEMT device, wherein the isolation structure 10 penetrates the metal layer 9, the insulating layer 8, the barrier layer 7, the insertion layer 6 and the channel layer 5.

[0077] Specifically, see Figure 2c In this embodiment, the isolation structure 10 can be any one of a table isolation structure and an ion implantation structure. For example, taking the ion implantation structure as an example, N ions are implanted at both ends of the upper surface of the metal layer 9 by a plasma implantation process to form an N ion implantation area, and the implantation depth is controlled to the upper surface of the buffer layer 4 to achieve planar device isolation.

[0078] S50 , forming a gate region on the upper surface of the metal layer 9 , etching away the metal layer 9 and the insulating layer 8 outside the gate region, and etching to a depth reaching the upper surface of the barrier layer 7 .

[0079] Specifically, see Figure 2d In this example, the metal layer 9 and the insulating layer 8 outside the gate region are etched away using ICP technology, and the etching depth reaches the upper surface of the barrier layer 7.

[0080] S60 , depositing a dielectric material on the upper surface of the barrier layer 7 , the upper surface of the metal layer 9 , the sidewall of the metal layer 9 , and the sidewall of the insulating layer 8 to form a passivation layer 11 .

[0081] Specifically, see Figure 2e In this embodiment, any one of the processes of plasma enhanced atomic layer deposition (PEALD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), and low pressure chemical vapor deposition (LPCVD) can be used to deposit dielectric materials on the upper surface of the barrier layer 7, the upper surface of the metal layer 9, the sidewall of the metal layer 9, and the sidewall of the insulating layer 8 to form a passivation layer 11 with a thickness range of 50 nm-400 nm, wherein the dielectric material of the passivation layer 11 can be: SiO2, SiN x , AlON and Al2O3.

[0082] It should be noted that the passivation layer 11 in this embodiment may be a passivation layer 11 formed by a single-layer medium, or may be a passivation layer 11 formed by multiple media.

[0083] S70, forming a gate opening region on the upper surface of the passivation layer 11 in the gate region, etching away the dielectric layer in the gate opening region until reaching the upper surface of the metal layer 9, and depositing metal material in the gate opening region to form a gate 12.

[0084] Specifically, see Figure 2f In this embodiment, a physical vapor deposition process can be used to deposit a gate metal material in the gate opening area to form a gate 12, wherein the gate 12 metal material can be Ti / Al / Ni / Au or TiN / Al / Ti / Au.

[0085] S80, forming a source region and a drain region on the upper surface of the passivation layer respectively, etching the passivation layer 11 in the source region and the drain region, the etching depth includes: the passivation layer 11, the barrier layer 7, the insertion layer 6 and a part of the channel layer 5, forming a source etching region and a drain etching region, and depositing metal materials in the source etching region and the drain etching region to form a source 13 and a drain 14.

[0086] Specifically, see Figure 2g In this embodiment, photolithography and development technology are used, and photoresist is used as a mask layer to form a source region and a drain region on the upper surface of the passivation layer 11, respectively, and the passivation layer 11 in the source region and the drain region is etched. The etching depth includes: the passivation layer 11, the barrier layer 7, the insertion layer 6 and a portion of the channel layer 5, forming a source etching region and a drain etching region, and depositing a metal material on the barrier layer 7 to form a source 13 and a drain 14. Finally, the entire device is annealed to achieve ohmic contact between the source 13 and the drain 14.

[0087] The present embodiment provides a method for preparing an insulated gate MIS HEMT device, which forms a gate dielectric layer under the insulated gate MIS HEMT device by epitaxially growing a C-doped C:GaN insulating layer 8 on a channel layer 5 using a metal organic chemical vapor deposition process (MOCVD), and etching the insulating layer 8 using a selective self-stop etching technique. The preparation method effectively reduces the gate leakage of the insulated gate MIS HEMT device and improves the gate withstand voltage.

[0088] The present application also provides a chip, wherein the chip comprises: an insulated gate MISHEMT device as described in any one of the above.

[0089] The present application also provides an electronic device, which includes: the chip as described above.

[0090] In all examples shown and described herein, any specific values ​​should be interpreted as merely exemplary and not as limiting, and thus other examples of the exemplary embodiments may have different values.

[0091] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0092] In the description of the present invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first" and "second" may explicitly or implicitly include: one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0093] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0094] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the scope of protection of the present invention.

[0095] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. An insulated gate MIS HEMT device, characterized in that: include: A substrate layer, and a nucleation layer, a transition layer, a buffer layer, a channel layer, an insertion layer and a barrier layer sequentially disposed on the substrate layer; The insulating layer is located on the barrier layer, wherein the material of the insulating layer is C-doped C:GaN, the thickness of the insulating layer is in the range of 50 nm-90 nm, and the C element doping concentration in the insulating layer is 10 18 cm -3 -10 20 cm -3 ; A metal layer, located on the insulating layer; an isolation structure, located on a sidewall of the HEMT device, wherein the isolation structure penetrates the barrier layer, the insertion layer and the channel layer, and is located on the buffer layer; a passivation layer, located on an upper surface of the metal layer and an upper surface of the barrier layer, a side wall of the insulating layer and a side wall of the metal layer; A gate, located in the gate opening region and penetrating the passivation layer to the upper surface of the metal layer; A source electrode, located at one side of the gate, wherein the source electrode penetrates the passivation layer, the barrier layer, the insertion layer and a portion of the channel layer; A drain electrode is located at the other side of the gate, wherein the drain electrode penetrates the barrier layer, the insertion layer and a portion of the channel layer.

2. The insulated gate MIS HEMT device according to claim 1, characterized in that: The thickness of the nucleation layer is in the range of 20 nm-500 nm, and the material of the nucleation layer includes: at least one of AlGaN and AlN; the thickness of the transition layer is in the range of 300 nm-400 nm, and the material of the transition layer includes: at least one of AlN, AlGaN and GaN; the thickness of the buffer layer is in the range of 1200 nm-6000 nm, and the material of the buffer layer includes: C-doped high-resistance GaN; the thickness of the channel layer is in the range of 200 nm-300 nm, and the material of the channel layer includes: unintentionally doped GaN; the thickness of the insertion layer is in the range of 0.5 nm-2 nm, and the material of the insertion layer includes: AlN; the thickness of the barrier layer is in the range of 10 nm-50 nm, and the Al component in the material of the barrier layer is 10%-30%.

3. The insulated gate MIS HEMT device according to claim 1, characterized in that: The thickness of the metal layer ranges from 5 nm to 300 nm, and the material of the metal layer includes at least one of TiN, Cu and Al.

4. The insulated gate MIS HEMT device according to claim 1, characterized in that: The thickness of the passivation layer ranges from 50 nm to 400 nm, and the materials of the passivation layer include: SiO2, SiN x , AlON and Al2O3.

5. The insulated gate MIS HEMT device according to claim 1, characterized in that: The isolation structure includes: any one of a mesa isolation structure and an ion implantation structure.

6. A method for preparing an insulated gate MIS HEMT device, characterized in that: include: providing a substrate layer; A nucleation layer, a transition layer, a buffer layer, a channel layer, an insertion layer, a barrier layer and an insulating layer are sequentially grown on the substrate layer, wherein the insulating layer is made of C-doped C:GaN, the thickness of the insulating layer is in the range of 50 nm to 90 nm, and the C element doping concentration in the insulating layer is 10 18 cm -3 -10 20 cm -3 ; Depositing a thin layer of metal on the upper surface of the insulating layer to form a metal layer; forming an isolation structure on the upper surface of the metal layer and outside the active region of the HEMT device, wherein the isolation structure penetrates the metal layer, the insulating layer, the barrier layer, the insertion layer and the channel layer; forming a gate region on the upper surface of the metal layer, and etching the metal layer and the insulating layer outside the gate region to a depth reaching the upper surface of the barrier layer; Depositing a dielectric material on the upper surface of the barrier layer, the upper surface of the metal layer, the sidewall of the metal layer and the sidewall of the insulating layer to form a passivation layer; Forming a gate opening region on the upper surface of the passivation layer in the gate region, etching away the dielectric layer in the gate opening region until reaching the upper surface of the metal layer, and depositing a metal material in the gate opening region to form a gate; A source region and a drain region are respectively formed on the upper surface of the passivation layer, and the passivation layers of the source region and the drain region are etched, and the etching depth includes: the passivation layer, the barrier layer, the insertion layer and a part of the channel layer, to form a source etching region and a drain etching region, and metal materials are deposited in the source etching region and the drain etching region to form a source and a drain.

7. The method for preparing an insulated gate MIS HEMT device according to claim 6, characterized in that: The step of sequentially growing a nucleation layer, a transition layer, a buffer layer, a channel layer, an insertion layer, a barrier layer and an insulating layer on the substrate layer comprises: A metal organic chemical vapor deposition process is adopted to sequentially grow a nucleation layer, a transition layer, a buffer layer, a channel layer, an insertion layer, a barrier layer and an insulating layer on the substrate layer.

8. The method for preparing an insulated gate MIS HEMT device according to claim 6, characterized in that: Depositing a thin layer of metal on the upper surface of the insulating layer to form a metal layer comprises: A metal material is deposited on the upper surface of the insulating layer by a physical vapor deposition process to form a metal layer.

9. A chip, characterized in that: The chip includes: an insulated gate MISHEMT device according to any one of claims 1 to 5.

10. An electronic device, characterized in that: The electronic device comprises: the chip as claimed in claim 9.

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