Voltage regulation modules, electronic devices and power supply optimization methods

Abstract

This application discloses a voltage regulation module, an electronic device, and a power optimization method. The voltage regulation module provided in this application includes: a SoC chip, a first voltage regulation module, and a second voltage regulation module; the SoC chip has a control terminal and a voltage detection terminal, and the first voltage regulation module has a control terminal and an output terminal; the control terminal of the SoC chip is coupled to the control terminal of the first voltage regulation module; the output terminal of the first voltage regulation module is coupled to the second voltage regulation module, and the second voltage regulation module is coupled to the voltage detection terminal of the SoC chip.

Description

Technical Field

[0001] This application belongs to the field of electronic technology, specifically relating to a voltage regulation module, electronic equipment, and power optimization method. Background Technology

[0002] Currently, in order to save power consumption, it is very common to use AVS (Adaptive Voltage Scaling) voltage regulation systems in electronic devices such as mobile phones and tablets, which adjust the power supply voltage output by the PMIC (Power Management Integrated Circuit) chip according to the load.

[0003] In related technologies, the power supply voltage within a System-on-Chip (SoC) is set by the platform vendor and cannot be modified by the user. This makes it difficult to meet actual usage requirements in many situations. Summary of the Invention

[0004] This application provides a voltage regulation module, electronic device, and power optimization method, which at least solves the problem that the power supply voltage within the SoC cannot be modified in related technologies.

[0005] In a first aspect, this application provides a voltage regulation module, including: a SoC chip, a first voltage regulation module, and a second voltage regulation module;

[0006] The SoC chip has a control terminal and a voltage detection terminal, and the first voltage regulation module has a control terminal and an output terminal; the control terminal of the SoC chip is coupled to the control terminal of the first voltage regulation module; the output terminal of the first voltage regulation module is connected to the second voltage regulation module, and the second voltage regulation module is connected to the voltage detection terminal of the SoC chip.

[0007] In a second aspect, this application provides an electronic device including the voltage regulating module as described in the first aspect.

[0008] Thirdly, this application provides a power optimization method applied to the voltage regulation module as described in the first aspect, comprising:

[0009] The second voltage regulation module adjusts the first voltage output by the first voltage regulation module to obtain a second voltage;

[0010] The second voltage regulation module outputs the second voltage to the SoC chip;

[0011] The SoC chip determines a voltage adjustment command based on the second voltage and outputs the voltage adjustment command to the first voltage adjustment module.

[0012] In embodiments of this application, the voltage regulation module includes a SoC chip, a first voltage regulation module, and a second voltage regulation module. The SoC chip has a control terminal and a voltage detection terminal, and the first voltage regulation module has a control terminal and an output terminal. The control terminal of the SoC chip is coupled to the control terminal of the first voltage regulation module. The output terminal of the first voltage regulation module is connected to the second voltage regulation module, and the second voltage regulation module is connected to the voltage detection terminal of the SoC chip. Thus, in scenarios where the SoC chip adjusts the power supply voltage output by the first voltage regulation module, in related technologies, after the SoC chip completes adaptive voltage regulation of the power supply voltage output by the first voltage regulation module, the internal power supply voltage of the SoC cannot be modified. However, the second voltage regulation module of this application can modify and set the power supply voltage output by the first voltage regulation module. The SoC chip can further set the power supply voltage output by the first voltage regulation module based on the modified voltage value set by the second voltage regulation module, thereby solving the problem of the inability to modify the internal power supply voltage of the SoC in related technologies. Attached Figure Description

[0013] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0014] Figure 1 This is a schematic diagram of an AVS voltage regulation system provided in related technologies;

[0015] Figure 2 This is a schematic diagram of a voltage regulating module provided in an embodiment of this application;

[0016] Figure 3 This is a schematic diagram of another voltage regulating module provided in an embodiment of this application;

[0017] Figure 4 This is a schematic diagram of another voltage regulating module provided in an embodiment of this application;

[0018] Figure 5 This is a schematic diagram of another voltage regulating module provided in an embodiment of this application;

[0019] Figure 6 This is a schematic diagram of another voltage regulating module provided in an embodiment of this application;

[0020] Figure 7 A schematic diagram of an electronic device provided in an embodiment of this application;

[0021] Figure 8 A schematic flowchart illustrating a power optimization method provided in an embodiment of this application;

[0022] Figure 9This is a schematic flowchart illustrating another power optimization method provided in an embodiment of this application.

[0023] Explanation of reference numerals in the attached figures:

[0024] 10 - Electronic device; 100 - Voltage regulating module; 110 - SoC chip; 111 - Communication interface; 112 - AVS sensor; 113 - AVS controller; 114 - Central processing unit; 115 - Memory; 116 - Arbitrator; 120 - First voltage regulating module; 121 - First controller; 122 - First voltage regulating element; 130 - Second voltage regulating module; 131 - Second controller; 132 - Second voltage regulating element; 200 - PMIC chip; A - Control terminal of SoC chip; B - Voltage detection terminal of SoC chip; C - Control terminal of first voltage regulating module; D - Output terminal of first voltage regulating module; E - Voltage output terminal of PMIC chip. Detailed Implementation

[0025] The embodiments of this application will now be described in detail. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0026] The terms "first" and "second" in the specification and claims of this application may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise stated, "multiple" means two or more. Furthermore, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0027] In the description of this application, it should be understood that the terms "inner" and "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0028] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0029] Currently, the power supply voltage within a System-on-Chip (SoC) is set by the platform vendor and cannot be modified by the user. This makes it difficult to meet actual usage requirements in many situations.

[0030] For example, refer to Figure 1 In related technologies, the AVS voltage regulation system in electronic devices may include a SoC chip and a PMIC chip. The SoC chip includes a central processing unit, memory, arbitrator, AVS sensor and AVS controller, and the PMIC chip includes a voltage regulation module. The voltage regulation scheme based on the AVS voltage regulation system includes: the central processing unit (CPU) reads the pre-stored initial voltage value from the memory and sends it to the arbitrator; the arbitrator sends a voltage regulation command to the PMIC chip via the SPMI (Serial Peripheral Management Interface) bus, the voltage regulation command including a power-on instruction and the initial voltage value; the voltage regulation module in the PMIC chip outputs the power supply voltage VDD to the AVS sensor of the SoC chip according to the voltage regulation command; the AVS sensor detects the current power supply voltage VDD, as well as the current load, temperature, and other sensor data within the SoC chip, and outputs it to the AVS controller; the AVS controller, based on the current power supply voltage VDD value and the current load, temperature, and other sensor data within the SoC chip, determines a more suitable voltage value and outputs it to the arbitrator to update the voltage value; the arbitrator sends another voltage regulation command to the PMIC chip via the SPMI bus, the voltage regulation command including the updated voltage value information; the voltage regulation module in the PMIC chip adjusts the current output power supply voltage VDD of the PMIC chip according to the updated voltage value information, and can adjust the voltage multiple times until the output power supply voltage VDD of the PMIC chip reaches the expected voltage value.

[0031] Among the relevant technologies, the traditional AVS voltage regulation scheme can be referred to in Table 1 below:

[0032]

[0033] Table 1

[0034] Referring to Table 1, for example, in related technologies, if the current output power supply voltage VDD of the PMIC chip is 900mV, and the SoC chip expects to output a power supply voltage of 800mV, the AVS sensor determines that the output power supply voltage VDD of the PMIC chip is excessive. In this case, the voltage difference to be adjusted is 100mV, the single voltage adjustment amplitude of the AVS controller is 25mV, and it is necessary to reduce the voltage 4 times to adjust to the expected voltage value of 800mV.

[0035] For example, if the current output power supply voltage VDD of the PMIC chip is 850mV, and the SoC chip expects to output a power supply voltage of 800mV, the AVS sensor determines that the output power supply voltage VDD of the PMIC chip is excessive. In this case, the voltage difference that needs to be adjusted is 50mV. The AVS controller adjusts the voltage by 15mV at a time, and it needs to reduce the voltage three times to reach the expected voltage value (adjusted to 805mV, which is about 800mV).

[0036] For example, if the current output power supply voltage VDD of the PMIC chip is 800mV, and the SoC chip expects to output a power supply voltage of 800mV, and the AVS sensor determines that the output power supply voltage VDD of the PMIC chip is normal, then the arbitrator can maintain or slightly adjust the output power supply voltage of the PMIC.

[0037] For example, if the current output power supply voltage VDD of the PMIC chip is 770mV, and the SoC chip expects to output a power supply voltage of 800mV, the AVS sensor determines that the output power supply voltage VDD of the PMIC chip is insufficient. In this case, the voltage difference that needs to be adjusted is -30mV. The AVS controller adjusts the voltage by 15mV at a time, and it needs to boost the voltage twice to reach the expected voltage value of 800mV.

[0038] For example, if the current output power supply voltage VDD of the PMIC chip is 700mV, and the SoC chip expects to output a power supply voltage of 800mV, the AVS sensor determines that the output power supply voltage VDD of the PMIC chip is insufficient. In this case, the voltage difference that needs to be adjusted is -100mV. The AVS controller adjusts the voltage by 25mV at a time, and it needs to boost the voltage 4 times to reach the expected voltage value of 800mV.

[0039] In the examples in Table 1 above, the AVS voltage regulation system, in order to ensure that the entire system circuit can operate normally under poor process and environmental conditions, reserves a certain supply voltage margin. This requires boosting the supply voltage VDD to make it greater than the lower operating voltage. Thus, the actual demand voltage exceeds the actual supply voltage, leading to unnecessary power consumption and potentially causing additional heat generation in the load equipment. For example, in a certain scenario, the target module can operate normally with a supply voltage of 770mV, but the related AVS voltage regulation solution will still set the target voltage at 800mV, resulting in unnecessary power consumption. Alternatively, if the current supply voltage is 800mV, traditional voltage regulation solutions in related technologies will not regulate the voltage, maintaining it at 800mV, leading to unnecessary power consumption.

[0040] Based on this, this application provides a voltage regulation module. A second voltage regulation module is set between the voltage regulation modules in the SoC chip and the PMIC chip. Furthermore, in related technologies, after the SoC chip completes the regulation of the power supply voltage output by the first voltage regulation module, the second voltage regulation module of this application can modify the power supply voltage output by the first voltage regulation module. The SoC chip can further set the power supply voltage output by the first voltage regulation module based on the modified spoof voltage value of the second voltage regulation module. Thus, the voltage within the SoC can be adjusted through the second voltage regulation module, thereby solving the problem of the inability to modify the power supply voltage within the SoC in related technologies. For example, in the voltage regulation scheme implemented in this application, the second voltage regulation module modifies the current power supply voltage of 800mV to 830mV output. The SoC chip treats the spoof voltage of 830mV as the current power supply voltage output by the PMIC chip and regulates the voltage, continuing to reduce the voltage by 30mV each time. After one voltage regulation, the actual power supply voltage output by the current PMIC chip drops from 800mV to the expected 770mV. This satisfies both the normal operation of the system and the goal of reducing power consumption.

[0041] Furthermore, in the examples in Table 1 above, the current AVS voltage regulation system's step-by-step, slow voltage adjustment scheme struggles to account for the impact of rapid anomalies, such as transient interference, thus failing to meet the need for faster voltage regulation. For instance, if the PMIC chip's current output power supply voltage VDD is 700mV, and the existing SoC chip expects to output a power supply voltage of 800mV, and the AVS controller's single voltage adjustment amplitude is 25mV, it needs to boost the voltage four times to reach the expected voltage value of 800mV.

[0042] Based on this, this application provides a voltage regulation module. A second voltage regulation module is set between the voltage regulation modules in the SoC chip and the PMIC chip. The SoC chip can then adjust the power supply voltage VDD_IN output by the voltage regulation module in the PMIC chip based on the deceptive voltage VDD_OUT adjusted by the second voltage regulation module, thereby accelerating the voltage regulation process. For example, in this application, the second voltage regulation module expects to output a power supply voltage of 770mV. If it determines that the power supply voltage VDD is lower than expected, the second voltage regulation module modifies the current power supply voltage of 700mV to 650mV. The AVS sensor determines that the current power supply voltage output by the PMIC chip (i.e., the deceptive voltage 650mV) is far lower than expected, requiring faster voltage boosting. The AVS controller sets the single voltage adjustment amplitude to 35mV, boosting the current output power supply voltage VDD (700mV) twice to 770mV. Compared to the related technologies that require four voltage boosts, this accelerates the voltage regulation process, achieving the effect of faster voltage regulation.

[0043] The voltage regulation module, electronic equipment, and power optimization method provided in the embodiments of this application are described in detail below with reference to the accompanying drawings.

[0044] like Figure 2 As shown, this application embodiment provides a voltage regulation module 100, which may include: a SoC chip 110, a first voltage regulation module 120, and a second voltage regulation module 130;

[0045] The SoC chip 110 has a control terminal A and a voltage detection terminal B, and the first voltage regulation module 120 has a control terminal C and an output terminal D. The control terminal A of the SoC chip 110 is coupled to the control terminal C of the first voltage regulation module 120. The output terminal D of the first voltage regulation module 120 is coupled to the second voltage regulation module 130, and the second voltage regulation module 130 is coupled to the voltage detection terminal B of the SoC chip 110.

[0046] In the embodiments of this application, the SoC chip 110 is a chip that integrates multiple functional modules, which may include, but are not limited to: a central processing unit (CPU), a graphics processing unit (GPU), a memory controller (DDR controller), a multimedia module (Multi-media), a display processing unit (DPU), a video processing unit (VPU), a communication module (Modem), etc., with the aim of integrating as many functional modules as possible onto a single chip to achieve high integration and reduce layout area.

[0047] In this embodiment, the output voltage of the first voltage regulation module 120 can be the power supply voltage VDD_IN, which can provide operating voltage for multiple functional modules on the SoC chip 110.

[0048] In this embodiment, the SoC chip 110 has an adaptive voltage regulation (AVS) function. The SoC chip 110 can detect and adjust the power supply voltage VDD_IN output by the first voltage regulation module 120 to a desired voltage value. The desired voltage value can be a predetermined target voltage, which is the minimum voltage threshold that satisfies the target condition.

[0049] In this embodiment, the voltage detection terminal of the SoC chip 110 does not detect the actual power supply voltage value (e.g., VDD_IN) output by the first voltage regulation module, but rather detects a spoofed voltage (e.g., VDD_OUT) obtained after the actual power supply voltage value has been modified by the second voltage regulation module. When the SoC chip 110 treats the spoofed voltage (e.g., VDD_OUT) as the current power supply voltage value output by the first voltage regulation module, the SoC chip can further set the power supply voltage output by the first voltage regulation module based on the spoofed voltage information, thereby solving the problem of the inability to modify the power supply voltage within the SoC in related technologies.

[0050] For example, in this embodiment, a second voltage regulation module 130 is provided between the voltage detection terminal of the SoC chip 110 and the output terminal of the first voltage regulation module 120. Therefore, in scenarios where the SoC chip adjusts the power supply voltage output by the first voltage regulation module, in related technologies, after the SoC chip completes adaptive voltage regulation of the power supply voltage output by the first voltage regulation module, the internal power supply voltage of the SoC cannot be modified. However, the second voltage regulation module of this application can modify and set the power supply voltage output by the first voltage regulation module to obtain a deceptive voltage value. The SoC chip can further set the power supply voltage output by the first voltage regulation module based on the deceptive voltage value modified and set by the second voltage regulation module. Thus, the voltage within the SoC is adjusted through the second voltage regulation module, thereby solving the problem of excessive power consumption caused by the inability to modify the internal power supply voltage of the SoC in related technologies.

[0051] According to the voltage regulation module provided in the embodiments of this application, the voltage regulation module includes a SoC chip, a first voltage regulation module, and a second voltage regulation module. The SoC chip has a control terminal and a voltage detection terminal, and the first voltage regulation module has a control terminal and an output terminal. The control terminal of the SoC chip is coupled to the control terminal of the first voltage regulation module. The output terminal of the first voltage regulation module is connected to the second voltage regulation module, and the second voltage regulation module is connected to the voltage detection terminal of the SoC chip. Thus, in scenarios where the SoC chip adjusts the power supply voltage output by the first voltage regulation module, in related technologies, after the SoC chip completes adaptive voltage regulation of the power supply voltage output by the first voltage regulation module, the power supply voltage within the SoC cannot be modified. However, the second voltage regulation module of this application can modify and set the power supply voltage output by the first voltage regulation module. The SoC chip can further set the power supply voltage output by the first voltage regulation module based on the modified and set voltage value of the second voltage regulation module, thereby solving the problem that the power supply voltage within the SoC cannot be modified in related technologies.

[0052] In addition, in this embodiment, a second voltage regulation module 130 is provided between the SoC chip 110 and the first voltage regulation module 120. Thus, the SoC chip 110 can adjust the output voltage VDD_IN of the first voltage regulation module 120 based on the output voltage VDD_OUT adjusted by the second voltage regulation module 130. In other words, the second voltage regulation module 130 can assist the SoC chip 110 in adjusting the output voltage VDD_IN of the first voltage regulation module 120.

[0053] Furthermore, in this embodiment, since the second voltage regulation module 130 can assist the SoC chip 110 in regulating the output voltage of the first voltage regulation module 120, it can accelerate the adaptive voltage regulation process of the SoC chip 110 on the output voltage VDD_IN of the first voltage regulation module 120, thereby achieving the effect of speeding up the voltage regulation process.

[0054] In practical applications, when the load on multiple functional modules within the SoC chip 110 changes, the SoC chip 110 can adaptively adjust the power supply voltage output by the first voltage regulation module 120. This adaptive voltage adjustment can be a step-by-step adjustment; for example, the larger the voltage difference between the current output power supply voltage and the desired voltage value, the larger the single voltage adjustment amplitude of the previously output power supply voltage by the SoC chip. The first voltage regulation module can be located within the PMIC chip, which outputs the power supply voltage to provide operating voltage for the multiple functional modules of the SoC chip.

[0055] For example, in a specific embodiment, such as Figure 3As shown, the first voltage regulation module 120 can be located within the PMIC chip 200;

[0056] The PMIC chip 200 has a control terminal and a voltage output terminal E. The control terminal A of the SoC chip 110 is connected to the control terminal of the PMIC chip 200. The control terminal of the PMIC chip 200 is coupled to the control terminal C of the first voltage regulation module 120. The output terminal D of the first voltage regulation module 120 is coupled to the voltage output terminal E of the PMIC chip 200.

[0057] Among them, the PMIC chip 200 has power management function. It is a highly integrated circuit chip that can effectively manage and regulate the power supply in electronic devices.

[0058] The first voltage regulation module 120 is located inside the PMIC chip 200. The control terminal A of the SoC chip 110 can be connected to the control terminal of the PMIC chip 200 via the SPMI bus. The control terminal of the PMIC chip 200 is connected to the control terminal C of the first voltage regulation module 120. The output terminal D of the first voltage regulation module 120 is connected to the voltage output terminal E of the PMIC chip 200.

[0059] The SoC chip 110 can send a voltage adjustment command to the PMIC chip 200 via the SPMI bus. The voltage adjustment command can include an updated voltage value, which can be based on the second voltage VDD_OUT output by the second voltage adjustment module and the updated voltage value determined by the current load in the SoC chip. The first voltage adjustment module 120 can adjust the output voltage VDD_IN according to the voltage adjustment command.

[0060] The output terminal D of the first voltage regulation module 120 is connected to the voltage output terminal E of the PMIC chip 200. Thus, the voltage output terminal E of the PMIC chip 200 can output voltage VDD_IN to the voltage detection terminal B of the SoC chip 110.

[0061] In addition, the voltage output terminal E of the PMIC chip 200 can also output voltage VDD_IN to various functional modules within the SoC chip 110 to provide operating voltage to each functional module within the SoC chip 110.

[0062] It should be noted that in related technologies, the PMIC chip typically outputs a voltage VDD directly to the SoC chip 110 for voltage detection. However, in this embodiment, the PMIC chip 200 outputs a first voltage VDD_IN to a second voltage regulation module, which then boosts or bucks it to obtain a suitable second voltage VDD_OUT. This second voltage is then transmitted to the voltage detection terminal of the SoC chip 110. Upon receiving VDD_OUT, the voltage detection terminal of the SoC chip 110 updates the voltage value based on the information in VDD_OUT and the current load within the SoC chip, and adjusts the output voltage VDD_IN of the PMIC chip 200 accordingly. This method allows for the output of the desired PMIC voltage, speeds up the voltage regulation process, saves power consumption, and verifies system stability.

[0063] In this way, the PMIC chip can output a power supply voltage VDD_IN to provide operating voltage to multiple functional modules of the SoC chip. The second voltage regulation module can assist the SoC chip in regulating the output voltage VDD_IN of the PMIC chip, thereby accelerating the voltage regulation process.

[0064] In practical applications, the specific location of the second voltage regulation module 130 can be determined according to actual needs. For example, the second voltage regulation module 130 can be located between the PMIC chip 200 and the SoC chip 110. In this case, the second voltage regulation module 130 can be an independent voltage regulation IC chip, which can be customized according to actual needs. Alternatively, the second voltage regulation module 130 can be located within the PMIC chip 200. In this case, the existing circuitry within the PMIC chip 200 can be reused, resulting in high feasibility and space saving. Examples are given below.

[0065] In a specific embodiment, such as Figure 3 As shown, the second voltage regulation module 130 can be disposed between the PMIC chip 200 and the SoC chip 110. The output terminal D of the first voltage regulation module 120 is connected to the input terminal of the second voltage regulation module 130 via the voltage output terminal E of the PMIC chip 200.

[0066] Specifically, the second voltage regulation module 130 can be set on the power path between the PMIC chip 200 and the SoC chip 110.

[0067] The output terminal D of the first voltage regulation module 120 is connected to the input terminal of the second voltage regulation module 130 via the voltage output terminal E of the PMIC chip 200. The voltage output terminal E of the PMIC chip 200 can output a first voltage VDD_IN to the second voltage regulation module 130, which then boosts or bucks the first voltage VDD_IN to obtain a suitable second voltage VDD_OUT. This voltage is then transmitted to the voltage detection terminal B of the SoC chip 110. After receiving VDD_OUT, the voltage detection terminal B of the SoC chip 110 updates the voltage value based on the information in VDD_OUT and the current load condition within the SoC chip, and adjusts the output voltage VDD_IN of the PMIC chip 200 according to the updated voltage value.

[0068] In addition, the voltage output terminal E of the PMIC chip 200 can also output the first voltage VDD_IN to multiple functional modules of the SoC chip 110 to enable the multiple functional modules to work normally.

[0069] In this embodiment, the second voltage regulation module 130 can be an independent voltage regulation IC, which can be customized according to actual needs.

[0070] In this way, by setting an independent voltage regulator IC as a second voltage regulation module 130 in the power path between the PMIC chip 200 and the SoC chip 110, the voltage regulator IC assists the SoC chip in regulating the output voltage VDD_IN of the PMIC chip, thereby accelerating the voltage regulation process. Furthermore, the second voltage regulation module 130 is an independent voltage regulator IC that can be customized according to actual needs.

[0071] In another specific embodiment, such as Figure 4 As shown, the second voltage regulation module 130 is disposed in the PMIC chip 200, and the output terminal D of the first voltage regulation module 120 is connected to the voltage output terminal E of the PMIC chip 200 and the input terminal of the second voltage regulation module 130, respectively.

[0072] The output terminal D of the first voltage regulation module 120 is connected to the voltage output terminal E of the PMIC chip 200 and the input terminal of the second voltage regulation module 130, respectively. Thus, the voltage output terminal E of the PMIC chip 200 can output a first voltage VDD_IN to multiple functional modules of the SoC chip 110, enabling these modules to operate normally. Simultaneously, the output terminal D of the first voltage regulation module 120 can output the first voltage VDD_IN to the second voltage regulation module 130. The second voltage regulation module then boosts or bucks this first voltage VDD_IN to obtain a suitable second voltage VDD_OUT, which is then transmitted to the voltage detection terminal B of the SoC chip 110. Upon receiving VDD_OUT, the voltage detection terminal B of the SoC chip 110 updates the voltage value based on the information in VDD_OUT and the current load within the SoC chip, and adjusts the output voltage VDD_IN of the PMIC chip 200 according to the updated voltage value.

[0073] In this embodiment, the second voltage regulation module 130 can be specifically located inside the SoC chip. The second voltage regulation module 130 can reuse the circuitry within the existing PMIC chip 200, offering high feasibility and saving area.

[0074] In this way, the second voltage regulation module 130 can be specifically set inside the SoC chip. The second voltage regulation module 130 assists the SoC chip 110 in regulating the output voltage VDD_IN of the PMIC chip 200, which can speed up the voltage regulation process. At the same time, integrating the second voltage regulation module into the PMIC chip saves external PCB layout area and reduces the risk of power supply interference.

[0075] It should be noted that the SoC chip 110, the first voltage regulation module 120, and the second voltage regulation module 130 all have voltage regulation functions. The internal structure of the SoC chip 110, the first voltage regulation module 120, and the second voltage regulation module 130, as well as the working principle of the voltage regulation module 100, will be illustrated below with examples.

[0076] In one specific embodiment, reference Figure 5 or Figure 6 The second voltage regulation module 130 may include a second controller 131 and a second voltage regulating element 132; the second controller 131 is connected to the second voltage regulating element 132.

[0077] The second controller 131 has a first input terminal, a second input terminal, and an output terminal. The second voltage regulating element 132 has a control terminal, an input terminal, and an output terminal. The first input terminal of the second controller 131 is coupled to the output terminal D of the first voltage regulation module 120. The second input terminal of the second controller 131 is connected to the communication interface 111 of the SoC chip 110. The output terminal of the second controller 131 is connected to the control terminal of the second voltage regulating element 132. The input terminal of the second voltage regulating element 132 is coupled to the output terminal D of the first voltage regulation module 120. The output terminal of the second voltage regulating element 132 is connected to the voltage detection terminal B of the SoC chip 110.

[0078] The first input terminal of the second controller 131 is coupled to the output terminal D of the first voltage regulation module 120, and the first input terminal of the second controller 131 can receive the first voltage VDD_IN output by the first voltage regulation module 120.

[0079] The second input terminal of the second controller 131 is connected to the communication interface 111 of the SoC chip 110 via a communication bus to enable communication between the second controller 131 and the SoC chip 110. The second input terminal of the second controller 131 can receive clock signals, control signals, load information, temperature information, etc.

[0080] The second controller 131 contains a preset control logic algorithm. It determines whether to perform a boost or buck operation on VDD_IN by combining the input first voltage VDD_IN voltage with the input SoC chip load, temperature and other information.

[0081] The output of the second controller 131 can output a control signal to the second voltage regulating element 132 to control the boost / buck operation of the first voltage VDD_IN, including the specific voltage regulation amplitude.

[0082] The second voltage regulating element 132 includes a boost element and a buck element. After receiving the control signal from the second controller 131, it boosts or bucks the input first voltage VDD_IN to obtain the second voltage VDD_OUT, and then outputs it to the voltage detection terminal B of the SoC chip in the form of VDD_OUT.

[0083] In this way, the second controller 131 in the second voltage regulation module 130 can generate a control signal based on the input first voltage VDD_IN and information such as the load and temperature of the input SoC chip. Then, the second voltage regulating element 132 performs a boost or buck operation on the input first voltage VDD_IN according to the control signal to obtain the second voltage VDD_OUT. Thus, the SoC chip can adjust the output voltage VDD_IN of the first voltage regulation module based on the second voltage VDD_OUT output by the second voltage regulation module. Since the second voltage regulation module 130 can assist the SoC chip 110 in adjusting the output voltage VDD_IN of the first voltage regulation module 120, the voltage regulation process can be accelerated.

[0084] refer to Figure 5 or Figure 6 The first voltage regulation module 120 may include a first controller 121 and a first voltage regulating element 122. The control terminal of the PMIC chip 200 is connected to the first controller 121, the first controller 121 is connected to the first voltage regulating element 122, and the first voltage regulating element 122 is coupled to the voltage output terminal E of the PMIC chip 200.

[0085] The control terminal A of the SoC chip 110 can be connected to the first controller 121 via the control terminal of the PMIC chip 200, and send a voltage adjustment command to the first controller 121. The voltage adjustment command may include updating voltage value information. The first controller 121 can generate a control signal according to the voltage adjustment command and send the control signal to the first voltage regulating element 122. The first voltage regulating element 122 can adjust the output first voltage VDD_IN according to the control signal, which can speed up the voltage regulation process.

[0086] refer to Figure 5 or Figure 6 The SoC chip 110 may include an AVS sensor 112, an AVS controller 113, a central processing unit 114, a memory 115, and an arbitrator 116;

[0087] The second voltage regulation module 130 is connected to the AVS sensor 112 through the voltage detection terminal B of the SoC chip 110. The AVS sensor 112 is connected to the AVS controller 113 and the central processing unit 114 respectively. The central processing unit 114 is connected to the memory 115. The AVS controller 113 and the central processing unit 114 are both connected to the arbitrator 116. The arbitrator 116 is coupled to the control terminal C of the first voltage regulation module 120 through the control terminal A of the SoC chip 110.

[0088] The SoC chip 110 features an Adaptive Voltage Regulation (AVS) function. The adaptive voltage regulation process based on the SoC chip 110 can include: the central processing unit 114 reads a pre-stored initial voltage value from the memory 115 and sends the initial voltage value to the arbitrator 116; the arbitrator 116 sends a voltage regulation command to the PMIC chip 200 via the SPMI bus, the voltage regulation command including a power-on command and the initial voltage value; the first voltage regulation module 120 in the PMIC chip 200 outputs a first voltage VDD_IN to the second voltage regulation module 130 according to the voltage regulation command; the second voltage regulation module 130, based on the input first voltage VDD_IN and combined with information such as the load and temperature of the input SoC chip, performs a boost or buck operation on the input first voltage VDD_IN to obtain a second voltage VDD_OUT; the second voltage regulation module 130 outputs the second voltage VDD_OUT. The voltage VDD_OUT is sent to the AVS sensor 112 of the SoC chip 110; the AVS sensor 112 detects the second voltage VDD_OUT, as well as the current load, temperature and other sensor data in the SoC chip, and outputs it to the AVS controller 113; the AVS controller 113 comprehensively judges a more suitable voltage value based on the currently detected second voltage VDD_OUT value and the current load, temperature and other sensor data in the SoC chip, and outputs it to the arbitrator 116 to update the voltage value; the arbitrator 116 sends a voltage adjustment command to the PMIC chip 200 again through the SPMI bus, and the voltage adjustment command includes the updated voltage value information; the first voltage adjustment module 120 in the PMIC chip 200 adjusts the current output voltage VDD_IN of the PMIC chip 200 according to the updated voltage value information, and can adjust the voltage multiple times until the first voltage VDD_IN output by the PMIC chip reaches the expected voltage value.

[0089] In this way, the SoC chip 110 can adaptively adjust the first voltage VDD_IN output by the first voltage adjustment module 120 based on the second voltage VDD_OUT output by the second voltage adjustment module 130. Since the second voltage adjustment module 130 can assist the SoC chip 110 in adjusting the first voltage VDD_IN output by the first voltage adjustment module 120, the voltage regulation process can be accelerated.

[0090] It is understandable that the second voltage VDD_OUT output by the second voltage regulation module 130 can be regarded as a kind of deceptive voltage information. After the SoC chip 110 detects the deceptive voltage information, it can increase the single voltage regulation amplitude compared with related technologies, thereby reducing the number of voltage regulation times and achieving the effect of accelerating voltage regulation.

[0091] For example, in a specific case, when the first voltage VDD_IN output by the first voltage regulation module 120 is greater than or equal to the target voltage, the second voltage VDD_OUT output by the second voltage regulation module 130 is greater than the first voltage VDD_IN output by the first voltage regulation module 120.

[0092] When the first voltage VDD_IN output by the first voltage regulation module 120 is less than the target voltage, the second voltage VDD_OUT output by the second voltage regulation module 130 is less than the first voltage VDD_IN output by the first voltage regulation module.

[0093] The target voltage is the minimum voltage threshold that satisfies the target conditions.

[0094] For example, the target voltage is the minimum voltage threshold required for the functional modules inside the SoC chip 110 to operate normally. The voltage regulation module can perform at least one voltage regulation process on the first voltage VDD_IN output by the first voltage regulation module 120 to adjust the first voltage VDD_IN output by the first voltage regulation module 120 to the desired target voltage.

[0095] In practical applications, the case where the first voltage VDD_IN output by the first voltage regulation module 120 is greater than the target voltage is a step-down scenario. The SoC chip 110 can control the first voltage VDD_IN currently output by the first voltage regulation module 120 to perform at least one step-down operation until it is adjusted to the target voltage.

[0096] In this case, the second voltage regulation module 130 can boost the input first voltage VDD_IN to obtain a second voltage VDD_OUT that is greater than the first voltage VDD_IN. Compared with the current power supply voltage detected by the SoC chip 110 in the related technology, which is VDD_IN, the current power supply voltage detected by the SoC chip 110 in this application is a larger second voltage VDD_OUT. This is equivalent to expanding the voltage difference between the detected current power supply voltage and the target voltage to be regulated. As a result, the SoC chip 110 can use a larger single voltage regulation amplitude, thereby increasing the single voltage regulation amplitude and reducing the number of voltage reduction steps, thus achieving the effect of accelerating voltage reduction.

[0097] In practical applications, when the first voltage VDD_IN output by the first voltage regulation module 120 is less than the target voltage, it is a boost scenario. The SoC chip 110 can control the first voltage VDD_IN currently output by the first voltage regulation module 120 to perform at least one boost operation until it is adjusted to the target voltage.

[0098] In this case, the second voltage regulation module 130 can perform a step-down operation on the input first voltage VDD_IN to obtain a second voltage VDD_OUT that is smaller than the first voltage VDD_IN. Compared with the current power supply voltage detected by the SoC chip 110 in the related art, which is VDD_IN, the current power supply voltage detected by the SoC chip 110 in this application is a smaller VDD_OUT. This is equivalent to expanding the voltage difference between the current power supply voltage and the target voltage to be regulated. As a result, the SoC chip 110 can use a larger single voltage regulation amplitude, which increases the single voltage regulation amplitude, reduces the number of boost cycles, and achieves the effect of accelerating the boost.

[0099] Furthermore, in practical applications, when the first voltage VDD_IN output by the first voltage regulation module 120 is equal to the target voltage, in order to ensure that the entire system circuit can work normally under poor process and environment, a certain supply voltage margin is reserved. It is necessary to boost the first voltage VDD_IN so that the first voltage VDD_IN is slightly greater than the target voltage. In this way, the actual demand voltage is slightly greater than the actual supply voltage, resulting in unnecessary power consumption. At the same time, it may also cause additional heat generation problems for the load equipment.

[0100] In this case, in this embodiment of the application, when the first voltage VDD_IN output by the first voltage adjustment module 120 is equal to the target voltage, the second voltage adjustment module 130 can perform a boost operation on the input first voltage VDD_IN to obtain a second voltage VDD_OUT that is slightly greater than the target voltage. The SoC chip 110 detects that the current power supply voltage is slightly greater than the target voltage VDD_OUT, and considers that a certain power supply voltage margin has been reserved, so it maintains the current power supply voltage and does not adjust it.

[0101] Therefore, the first voltage VDD_IN output by the first voltage regulation module 120 can be maintained at the target voltage (i.e., the minimum voltage threshold that meets the target conditions) and no longer boosted, which can both meet the normal operation of the system and achieve the purpose of reducing power consumption.

[0102] Based on the same concept as the voltage regulating module provided in any of the above embodiments, this application also provides an electronic device.

[0103] like Figure 7 As shown in the figure, this application provides an electronic device 10, including a voltage regulating module 100.

[0104] It should be noted that the electronic device 10 provided in this application embodiment includes the voltage regulating module provided in any of the above embodiments, and can realize all the functions of the voltage regulating module. To avoid repetition, it will not be described again here.

[0105] In the embodiments of this application, the electronic device can be a terminal or other devices besides a terminal. For example, the electronic device can be a smartwatch, mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), etc. The embodiments of this application do not specifically limit the scope.

[0106] Based on a concept similar to the voltage regulation module provided in any of the above embodiments, this application also provides a power optimization method applied to the voltage regulation module provided in any of the above embodiments.

[0107] For example, such as Figure 8 As shown, this application provides a power optimization method applied to the voltage regulation module provided in any of the above embodiments. The power optimization method may include:

[0108] Step 810: The second voltage regulation module adjusts the first voltage output by the first voltage regulation module to obtain the second voltage;

[0109] Step 820: The second voltage regulation module outputs a second voltage to the SoC chip;

[0110] Step 830: The SoC chip determines the voltage adjustment command based on the second voltage and outputs the voltage adjustment command to the first voltage adjustment module.

[0111] Before step 810, the first voltage regulation module can output the current power supply voltage VDD in the form of a first voltage VDD_IN.

[0112] In step 810, the second voltage regulation module 130 can boost or buck the first voltage VDD_IN output by the first voltage regulation module to obtain the second voltage VDD_OUT (i.e., the deception voltage).

[0113] In step 820, the second voltage regulation module outputs a second voltage VDD_OUT to the voltage detection terminal of the SoC chip. The second voltage VDD_OUT is a deceptive voltage information. The SoC chip regards the second voltage VDD_OUT detected by the voltage detection terminal as the current power supply voltage VDD output by the first voltage regulation module, which can amplify the voltage difference between the current power supply voltage and the target voltage to be regulated.

[0114] Furthermore, in step 830, during the process of determining the voltage adjustment command based on the second voltage, the SoC chip can determine a larger single voltage adjustment amplitude based on the amplifiable voltage difference, thereby increasing the single voltage adjustment amplitude, reducing the number of voltage adjustments, and achieving the effect of accelerating voltage adjustment.

[0115] According to the power optimization method provided in this application embodiment, a second voltage adjustment module adjusts the first voltage output by the first voltage adjustment module to obtain a second voltage; the second voltage adjustment module outputs the second voltage to the SoC chip; the SoC chip determines a voltage adjustment command based on the second voltage and outputs the voltage adjustment command to the first voltage adjustment module. In this way, the SoC chip regards the second voltage detected by the voltage detection terminal (i.e., the deceptive voltage) as the actual first voltage output by the first voltage adjustment module (i.e., the power supply voltage). The SoC chip can further set the first voltage output by the first voltage adjustment module based on the second voltage. Thus, the voltage within the SoC can be adjusted through the second voltage adjustment module, thereby solving the problem of the inability to modify the power supply voltage within the SoC in related technologies.

[0116] In addition, the SoC chip regards the second voltage detected by the voltage detection terminal as the first voltage (power supply voltage) output by the current first voltage regulation module, which expands the voltage difference between the current power supply voltage and the target voltage to be regulated. In the process of determining the voltage regulation command based on the second voltage, a larger single voltage regulation amplitude is determined, which increases the single voltage regulation amplitude and reduces the number of voltage regulation times, thereby achieving the effect of accelerating voltage regulation.

[0117] In one specific embodiment, the voltage adjustment command output by the SoC chip may include a single voltage adjustment amplitude. In order to ensure the stability of the system, the SoC chip can adjust the voltage step by step during the adaptive voltage adjustment process. The larger the voltage difference between the current power supply voltage and the target voltage, the larger the single voltage adjustment amplitude.

[0118] For example, in step 830 above, the SoC chip determines a voltage adjustment command based on the second voltage, including:

[0119] Based on the second voltage, the target voltage difference is determined; the target voltage difference is the difference between the second voltage and the target voltage.

[0120] The single voltage regulation amplitude is determined based on the target voltage difference; wherein the single voltage regulation amplitude is proportional to the target voltage difference.

[0121] The target voltage is the minimum voltage threshold that satisfies the target conditions.

[0122] For example, the target voltage is the minimum voltage threshold required for the functional modules inside the SoC chip to function normally. The voltage regulation module can perform at least one voltage regulation process on the first voltage VDD_IN output by the first voltage regulation module 120 to adjust the first voltage VDD_IN output by the first voltage regulation module 120 to the desired target voltage.

[0123] In this design, the second voltage VDD_OUT is a deceptive voltage information. The SoC chip treats the second voltage VDD_OUT detected by the voltage detection terminal as the current power supply voltage VDD output by the first voltage regulation module. Compared with related technologies that consider the difference between the first voltage and the target voltage as the voltage difference to be adjusted, this application considers the difference between the second voltage and the target voltage as the target voltage difference to be adjusted. The SoC chip can determine a larger single voltage regulation amplitude based on a larger target voltage difference, thereby increasing the single voltage regulation amplitude, reducing the number of voltage regulation steps, and achieving the effect of accelerating voltage regulation.

[0124] The single voltage adjustment amplitude is directly proportional to the target voltage difference. The larger the target voltage difference, the larger the single voltage adjustment amplitude. For example, if the target voltage difference is 130mV, the single voltage adjustment amplitude is 40mV; if the target voltage difference is 50mV, the single voltage adjustment amplitude is 15mV.

[0125] In this way, by determining the corresponding single voltage regulation amplitude based on different target voltage differences, the effect of step-by-step voltage regulation can be achieved, ensuring the stability of the system during adaptive voltage regulation.

[0126] In another specific embodiment, in order to achieve the effects of accelerated voltage regulation and power saving, in step 810 above, the second voltage regulation module adjusts the first voltage output by the first voltage regulation module to obtain a second voltage, including:

[0127] When the first voltage output by the first voltage regulation module is greater than or equal to the target voltage, the second voltage regulation module boosts the first voltage output by the first voltage regulation module so that the second voltage output by the second voltage regulation module is greater than the first voltage output by the first voltage regulation module.

[0128] When the first voltage output by the first voltage regulation module is less than the target voltage, the second voltage regulation module reduces the first voltage output by the first voltage regulation module, so that the second voltage output by the second voltage regulation module is less than the first voltage output by the first voltage regulation module.

[0129] It is understandable that when the first voltage VDD_IN output by the first voltage regulation module is greater than the target voltage, it is a bucking scenario. The SoC chip can control the first voltage regulation module to perform at least one bucking operation on the current output voltage VDD_IN until it is adjusted to the target voltage. In this case, the second voltage regulation module boosts the input first voltage VDD_IN to obtain a second voltage VDD_OUT that is greater than the first voltage VDD_IN. Compared with the current power supply voltage detected by the SoC chip in related technologies, which is VDD_IN, the current power supply voltage detected by the SoC chip in this application is a larger second voltage VDD_OUT. This is equivalent to expanding the difference between the detected current power supply voltage and the target voltage to be adjusted. Therefore, the SoC chip can use a larger single voltage regulation amplitude to buck the output voltage of the first voltage regulation module, increasing the single voltage regulation amplitude, thereby reducing the number of bucking operations and achieving the effect of accelerating bucking.

[0130] Similarly, when the first voltage VDD_IN output by the first voltage regulation module is less than the target voltage, it is a boost scenario. The SoC chip can control the first voltage VDD_IN currently output by the first voltage regulation module to be boosted at least once until the target voltage is reached. In this case, the second voltage regulation module can de-voltage the input first voltage VDD_IN to obtain a second voltage VDD_OUT that is less than the first voltage VDD_IN. Compared with the related technology where the current power supply voltage detected by the SoC chip is VDD_IN, in this application, the current power supply voltage detected by the SoC chip is a smaller VDD_OUT. This is equivalent to expanding the voltage difference to be adjusted between the current power supply voltage and the target voltage. As a result, the SoC chip can use a larger single voltage regulation amplitude to boost the output voltage of the first voltage regulation module, increasing the single voltage regulation amplitude, reducing the number of boost operations, and achieving the effect of accelerated boosting.

[0131] Furthermore, regarding the case where the first voltage VDD_IN output by the first voltage regulation module is equal to the target voltage, in related technologies, to ensure the normal operation of the entire system circuit under poor process conditions and environments, a certain supply voltage margin is reserved. This requires boosting the first voltage VDD_IN to make it slightly greater than the target voltage. Thus, the actual required voltage is slightly greater than the actual supplied voltage, leading to unnecessary power consumption and potentially causing additional heat generation in the load equipment. In this case, according to this embodiment, when the first voltage VDD_IN output by the first voltage regulation module 120 is equal to the target voltage, the second voltage regulation module 130 can boost the input first voltage VDD_IN to obtain a second voltage VDD_OUT slightly greater than the target voltage. The SoC chip 110 detects that the current power supply voltage is slightly greater than the target voltage VDD_OUT, and considers that the current power supply voltage output by the first voltage regulation module has already reserved a certain supply voltage margin, maintaining the current power supply voltage without further adjustment. Therefore, the first voltage VDD_IN output by the first voltage regulation module can be maintained at the target voltage (i.e., the minimum voltage threshold that meets the target conditions) and no longer boosted, which can both meet the normal operation of the system and achieve the purpose of reducing power consumption.

[0132] In practical applications, for example, with Figure 5 Taking the voltage regulation module shown as an example, the second voltage regulation module 130 can be a voltage regulation IC disposed on the power path between the SoC chip 110 and the PMIC chip 200. Figure 9 As shown, this application provides a power optimization method that can be applied to... Figure 5 The power optimization method for the voltage regulating module shown may include the following steps:

[0133] Determine that the current output power supply voltage of the PMIC chip is VDD;

[0134] Input the current power supply voltage of the PMIC chip to the voltage regulator IC in the form of VDD_IN;

[0135] The voltage regulator IC determines whether to boost or buck VDD_IN. The second controller within the voltage regulator IC integrates a pre-defined logic algorithm. Upon receiving VDD_IN, it considers the current system operating scenario (e.g., load and temperature information transmitted to the voltage regulator IC via the communication bus by the SoC chip) to determine whether to boost or buck VDD_IN, identifies the boost or buck magnitude, and then controls the second voltage regulating element within the voltage regulator IC to adjust VDD_IN to obtain VDD_OUT.

[0136] The voltage regulator IC outputs VDD_OUT to the AVS sensor;

[0137] The AVS sensor transmits information such as VDD_OUT, SoC current load, and temperature to the AVS controller. The AVS controller determines the updated voltage value based on the VDD_OUT, SoC current load, and temperature information, and then the arbitrator updates the voltage value.

[0138] The arbitrator updates the power supply voltage VDD output by the PMIC chip via the SPMI bus, completing one round of voltage regulation;

[0139] After one round of voltage regulation is completed, the voltage regulating IC determines whether further voltage regulation is needed. For example, the second controller of the voltage regulating IC can compare the current VDD_IN with the expected target voltage value. If they do not match, the voltage is regulated again. If they match the expectation, the current round of voltage regulation ends.

[0140] For example, in the embodiments of this application, the voltage regulation scheme can be referred to Table 2 below:

[0141]

[0142] Table 2

[0143] Referring to Table 2, for example, if the current output power supply voltage VDD_IN of the PMIC chip is 900mV, and the voltage regulator IC expects the output power supply voltage to be 770mV, the voltage regulator IC determines that the power supply voltage VDD_IN is much higher than expected. The voltage regulator IC adjusts VDD_IN to obtain VDD_OUT, which is 950mV. The AVS sensor determines that the output power supply voltage VDD of the PMIC chip is over-performance and needs to be stepped down faster. The target voltage difference to be adjusted is 950-770=180mV. The single voltage adjustment amplitude of the AVS controller is set to 43mV. The current output power supply voltage VDD_IN (900mV) can be stepped down 3 times to adjust to 770mV.

[0144] For example, if the current output power supply voltage VDD_IN of the PMIC chip is 850mV, and the desired output power supply voltage is 770mV, the voltage regulator IC determines that the power supply voltage VDD_IN is slightly higher than expected. The voltage regulator IC adjusts VDD_IN to obtain VDD_OUT, which is 900mV. The AVS sensor determines that the output power supply voltage VDD of the PMIC chip is excessive and needs to be stepped down. The target voltage difference to be adjusted is 900-770=130mV. The single voltage adjustment amplitude of the AVS controller is set to 40mV. The current output power supply voltage VDD_IN (850mV) can be stepped down twice to adjust to 770mV.

[0145] For example, if the current output power supply voltage VDD_IN of the PMIC chip is 800mV, and the desired output power supply voltage is 770mV, the voltage regulator IC determines that the power supply voltage VDD_IN can be reduced to reduce power consumption. The voltage regulator IC adjusts VDD_IN to obtain VDD_OUT, which is 830mV. The AVS sensor determines that the output power supply voltage VDD of the PMIC chip is excessive and needs to be reduced. The target voltage difference to be adjusted is 830-770=60mV. The single voltage adjustment amplitude of the AVS controller is set to 30mV. The current output power supply voltage VDD_IN (800mV) can be reduced once to 770mV.

[0146] For example, if the current output power supply voltage VDD_IN of the PMIC chip is 770mV, and the desired output power supply voltage is 770mV, the voltage regulator IC determines that the current power supply voltage can operate normally. The voltage regulator IC adjusts VDD_IN to obtain VDD_OUT, which is 800mV. The AVS sensor determines that the output power supply voltage VDD of the PMIC chip is normal. Then the arbitrator can maintain or slightly adjust the output power supply voltage of the PMIC.

[0147] For example, if the current output power supply voltage VDD_IN of the PMIC chip is 700mV, and the desired output power supply voltage is 800mV, the voltage regulator IC determines that the power supply voltage VDD_IN is slightly lower than expected. The voltage regulator IC adjusts VDD_IN to obtain VDD_OUT, which is 650mV. The AVS sensor determines that the output power supply voltage VDD of the PMIC chip is slightly lower than expected and needs to be boosted faster. The target voltage difference to be adjusted is 650-770=-120mV. The single voltage adjustment amplitude of the AVS controller is set to 35mV. The current output power supply voltage VDD_IN (700mV) can be boosted twice to adjust to 770mV.

[0148] Comparing the voltage regulation schemes of related technologies in Table 1 above with the examples of voltage regulation schemes in the embodiments of this application in Table 2 above, the embodiments of this application can achieve the effects of accelerating voltage regulation and saving power consumption. For example, if the current power supply voltage is 850mV, and the expected voltage value in related technologies is 800mV, adjusting by 15mV at a time requires three voltage reductions to reach the expected voltage value. However, the embodiments of this application use a voltage regulating IC to adjust the current power supply voltage VDD_IN to VDD_OUT, becoming 900mV. The AVS decision unit can use 900mV as the current power supply voltage of the PMIC for voltage regulation, with a single voltage adjustment amplitude of 40mV. Each voltage adjustment reduces the voltage by 40mV, and after two voltage adjustments, the expected voltage value of 770mV is reached. Compared with related technologies, one voltage adjustment is reduced, achieving the effect of accelerating voltage reduction.

[0149] For example, if the current power supply voltage is 700mV and the expected voltage value in related technologies is 800mV, each adjustment increases the voltage by 25mV, requiring four voltage boosts to reach the expected voltage value of 800mV. However, in this embodiment, the current power supply voltage VDD_IN is adjusted to VDD_OUT via a voltage regulating IC, becoming 650mV. The AVS decision unit can then use 650mV as the current PMIC power supply voltage for voltage regulation, with a single voltage adjustment amplitude of 35mV. Each adjustment increases the voltage by 35mV, and after two adjustments, the expected voltage value of 770mV is reached. Compared to related technologies, this reduces the number of voltage adjustments by two, achieving a faster voltage boost effect.

[0150] Furthermore, in related technologies, the AV voltage regulation scheme is embedded within the SoC chip, and to balance consistency, reliability, and other factors, the supply voltage margin is quite large. For example, in a certain scenario, 770mV is sufficient for normal operation, but the AVS voltage regulation scheme in related technologies still sets the target voltage at 800mV. However, the voltage regulation scheme provided in this application can control the SoC chip to reduce the power supply voltage to 770mV, achieving the effect of reducing power consumption in the target scenario. For example, if the current power supply voltage is 800mV, the traditional voltage regulation scheme in related technologies does not regulate the voltage and maintains the output at 800mV. However, the voltage regulation scheme implemented in this application raises VDD_OUT to 830mV output, and the AVS decision unit uses 830mV as the current power supply voltage output of the PMIC chip for voltage regulation, and then reduces the voltage by 30mV each time, until it reaches the expected 770mV. In this way, both normal system operation and power consumption reduction are achieved.

[0151] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0152] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A voltage regulating module, characterized in that, include: System-on-a-chip (SoC), first voltage regulation module, and second voltage regulation module; The second voltage regulation module is located outside the SoC chip; The SoC chip has a control terminal and a voltage detection terminal, and the first voltage regulation module has a control terminal and an output terminal; the control terminal of the SoC chip is coupled to the control terminal of the first voltage regulation module; the output terminal of the first voltage regulation module is coupled to the second voltage regulation module, and the second voltage regulation module is coupled to the voltage detection terminal of the SoC chip; The SoC chip includes an adaptive voltage-regulating AVS sensor, an AVS controller, a central processing unit, a memory, and an arbitrator. The second voltage regulation module is connected to the AVS sensor through the voltage detection terminal of the SoC chip. The AVS sensor is connected to the AVS controller and the central processing unit (CPU) respectively. The CPU is connected to the memory. The AVS controller and the CPU are both connected to the arbitrator. The arbitrator is coupled to the control terminal of the first voltage regulation module through the control terminal of the SoC chip.

2. The voltage regulating module according to claim 1, characterized in that, The first voltage regulation module is located within the power management integrated circuit (PMIC) chip; The PMIC chip has a control terminal and a voltage output terminal. The control terminal of the SoC chip is connected to the control terminal of the PMIC chip, and the control terminal of the PMIC chip is coupled to the control terminal of the first voltage regulation module. The output terminal of the first voltage regulation module is coupled to the voltage output terminal of the PMIC chip.

3. The voltage regulating module according to claim 2, characterized in that, The second voltage regulation module is disposed between the PMIC chip and the SoC chip, and the output terminal of the first voltage regulation module is connected to the input terminal of the second voltage regulation module via the voltage output terminal of the PMIC chip.

4. The voltage regulating module according to claim 2, characterized in that, The second voltage regulation module is disposed within the PMIC chip, and the output terminal of the first voltage regulation module is connected to the voltage output terminal of the PMIC chip and the input terminal of the second voltage regulation module, respectively.

5. The voltage regulating module according to any one of claims 1-4, characterized in that, When the first voltage output by the first voltage regulation module is greater than or equal to the target voltage, the second voltage output by the second voltage regulation module is greater than the first voltage output by the first voltage regulation module; When the first voltage output by the first voltage regulation module is less than the target voltage, the second voltage output by the second voltage regulation module is less than the first voltage output by the first voltage regulation module. The target voltage is the minimum voltage threshold that satisfies the target condition.

6. The voltage regulating module according to any one of claims 1-4, characterized in that, The second voltage regulation module includes a second controller and a second voltage regulating element; the second controller is connected to the second voltage regulating element. The second controller has a first input terminal, a second input terminal, and an output terminal; the second voltage regulating element has a control terminal, an input terminal, and an output terminal; the first input terminal of the second controller is coupled to the output terminal of the first voltage regulating module; the second input terminal of the second controller is connected to the communication interface of the SoC chip; and the output terminal of the second controller is connected to the control terminal of the second voltage regulating element. The input terminal of the second voltage regulating element is coupled to the output terminal of the first voltage regulation module, and the output terminal of the second voltage regulating element is connected to the voltage detection terminal of the SoC chip.

7. The voltage regulating module according to claim 2, characterized in that, The first voltage regulation module includes a first controller and a first voltage regulating element. The control terminal of the PMIC chip is connected to the first controller, the first controller is connected to the first voltage regulating element, and the first voltage regulating element is coupled to the voltage output terminal of the PMIC chip.

8. An electronic device, characterized in that, Includes the voltage regulating module as described in any one of claims 1-7.

9. A power optimization method, applied to a voltage regulation module as described in any one of claims 1-7, characterized in that, The method includes: The second voltage regulation module adjusts the first voltage output by the first voltage regulation module to obtain a second voltage; The second voltage regulation module outputs the second voltage to the SoC chip; The SoC chip determines a voltage adjustment command based on the second voltage and outputs the voltage adjustment command to the first voltage adjustment module.

10. The method according to claim 9, characterized in that, The voltage adjustment command includes a single voltage adjustment amplitude; The SoC chip determines a voltage adjustment command based on the second voltage, including: Based on the second voltage, a target voltage difference is determined; the target voltage difference is the difference between the second voltage and the target voltage, and the target voltage is the minimum voltage threshold that satisfies the target condition; Based on the target voltage difference, determine the amplitude of a single voltage regulation; The single voltage adjustment amplitude is proportional to the target voltage difference.

11. The method according to claim 10, characterized in that, The second voltage regulation module adjusts the first voltage output by the first voltage regulation module to obtain a second voltage, including: When the first voltage output by the first voltage regulation module is greater than or equal to the target voltage, the second voltage regulation module boosts the first voltage output by the first voltage regulation module so that the second voltage output by the second voltage regulation module is greater than the first voltage output by the first voltage regulation module. When the first voltage output by the first voltage regulation module is less than the target voltage, the second voltage regulation module performs a voltage reduction process on the first voltage output by the first voltage regulation module, so that the second voltage output by the second voltage regulation module is less than the first voltage output by the first voltage regulation module.

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