Data processing method and device, electronic equipment, and storage medium

Abstract

The present disclosure provides a data processing method and device, electronic equipment and storage medium. The data processing method provided by the present disclosure comprises: receiving a first request message from a first device, wherein the first request message comprises a first address aligned according to a first data length and a first size in units of the first data length; converting the first address into a second address aligned according to a second data length, wherein the second data length is greater than the first data length; converting the first size into a second size in units of the second data length; and sending a second request message to a second device, wherein the second request message comprises the second address and the second size. The data processing method converts the processing request, so that the processing request can be easily switched between different hardware, and the overall processing efficiency is improved.

Description

Technical Field

[0001] The embodiments disclosed herein relate to the field of data processing technology, and more specifically, to a data processing method, a data processing apparatus, an electronic device, and a storage medium. Background Technology

[0002] For different operators such as Convolutional Neural Networks (CNNs) and matrix multiplication (Mat Mul), existing computing devices, coprocessors, and accelerators employ varying implementations. The different granularities of data reading and writing on different hardware can lead to gaps within or between data rows. For example, some computing devices can read and write data byte-by-byte, allowing for tightly packed data, but for some external accelerators (e.g., open-source neural network accelerators), the starting address of each row of data must be aligned to a specific data length (e.g., 32 bytes), potentially creating gaps between rows. These different data format requirements further complicate the switching of computing tasks between different hardware. Summary of the Invention

[0003] This summary section is provided to briefly introduce the concepts, which will be described in detail in the detailed description section below. This summary section is not intended to identify key or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0004] At least one embodiment of this disclosure provides a data processing method, comprising: receiving a first request message from a first device, wherein the first request message includes a first address aligned to a first data length and a first size in units of the first data length; converting the first address to a second address aligned to a second data length, wherein the second data length is greater than the first data length; converting the first size to a second size in units of the second data length; and sending a second request message to a second device, wherein the second request message includes the second address and the second size.

[0005] At least one embodiment of this disclosure provides a data processing apparatus, comprising: a first interface for receiving a first request message from a first device, wherein the first request message includes a first address aligned to a first data length and a first size in units of the first data length; a first conversion module for converting the first address to a second address aligned to a second data length, wherein the second data length is greater than the first data length; a second conversion module for converting the first size to a second size in units of the second data length; and a second interface for sending a second request message to a second device, wherein the second request message includes the second address and the second size.

[0006] At least one embodiment of this disclosure provides a data processing apparatus, including: at least one processor; and a storage device having at least one program stored thereon, which, when executed by the at least one processor, causes the at least one processor to implement any data processing method according to an embodiment of this disclosure.

[0007] At least one embodiment of this disclosure provides an electronic device, including any data processing apparatus according to embodiments of this disclosure.

[0008] At least one embodiment of this disclosure provides a non-transitory storage medium containing computer-executable instructions, wherein the computer-executable instructions, when executed by a computer processor, are used to perform any data processing method according to embodiments of this disclosure.

[0009] The data processing method provided by the embodiments of this disclosure improves overall processing efficiency by converting the format of processing requests (e.g., read / write requests) so that processing requests can be easily switched between different hardware. Attached Figure Description

[0010] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0011] Figure 1 A schematic diagram of the architecture of an unaligned direct memory access converter (UDMAC) according to at least one embodiment of the present disclosure is shown;

[0012] Figure 2 A flowchart of an example data processing method according to at least one embodiment of the present disclosure is shown;

[0013] Figure 3 An exemplary processing flow diagram of an example data processing method according to at least one embodiment of the present disclosure is shown;

[0014] Figure 4 Another exemplary processing flow diagram of an example data processing method according to at least one embodiment of the present disclosure is shown;

[0015] Figure 5 A schematic diagram of a data processing apparatus according to at least one embodiment of the present disclosure is shown;

[0016] Figure 6 A schematic diagram of another data processing apparatus according to at least one embodiment of the present disclosure is shown; and

[0017] Figure 7 An example structural schematic diagram is shown that is suitable for implementing an electronic device according to at least one embodiment of the present disclosure. Detailed Implementation

[0018] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0019] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0020] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0021] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0022] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0023] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.

[0024] As mentioned above, the interfaces of some neural network accelerators (e.g., Deep Learning Accelerator (DLA)) require that the address (addr) and size (size) being processed must be integer multiples of a specific data length (e.g., 32 bytes), and the starting address of each line of data must be aligned to that specific data length. Therefore, it is not possible to directly read tightly packed (e.g., per-byte aligned) data that some specific computing devices process.

[0025] Embodiments of this disclosure provide an Unaligned Direct Memory Access Converter (UDMAC) to support the conversion between aligned and unaligned data. The UDMAC can convert unaligned read / write requests into aligned formats, enabling support for operations, commands, or requests (e.g., read / write requests) in unaligned formats, allowing the DLA to directly read tightly packed data in memory.

[0026] In this document, "aligned data" can also be referred to as data whose address and size are aligned according to a second data length. In some implementations, the second data length can be greater than 2 times the first data length. N The second data length is 32 bytes, where N is an integer greater than or equal to 1. For example, the second data length could be 32 bytes, 64 bytes, etc. Correspondingly, data whose address and size are not aligned to the second data length is called "unaligned data." For example, data whose address and size are aligned to a first data length less than the second data length can be called "unaligned data." In some implementations, the first data length can be 2 bytes. X A byte is a unit of data, where X is an integer greater than or equal to 0. For example, the first data length can be 1 byte, 2 bytes, etc. In the following description, a first data length of 1 byte and a second data length of 32 bytes are used as examples. Furthermore, while "byte" is used as the basic unit of data in this document, other data units such as "bit" or "half-byte" may be used in some implementations, and this document does not impose any restrictions.

[0027] Next, Figure 1 A schematic diagram of the architecture of an unaligned direct memory access converter (UDMAC) according to at least one embodiment of the present disclosure is shown.

[0028] like Figure 1According to at least one embodiment of this disclosure, UDMAC 102 may be located between the first device 101 and the second device 103, and may be communicatively connected to the first device 101 and the second device 103 respectively. For example, the communication connection may be based on a certain bus protocol and the bus width (e.g., 16 bytes, 32 bytes, etc.) may be selected as needed. The bus may be an on-chip bus (e.g., AXI) or an inter-chip bus (e.g., PCIE). The embodiments of this disclosure do not limit this.

[0029] The first device 101 may be a computing device that arranges and processes data according to a first data length (e.g., 1 byte). The embodiments of this disclosure are not limited in this regard. For example, the computing device may be a processor based on any instruction set (e.g., x86, RISC-V, or ARM instruction set), and may be a single-core or multi-core processor. For example, in some embodiments, the first device 101 may further refer to an interface device of the computing device that arranges and processes data according to the first data length, such as the DMA interface device of the computing device. UDMAC 102 may receive a first request message 104 aligned to the first data length from the first device 101.

[0030] The first request message 104 may be or may include one or more of a first write request message (or write command), a first read request message (or read command), etc. It should be understood that in other embodiments, the first request message may also be any other request such as a data transfer request.

[0031] The second device 103 may be a device that arranges and processes data according to a second data length (e.g., 32 bytes), and the embodiments of this disclosure are not limited thereto. For example, the second device may be provided as a coprocessor. For example, in some embodiments, the second device 103 may further refer to the interface device of the device that arranges and processes data according to the second data length, such as the data bus interface device of the device, such as the AXI interface or ACE interface of DLA.

[0032] UDMAC 102 can convert a first request message 104 received from the first device 101 corresponding to a first data length to generate a second request message 105 corresponding to a second data length, and then send the second request message 105 corresponding to a second data length to the second device 103 for subsequent processing.

[0033] The data processing method of UDMAC 102 according to at least one embodiment of the present disclosure will be described below in conjunction with Figures 2 to 4 Provide a detailed description.

[0034] Figure 2A flowchart of an example data processing method according to at least one embodiment of the present disclosure is shown. Figure 3 An exemplary processing flow diagram of an example data processing method according to at least one embodiment of the present disclosure is shown; Figure 4 Another exemplary processing flow diagram of an example data processing method according to at least one embodiment of the present disclosure is shown.

[0035] like Figure 2 As shown, the example data processing method 200 according to an embodiment of this disclosure may include the following steps:

[0036] Step S201: Receive a first request message from the first device, wherein the first request message may include a first address aligned to a first data length and a first size in units of the first data length;

[0037] Step S202: Convert the first address to a second address aligned with the second data length, wherein the second data length may be greater than the first data length;

[0038] Step S203: Convert the first size to a second size in units of the second data length; and

[0039] Step S204: Send a second request message to the second device, wherein the second request message includes a second address and a second size.

[0040] For example, in one example, in step S201, the data processing method 200 may include receiving a first request message 104 from a first device.

[0041] In some implementations, the first request message 104 may be a first write request message or a first read request message. As described above, in some implementations, the first device may be a computing device or its interface device that arranges and processes data according to a first data length. Therefore, the first request message 104 may include a first address addr_u_start aligned to the first data length and a first size size_u in units of the first data length. When the first request message 104 is a first write request message, the first request message 104 may also include first write data data_u in units of the first data length. The processing of the first address addr_u_start, the first size size_u, and / or the first write data data_u by the UDMAC 102 will be described in detail below in conjunction with specific embodiments.

[0042] Figure 3 The following is an example of a first write request message, 104.

[0043] like Figure 3As shown in 310, the first address addr_u_start, aligned to the first data length (i.e., 1 byte), can be any address within the memory range, and the first size size_u, in units of the first data length, can be any size in bytes. Figure 3 In this context, assume that the first address addr_u_start included in the first request message 104 is 0x10052 and the first size size_u is 0x0005f (i.e., 95 bytes).

[0044] Continuing as shown in 310, the first data to be written, data_u, can be the shaded portion from the first address addr_u_start (0x10052) to the first end address addr_u_end (0x100b0). Here, the first end address addr_u_end can be determined by the first address addr_u_start and the first size size_u. For example, the first end address addr_u_end can be determined according to the following equation (1):

[0045] addr_u_end = addr_u_start + size_u - 1 (1)

[0046] For example, in this example, in step S202, the data processing method 200 may include converting the first address addr_u_start into a second address addr_a_start aligned with the second data length.

[0047] As mentioned above, the second data length can be greater than 2 times the first data length. N Bytes, where N is an integer greater than or equal to 1. Figure 3 In this context, we assume that the first data length is 1 byte and the second data length is 32 bytes.

[0048] In some implementations, converting the first address `addr_u_start` to a second address `addr_a_start` aligned to the second data length may include setting the low-order bits corresponding to the low-order bits of the 0 values ​​in the binary representation of the second data length in the first address `addr_u_start` to 0, thereby obtaining the second address `addr_a_start`. For example, taking a second data length of 32 bytes as an example, its corresponding binary representation is 0010 0000, where the low-order bits of the 0 values ​​are the lowest 5 bits. Therefore, the lowest 5 bits in the first address 0x10052 (i.e., 0001 0000 0000 0101 0010) can be set to 0, thereby obtaining the second address `addr_a_start` = 0x10040 (i.e., 0001 0000 0000 0100 0000). It can be seen that the converted second address 0x10040 is an integer multiple of 32 bytes, that is, it is aligned to the second data length of 32 bytes.

[0049] Figure 3 The 320 in the figure represents four consecutive 32-byte data units starting from the second address 0x10040. The second address addr_a_start, aligned to the second data length, can be easily and efficiently determined by setting the low bits corresponding to the low bits of the 0 values ​​in the binary representation of the second data length in the first address addr_u_start to 0.

[0050] For example, in one example, in step S203, the data processing method 200 may include converting the first size size_u into a second size size_a in units of the second data length.

[0051] In some implementations, the quotient of the first size size_u = 0x0005f (i.e., 95 bytes) and the second data length 32 bytes can be rounded up to obtain an intermediate size size_m in 32-byte units. For example, in the example above, in This is the rounding function. In some implementations, the first boundary address addr_bound1 can also be determined based on the second address addr_a_start = 0x10040 and the intermediate size size_m = 3 obtained in step S202. For example, the first boundary address addr_bound1 can be determined by the following equation (2):

[0052] addr_bound1 = addr_a_start + 0x00020*size_m - 1 (2)

[0053] Here, "0x00020" is the hexadecimal representation of the second data length of 32. In the example above, the first boundary address addr_bound1 = 0x1009f can be calculated using equation (2), which is the end address of the third "32-byte" data unit in 320.

[0054] In some implementations, as described above, the first end address addr_u_end can be determined based on the first address addr_u_start and the first size size_u using the above equation (1). In the example above, the first end address addr_u_end = 0x100b0 can be calculated using equation (1).

[0055] In some implementations, the required second size `size_a` can be determined based on a comparison of the first end address `addr_u_end` = 0x100b0 and the first boundary address `addr_bound1` = 0x1009f, and the intermediate size `size_m` = 3. In some implementations, if the first end address `addr_u_end` is greater than the first boundary address `addr_bound1`, the value of the intermediate size `size_m+1` can be determined as the second size `size_a`. Figure 3 This situation is illustrated in 320. In, for example... Figure 3 In the example shown in 320, since the starting address of the data in the request message is changed from the first address 0x10052 to the second address 0x10040 aligned with the second data length, it is essentially equivalent to shifting the valid data corresponding to the first written data data_u backward from the second address 0x10040. Therefore, if the end address 0x100b0 of the valid data corresponding to the first written data data_u after the shift exceeds the first boundary address addr_bound1 = 0x1009f calculated based on the second address 0x10040 and the intermediate size size_m = 3, that is, the shifted valid data exceeds the third "32-byte" data unit and falls into the fourth "32-byte" data unit, then the value of the intermediate size size_m+1 should be determined as the second size size_a, that is, size_a = 4 (i.e., 0x00004).

[0056] However, in other implementations, for example, when the first end address `addr_u_end` is less than or equal to the first boundary address `addr_bound1`, the value of the intermediate size `size_m` can be directly determined as the second size `size_a`. For instance, in another example, suppose the first address `addr_u_start'` is still 0x10052, but the first size `size_u'` = 0x0004a (i.e., 74 bytes). In this case, the second address `addr_a_start'` = 0x10040 and the intermediate size `size_a` can be calculated according to the method described above. The first boundary address addr_bound1' = 0x1009f, and the first end address addr_u_end' = 0x1009b. In this case, since the starting address of the data in the request message is changed from the first address 0x10052 to the second address 0x10040 aligned with the second data length, it is essentially equivalent to shifting the valid data corresponding to the first written data data_u' backward from the second address 0x10040. However, since the end address 0x1009b of the valid data corresponding to the first written data data_u' after the shift does not exceed the first boundary address addr_bound1' = 0x1009f calculated based on the second address 0x10040 and the intermediate size size_m' = 3, that is, the end address of the valid data after the shift still falls in the third "32-byte" data unit, the value of the intermediate size size_m' can be directly determined as the second size size_a', that is, size_a' = 3 (i.e., 0x00003). In this way, the transformed second size can be optimally determined, such that the transformed second size can be the smallest size that can contain the original first size.

[0057] In such Figure 3 In the example shown, according to the method described above, the first address, addr_u_start = 0x10052, which is aligned to 1 byte, is converted to the second address, addr_a_start = 0x10040, which is aligned to 32 bytes. The first size, size_u = 0x0005f (i.e., 95 bytes), which is in units of 1 byte, is converted to the second size, size_a = 4 (i.e., 0x00004), which corresponds to an integer multiple of 32 bytes, i.e., 128 bytes.

[0058] For example, in one example, in step S204, the data processing method 200 may further include sending a second request message 105 to the second device 103, including a second address addr_a_start and a second size size_a, for subsequent operation or processing by the second device 103. As described above, the second device 105 may be a device or its interface device that arranges and processes data according to a second data length (e.g., 32 bytes).

[0059] In some implementations, as described above, when the first request message 104 is or includes a first write request message, the first request message 104 may further include first write data data_u in units of a first data length. In this case, the example data processing method 200 according to an embodiment of this disclosure may further include converting the first write data data_u into second write data data_a in units of a second data length.

[0060] Still as Figure 3 Taking the example shown, firstly, the first offset value offset1 = addr_u_start - addr_a_start = 0x00012 (i.e., 18) bytes between the first address addr_u_start = 0x10052 and the converted second address addr_a_start = 0x10040 (aligned to 32 bytes) included in the first request message 104 can be determined. After determining the value J of the first offset value offset1 (J is an integer, for example, 18 in this example), J bytes of "0" can be added before the first data to be written, data_u. These J bytes of "0" can be considered invalid data.

[0061] Next, the first end address of the first written data data_u, addr_u_end = 0x100b0, can be calculated based on the first address addr_u_start = 0x10052 and the first size size_u = 0x0005f included in the first request message 104, according to equation (1) as described above. The second end address, addr_a_end, is then determined based on the converted second address addr_a_start = 0x10040 and the second size size_a = 4 (i.e., 0x00004). For example, the second end address, addr_a_end, can be determined using the following equation (3):

[0062] addr_a_end = addr_a_start + 0x00020*size_a - 1 (3)

[0063] Here, "0x00020" is the hexadecimal representation of the second data length of 32. In the example above, the second end address addr_a_end = 0x100bf can be calculated using equation (3), which is the end address of the fourth "32-byte" data unit in 320.

[0064] After determining the second end address addr_a_end, a second offset value offset2 = addr_a_end - addr_u_end = 0x0000f (i.e., 15 bytes) between the first end address addr_u_end = 0x100b0 and the second end address addr_a_end = 0x100bf can be further determined. After determining the value M of the second offset value offset2 (M is an integer, for example, 15 in this example), M bytes of "0" can be added after the first written data data_u. These M bytes of "0" can be considered invalid data. In other embodiments, "1" can also be added as invalid data, which is not limited herein.

[0065] Therefore, by padding the first write data_u, which has a first size of 0x0005f (i.e., 95 bytes), with zeros at the beginning and end according to the above method, a second write data_a, with a second size of 0x00004 (i.e., 128 bytes) in units of 32 bytes, can be obtained, which satisfies the processing format requirements of the second device 103. For example, as shown... Figure 3 The data corresponding to addresses 0x10040 to 0x100bf in 320 is shown. This second write data, data_a, can be further included in the second request message 105 to be sent to the second device 103 for subsequent operations or processing, such as a write operation.

[0066] As described above, since the second written data data_a is generated by padding the beginning and end of the first written data data_u with zeros, the beginning and end portions of the second written data data_a may contain a certain length of invalid data (such as "invalid data" as shown in 320). In some embodiments, an indication signal can also be generated to indicate which data in the second written data data_a is valid data corresponding to the first written data data_u, and this indication signal can be included in the second request message 105 and sent to the second device 103. By sending this indication signal, the second device 103 can easily know which data in the received second written data data_a is valid data, thereby improving operational efficiency.

[0067] In some implementations, the indication signal may include a first indication signal and a second indication signal. The first indication signal may be used to indicate which data in the first 32-byte data unit of the second written data data_a is valid data corresponding to the first written data data_u, and the second indication signal may be used to indicate which data in the last 32-byte data unit of the second written data data_a is valid data corresponding to the first written data data_u.

[0068] For example, still using Figure 3 In the example shown, since it has been determined according to the method described above that 18 bytes of "0" have been added before the first written data data_u to generate the second written data data_a, it can be determined that the first 18 bytes in the first 32-byte data unit are invalid data. Therefore, for example, a 32-bit first indication signal "0000 0000 00000000 0011 1111 1111 1111" can be generated to indicate which data in the first 32-byte data unit is valid data corresponding to the first written data data_u, where the high 18 bits of this 32 bits are 0 to indicate "invalid" and the low 14 bits are 1 to indicate "valid". In other embodiments, "1" can be used to indicate "invalid" and "0" can be used to indicate "valid". Similarly, since it has been determined, according to the method described above, that 15 bytes of "0" were added after the first written data data_u to generate the second written data data_a, it can be determined that the last 15 bytes in the last 32-byte data unit are invalid data. Therefore, for example, a 32-bit second indication signal "1111 1111 1111 1111 1000 0000 0000 0000" can also be generated to indicate which data in the last 32-byte data unit is valid data corresponding to the first written data data_u, wherein the high 17 bits of this 32 bits are 1 to indicate "valid" and the low 15 bits are 0 to indicate "invalid".

[0069] Furthermore, since the intermediate data units between the first and last 32 bytes of the second written data data_a are all valid data corresponding to the first written data data_u, there is no need to generate additional indication signals to indicate the validity of these data. In this way, by generating and sending only indication signals indicating the validity of the data in the first and last 32 bytes of the second written data data_a, not only can the second device 103 be informed which data in the second written data is valid, but signaling overhead can also be saved and processing efficiency improved.

[0070] As mentioned above, Figure 3 This illustrates an example where the first request message 104 is a first write request message (or a first write command). Next, Figure 4 An example of a scenario is shown where the first request message 104 is a first read request message (or a first read command).

[0071] The above combination Figure 3 The various methods described for write command scenarios can also be applied to read command scenarios. For example, ... Figure 4 As shown, in the case that the first request message 104 is a first read command, it is still assumed that the first address addr_u_start included in the first request message 104 is 0x10052 and the first size size_u is 0x0005f (i.e., 95 bytes). The converted second address addr_a_start aligned to the second data length, i.e., 0x10040, and the second size size_a, in units of the second data length, i.e., 4 (i.e., 0x00004), can be determined according to the method described above. Therefore, UDMAC 102 can read data in units of 32 bytes (which can be called the second read data) from the second device 103 from 0x10040 to 0x100bf (size of 4 "32-byte" data units, i.e., 128 bytes). Simultaneously, for read commands, UDMAC 102 can also store the first address addr_u_start and the first size size_u in the read command in memory or cache (e.g., command FIFO) for use in subsequent operations (e.g., when converting read data). Since, according to the read command, it is only desired to read the first read data starting from the first address addr_u_start = 0x10052 with a size of the first size size_u = 0x0005f, the second read data read from the second device 103 can be converted based on the first address addr_u_start and the first size size_u to obtain the first read data.

[0072] In some implementations, with combination Figure 3 Similarly, the described method allows determining a third offset value, offset3 = addr_u_start - addr_a_start = 0x00012 (i.e., 18 bytes), between the first address addr_u_start = 0x10052 and the second address addr_a_start = 0x10040. After determining the value K of the third offset value offset3 (K is an integer, for example, 18 in this example), the first K bytes of data in the second read can be removed or discarded.

[0073] Next, the third end address of the first read data, addr_u_end = 0x100b0, can be calculated based on the first address addr_u_start = 0x10052 and the first size size_u = 0x0005f included in the first request message 104, according to equation (1) as described above. The fourth end address, addr_a_end = 0x100bf, is determined based on the converted second address addr_a_start = 0x10040 and the second size size_a = 4 (i.e., 0x00004), which is the end address of the fourth "32-byte" data unit in 420.

[0074] After determining the fourth end address addr_a_end, the fourth offset value offset4 = addr_a_end - addr_u_end = 0x0000f (i.e., 15 bytes) between the third end address addr_u_end = 0x100b0 and the fourth end address addr_a_end = 0x100bf can be further determined. After determining the value L of the fourth offset value offset4 (L is an integer, for example, 15 in this example), the last L bytes of data in the second read data can be removed or discarded, thereby allowing the first read data to be obtained from the second read data (as shown in 410). UDMAC 102 can send the converted first read data to the first device 101 that has arranged and processed the data according to the first data length (e.g., 1 byte) to complete the read operation.

[0075] Next, Figure 5 A schematic diagram of a data processing apparatus according to at least one embodiment of the present disclosure is shown.

[0076] like Figure 5 As shown, a data processing apparatus 500 according to at least one embodiment of the present disclosure may include a first interface 501, a first conversion module 502, a second conversion module 503, and a second interface 504, etc. In one embodiment, the data processing apparatus 500 may be a combination of the above. Figure 1 The UDMAC 102 is described above. In other embodiments, the data processing apparatus 500 may also include the combination described above. Figure 1 Any other data processing device of the UDMAC 102.

[0077] The first interface 501 can be used to receive a first request message from the first device 101. In some embodiments, the first request message may include a first address aligned to a first data length and a first size in units of the first data length.

[0078] The first conversion module 502 can be used to convert the first address into a second address aligned with the second data length. In some embodiments, the second data length can be greater than 2 times the first data length. N The length in bytes, where N is an integer greater than or equal to 1.

[0079] The second conversion module 503 can be used to convert the first size into a second size in units of the second data length.

[0080] The second interface 504 can be used to send a second request message to the second device 103, wherein the second request message may include a second address and a second size.

[0081] For example, the first conversion module 502 and the second conversion module 503 can be implemented by software, hardware, firmware or any combination thereof; for example, the first conversion module 502 and the second conversion module 503 can be implemented by converters or conversion circuits, respectively.

[0082] For example, the first interface 501 can be a bus interface (e.g., AXI interface, ACE interface, etc.) that interfaces or communicates with a computing device or its interface device (e.g., DMA interface device) that performs data arrangement and processing according to a first data length (e.g., 1 byte); the second interface 504 can be a bus interface (e.g., AXI interface, ACE interface, etc.) that performs data arrangement and processing according to a second data length (e.g., 32 bytes). For example, the first interface 501 and the second interface 504 can be implemented by software, hardware, firmware, or any combination thereof; for example, the first interface 501 and the second interface 504 can be implemented by bus interface circuits respectively.

[0083] In some implementations, converting a first address to a second address aligned with a second data length may include setting the low bits of the first address corresponding to the low bits of the 0 values ​​in the binary representation of the second data length to 0, thereby obtaining the second address.

[0084] In some implementations, converting the first size to a second size in units of the second data length may include: rounding up the quotient of the first size and the second data length to obtain an intermediate size in units of the second data length; determining a first boundary address based on a second address and the intermediate size; determining a first end address based on the first address and the first size; and determining the second size based on a comparison of the first end address and the first boundary address and the intermediate size.

[0085] In some implementations, determining the second size based on a comparison of the first end address and the first boundary address and an intermediate size may include: determining the intermediate size as the second size if the first end address is less than or equal to the first boundary address; and determining the intermediate size as the second size by adding 1 if the first end address is greater than the first boundary address.

[0086] In some implementations, the first request message may include a first write request message, which may also include first write data in units of a first data length. The data processing apparatus 500 may further include: a third conversion module for converting the first write data into second write data in units of a second data length; and a first processing module for including the second write data in the second request message.

[0087] In some implementations, converting the first write data into second write data in units of a second data length may further include: determining a first offset value between a first address and a second address; adding J zeros corresponding to the first data length before the first write data, where J is an integer with the same first offset value; determining a first end address based on the first address and a first size; determining a second end address based on the second address and a second size; determining a second offset value between the first end address and the second end address; and adding M zeros corresponding to the first data length after the first write data to generate the second write data, where M is an integer with the same second offset value.

[0088] In some embodiments, the data processing apparatus 500 may further include: a first generation module for generating an indication signal for indicating which data in the second write data is valid data corresponding to the first write data; and a second processing module for including the indication signal in a second request message.

[0089] In some implementations, the indication signal may include a first indication signal and a second indication signal, wherein the first indication signal may be used to indicate which data in the first second data length of the second written data is valid data corresponding to the first written data; and wherein the second indication signal is used to indicate which data in the last second data length of the second written data is valid data corresponding to the first written data.

[0090] In some implementations, the first request message may include a first read request message, and the data processing apparatus 500 may further include: a first receiving module for receiving second read data in units of a second data length from a second device based on a second address and a second size; a fourth conversion module for converting the second read data into first read data based on a first address and a first size; and a first sending module for sending the first read data to a first device.

[0091] In some implementations, converting second read data into first read data based on a first address and a first size may include: determining a third offset value between the first address and the second address; removing data corresponding to the first K lengths of the first data in the second read data, where K is an integer with the same third offset value; determining a third end address based on the first address and the first size; determining a fourth end address based on the second address and the second size; determining a fourth offset value between the third end address and the fourth end address; and removing data corresponding to the last L lengths of the first data in the second read data to generate the first read data, where L is an integer with the same fourth offset value.

[0092] In some implementations, the first device may be a direct memory access interface device, and the second device may be a data bus interface device.

[0093] In some implementations, the first data length can be 1 byte, and the second data length can be 2 bytes. N Bytes, where N is an integer greater than or equal to 1.

[0094] It should be understood that the data processing apparatus 500 according to embodiments of the present disclosure may further include performing any data processing method described in embodiments of the present disclosure (e.g., the data processing method 200 above and the combination thereof). Figures 1-4 Modules (of any other data processing methods described). Similarly, these modules can be implemented by software, hardware, firmware, or any combination thereof; for example, these modules can be implemented individually by functional circuits that implement their respective functions. Furthermore, these modules, as well as the various modules described above, can be implemented in an integrated manner in any combination, or they can be implemented individually.

[0095] Figure 6 A schematic diagram of another data processing apparatus according to at least one embodiment of the present disclosure is shown.

[0096] like Figure 6As shown, the data processing apparatus 600 according to an embodiment of the present disclosure may include at least one processor 601 and a storage device 602. The storage device 602 may store at least one program, which, when executed by the at least one processor 601, can cause the at least one processor 601 to implement any method according to an embodiment of the present disclosure, such as the data processing method 200 described above and the combination thereof. Figures 1-4 Any other data processing method described.

[0097] Furthermore, embodiments of this disclosure also provide an electronic device that may include a data processing apparatus 500 or 600 according to embodiments of this disclosure, and may perform or implement any method according to embodiments of this disclosure, such as the data processing method 200 described above and its combination with... Figures 1-4 Any other data processing method described.

[0098] For example, the electronic device may also include other devices that work in conjunction with the data processing device 500 or 600, such as the first device and the second device mentioned in the foregoing embodiments. The data processing device 500 or 600 is communicatively connected to the first device and the second device, respectively. For example, this communication connection may be based on a certain bus protocol, and the bus width (e.g., 16 bytes, 32 bytes, etc.) can be selected as needed; the embodiments of this disclosure do not limit this. For example, the electronic device may include, but is not limited to, personal computers (PCs), servers, mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), digital TVs, desktop computers, etc.

[0099] Figure 7 A schematic diagram of an example structure suitable for implementing an electronic device 700 according to at least one embodiment of the present disclosure is shown. The electronic device in the embodiments of the present disclosure may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 7 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0100] like Figure 7As shown, the electronic device 700 may include a processing device 701, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 702 or a program loaded from a storage device 706 into a random access memory (RAM) 703. For example, the processing device 701 may include a data processing device 500 or 600 according to embodiments of the present disclosure, and may perform or implement any method according to embodiments of the present disclosure, such as the data processing method 200 described above and the method in combination with... Figures 1-4 Any other data processing method described. As described above, the processing device 701 may also include other devices that cooperate with the data processing device 500 or 600, such as the first and second devices mentioned in the foregoing embodiments, such as a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose graphics processing unit (GPGPU), a tensor processor (TPU), a data processing unit (DPU), an artificial intelligence (AI) accelerator, a deep learning accelerator (DLA), etc. In some embodiments, various programs and data required for the operation of the electronic device 700 are also stored in the RAM 703. The processing device 701, ROM 702, and RAM 703 are connected to each other via a bus 704. An input / output (I / O) interface 705 is also connected to the bus 704.

[0101] Typically, the following devices can be connected to I / O interface 705: input devices 706 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 707 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 706 including, for example, magnetic tapes, hard disks, etc.; and communication devices 709. Communication device 709 allows electronic device 700 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 7 An electronic device 700 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively.

[0102] Furthermore, embodiments of this disclosure also provide a non-transitory storage medium containing computer-executable instructions, wherein the computer-executable instructions, when executed by a computer processor, are used to perform any method according to embodiments of this disclosure, such as the data processing method 200 described above and the method in combination with... Figures 1-4 Any other data processing method described.

[0103] The data processing method provided by the embodiments of this disclosure improves overall processing efficiency by converting the format of processing requests (e.g., read / write requests) so that processing requests can be easily switched between different hardware.

[0104] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device, or installed from a storage device, or installed from a ROM. When the computer program is executed by a processing device, it performs the functions defined above in the methods of embodiments of this disclosure.

[0105] It should be noted that the computer-readable medium described in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0106] In some implementations, clients and servers can communicate using any currently known or future-developed network protocol such as HTTP (Hypertext Transfer Protocol) and can interconnect with digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), the Internet (e.g., the Internet of Things), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future-developed networks.

[0107] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device.

[0108] The aforementioned computer-readable medium carries one or more programs that, when executed by the electronic device, cause the electronic device to: receive a first request message from a first device, wherein the first request message includes a first address aligned to a first data length and a first size in units of the first data length; convert the first address to a second address aligned to a second data length, wherein the second data length is greater than the first data length; convert the first size to a second size in units of the second data length; and send a second request message to a second device, wherein the second request message includes the second address and the second size.

[0109] Computer program code for performing the operations of this disclosure can be written in one or more programming languages ​​or a combination thereof, including but not limited to object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0110] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0111] The units described in the embodiments of this disclosure can be implemented in software or in hardware. The name of a unit does not necessarily limit the unit itself; for example, the first acquisition unit can also be described as "a unit that acquires at least two Internet Protocol addresses".

[0112] The functions described above in this document can be performed, at least in part, by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: Field Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application Standard Products (ASSPs), System-on-Chip (SoCs), Complex Programmable Logic Devices (CPLDs), and so on.

[0113] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0114] A data processing method is provided according to one or more embodiments of this disclosure, including:

[0115] Receive a first request message from a first device, wherein the first request message includes a first address aligned to a first data length and a first size in units of the first data length;

[0116] The first address is converted into a second address aligned with the second data length, wherein the second data length is greater than the first data length;

[0117] Convert the first size to a second size in units of the second data length; and

[0118] Send a second request message to the second device, wherein the second request message includes the second address and the second size.

[0119] According to one or more embodiments of this disclosure, converting the first address to a second address aligned with a second data length includes:

[0120] Set the low bit corresponding to the low bit of the 0 value in the binary representation of the second data length in the first address to 0 to obtain the second address.

[0121] According to one or more embodiments of this disclosure, converting the first size to a second size in units of the second data length includes:

[0122] The quotient of the first size and the second data length is rounded up to obtain the intermediate size in units of the second data length;

[0123] The first boundary address is determined based on the second address and the intermediate size;

[0124] Determine the first end address based on the first address and the first size; and

[0125] The second size is determined based on the comparison between the first end address and the first boundary address, and the intermediate size.

[0126] According to one or more embodiments of this disclosure, determining the second size based on a comparison of the first end address and the first boundary address and the intermediate size includes:

[0127] If the first end address is less than or equal to the first boundary address, the intermediate size is determined as the second size; and

[0128] If the first end address is greater than the first boundary address, the intermediate size is incremented by 1 to determine the second size.

[0129] According to one or more embodiments of this disclosure, wherein the first request message includes a first write request message, the first write request message further includes first write data in units of the first data length, and the method further includes:

[0130] Convert the first written data into a second written data in units of the second data length; and

[0131] Include the second write data in the second request message.

[0132] According to one or more embodiments of this disclosure, converting the first written data into second written data in units of the second data length includes:

[0133] Determine the first offset value between the first address and the second address;

[0134] Add J zeros corresponding to the first data length before the first data to be written, where J is an integer with the same offset value as the first data;

[0135] The first end address is determined based on the first address and the first size;

[0136] The second end address is determined based on the second address and the second size;

[0137] Determine the second offset value between the first end address and the second end address; and

[0138] M zeros corresponding to the first data length are added after the first written data to generate the second written data, where M is an integer with the same offset value as the second offset value.

[0139] According to one or more embodiments of this disclosure, the method further includes:

[0140] Generate an indication signal to indicate which data in the second written data is valid data corresponding to the first written data; and

[0141] Include the indication signal in the second request message.

[0142] According to one or more embodiments of this disclosure, the indication signal includes a first indication signal and a second indication signal, wherein,

[0143] The first indication signal is used to indicate which data in the first second data length of the second written data is valid data corresponding to the first written data; and wherein,

[0144] The second indication signal is used to indicate which data in the last second data length of the second written data is valid data corresponding to the first written data.

[0145] According to one or more embodiments of this disclosure, the first request message includes a first read request message.

[0146] The method further includes:

[0147] Based on the second address and the second size, receive second read data from the second device in units of the second data length;

[0148] Based on the first address and the first size, the second read data is converted into the first read data; and

[0149] The first read data is sent to the first device.

[0150] According to one or more embodiments of this disclosure, converting the second read data into first read data based on the first address and the first size includes:

[0151] Determine a third offset value between the first address and the second address;

[0152] Remove the first K data corresponding to the first data length from the second read data, where K is an integer that is the same as the third offset value;

[0153] The third end address is determined based on the first address and the first size;

[0154] The fourth end address is determined based on the second address and the second size;

[0155] Determine the fourth offset value between the third end address and the fourth end address; and

[0156] Remove the last L first data lengths from the second read data to generate the first read data, where L is the same integer as the fourth offset value.

[0157] According to one or more embodiments of this disclosure, the first device is a direct memory access interface device, and the second device is a data bus interface device.

[0158] According to one or more embodiments of this disclosure, the first data length is 1 byte, and the second data length is 2 bytes. N Bytes, where N is an integer greater than or equal to 1.

[0159] According to one or more embodiments of this disclosure, a data processing apparatus is provided, comprising:

[0160] A first interface is configured to receive a first request message from a first device, wherein the first request message includes a first address aligned to a first data length and a first size in units of the first data length;

[0161] A first conversion module is used to convert the first address into a second address aligned with a second data length, wherein the second data length is greater than the first data length;

[0162] The second conversion module is used to convert the first size into a second size in units of the second data length; and

[0163] The second interface is used to send a second request message to the second device, wherein the second request message includes the second address and the second size.

[0164] According to one or more embodiments of this disclosure, converting the first address to a second address aligned with a second data length includes:

[0165] Set the low bit corresponding to the low bit of the 0 value in the binary representation of the second data length in the first address to 0 to obtain the second address.

[0166] According to one or more embodiments of this disclosure, converting the first size to a second size in units of the second data length includes:

[0167] The quotient of the first size and the second data length is rounded up to obtain the intermediate size in units of the second data length;

[0168] The first boundary address is determined based on the second address and the intermediate size;

[0169] Determine the first end address based on the first address and the first size; and

[0170] The second size is determined based on the comparison between the first end address and the first boundary address, and the intermediate size.

[0171] According to one or more embodiments of this disclosure, determining the second size based on a comparison of the first end address and the first boundary address and the intermediate size includes:

[0172] If the first end address is less than or equal to the first boundary address, the intermediate size is determined as the second size; and

[0173] If the first end address is greater than the first boundary address, the intermediate size is incremented by 1 to determine the second size.

[0174] According to one or more embodiments of this disclosure, the first request message includes a first write request message, and the first write request message further includes first write data in units of the first data length.

[0175] The data processing device further includes:

[0176] The third conversion module is used to convert the first written data into second written data in units of the second data length; and

[0177] A first processing module is configured to include the second write data in the second request message.

[0178] According to one or more embodiments of this disclosure, converting the first written data into second written data in units of the second data length includes:

[0179] Determine the first offset value between the first address and the second address;

[0180] Add J zeros corresponding to the first data length before the first data to be written, where J is an integer with the same offset value as the first data;

[0181] The first end address is determined based on the first address and the first size;

[0182] The second end address is determined based on the second address and the second size;

[0183] Determine the second offset value between the first end address and the second end address; and

[0184] M zeros corresponding to the first data length are added after the first written data to generate the second written data, where M is an integer with the same offset value as the second offset value.

[0185] According to one or more embodiments of this disclosure, the data processing apparatus further includes:

[0186] A first generation module is configured to generate an indication signal that indicates which data in the second written data is valid data corresponding to the first written data; and

[0187] The second processing module is used to include the indication signal in the second request message.

[0188] According to one or more embodiments of this disclosure, the indication signal includes a first indication signal and a second indication signal, wherein,

[0189] The first indication signal is used to indicate which data in the first second data length of the second written data is valid data corresponding to the first written data; and wherein,

[0190] The second indication signal is used to indicate which data in the last second data length of the second written data is valid data corresponding to the first written data.

[0191] According to one or more embodiments of this disclosure, the first request message includes a first read request message.

[0192] The data processing device further includes:

[0193] The first receiving module is configured to receive second read data from the second device based on the second address and the second size, in units of the second data length;

[0194] The fourth conversion module is used to convert the second read data into first read data based on the first address and the first size; and

[0195] The first sending module is used to send the first read data to the first device.

[0196] According to one or more embodiments of this disclosure, converting the second read data into first read data based on the first address and the first size includes:

[0197] Determine a third offset value between the first address and the second address;

[0198] Remove the first K data corresponding to the first data length from the second read data, where K is an integer that is the same as the third offset value;

[0199] The third end address is determined based on the first address and the first size;

[0200] The fourth end address is determined based on the second address and the second size;

[0201] Determine the fourth offset value between the third end address and the fourth end address; and

[0202] Remove the last L lengths of the first data from the second read data to generate the first read data, where L is the same integer as the fourth offset value.

[0203] According to one or more embodiments of this disclosure, the first device is a direct memory access interface device, and the second device is a data bus interface device.

[0204] According to one or more embodiments of this disclosure, the first data length is 1 byte, and the second data length is 2 bytes. N Bytes, where N is an integer greater than or equal to 1.

[0205] A data processing apparatus is provided according to one or more embodiments of the present disclosure, comprising:

[0206] At least one processor; and

[0207] A storage device having at least one program stored thereon, which, when executed by the at least one processor, causes the at least one processor to implement any data processing method according to embodiments of the present disclosure.

[0208] An electronic device is provided according to one or more embodiments of the present disclosure, including any data processing apparatus according to embodiments of the present disclosure.

[0209] One or more embodiments of the present disclosure provide a non-transitory storage medium comprising computer-executable instructions, wherein the computer-executable instructions, when executed by a computer processor, are used to perform any data processing method according to embodiments of the present disclosure.

[0210] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0211] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0212] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

Claims

1. A data processing method, comprising: Receive a first request message from a first device, wherein the first request message includes a first address aligned to a first data length and a first size in units of the first data length; The first address is converted into a second address aligned with the second data length, wherein the second data length is greater than the first data length; Convert the first size to a second size in units of the second data length; and Send a second request message to the second device, wherein the second request message includes the second address and the second size. Converting the first size to a second size in units of the second data length includes: The quotient of the first size divided by the second data length is rounded up to obtain the intermediate size in units of the second data length; The first boundary address is determined based on the second address and the intermediate size; Determine the first end address based on the first address and the first size; and The second size is determined based on the comparison between the first end address and the first boundary address, and the intermediate size.

2. The method according to claim 1, wherein, Converting the first address to a second address aligned with the second data length includes: Set the low bit corresponding to the low bit of the 0 value in the binary representation of the second data length in the first address to 0 to obtain the second address.

3. The method according to claim 1, wherein, Determining the second size based on a comparison of the first end address and the first boundary address, and the intermediate size, includes: If the first end address is less than or equal to the first boundary address, the intermediate size is determined as the second size; and If the first end address is greater than the first boundary address, the intermediate size is incremented by 1 to determine the second size.

4. The method according to claim 1, wherein, The first request message includes a first write request message, and the first write request message further includes first write data in units of the first data length. The method further includes: Convert the first written data into a second written data in units of the second data length; and Include the second write data in the second request message.

5. The method according to claim 4, wherein, Converting the first written data into second written data in units of the second data length includes: Determine the first offset value between the first address and the second address; Add J zeros corresponding to the first data length before the first data to be written, where J is an integer with the same offset value as the first data; The first end address is determined based on the first address and the first size; The second end address is determined based on the second address and the second size; Determine the second offset value between the first end address and the second end address; and M zeros corresponding to the first data length are added after the first written data to generate the second written data, where M is an integer with the same offset value as the second offset value.

6. The method according to claim 4, further comprising: Generate an indication signal to indicate which data in the second written data is valid data corresponding to the first written data; as well as Include the indication signal in the second request message.

7. The method according to claim 6, wherein, The indication signal includes a first indication signal and a second indication signal, wherein, The first indication signal is used to indicate which data in the first second data length of the second written data is valid data corresponding to the first written data; and wherein, The second indication signal is used to indicate which data in the last second data length of the second written data is valid data corresponding to the first written data.

8. The method according to claim 1, wherein, The first request message includes a first read request message. The method further includes: Based on the second address and the second size, receive second read data from the second device in units of the second data length; Based on the first address and the first size, the second read data is converted into the first read data; and The first read data is sent to the first device.

9. The method according to claim 8, wherein, Based on the first address and the first size, converting the second read data into first read data includes: Determine a third offset value between the first address and the second address; Remove the first K data corresponding to the first data length from the second read data, where K is an integer that is the same as the third offset value; The third end address is determined based on the first address and the first size; The fourth end address is determined based on the second address and the second size; Determine the fourth offset value between the third end address and the fourth end address; and Remove the last L first data lengths from the second read data to generate the first read data, where L is the same integer as the fourth offset value.

10. The method according to claim 1, wherein, The first device is a direct memory access interface device, and the second device is a data bus interface device.

11. The method according to claim 1, wherein, The first data has a length of 1 byte, and the second data has a length of 2 bytes. N Bytes, where N is an integer greater than or equal to 1.

12. A data processing apparatus, comprising: A first interface is configured to receive a first request message from a first device, wherein the first request message includes a first address aligned to a first data length and a first size in units of the first data length; A first conversion module is used to convert the first address into a second address aligned with a second data length, wherein the second data length is greater than the first data length; The second conversion module is used to convert the first size into a second size in units of the second data length; and The second interface is used to send a second request message to the second device, wherein the second request message includes the second address and the second size. The second conversion module is further configured as follows: The quotient of the first size divided by the second data length is rounded up to obtain the intermediate size in units of the second data length; The first boundary address is determined based on the second address and the intermediate size; Determine the first end address based on the first address and the first size; and The second size is determined based on the comparison between the first end address and the first boundary address, and the intermediate size.

13. A data processing apparatus, comprising: At least one processor; and A storage device having stored at least one program thereon, which, when executed by the at least one processor, causes the at least one processor to implement the method as described in any one of claims 1-11.

14. An electronic device comprising the data processing apparatus as described in claim 12 or 13.

15. A non-transitory storage medium containing computer-executable instructions, wherein, The computer-executable instructions, when executed by a computer processor, are used to perform the method as described in any one of claims 1-11.

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