Integrated circuit wire optimization method and apparatus, electronic device, and storage medium

Abstract

The application provides an integrated circuit winding optimization method and device, electronic equipment and storage medium, and belongs to the technical field of integrated circuits. The method comprises the following steps: obtaining timing path index threshold information and winding index threshold information; performing static timing analysis on the integrated circuit after winding to obtain static timing information; determining key path information according to the static timing information and the timing path index threshold information; determining the driving position of the to-be-optimized interconnection line according to the key path information and the winding index threshold information; and resetting the winding attribute corresponding to the driving position of the to-be-optimized interconnection line to a via pillar winding attribute, so that the parasitic parameters of the interconnection line in the key path information are reduced, the part with large interconnection line delay is effectively reduced, and then the proportion of the interconnection line delay in the overall circuit delay is also reduced, which helps to meet the timing requirement, saves the area size and quantity of the driving unit, and can more accurately optimize the power consumption, performance and area of the integrated circuit.

Description

Technical Field

[0001] This application belongs to the field of integrated circuit technology, and in particular relates to an integrated circuit winding optimization method, apparatus, electronic device and storage medium. Background Technology

[0002] An integrated circuit (IC) is a miniature electronic device or component. Through a series of complex processes, an IC integrates electronic components such as transistors, resistors, capacitors, and inductors, along with their interconnections, to form a circuit with a specific function. IC wiring refers to the process of laying out and planning the metal wires connecting the various electronic components (such as transistors, resistors, and capacitors) during the design and manufacturing of an IC.

[0003] As advanced process technologies shrink the size of circuits, the width of interconnects between logic units in integrated circuits decreases. This leads to an increase in the parasitic parameters of each interconnect, resulting in a higher proportion of interconnect delay to overall circuit delay. Consequently, the power consumption, performance, and area of ​​integrated circuits are affected. Summary of the Invention

[0004] The purpose of this application is to provide an integrated circuit winding optimization method, apparatus, electronic device, and storage medium, which aims to solve the problem of high interconnect delay ratio in traditional methods.

[0005] This application provides a method for optimizing integrated circuit winding, including:

[0006] Obtain the time-series path indicator threshold information and the winding indicator threshold information;

[0007] Static timing analysis is performed on the wound integrated circuit to obtain static timing information;

[0008] Based on the static time series information and the time series path indicator threshold information, the critical path information is determined;

[0009] Based on the critical path information and the winding index threshold information, determine the driving position of the interconnect to be optimized;

[0010] Reset the winding attributes corresponding to the drive position of the interconnect to be optimized to the through-hole post winding attributes.

[0011] This application provides an integrated circuit winding optimization device, comprising:

[0012] The threshold information acquisition module is used to acquire the threshold information of time-series path indicators and the threshold information of winding indicators;

[0013] The timing analysis module is used to perform static timing analysis on the wound integrated circuit to obtain static timing information;

[0014] The critical path determination module is used to determine critical path information based on the static time series information and the time series path index threshold information;

[0015] The optimization position determination module is used to determine the driving position of the interconnect to be optimized based on the critical path information and the winding index threshold information.

[0016] The winding attribute reset module is used to reset the winding attribute corresponding to the drive position of the interconnect to be optimized to the through-hole post winding attribute.

[0017] This application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the method as described in any of the above embodiments.

[0018] This application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the method as described in any of the above embodiments.

[0019] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows:

[0020] The integrated circuit winding optimization method provided in this application, based on the static timing analysis information of the wound integrated circuit, uses timing path index threshold information as a screening criterion to identify critical paths with large delays, thereby optimizing these critical paths. Based on the critical path information, and using winding index threshold information as a screening criterion, the location of the interconnect with large delays within the critical path information is identified, thus determining the driving position of the interconnect to be optimized. The winding attribute corresponding to the driving position of the interconnect to be optimized is reset to a through-hole pillar winding attribute, replacing the original winding with a through-hole pillar winding.

[0021] For long-distance interconnects, using viapillar windings to connect different layers of metal wiring can significantly reduce parasitic resistance and capacitance, thus reducing line delay. Compared to traditional via winding techniques in advanced process technologies, this application sets viapillar windings (which can also be understood as windings with viapillars) at different drive positions of the interconnects to be optimized in the same metal layer. This is equivalent to connecting multiple metal wires in parallel in the same metal layer, effectively reducing coupling capacitance, parasitic capacitance, and resistance, thereby reducing the parasitic parameters of the interconnects. The reduction in parasitic parameters of the interconnects can reduce the interconnect delay in the critical path information, effectively reducing the portion of interconnect delay that is too large in the critical path information. Therefore, the reduction in interconnect delay in the critical path information can also reduce the proportion of interconnect delay to the overall circuit delay, which helps to meet timing requirements, provides more space for integrated circuit circuit structure optimization, saves the area and number of drive units, and enables more precise optimization of integrated circuit power consumption, performance, and area. Attached Figure Description

[0022] Figure 1 A flowchart illustrating the steps of an integrated circuit winding optimization method in one embodiment of this application;

[0023] Figure 2 A flowchart illustrating the steps of an integrated circuit winding optimization method in one embodiment of this application;

[0024] Figure 3 A schematic flowchart illustrating the line delay determination steps in one embodiment provided in this application;

[0025] Figure 4 A schematic flowchart illustrating the determination steps for line load in one embodiment provided in this application;

[0026] Figure 5 A flowchart illustrating the steps for determining line length in one embodiment provided in this application;

[0027] Figure 6 A flowchart illustrating the steps for determining line delay, line load, and line length in one embodiment provided in this application;

[0028] Figure 7 A flowchart illustrating the steps of an integrated circuit winding optimization method in one embodiment of this application;

[0029] Figure 8 This is a timing path diagram of a module in an integrated circuit after winding, provided in one embodiment of this application;

[0030] Figure 9This is a schematic diagram of the integrated circuit winding optimization device in one embodiment of this application;

[0031] Figure 10 This is a schematic diagram of the structure of an electronic device in one embodiment provided in this application. Detailed Implementation

[0032] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0033] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0034] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0035] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0036] Please see Figure 1 This application provides a method for optimizing integrated circuit winding, comprising:

[0037] Step S10: Obtain the time-series path index threshold information and the winding index threshold information;

[0038] Step S20: Perform static timing analysis on the wound integrated circuit to obtain static timing information;

[0039] Step S30: Determine the critical path information based on the static time series information and the time series path indicator threshold information;

[0040] Step S40: Determine the driving position of the interconnect to be optimized based on the critical path information and the winding index threshold information;

[0041] Step S50: Reset the winding attribute corresponding to the drive position of the interconnect to be optimized to the through-hole post winding attribute.

[0042] In this embodiment, in step S10, the timing path indicator threshold information can be understood as indicator thresholds related to timing paths in the integrated circuit. The timing path indicator threshold information may include setup time margin thresholds, hold time margin thresholds, and other threshold information that characterizes timing paths. The wiring indicator threshold information can be understood as indicator thresholds related to interconnects in the integrated circuit. The wiring indicator threshold information includes line delay thresholds, line load thresholds, line length thresholds, and other threshold information that characterizes interconnects. The timing path indicator threshold information and the wiring indicator threshold information can vary depending on the process node, power supply voltage, and design density in the actual application scenario, and the specific values ​​can be adjusted according to the actual application scenario.

[0043] In step S20, Static Timing Analysis (STA) is the process of determining whether timing requirements are met by analyzing the delays and timing constraints of each timing path in the integrated circuit. Static timing information can be understood as the static timing analysis result formed after performing static timing analysis on the wound integrated circuit.

[0044] Static timing information includes information that characterizes the integrated circuit, such as the delay time of each timing path, the start and end points of each timing path, the type of each timing path, setup time violations, hold time violations, clock cycle violations, setup time margin, hold time margin, clock cycle time margin, input / output delay, line load, line delay, line length, and timing report summary.

[0045] A timing path can be understood as the signal propagation path of a signal from the clock edge of one component in an integrated circuit to the clock edge of another component. The starting point of a timing path can be a clock source, an input port, or the output of a memory element (such as a register). The ending point of a timing path can be the input of a memory element, an output port, or another clock source. A timing path includes a series of logic units (such as AND gates, OR gates, NOT gates, etc.) and interconnects. Signals undergo logical operations within the logic units and propagate through the interconnects. The delays of the logic units and the interconnects together determine the total delay of the timing path.

[0046] In step S30, the static timing information includes multiple timing paths, each with corresponding path parameters, such as setup time margin, hold time margin, and clock cycle time margin. Critical path information can be understood as the information corresponding to the longest delay paths traversed by a signal during transmission, from the clock edge of one component to the clock edge of another. Using timing path index thresholds as a filtering criterion, the timing paths with long delays are selected from the static timing information as critical path information. Furthermore, routing optimization is performed on the long-delay critical paths.

[0047] In step S40, each critical path includes multiple interconnects. An interconnect is part of the critical path and can be understood as a signal transmission link. Using the winding index threshold information as a screening criterion, the line characteristic values ​​of each interconnect in the critical path information are compared with the winding index threshold to screen out the interconnects that need optimization, obtain the driving port of the interconnect to be optimized, and thus determine the driving position of the interconnect to be optimized. The driving position of an interconnect can be understood as the position corresponding to the driving port of the interconnect during signal transmission, or as the port that provides signal driving to the interconnect. In one embodiment, when buffer 1 outputs a signal to the interconnect and transmits it through the interconnect to buffer 2 for reception, if the interconnect between buffer 1 and buffer 2 is the interconnect to be optimized, then the output port of buffer 1 is the driving port of the interconnect to be optimized, which is the driving position of the interconnect to be optimized.

[0048] By using timing path index threshold information and routing index threshold information, interconnects that need to be optimized can be screened from static timing information and critical path information, respectively. This can reduce the line network load formed by interconnects in critical path information from the physical routing design level of signal line network, which can save area and power consumption, and thus more effectively improve the power consumption, performance and area of ​​integrated circuits without over-design.

[0049] In step S50, after obtaining the driving position of the interconnect to be optimized, the original winding attribute at the driving position of the interconnect to be optimized is deleted, and it is reset to viapillar winding. A viapillar is a vertical conductive structure used to connect metal wiring of different layers, which can play a role in conducting current and transmitting signals in multilayer integrated circuits. For long-distance interconnects, using viapillar winding to connect metal wiring of different layers can greatly reduce the parasitic resistance and parasitic capacitance of long-distance interconnects and reduce line delay.

[0050] In advanced process technologies, traditional via-hole winding technology results in only a single via and current path per metal layer, leading to high impedance. Compared to traditional via-hole winding in advanced process technologies, the via-pillar winding (which can also be understood as winding with a viapillar) provided in this application increases the number of vias, expands the current path, reduces signal resistance and capacitance during transmission, and decreases signal delay and power consumption.

[0051] This application utilizes via-pillar windings (which can also be understood as windings with viapillars) at different drive positions of the interconnects to be optimized within the same metal layer. This is equivalent to connecting multiple metal lines in parallel within the same metal layer, effectively reducing coupling capacitance, parasitic capacitance, and resistance. This reduces the parasitic parameters of the interconnects, thereby significantly reducing interconnect delay and consequently lowering voltage drop and power loss during signal transmission. The reduced interconnect delay allows the integrated circuit to integrate fewer large drive units and low-threshold units, enabling more precise optimization of the integrated circuit's power consumption, performance, and area.

[0052] Therefore, the integrated circuit winding optimization method provided in this application, based on the static timing analysis information of the wound integrated circuit, uses timing path index threshold information as the screening criterion to filter out critical path information with large delays, thereby optimizing the critical paths with large delays. Based on the critical path information, using winding index threshold information as the screening criterion, the positions of interconnects with large delays in the critical path information are screened out, and then the driving positions of the interconnects to be optimized are determined. The winding attributes corresponding to the driving positions of the interconnects to be optimized are reset to through-hole pillar winding attributes, replacing the original winding with through-hole pillar winding, reducing the parasitic parameters of the interconnects, thereby reducing the delay of the interconnects in the critical path information, and effectively reducing the portion of interconnects with excessive delay in the critical path information. Thus, the reduction of the interconnect delay in the critical path information can reduce the proportion of interconnect delay to the overall circuit delay, which helps to meet timing requirements, provides more space for integrated circuit circuit structure optimization, saves the area and number of driving units, and enables more precise optimization of the integrated circuit's power consumption, performance, and area.

[0053] Please see Figure 2 In one embodiment, step S10, the step of obtaining the timing path index threshold information and the winding index threshold information, includes:

[0054] Step S110: Obtain the process node, power supply voltage, and design density;

[0055] Step S120: Based on the adaptive threshold setting mechanism, determine the timing path index threshold information and the winding index threshold information according to the process node, power supply voltage and design density.

[0056] In this embodiment, the process node is a marker of the technological level employed in integrated circuit manufacturing, representing the minimum size of semiconductor devices such as transistors. The power supply voltage is the voltage value that provides power to the integrated circuit. This voltage is supplied by an external power source and distributed to various circuit modules through the power network on the integrated circuit. Design density is the number of logic gates or transistors that can be implemented per unit area on the integrated circuit, reflecting the degree of integration at the design level. The process node, power supply voltage, and design density interact to determine the performance, power consumption, and area of ​​the integrated circuit. In integrated circuit design, appropriately selecting the process node, power supply voltage, and design density allows for more precise optimization of the integrated circuit's power consumption, performance, and area.

[0057] Process node, power supply voltage, and design density are design parameters for integrated circuits, which can be set according to the actual application scenario. Adaptive threshold setting mechanisms can employ statistical or machine learning-based methods. These mechanisms establish relationships between process node, power supply voltage, design density, and timing path and routing parameter thresholds. Process node, power supply voltage, and design density serve as input parameters to the adaptive threshold setting mechanism. Timing path and routing parameter thresholds serve as output parameters. The adaptive threshold setting mechanism adaptively adjusts based on different application scenarios with varying process nodes, power supply voltages, and design densities to obtain the appropriate timing path and routing parameter thresholds.

[0058] An adaptive threshold setting mechanism is employed, inputting parameters such as process node, power supply voltage, and design density to generate adaptive thresholds, thereby determining the timing path index thresholds and winding index thresholds. This mechanism adapts to dynamic changes in process node, power supply voltage, and design density, dynamically adjusting the corresponding timing path index and winding index thresholds accordingly. Therefore, the adaptive threshold setting mechanism automatically learns the characteristics and trends of the data, adjusting thresholds without manual intervention. It is applicable to different input parameters, improving the accuracy and reliability of the timing path index and winding index threshold information.

[0059] In one embodiment, step S120, the step of determining timing path index threshold information and winding index threshold information based on the adaptive threshold setting mechanism, according to the process node, power supply voltage, and design density, includes:

[0060] Step a: Using the power consumption, performance, and area of ​​the integrated circuit as reward mechanisms, and based on machine reinforcement learning algorithms, determine the timing path index threshold information and the winding index threshold information according to the process node, power supply voltage, and design density.

[0061] In this embodiment, the machine reinforcement learning algorithm can be Q-learning, policy gradient, deep Q network (DQN), or dynamic programming. The reward mechanism is based on the integrated circuit's power consumption, performance, and area. Power consumption, performance, and area are key indicators for evaluating the quality of integrated circuit design. By using these three indicators as reward mechanisms, trade-offs and optimizations can be made among them to meet design requirements. Using the degree of improvement in power consumption, performance, and area as a reward mechanism, the timing path indicator threshold and routing indicator threshold are dynamically adjusted during the design process using reinforcement learning algorithms in machine learning. The threshold that achieves the optimal power consumption, performance, and area (i.e., PPA) optimization effect is used as the output threshold of the machine reinforcement learning algorithm, namely the timing path indicator threshold information and the routing indicator threshold information. Machine reinforcement learning algorithms can adapt to dynamic changes in design requirements for different process nodes, power supply voltages, and design densities. They can dynamically adjust adaptive thresholds in a timely manner to obtain timing path indicator thresholds and wiring indicator thresholds, enabling more precise optimization of integrated circuit power consumption, performance, and area. Therefore, based on the timing path indicator thresholds and wiring indicator thresholds, it can determine whether to reset the wiring attributes of the interconnect to be optimized to via pillar wiring attributes, thereby optimizing the wiring of integrated circuits and reducing the proportion of interconnect delay in the integrated circuit.

[0062] In one embodiment, step S20, which involves performing static timing analysis on the wound integrated circuit to obtain static timing information, includes:

[0063] Step S210: Extract the parasitic parameters of the integrated circuit after winding;

[0064] Step S220: Based on parasitic parameters, perform static timing analysis on the wound integrated circuit using a static timing analysis tool to obtain static timing information.

[0065] In this embodiment, parasitic parameters can be understood as electrical parameters in integrated circuits that are not intentionally added or designed by the designer, but are unavoidable due to the physical structure and manufacturing process of the integrated circuit. Parasitic parameters include parasitic capacitance, parasitic resistance, and parasitic inductance. The various logic units in an integrated circuit are connected by interconnects. Interconnects are made of conductive materials, such as metals, and generate parasitic parameters (e.g., line resistance, line capacitance, line inductance). The line resistance, line capacitance, and line inductance of interconnects form the line load of the interconnects, which affects the signal transmission and circuit performance of the integrated circuit.

[0066] In step S210, parasitic parameters are extracted from the wire-wound integrated circuit. These parasitic parameters can be incorporated into the static timing analysis, thereby enabling a more accurate analysis of the integrated circuit's performance and obtaining more accurate static timing analysis results, i.e., static timing information. In one embodiment, parasitic parameter extraction tools, such as Cadence's Assura and Synopsys' StarRC, can automatically extract parasitic parameters from the circuit layout and generate corresponding parasitic parameter files for circuit simulation and analysis. In step S220, the static timing analysis tool can be PrimeTime, Design Compiler, TimeQuest, or other static timing analysis tools to perform static timing analysis on the wire-wound integrated circuit.

[0067] In one embodiment, step S30, the step of determining critical path information based on static time-series information and time-series path indicator threshold information, includes:

[0068] Step S310: Traverse each establishment time violation path in the static timing information;

[0069] Step S320: Determine whether the absolute value of the establishment time margin of the current establishment time violation path is greater than the establishment time margin threshold in the time sequence path indicator threshold information.

[0070] Step S330: If yes, then the current creation time violation path is identified as critical path information;

[0071] If not, skip the current setup time violation path and continue to execute step S310, traversing the steps of each setup time violation path in the static timing information.

[0072] In this embodiment, in the integrated circuit, static timing information refers to the static timing analysis results formed after static timing analysis of the wound integrated circuit. Static timing information includes the delay time of each timing path, the start and end points of each timing path, the type of each timing path, setup time violation paths, hold time violation paths, clock cycle violation paths, setup time margin paths, hold time timing margins, clock cycle timing margins, input / output delays, and timing report summaries, etc. Setup time violation paths and their corresponding setup time margins within the timing paths form the setup time violation paths in step S310.

[0073] A setup timing violation path can be understood as a timing violation that occurs because there is insufficient time for the data to stabilize before the valid edge of the clock signal arrives; it can also be understood as a timing violation path. In one embodiment, a register requires data to stabilize 500ps before the rising edge of the clock, but the actual data stabilizes at 450ps, thus a setup timing violation path has occurred. Setup timing violation paths prevent data from being correctly sampled and stored, thereby affecting the functionality of the integrated circuit.

[0074] Setup time margin can be understood as the amount of time remaining after the data has met the setup time requirement. A positive setup time margin indicates that the data has sufficient time to stabilize, and the integrated circuit is reliable in terms of setup time. A negative setup time margin indicates the existence of a corresponding setup time violation path. Therefore, the setup time margin corresponding to a setup time violation path is negative. In one embodiment, if the setup time requirement for a timing path is 500 ps and the actual data stabilization time is 550 ps, ​​then the setup time margin is 50 ps, ​​which is positive. In another embodiment, if the setup time requirement for a timing path is 500 ps and the actual data stabilization time is 450 ps, ​​then the setup time margin is -50 ps, ​​which is negative. The setup time margin can be used to evaluate the reliability of the integrated circuit in terms of setup time and determine whether optimization is needed.

[0075] Since the establishment time margin corresponding to the establishment time violation path is negative, when searching for each establishment time violation path in the static time series information, it is determined whether the absolute value of the establishment time margin corresponding to the establishment time violation path is greater than the establishment time margin threshold. In this embodiment, the establishment time margin threshold is set to a positive value and can be obtained through the method provided in step a. Based on the establishment time margin threshold, multiple establishment time violation paths in the static time series information are filtered. If the absolute value of the establishment time margin of the current establishment time violation path is greater than the establishment time margin threshold, the current establishment time violation path is used as critical path information. If the absolute value of the establishment time margin of the current establishment time violation path is less than or equal to the establishment time margin threshold, the current establishment time violation path is skipped, and the subsequent step S40 is not performed. Instead, step S310 is executed to judge the next establishment time violation path until multiple establishment time violation paths in the static time series information have been traversed.

[0076] The establishment time margin threshold set in the timing path indicator threshold information provided in step a allows for more precise optimization of the integrated circuit's power consumption, performance, and area. Using the establishment time margin threshold as the filtering criterion, steps S310 to S340 iterate through each establishment time violation path in the static timing information, filtering out critical path information as timing paths requiring further optimization and routing. Therefore, by using the establishment time margin threshold as the filtering criterion in steps S310 to S340, critical path information can be filtered from the static timing information, accurately determining the timing path information that needs optimization and reducing routing optimization time.

[0077] In one embodiment, step S40, the step of determining the drive position of the interconnect to be optimized based on critical path information and winding index threshold information, includes:

[0078] Step S410: Traverse each interconnect in the critical path information;

[0079] Step S420: Determine whether the current interconnect line characteristic value is greater than the line threshold in the winding index threshold information;

[0080] Step S430: If yes, then determine the driving position corresponding to the current interconnect as the driving position of the interconnect to be optimized.

[0081] If not, skip the current interconnect in step S440 and continue with step S410, iterating through each interconnect in the critical path information.

[0082] In this embodiment, each critical path includes multiple interconnects. An interconnect is a part of the critical path and can be understood as a signal transmission link. One interconnect corresponds to one timing arc. Alternatively, each critical path can be understood as including multiple timing arcs. Interconnects will generate line characteristic values ​​such as line load, line delay, and line length, affecting the delay of the interconnect. The line threshold in the winding index threshold information can be obtained using the method provided in step a. The line threshold can be a line load threshold, line delay threshold, or line length threshold, etc., that characterizes the interconnect's features.

[0083] Based on a line threshold, multiple interconnects in the critical path are filtered. If the line feature value of the current interconnect is greater than the line threshold, the line driving position of the current interconnect is taken as the driving position of the interconnect to be optimized. If the line feature value of the current interconnect is less than or equal to the line threshold, the current interconnect is skipped, and step S50 is not performed. Instead, step S410 is executed to determine the next interconnect, until multiple interconnects in the critical path have been traversed. In this embodiment, the driving position of the interconnect to be optimized can also be understood as the driving port of the interconnect to be optimized.

[0084] The setting of the line threshold in the winding index threshold information provided in step a can more accurately optimize the power consumption, performance, and area of ​​the integrated circuit. Using the line threshold as the filtering basis, through steps S410 to S440, each interconnect in the critical path is traversed to filter out the line driving positions as the driving positions of the interconnects to be optimized. Therefore, through steps S410 to S440, using the line threshold as the filtering basis, the driving positions of the interconnects to be optimized can be filtered out from the critical path, accurately determining the driving positions that need to be optimized for winding, reducing winding optimization time, and improving the accuracy and efficiency of winding optimization. After determining the driving positions of the interconnects to be optimized, step S50 is executed to reset the winding attributes corresponding to the driving positions of the interconnects to be optimized to via pillar winding attributes. Therefore, after establishing the time margin threshold and line threshold filtering in steps S310 to S340 and steps S410 to S440, the filtered interconnects are the lines that need to be optimized using via pillars for winding. Therefore, the winding attributes corresponding to the drive position of the interconnect to be optimized are reset to the through-hole pillar winding attributes, and the winding is re-wound, which reduces the parasitic parameters generated by the interconnect, thereby reducing the interconnect delay and enabling more precise optimization of the integrated circuit's power consumption, performance, and area.

[0085] Please see Figure 3 In one embodiment, step S420, determining whether the current interconnect line feature value is greater than the line threshold in the winding index threshold information, includes:

[0086] Step S421: Determine whether the current interconnect line delay is greater than the line delay threshold in the winding index threshold information.

[0087] In this embodiment, line characteristic values ​​include line load, line delay, line length, and other characteristic information that characterizes the interconnect. Line load includes line resistance, line capacitance, and line inductance. Line load can also be understood as parasitic parameters generated by the interconnect. The line delay threshold can be understood as a limit value set for the maximum allowable delay time for signal transmission by the interconnect (or signal line) in the integrated circuit. The line delay threshold is obtained through the method provided in step a, which can more accurately optimize the power consumption, performance, and area of ​​the integrated circuit.

[0088] Based on the line delay threshold, if the line delay of the current interconnect is greater than the line delay threshold, it indicates that the current interconnect needs to be optimized. Step S430 is executed to determine the driving position of the current interconnect as the driving position of the interconnect to be optimized. If the line delay of the current interconnect is less than or equal to the line delay threshold, it indicates that the current interconnect does not need to be optimized. Then step S440 is executed to skip the current interconnect and continue to determine the threshold of the next interconnect in the critical path information.

[0089] By determining the line delay threshold in step S421, the interconnects that need optimization can be accurately located in the critical path information, thus pinpointing the driving position of the interconnect to be optimized. The winding attribute corresponding to the driving position of the interconnect to be optimized is then reset to a via post winding attribute, and the winding is re-entered to reduce the interconnect delay. This allows for more precise optimization of the integrated circuit's power consumption, performance, and area.

[0090] Please see Figure 4 In one embodiment, step S420, determining whether the current interconnect line characteristic value is greater than the line threshold in the winding index threshold information, further includes:

[0091] Step S422: Determine whether the current line load of the interconnect is greater than the line load threshold in the winding index threshold information.

[0092] In this embodiment, the line load threshold can be understood as a limit value set for the maximum line load allowed to be transmitted by interconnects (or signal lines) in an integrated circuit. The line load threshold is obtained through the method provided in step a, which enables more precise optimization of the integrated circuit's power consumption, performance, and area.

[0093] Using the line load threshold as the criterion, if the line load of the current interconnect is greater than the line load threshold, it indicates that the current interconnect needs to be optimized. Step S430 is executed, and the driving position corresponding to the current interconnect is determined as the driving position of the interconnect to be optimized. If the line load of the current interconnect is less than or equal to the line load threshold, it indicates that the current interconnect does not need to be optimized. Step S440 is then executed, skipping the current interconnect and continuing with the threshold judgment of the next interconnect in the critical path information. By judging the line load threshold of the interconnect in step S422, the interconnect that needs to be optimized can be accurately located in the critical path information, thus accurately finding the driving position of the interconnect to be optimized. Therefore, the winding attribute corresponding to the driving position of the interconnect to be optimized is reset to the through-hole pillar winding attribute, and rewinding is performed to reduce the interconnect delay, enabling more precise optimization of the integrated circuit's power consumption, performance, and area.

[0094] Please see Figure 5 In one embodiment, step S420, determining whether the current interconnect line characteristic value is greater than the line threshold in the winding index threshold information, further includes:

[0095] Step S423: Determine whether the current interconnect length is greater than the line length threshold in the winding index threshold information.

[0096] In this embodiment, line length can be understood as the winding length of the interconnect or simply the length of the interconnect. In integrated circuits, as the interconnect length increases, the line resistance, line capacitance, and line inductance also increase accordingly; this can also be understood as the parasitic resistance, parasitic capacitance, and parasitic inductance also increasing accordingly. The line length of the interconnect has a significant impact on parasitic parameters (such as resistance, capacitance, and inductance), thus requiring reasonable control of the interconnect length to reduce the adverse effects of parasitic parameters on integrated circuit performance. Both the line length and line load of the interconnect affect the line delay. Line load and line length are interrelated and jointly affect line delay. Increasing the line length increases the line load, thereby further increasing the line delay.

[0097] The line length threshold can be understood as a limit value set for the maximum allowable line length of an interconnect (or signal line) in an integrated circuit to transmit signals. The line length threshold is obtained through the method provided in step a, enabling more precise optimization of the integrated circuit's power consumption, performance, and area. Based on the line length threshold, if the line length of the current interconnect is greater than the threshold, it indicates that the current interconnect needs optimization. Step S430 is executed, determining the driving position of the current interconnect as the driving position of the interconnect to be optimized. If the line length of the current interconnect is less than or equal to the line length threshold, it indicates that the current interconnect does not need optimization. Step S440 is then executed, skipping the current interconnect and continuing with the threshold judgment of the next interconnect in the critical path information.

[0098] Step S423, which determines the line length threshold of the interconnect, allows for precise location of the interconnect requiring optimization within the critical path information. This enables accurate identification of the drive position of the interconnect to be optimized. Consequently, the winding attribute corresponding to the drive position of the interconnect to be optimized is reset to a through-hole pillar winding attribute, and the winding is re-performed to reduce interconnect latency. This allows for more precise optimization of the integrated circuit's power consumption, performance, and area.

[0099] In one embodiment, in step S420, steps S421, S422, or S423 can all be used to accurately locate the interconnect that needs to be optimized in the critical path information, thereby determining the driving position of the interconnect to be optimized. In another embodiment, in step S420, by continuously judging steps S421 and S422, or continuously judging steps S421 and S423, or continuously judging steps S422 and S423, it is also possible to accurately locate the interconnect that needs to be optimized in the critical path information, thereby determining the driving position of the interconnect to be optimized.

[0100] Please see Figure 6 In one embodiment, in step S420, through steps S421, S422 and S423, it is possible to accurately locate the interconnect that needs to be optimized in the critical path information, and thus determine the driving position of the interconnect to be optimized.

[0101] In this embodiment, in step S421, it is determined whether the current interconnect line delay is greater than the line delay threshold in the winding index threshold information. If yes, step S422 is executed. If no, step S440 is executed. In step S422, it is determined whether the current interconnect line load is greater than the line load threshold in the winding index threshold information. If yes, step S423 is executed. If no, step S440 is executed. In step S423, it is determined whether the current interconnect line length is greater than the line length threshold in the winding index threshold information. If yes, step S430 is executed. If no, step S440 is executed. Through the multi-layer threshold judgment in steps S421, S422, and S423, the threshold judgment of the line delay, line load, and line length of the interconnect in the critical path information is realized in sequence. It can accurately locate the interconnect that needs to be optimized from multiple perspectives and avoid blind optimization. Therefore, by using multi-level threshold judgments in steps S421, S422, and S423, the optimization accuracy and efficiency of the integrated circuit winding optimization method can be further improved.

[0102] Therefore, by performing line threshold judgment through one or more judgment steps in steps S421, S422 and S423 of step S420 in this application, the driving position of the interconnect to be optimized can be determined. This allows for precise location of the interconnect to be optimized in the critical path information, and the winding attribute corresponding to the driving position of the interconnect to be optimized can be reset to the through-hole pillar winding attribute for rewinding, thereby reducing the interconnect delay and enabling more precise optimization of the integrated circuit's power consumption, performance and area.

[0103] Please see Figure 7 In one embodiment, after step S430, which determines the driving position corresponding to the current interconnect as the driving position of the interconnect to be optimized, the method further includes:

[0104] Step S450: Determine whether the winding density at the drive position of the interconnect to be optimized is less than the winding density threshold.

[0105] If so, then proceed to step S50, which is to reset the winding attribute corresponding to the drive position of the interconnect to be optimized to the through-hole post winding attribute.

[0106] If not, proceed to step S440, skip the current interconnect, and continue to step S410, iterating through each interconnect in the critical path information.

[0107] In this embodiment, wiring density can be understood as the length or number of metal interconnects per unit area in an integrated circuit, reflecting the compactness of the integrated circuit at the wiring level. Wiring density can reflect whether wiring resources are sufficient or whether the wiring area is tight. Integrated circuit design rules impose limitations on wiring density. In one embodiment, wiring density can be obtained through design tool analysis, physical measurement and observation, or theoretical calculation and model prediction. Excessive wiring density will increase interconnect latency, thereby affecting the performance of the integrated circuit. The wiring density threshold can be understood as a limit value set for the maximum allowed wiring density for signal transmission by interconnects (or signal lines) in an integrated circuit. Using the winding density threshold as a criterion, if the winding density at the drive position of the interconnect to be optimized is less than the winding density threshold, it indicates that there are sufficient winding resources at the drive position of the interconnect to be optimized, and that the winding area at the drive position of the interconnect to be optimized is not strained. Therefore, at the drive position of the interconnect to be optimized, the original winding can be deleted and re-wound with via pillars, which can make more efficient use of winding resources, reduce interconnect delay, and more accurately optimize the power consumption, performance, and area of ​​the integrated circuit.

[0108] Using the winding density threshold as a criterion, if the winding density at the drive position of the interconnect to be optimized exceeds the threshold, it indicates that there are insufficient winding resources at the drive position of the interconnect to be optimized, and also indicates that the winding area at the drive position of the interconnect to be optimized is tight. Therefore, the current interconnect is skipped, and the threshold judgment of the next interconnect in the critical path information continues. By judging the winding density at the drive position of the interconnect to be optimized in step S450, it can be determined whether a via pillar can be re-wound at this position, avoiding the problem of increased interconnect delay caused by excessive winding density.

[0109] In one embodiment, after step S50, which resets the winding attribute corresponding to the drive position of the interconnect to be optimized to the through-hole pillar winding attribute, the integrated circuit winding optimization method further includes:

[0110] Step S60: Based on the through-hole post winding properties, the driving position of the interconnect to be optimized is rewound to obtain the rewound integrated circuit. Steps S20 to S50 are then executed on the rewound integrated circuit, and the process is repeated until there are no interconnects that need to be optimized in the integrated circuit.

[0111] In this embodiment, after deleting the original winding at the drive location of the interconnect to be optimized in step S60, the via pillar is rewound to obtain the rewound integrated circuit. The rewound integrated circuit can then undergo further winding optimization and timing iteration convergence. The relevant optimization steps can be referred to the descriptions in the above embodiments, enabling more precise optimization of the integrated circuit's power consumption, performance, and area.

[0112] In one embodiment, after step S60, which involves rewinding the drive position of the interconnect to be optimized according to the via post winding properties to obtain the rewound integrated circuit, the integrated circuit winding optimization method further includes:

[0113] Step S70 involves inspecting and correcting the rewound integrated circuit according to design rule inspection criteria. In this embodiment, performing a rewinding design rule inspection and correction on the rewound viapillar of the integrated circuit allows for the inspection and correction of some interconnects after forced rewinding optimization, avoiding optimization errors and enabling more precise optimization of the integrated circuit's power consumption, performance, and area. In this embodiment, step S70 allows the integrated circuit rewinding optimization method to ensure that the rewound integrated circuit design meets manufacturing requirements even without the rewinding density judgment in step S450 (which can also be understood as a judgment on whether the winding resources are sufficient or whether the winding area is tight), and can directly perform viapillar rewinding. This allows for more precise optimization of the integrated circuit's power consumption, performance, and area.

[0114] In one embodiment, a Design Rule Check (DRC) is used to inspect and correct the rewound integrated circuit, ensuring that the design of the rewound integrated circuit meets manufacturing requirements and that the integrated circuit can be correctly manufactured during the manufacturing process. The DRC checks whether parameters such as transistor size, metal line width and spacing, and via size in the rewound via pillars conform to relevant rules. The DRC allows for early detection and correction of issues. In one embodiment, Electronic Design Automation (EDA) tools are used to perform the DRC check on the rewound integrated circuit.

[0115] Therefore, by checking and correcting the rewound integrated circuit in step S70, even when routing resources or performance timing are prioritized, forcibly setting viapillar routing attributes for some routing can still ensure that the rewound integrated circuit design meets manufacturing requirements. This allows for more precise optimization of the integrated circuit's power consumption, performance, and area. Furthermore, by checking and correcting the rewound integrated circuit in step S70, it can be ensured that in areas where the routing density exceeds the routing density threshold (which can also be understood as areas of tight routing or insufficient routing resources) or areas where viapillars are prohibited, adding viapillar routing attributes will not affect the integrated circuit, further improving the optimization efficiency of the integrated circuit routing optimization method.

[0116] In one embodiment, after step S20, which involves performing static timing analysis on the wound integrated circuit to obtain static timing information, the integrated circuit winding optimization method further includes:

[0117] Step S30': Outside the prohibited addition area, execute step S30, which is the step of determining critical path information based on static time series information and time series path indicator threshold information.

[0118] In this embodiment, the prohibited addition area can be understood as an area with severe congestion due to limited winding resources, or an area in the integrated circuit with high winding requirements, such as a high-speed signal transmission area, a critical logic module area, or an analog signal processing area. Adding via pillars within the prohibited addition area will cause winding congestion. Therefore, by executing subsequent steps S30 to S50 outside the prohibited addition area in step S30', it is possible to ensure that the winding of the area requiring optimization is more accurately performed without affecting the normal winding of the prohibited addition area, thereby more accurately optimizing the power consumption, performance, and area of ​​the integrated circuit. In one embodiment, the prohibited addition area can be set according to the actual application scenario and can be set before steps S30 to S50, further narrowing the winding optimization area, improving the efficiency of integrated circuit winding optimization, more accurately screening the interconnects that need to be optimized, and reducing the latency of interconnects in critical path information.

[0119] Please see Figure 8In one embodiment, the setup time margin threshold is 30 ps, ​​and in this embodiment, the setup time margin threshold is set to a positive value. The setup time margin corresponding to a setup time violation path is a negative value. Therefore, the absolute value of the setup time margin of the setup time violation path is compared with the setup time margin threshold. If the absolute value of the setup time margin of the setup time violation path is greater than 30 ps, ​​then the setup time violation path is defined as a critical path. The line delay threshold is set to 80 ps, ​​and the line load threshold is set to 80 pf.

[0120] In a module where both clock and data lines are fully wound, parasitic parameters are extracted, and then static timing analysis is performed. A set of synchronization registers exists in the synchronous clock domain CLKA. A setup time violation path exists between register FF1 and register FF2, and the absolute value of the setup time margin of this path is greater than 30 ps. Therefore, the setup time violation path from register FF1 to register FF2 is defined as a critical path.

[0121] The process begins by screening interconnects in the critical path for interconnects with line delays exceeding the line delay threshold and line loads exceeding the line load threshold. Interconnect b has a line delay of 100 ps, ​​exceeding the line delay threshold of 80 ps, ​​and a line load of 90 pf, exceeding the line load threshold of 80 pf. Therefore, interconnect b can be optimized using the integrated circuit winding optimization method provided in this application, resetting the winding attribute corresponding to the drive position of interconnect b to a via pillar winding attribute. The drive position of interconnect b can also be understood as the drive port, which is the output port of buffer 1. Furthermore, the physical location of the drive end of the output port of buffer 1 is located, and the winding density at the corresponding location is obtained. If the winding density is less than the winding density threshold, it indicates sufficient winding resources. The physical location of the drive end of the output port of buffer 1 can be set to via pillar winding mode, and the original ordinary winding is deleted, followed by re-winding via pillar. If the winding density is greater than or equal to the winding density threshold, it indicates insufficient winding resources. Interconnect b is skipped, and the next loop continues, executing step S410. Therefore, the integrated circuit winding optimization method provided in this application can accurately reduce data path latency on the critical path, effectively repair setup time violation paths, reduce interconnect latency in the critical path, help meet timing requirements, and more accurately optimize the power consumption, performance, and area of ​​the integrated circuit.

[0122] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0123] Please see Figure 9 This application provides an integrated circuit winding optimization device 100. The integrated circuit winding optimization device 100 includes a threshold information acquisition module 10, a timing analysis module 20, a critical path determination module 30, an optimization position determination module 40, and a winding attribute reset module 50. The threshold information acquisition module 10 is used to acquire timing path index threshold information and winding index threshold information. The timing analysis module 20 is used to perform static timing analysis on the wound integrated circuit to obtain static timing information. The critical path determination module 30 is used to determine critical path information based on the static timing information and the timing path index threshold information. The optimization position determination module 40 is used to determine the driving position of the interconnect to be optimized based on the critical path information and the winding index threshold information. The winding attribute reset module 50 is used to reset the winding attribute corresponding to the driving position of the interconnect to be optimized to a through-hole post winding attribute.

[0124] In this embodiment, the description of the threshold information acquisition module 10 can be found in the description of step S10 in the above embodiments. The description of the time series analysis module 20 can be found in the description of step S20 in the above embodiments. The description of the critical path determination module 30 can be found in the description of step S30 in the above embodiments. The description of the optimized position determination module 40 can be found in the description of step S40 in the above embodiments. The description of the winding attribute reset module 50 can be found in the description of step S50 in the above embodiments.

[0125] Please see Figure 10 This application provides an electronic device 200, including a memory 210, a processor 220, and a computer program 230 stored in the memory and executable on the processor. When the processor 220 executes the computer program 230, it implements the steps of the integrated circuit winding optimization method as described in any of the above embodiments. In this embodiment, the electronic device 200 may be a desktop computer, a laptop, a handheld computer, or a cloud server, etc. The electronic device 200 may include, but is not limited to, the processor 220 and the memory 210. Those skilled in the art will understand that... Figure 10This is merely an example of electronic device 200 and does not constitute a limitation on electronic device 200. It may include more or fewer components than shown, or combine certain components, or use different components. Processor 220 may be a Central Processing Unit (CPU), or other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. General-purpose processors may be microprocessors or any conventional processor, etc. Memory 210 may be an internal storage unit of electronic device 200, an external storage device of electronic device 200, or both internal and external storage units of electronic device 200. Memory 210 is used to store computer program 230 and other programs and data required by electronic device 200. Memory 210 may also be used to temporarily store data that has been output or will be output.

[0126] This application provides a computer-readable storage medium storing a computer program 230. When executed by a processor 220, the computer program 230 implements the steps of the integrated circuit winding optimization method as described in any of the above embodiments. Those skilled in the art will understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here. In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not described in detail or in a particular embodiment can be referred to in the relevant descriptions of other embodiments. Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0127] In the embodiments provided in this application, it should be understood that the disclosed devices / terminal equipment and methods can be implemented in other ways. For example, the device / terminal equipment embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0128] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated units can be implemented in hardware or as software functional units. If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of this application can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium may be appropriately added to or subtracted according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media may not include electrical carrier signals and telecommunication signals.

[0129] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for optimizing integrated circuit winding, characterized in that, include: Step S10, obtaining timing path indicator threshold information and wiring indicator threshold information, including: obtaining process node, power supply voltage, and design density; using the power consumption, performance, and area of ​​the integrated circuit as a reward mechanism, and based on a machine reinforcement learning algorithm, determining the timing path indicator threshold information and the wiring indicator threshold information according to the process node, the power supply voltage, and the design density; wherein, the wiring indicator threshold information includes line delay threshold, line load threshold, and line length threshold; Step S20 involves performing static timing analysis on the wound integrated circuit to obtain static timing information, including: extracting parasitic parameters of the wound integrated circuit; and performing static timing analysis on the wound integrated circuit using a static timing analysis tool based on the parasitic parameters to obtain the static timing information. Step S30: Determine the critical path information based on the static time series information and the time series path index threshold information; Step S40, determining the driving position of the interconnect to be optimized based on the critical path information and the winding index threshold information, includes: traversing each interconnect in the critical path information; if the line feature value of the current interconnect is greater than the line threshold in the winding index threshold information, then determining the driving position corresponding to the current interconnect as the driving position of the interconnect to be optimized; Step S50: Reset the winding attribute corresponding to the driving position of the interconnect to be optimized to the through-hole post winding attribute; Step S60: Based on the winding properties of the through-hole post, the driving position of the interconnect to be optimized is rewound to obtain the rewound integrated circuit. Steps S20 to S50 are then executed on the rewound integrated circuit, and the process is repeated until there are no interconnects in the integrated circuit that need to be optimized.

2. The integrated circuit wire optimization method of claim 1, wherein, The step of determining critical path information based on the static time series information and the time series path indicator threshold information includes: Traverse each establishment time violation path in the static timing information; If the absolute value of the establishment time margin of the current establishment time violation path is greater than the establishment time margin threshold in the time-series path indicator threshold information, then the current establishment time violation path is determined as the critical path information.

3. The integrated circuit wire optimization method of claim 1, wherein, The step of determining the driving position corresponding to the current interconnect as the driving position of the interconnect to be optimized if the current line characteristic value of the interconnect is greater than the line threshold in the winding index threshold information includes: If the current line delay of the interconnect is greater than the line delay threshold in the winding index threshold information, then the driving position corresponding to the current interconnect is determined as the driving position of the interconnect to be optimized.

4. The integrated circuit wire optimization method of claim 1, wherein, The step of determining the driving position corresponding to the current interconnect as the driving position of the interconnect to be optimized if the current line feature value of the interconnect is greater than the line threshold in the winding index threshold information further includes: If the current line load of the interconnect is greater than the line load threshold in the winding index threshold information, then the driving position corresponding to the current interconnect is determined as the driving position of the interconnect to be optimized.

5. The integrated circuit wire optimization method of claim 1, wherein, The step of determining the driving position corresponding to the current interconnect as the driving position of the interconnect to be optimized if the current line feature value of the interconnect is greater than the line threshold in the winding index threshold information further includes: If the current interconnect length is greater than the line length threshold in the winding index threshold information, then the driving position corresponding to the current interconnect is determined as the driving position of the interconnect to be optimized.

6. An integrated circuit winding optimization device, characterized in that, include: The threshold information acquisition module is used to acquire timing path indicator threshold information and winding indicator threshold information, including: acquiring process node, power supply voltage, and design density; using the power consumption, performance, and area of ​​the integrated circuit as a reward mechanism, and based on a machine reinforcement learning algorithm, determining the timing path indicator threshold information and the winding indicator threshold information according to the process node, the power supply voltage, and the design density; wherein, the winding indicator threshold information includes line delay threshold, line load threshold, and line length threshold; The timing analysis module is used to perform static timing analysis on the wound integrated circuit to obtain static timing information, including: extracting parasitic parameters of the wound integrated circuit; and based on the parasitic parameters, performing static timing analysis on the wound integrated circuit using a static timing analysis tool to obtain the static timing information. The critical path determination module is used to determine critical path information based on the static time series information and the time series path index threshold information; The optimization position determination module is used to determine the driving position of the interconnect to be optimized based on the critical path information and the winding index threshold information, including: traversing each interconnect in the critical path information; if the line feature value of the current interconnect is greater than the line threshold in the winding index threshold information, then the driving position corresponding to the current interconnect is determined as the driving position of the interconnect to be optimized. The winding attribute reset module is used to reset the winding attribute corresponding to the driving position of the interconnect to be optimized to the through-hole post winding attribute. The device is also used for: Based on the via post winding attributes, the drive position of the interconnect to be optimized is rewound to obtain the rewound integrated circuit. The timing analysis module, the critical path determination module, the optimization position determination module, and the winding attribute reset module then perform operations on the rewound integrated circuit in a sequential loop until there are no interconnects in the integrated circuit that need optimization.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method as described in any one of claims 1 to 5.

8. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1 to 5.

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