Semiconductor structure and method of forming the same

Abstract

The application provides a semiconductor structure and a forming method. The semiconductor structure comprises a substrate, a plurality of first electrode layers which are overlaid on the substrate, each of the first electrode layers has a plurality of first electrode layer openings, each of the first electrode layer openings has a plurality of first compensation portions, and the sidewalls of the first compensation portions are convex to the central axis of the first electrode layer opening; at least one second electrode layer, each of the second electrode layers is located between two adjacent first electrode layers, and each of the second electrode layers has a plurality of second electrode layer openings; a plurality of first conductive plugs which penetrate through the second electrode layers, each of the first conductive plugs passes through the first electrode layer openings in the plurality of first electrode layers, and the sidewalls of the first conductive plugs are in contact with the second electrode layers; and a plurality of second conductive plugs which penetrate through the first electrode layers, each of the second conductive plugs passes through the second electrode layer openings in the plurality of second electrode layers, and the sidewalls of the second conductive plugs are in contact with the first electrode layers, so that the electrical performance is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] Capacitors are commonly used passive components in very large-scale integrated circuits. They mainly include polysilicon-insulator-polysilicon (PIP) capacitors, metal-insulator-silicon (MIS) capacitors, and metal-insulator-metal (MIM) capacitors.

[0003] With the rapid development of wireless communication technology, there is a strong demand to embed high-performance decoupling and bypass capacitors suitable for System-on-Chip (SoC) into the copper interconnect terminals of integrated circuits to obtain powerful RF systems. This further requires the embedded capacitors to have high capacitance density, ideal voltage linearity, precise capacitance control, and high reliability: traditional PIP, MIS, and MOS structures are no longer sufficient to meet these performance requirements. Because MIM capacitors cause less interference to transistors and can provide better linearity and symmetry, the use of MIM capacitors will be a development trend in RF and analog / mixed-signal integrated circuits.

[0004] However, the electrical performance of MIM capacitors produced by existing technologies needs to be improved. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the electrical performance of the semiconductor structure.

[0006] To address the aforementioned problems, the present invention provides a semiconductor structure comprising: a substrate; a plurality of overlapping first electrode layers on the substrate, each first electrode layer having a plurality of first electrode layer openings, the projected patterns of the first electrode layer openings in different first electrode layers overlapping, each first electrode layer opening having a plurality of first compensation portions, the sidewalls of the first compensation portions protruding toward the central axis of the first electrode layer opening; at least one second electrode layer, each second electrode layer being located between two adjacent first electrode layers and insulated from the first electrode layers, each second electrode layer having a plurality of second electrode layer openings; a plurality of first conductive plugs penetrating the second electrode layers, each first conductive plug passing through a first electrode layer opening in the plurality of first electrode layers, the sidewalls of the first conductive plugs contacting the second electrode layers; and a plurality of second conductive plugs penetrating the first electrode layers, each second conductive plug passing through a second electrode layer opening in the plurality of second electrode layers, the sidewalls of the second conductive plugs contacting the first electrode layers.

[0007] Optionally, there is a first distance between the opening of the first electrode layer and the sidewall of the first conductive plug, and the dimension of the first distance is greater than 0.

[0008] Optionally, there is a second distance between the opening of the second electrode layer and the sidewall of the second conductive plug, the dimension of the second distance being greater than 0.

[0009] Optionally, the first electrode layer opening includes a first side parallel to each other along a first direction and a second side parallel to each other along a second direction, the first direction and the second direction being perpendicular. The sidewall of the first compensation part includes a first compensation side and a second compensation side connected to each other. The first compensation side extends along the first direction and its other end is connected to the second side. The second compensation side extends along the second direction and its other end is connected to the first side. The sidewall of the first compensation part protrudes toward the central axis of the first electrode layer opening. A plurality of first compensation parts are symmetrically distributed along the center of the first electrode layer opening.

[0010] Optionally, the length of the first side is the same as the length of the second side, the length of the first compensation side is the same as the length of the second compensation side, and the ratio of the length of the first compensation side to the length of the first side is in the range of 0.05:1 to 0.25:1.

[0011] Optionally, the opening of the second electrode layer has a plurality of second compensation portions, the sidewalls of which protrude toward the central axis of the opening of the second electrode layer.

[0012] Optionally, the second electrode layer opening includes a third side parallel to each other along the first direction and a fourth side parallel to each other along the second direction. The sidewall of the second compensation part includes a third compensation side and a fourth compensation side connected to each other. The third compensation side extends along the first direction and its other end is connected to the fourth side. The fourth compensation side extends along the second direction and its other end is connected to the third side. The sidewall of the second compensation part protrudes toward the central axis of the second electrode layer opening. A plurality of second compensation parts are symmetrically distributed along the center of the second electrode layer opening.

[0013] Optionally, the length of the third side is the same as the length of the fourth side, the length of the third compensation side is the same as the length of the fourth compensation side, and the ratio of the length of the third compensation side to the length of the third side is in the range of 0.05:1 to 0.25:1.

[0014] Optionally, it may also include a first conductive structure located on the first conductive plug and a second conductive structure located on the second conductive plug.

[0015] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a plurality of overlapping first electrode layers on the substrate; forming a plurality of first electrode layer openings in each first electrode layer, wherein the projected patterns of the first electrode layer openings in different first electrode layers overlap; forming a plurality of first compensation portions in each first electrode layer opening, wherein the sidewalls of the first compensation portions protrude toward the central axis of the first electrode layer opening; forming at least one second electrode layer, wherein each second electrode layer is located between two adjacent first electrode layers and is insulated from the first electrode layers, and each second electrode layer has a plurality of second electrode layer openings; forming a plurality of first conductive plugs penetrating the second electrode layer, wherein each first conductive plug passes through the first electrode layer openings in the plurality of first electrode layers and the sidewalls of the first conductive plugs are in contact with the second electrode layer; and forming a plurality of second conductive plugs penetrating the first electrode layer, wherein each second conductive plug passes through the second electrode layer openings in the plurality of second electrode layers and the sidewalls of the second conductive plugs are in contact with the first electrode layer.

[0016] Optionally, there is a first distance between the opening of the first electrode layer and the sidewall of the first conductive plug, and the dimension of the first distance is greater than 0.

[0017] Optionally, there is a second distance between the opening of the second electrode layer and the sidewall of the second conductive plug, the dimension of the second distance being greater than 0.

[0018] Optionally, the first electrode layer opening includes a first side parallel to each other along a first direction and a second side parallel to each other along a second direction, the first direction and the second direction being perpendicular. The sidewall of the first compensation part includes a first compensation side and a second compensation side connected to each other. The first compensation side extends along the first direction and its other end is connected to the second side. The second compensation side extends along the second direction and its other end is connected to the first side. The sidewall of the first compensation part protrudes toward the central axis of the first electrode layer opening. A plurality of first compensation parts are symmetrically distributed along the center of the first electrode layer opening.

[0019] Optionally, the length of the first side is the same as the length of the second side, the length of the first compensation side is the same as the length of the second compensation side, and the ratio of the length of the first compensation side to the length of the first side is in the range of 0.05:1 to 0.25:1.

[0020] Optionally, a plurality of second compensation portions are formed within the opening of the second electrode layer, and the sidewalls of the second compensation portions protrude toward the central axis of the opening of the second electrode layer.

[0021] Optionally, the second electrode layer opening includes a third side parallel to each other along the first direction and a fourth side parallel to each other along the second direction. The sidewall of the second compensation part includes a third compensation side and a fourth compensation side connected to each other. The third compensation side extends along the first direction and its other end is connected to the fourth side. The fourth compensation side extends along the second direction and its other end is connected to the third side. The sidewall of the second compensation part protrudes toward the central axis of the second electrode layer opening. A plurality of second compensation parts are symmetrically distributed along the center of the second electrode layer opening.

[0022] Optionally, the length of the third side is the same as the length of the fourth side, the length of the third compensation side is the same as the length of the fourth compensation side, and the ratio of the length of the third compensation side to the length of the third side is in the range of 0.05:1 to 0.25:1.

[0023] Optionally, it may also include forming a first conductive structure on the first conductive plug and forming a second conductive structure on the second conductive plug.

[0024] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0025] In the semiconductor structure of the present invention, several overlapping first electrode layers on the substrate each have several first electrode layer openings. The projected patterns of the first electrode layer openings in different first electrode layers overlap. Each first electrode layer opening has multiple first compensation portions. The sidewalls of the first compensation portions protrude toward the central axis of the first electrode layer opening. This increases the remaining area left by the first electrode layers, thereby increasing the effective capacitance of the semiconductor structure and improving the electrical performance of the final semiconductor structure. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of a semiconductor structure.

[0027] Figures 2 to 16 This is a schematic diagram of the steps in the method for forming a semiconductor structure in the first embodiment of the present invention;

[0028] Figure 17 This is a schematic diagram of the structure of the opening of the second electrode layer in the second embodiment of the present invention. Detailed Implementation

[0029] As mentioned in the background section, the electrical performance of MIM capacitors produced by existing technologies needs improvement. This will be explained in detail below with reference to the accompanying drawings.

[0030] Figure 1 This is a schematic diagram of a semiconductor structure. To make the internal structure clearer, the electrode plates are made transparent and simply represented by different types of lines, while the insulating layers involved are omitted.

[0031] Please refer to Figure 1 A semiconductor structure includes: a substrate (not shown); a first electrode layer 101 located on the substrate, the first electrode layer 101 including a stacked first sub-electrode layer 101a and a second sub-electrode layer 101b, the first electrode layer 101 having a first electrode layer opening 102, the projection of the first electrode layer opening 102 in the first sub-electrode layer 101a toward the substrate and the projection of the first electrode layer opening 102 in the second sub-electrode layer 101b toward the substrate coinciding; a second electrode layer 103 located between the first sub-electrode layer 101a and the second sub-electrode layer 101b, the second electrode layer 103 having a second electrode layer opening 103a; and a first conductive insert penetrating the second electrode layer 103. The first conductive plug (not shown in the figure) passes through a first electrode layer opening 102 within a plurality of first electrode layers 101 (first sub-electrode layer 101a and second sub-electrode layer 101b); a first conductive structure 103b is located on the first conductive plug; a plurality of second conductive plugs (not shown in the figure) penetrate the first electrode layer 101 (first sub-electrode layer 101a and second sub-electrode layer 101b), the second conductive plugs passing through a second electrode layer opening 103a within a plurality of second electrode layers 103; a second conductive structure 104 is located on the second conductive plug; a first pin 105 is located on the first conductive structure 103b; and a second pin 106 is located on the second conductive structure 104.

[0032] The inventors discovered that the pattern projected onto the substrate by the opening 102 of the first electrode layer is a square, and the pattern projected onto the substrate by the opening 103a of the second electrode layer is also a square. Since a large part of the capacitor is occupied by the opening of the electrode layer, the reduction in the effective area ratio of the electrode layer will lead to a reduction in capacitance, which in turn affects the electrical performance of the final semiconductor structure.

[0033] Based on this, the present invention provides a semiconductor structure and a method for forming the same. Several overlapping first electrode layers on a substrate each have several first electrode layer openings. The projected patterns of the first electrode layer openings in different first electrode layers overlap. Each first electrode layer opening has multiple first compensation portions. The sidewalls of the first compensation portions protrude toward the central axis of the first electrode layer opening. This increases the remaining area left by the first electrode layers, thereby increasing the effective capacitance of the semiconductor structure and improving the electrical performance of the final semiconductor structure.

[0034] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0035] Figures 2 to 16 This is a schematic diagram of the steps in the method for forming a semiconductor structure in the first embodiment of the present invention; Figure 17 This is a schematic diagram of the structure of the opening of the second electrode layer in the second embodiment of the present invention.

[0036] First Embodiment

[0037] Please refer to the following first. Figure 2 and Figure 3 Provides a base of 200.

[0038] Figure 3 for Figure 2 In the cross-sectional view of AA, Figure 2 for Figure 3 Top view.

[0039] In this embodiment, the substrate 200 has a first conductive layer 201 and a second conductive layer 202.

[0040] In this embodiment, the substrate 200 also has several device structures (not shown), and the first conductive layer 201 and the second conductive layer 202 are electrically connected to the several device structures respectively.

[0041] Please refer to Figure 4 A first electrode layer 203 with several overlapping layers is formed on the substrate 200.

[0042] Figure 4 View direction and Figure 2 The view orientation is consistent.

[0043] exist Figure 4 First, a first electrode layer 203 is formed on the substrate 200.

[0044] In this embodiment, the method for forming a first electrode layer 203 on a substrate 200 includes: forming a first electrode material layer (not shown) on the substrate 200; and performing a first patterning process on the first electrode material layer to form the first electrode layer 203.

[0045] The formation process of the first electrode material layer includes: atomic layer deposition, plasma chemical vapor deposition, low-pressure chemical vapor deposition, sputtering deposition, ion beam deposition, or ion beam-assisted deposition.

[0046] In this embodiment, the first electrode material layer is formed using atomic layer deposition.

[0047] The material of the first electrode layer 203 includes one or more of tantalum, titanium, tantalum nitride, titanium nitride, and tungsten.

[0048] In this embodiment, the first electrode layer 203 is made of titanium nitride.

[0049] Please refer to Figure 5 An opening 203a of the first electrode layer is formed within the first electrode layer 203.

[0050] Figure 5 View direction and Figure 4 The view orientation is the same.

[0051] In this embodiment, the first electrode layer opening 203a forms a plurality of first compensation portions 203b, and the sidewalls of the first compensation portions 203b protrude toward the central axis of the first electrode layer opening 203a.

[0052] In this embodiment, the first electrode layer opening 203a includes a first side (not marked in the figure) parallel to each other along a first direction (X) and a second side (not marked in the figure) parallel to each other along a second direction (Y). The first direction (X) and the second direction (Y) are perpendicular. The sidewall of the first compensation part 203b includes a first compensation side (not marked in the figure) and a second compensation side (not marked in the figure) connected to each other. The first compensation side extends along the first direction (X) and its other end is connected to the second side. The second compensation side extends along the second direction (Y) and its other end is connected to the first side. The sidewall of the first compensation part 203b protrudes toward the central axis of the first electrode layer opening 203a. A plurality of first compensation parts 203b are symmetrically distributed along the center of the first electrode layer opening 203a.

[0053] In this embodiment, the length of the first side W1 is the same as the length of the second side W1, the length of the first compensation side w2 is the same as the length of the second compensation side w2, and the ratio of the length of the first compensation side w2 to the length of the first side W1 ranges from 0.05:1 to 0.25:1.

[0054] In this embodiment, the sidewall of the first compensation part 203b protrudes towards the central axis of the opening 203a of the first electrode layer, that is, the first compensation edge is recessed relative to the center of the opening 203a of the first electrode layer, and the second compensation edge is recessed relative to the center of the opening 203a of the first electrode layer.

[0055] In this embodiment, the first compensation part 203b increases the remaining area left by the first electrode layer, thereby increasing the effective capacitance of the semiconductor structure and improving the electrical performance of the final semiconductor structure.

[0056] In this embodiment, there are four first compensation parts 203b, which are distributed at the four corners of the opening 203a in the first electrode layer.

[0057] Please refer to Figure 6 A first insulating layer 204 is formed on the substrate 200, the first insulating layer 204 covers the surface of the first electrode layer 203 and fills the opening 203a of the first electrode layer.

[0058] The material of the first insulating layer 204 includes: a high-K dielectric material; the high-K dielectric material includes: hafnium oxide, zirconium oxide, silicon oxynitride hafnium, silicon hafnium oxide, tantalum hafnium oxide, titanium hafnium oxide, zirconium hafnium oxide, or aluminum oxide.

[0059] In this embodiment, the first insulating layer 204 is made of hafnium oxide.

[0060] Please refer to Figure 7 A second electrode layer 205 is formed on the first insulating layer 204.

[0061] In this embodiment, the method for forming a second electrode layer 205 on the first insulating layer 204 includes: forming a second electrode material layer (not shown) on the first insulating layer 204; and performing a second patterning process on the second electrode material layer to form the second electrode layer 205.

[0062] The formation process of the second electrode material layer includes: atomic layer deposition, plasma chemical vapor deposition, low-pressure chemical vapor deposition, sputtering deposition, ion beam deposition, or ion beam-assisted deposition.

[0063] In this embodiment, the second electrode material layer is formed using atomic layer deposition.

[0064] The material of the second electrode layer 205 includes one or more of tantalum, titanium, tantalum nitride, titanium nitride, and tungsten.

[0065] In this embodiment, the material of the second electrode layer 205 is titanium nitride.

[0066] Please refer to Figure 8An opening 205a of the second electrode layer is formed within the second electrode layer 205.

[0067] In this embodiment, the shape of the second electrode layer opening 205a projected onto the substrate is a square.

[0068] In this embodiment, the second electrode layer opening 205a exposes the surface of the first insulating layer 204.

[0069] In this embodiment, the projection of the second electrode layer opening 205a toward the substrate does not overlap with the projection of the first electrode layer opening 203a toward the substrate.

[0070] Please refer to Figure 9 A second insulating layer 206 is formed on the first insulating layer 204, and the second insulating layer 206 covers the surface of the second electrode layer 205.

[0071] The material of the second insulating layer 206 includes: a high-K dielectric material; the high-K dielectric material includes: hafnium oxide, zirconium oxide, silicon oxynitride hafnium, silicon hafnium oxide, tantalum hafnium oxide, titanium hafnium oxide, zirconium hafnium oxide, or aluminum oxide.

[0072] In this embodiment, the material of the second insulating layer 206 is hafnium oxide.

[0073] Please refer to Figure 10 A first electrode layer 203 is then formed on the second insulating layer 206.

[0074] In this embodiment, the semiconductor structure only shows a first electrode layer 203 with two layers stacked, and a second electrode layer 205 is formed between the two first electrode layers 203.

[0075] In other embodiments, a second electrode layer 205 may be formed on the first electrode layer 203, and the first electrode layer 203 may be stacked on the second electrode layer 205. By continuously stacking in this manner, a multi-layered first electrode layer is formed, and a second electrode layer is formed between adjacent first electrode layers.

[0076] Please refer to Figure 11 A plurality of first electrode layer openings 203a are formed within the first electrode layer 203.

[0077] In this embodiment, the projected pattern of the first electrode layer opening 203a in the first electrode layer overlaps with the projected pattern of the first electrode layer opening 203a in the first electrode layer located at the bottom of the second electrode layer 205.

[0078] In this embodiment, the first compensation part 203b increases the remaining area left by the first electrode layer 203, thereby increasing the effective capacitance of the semiconductor structure and improving the electrical performance of the final semiconductor structure.

[0079] Please refer to Figure 12 A dielectric layer 207 is formed on the substrate 200, and the dielectric layer 207 covers the first electrode layer 203.

[0080] In this embodiment, the dielectric layer 207 is made of silicon oxide; in other embodiments, the dielectric layer may also be made of low-K dielectric material (low-K dielectric material refers to dielectric material with a relative permittivity of less than 3.9) or ultra-low-K dielectric material (ultra-low-K dielectric material refers to dielectric material with a relative permittivity of less than 2.5).

[0081] In this embodiment, the dielectric layer 207 covers the first electrode layer 203 on the second insulating layer 206.

[0082] In this embodiment, after forming the dielectric layer 207, the method further includes forming a first through-hole and a second through-hole within the dielectric layer 207. For the specific formation process of the first through-hole and the second through-hole, please refer to [reference needed]. Figures 9 to 11 .

[0083] Please refer to the process of forming the first conductive plug and the second conductive plug within the dielectric layer 207. Figures 13 to 15 .

[0084] Please refer to Figures 13 to 14 A first through hole 208 and a second through hole 209 are formed in the dielectric layer 207, respectively.

[0085] Figure 13 for Figure 14 Top view; Figure 14 for Figure 13 Cross-sectional view of AA.

[0086] In this embodiment, the first through hole 208 passes through the first electrode layer opening 203a in several layers of first electrode layer 203, penetrates the second insulating layer 206, the second electrode layer 205, and the first insulating layer 204, and extends to the substrate 200 to expose part of the top surface of the first conductive layer 201.

[0087] In this embodiment, the second through hole 209 extends through the second electrode layer opening 205a in several layers of second electrode layer 205, through the first electrode layer 203, the second insulating layer 206, the first electrode layer 203, the first insulating layer 204, and then extends into the substrate 200 to expose part of the top surface of the second conductive layer 202.

[0088] Please refer to Figure 15 A first conductive plug 210 is formed in the first through hole 208; a second conductive plug 211 is formed in the second through hole 209.

[0089] Figure 15 View direction and Figure 14 The view orientation is the same.

[0090] In this embodiment, the distance from the opening 203a of the first electrode layer to the sidewall of the first conductive plug 210 is greater than 0, and the sidewall of the first conductive plug 210 is in contact with the second electrode layer 205.

[0091] In this embodiment, the distance from the opening 205a of the second electrode layer to the sidewall of the second conductive plug 211 is greater than 0, and the sidewall of the second conductive plug 211 is in contact with the first electrode layer 203.

[0092] In this embodiment, the first conductive plug 210 is electrically connected to the first conductive layer 201; the second conductive plug 211 is electrically connected to the second conductive layer 202.

[0093] In this embodiment, the method for forming the first conductive plug 210 and the second conductive plug 211 includes: forming a conductive plug material layer (not shown) in the first through hole 208, the second through hole 209 and the dielectric layer 207; and planarizing the conductive plug material layer until the top surface of the dielectric layer 207 is exposed, thereby forming the first conductive plug 210 and the second conductive plug 211.

[0094] In this embodiment, before forming the first conductive plug 210, the method further includes: forming a first auxiliary layer (not shown in the figure) on the bottom surface and sidewall of the first through hole 208; the first conductive plug 210 is located on the first auxiliary layer (not shown in the figure).

[0095] In this embodiment, before forming the second conductive plug 211, the method further includes: forming a second auxiliary layer (not shown in the figure) on the bottom surface and sidewall of the second through hole 209; the second conductive plug 211 is located on the second auxiliary layer (not shown in the figure).

[0096] The materials of the first conductive plug 210 include copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten, or platinum; the materials of the second conductive plug 211 include copper, cobalt, nickel, titanium, tantalum, aluminum, tungsten, or platinum.

[0097] It should be noted that, in this embodiment, when the metal materials selected for the first conductive plug 210 and the second conductive plug 211 have strong metal activity, such as copper, the first auxiliary layer and the second auxiliary layer are barrier layers, which are used to prevent the metal diffusion of the first conductive plug 210 and the second conductive plug 211, thereby causing metal contamination; when the metal materials selected for the first conductive plug 210 and the second conductive plug 211 have poor adhesion, such as tungsten, the first auxiliary layer and the second auxiliary layer are adhesive layers, which are used to increase the adhesion between the first conductive plug 210 and the second conductive plug 211 and the dielectric layer.

[0098] Please refer to Figure 16A first conductive structure 212 is formed on the first conductive plug 210, and a second conductive structure 213 is formed on the second conductive plug 211.

[0099] Figure 16 View direction and Figure 13 The view orientation is consistent.

[0100] Please continue to refer to this. Figure 16 A first pin 214 is formed on the first conductive structure 212, and a second pin 215 is formed on the second conductive structure 213.

[0101] Accordingly, the present invention also provides a semiconductor structure, including a substrate 200; a plurality of overlapping first electrode layers 203 located on the substrate 200, each first electrode layer 203 having a plurality of first electrode layer openings 203a, the projected patterns of the first electrode layer openings 203a in different layers of first electrode layers 203 overlapping, each first electrode layer opening 203a having a plurality of first compensation portions 203b, the sidewalls of the first compensation portions 203b protruding toward the central axis of the first electrode layer openings 203a; at least one second electrode layer 205, each second electrode layer 205 located between two adjacent first electrode layers 203, and the second electrode layer 205 being insulated from the first electrode layer 203, each second electrode layer 205 having a plurality of first compensation portions 203b. The first electrode layer has an opening 205a; a plurality of first conductive plugs 210 penetrate the second electrode layer 205, each first conductive plug 210 passing through a first electrode layer opening 203a within a plurality of first electrode layers 203, the distance from the first electrode layer opening 203a to the sidewall of the first conductive plug 210 being greater than 0, and the sidewall of the first conductive plug 210 being in contact with the second electrode layer 205; a plurality of second conductive plugs 211 penetrate the first electrode layer 203, each second conductive plug 211 passing through a second electrode layer opening 205a within a plurality of second electrode layers 205, the distance from the second electrode layer opening 205a to the sidewall of the second conductive plug 211 being greater than 0, and the sidewall of the second conductive plug 211 being in contact with the first electrode layer 203.

[0102] In this embodiment, the first electrode layer opening 203a includes a first side parallel to each other along a first direction and a second side parallel to each other along a second direction, the first direction and the second direction being perpendicular. The sidewall of the first compensation part 203b includes a first compensation side and a second compensation side connected to each other. The first compensation side extends along the first direction and its other end is connected to the second side, and the second compensation side extends along the second direction and its other end is connected to the first side. The sidewall of the first compensation part 203b protrudes toward the central axis of the first electrode layer opening 203a, and a plurality of first compensation parts 203b are symmetrically distributed along the center of the first electrode layer opening 203a.

[0103] In this embodiment, the length of the first side (W1) is the same as the length of the second side (W1), the length of the first compensation side (w2) is the same as the length of the second compensation side (w2), and the ratio of the length of the first compensation side to the length of the first side is in the range of 0.05:1 to 0.25:1.

[0104] In this embodiment, the projection pattern of the second electrode layer opening 205a toward the substrate 200 is square.

[0105] In this embodiment, the projected patterns of the first electrode layer openings 203a in different first electrode layers 203 overlap, and each first electrode layer opening 203a has a plurality of first compensation portions 203b. The sidewalls of the first compensation portions 203b protrude toward the central axis of the first electrode layer opening 203a, which increases the remaining area left by the first electrode layer 203, thereby increasing the effective capacitance of the semiconductor structure and improving the electrical performance of the final semiconductor structure.

[0106] In this embodiment, a first conductive structure 212 located on the first conductive plug 210 and a second conductive structure 213 located on the second conductive plug 211 are also included.

[0107] In this embodiment, a first pin 214 located on the first conductive structure 212 and a second pin 215 located on the second conductive structure 213 are also included.

[0108] Second Embodiment

[0109] The difference between the second embodiment and the first embodiment is that the second electrode layer opening 205a in the second embodiment also has a second compensation part 205b.

[0110] Please refer to the structural diagram of the process from providing the substrate 200 to forming the opening 205a of the second electrode layer. Figures 2 to 7 .

[0111] Please refer to Figure 17 A second electrode layer opening 205a is formed in the second electrode layer 205, and the second electrode layer opening 205a has a second compensation portion 205b.

[0112] Figure 17 View direction and Figure 8 The view orientation is the same.

[0113] In this embodiment, the second electrode layer opening 205a includes a third side parallel to each other along the first direction (X) and a fourth side parallel to each other along the second direction (Y). The sidewall of the second compensation part 205b includes a third compensation side and a fourth compensation side connected to each other. The third compensation side extends along the first direction (X) and its other end is connected to the fourth side. The fourth compensation side extends along the second direction (Y) and its other end is connected to the third side. The sidewall of the second compensation part 205b protrudes toward the central axis of the second electrode layer opening 205a. A plurality of second compensation parts are symmetrically distributed along the center of the second electrode layer opening 205a.

[0114] In this embodiment, the length of the third side (W1) is the same as the length of the fourth side (W1), the length of the third compensation side (w2) is the same as the length of the fourth compensation side (w2), and the ratio of the length of the third compensation side (w2) to the length of the third side (W1) ranges from 0.05:1 to 0.25:1.

[0115] In this embodiment, the sidewall of the second compensation part 205b protrudes towards the central axis of the opening 205a of the second electrode layer, that is, the third compensation edge is recessed relative to the center of the opening 205a of the second electrode layer relative to the third edge, and the fourth compensation edge is recessed relative to the center of the opening 205a of the second electrode layer relative to the fourth edge.

[0116] In this embodiment, the second compensation section 205b increases the remaining area left by the second electrode layer 205, thereby increasing the effective capacitance of the semiconductor structure and improving the electrical performance of the final semiconductor structure.

[0117] After the second electrode layer opening 205a is formed, please refer to the structural diagram of the process from the formation of the second insulating layer 206 to the formation of the first pin 214 and the second pin 215. Figures 9 to 16 .

[0118] Accordingly, the present invention also provides a semiconductor structure, including a substrate 200; a plurality of overlapping first electrode layers 203 located on the substrate 200, each first electrode layer 203 having a plurality of first electrode layer openings 203a, the projected patterns of the first electrode layer openings 203a in different layers of first electrode layers 203 overlapping, each first electrode layer opening 203a having a plurality of first compensation portions 203b, the sidewalls of the first compensation portions 203b protruding toward the central axis of the first electrode layer opening 203a; at least one second electrode layer 205, each second electrode layer 205 located between two adjacent first electrode layers 203, and the second electrode layer 205 being insulated from the first electrode layer 203, each second electrode layer 205 having a plurality of A second electrode layer opening 205a; a plurality of first conductive plugs 210 penetrating the second electrode layer 205, each first conductive plug 210 passing through a first electrode layer opening 203a within a plurality of first electrode layers 203, the distance from the first electrode layer opening 203a to the sidewall of the first conductive plug 210 being greater than 0, and the sidewall of the first conductive plug 210 contacting the second electrode layer 205; a plurality of second conductive plugs 211 penetrating the first electrode layer 203, each second conductive plug 211 passing through a second electrode layer opening 205a within a plurality of second electrode layers 205, the distance from the second electrode layer opening 205a to the sidewall of the second conductive plug 211 being greater than 0, and the sidewall of the second conductive plug 211 contacting the first electrode layer 203.

[0119] In this embodiment, the first electrode layer opening 203a includes a first side parallel to each other along a first direction and a second side parallel to each other along a second direction, the first direction and the second direction being perpendicular. The sidewall of the first compensation part 203b includes a first compensation side and a second compensation side connected to each other. The first compensation side extends along the first direction and its other end is connected to the second side, and the second compensation side extends along the second direction and its other end is connected to the first side. The sidewall of the first compensation part 203b protrudes toward the central axis of the first electrode layer opening 203a, and a plurality of first compensation parts 203b are symmetrically distributed along the center of the first electrode layer opening 203a.

[0120] In this embodiment, the length of the first side is the same as the length of the second side, the length of the first compensation side is the same as the length of the second compensation side, and the ratio of the length of the first compensation side to the length of the first side is in the range of 0.05:1 to 0.25:1.

[0121] In this embodiment, the second electrode layer opening 205a includes a third side parallel to each other along a first direction and a fourth side parallel to each other along a second direction. The sidewall of the second compensation part includes a third compensation side and a fourth compensation side connected to each other. The third compensation side extends along the first direction and its other end is connected to the fourth side. The fourth compensation side extends along the second direction and its other end is connected to the third side. The sidewall of the second compensation part 205b protrudes toward the central axis of the second electrode layer opening 205a. A plurality of second compensation parts 205b are symmetrically distributed along the center of the second electrode layer opening 205a.

[0122] In this embodiment, the length of the third side is the same as the length of the fourth side, the length of the third compensation side is the same as the length of the fourth compensation side, and the ratio of the length of the third compensation side to the length of the third side ranges from 0.05:1 to 0.25:1.

[0123] In this embodiment, a first conductive structure 212 located on the first conductive plug 210 and a second conductive structure 213 located on the second conductive plug 211 are also included.

[0124] In this embodiment, a first pin 214 located on the first conductive structure 212 and a second pin 215 located on the second conductive structure 213 are also included.

[0125] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; The substrate has several overlapping first electrode layers, each first electrode layer having several first electrode layer openings. The projected patterns of the first electrode layer openings in different first electrode layers overlap. Each first electrode layer opening has multiple first compensation portions. The sidewalls of the first compensation portions protrude toward the central axis of the first electrode layer opening. The first compensation portions are used to increase the remaining area left by the first electrode layers. At least one second electrode layer, each second electrode layer is located between two adjacent first electrode layers, and the second electrode layer is insulated from the first electrode layer. Each second electrode layer has a plurality of second electrode layer openings. A plurality of first conductive plugs penetrate the second electrode layer, each first conductive plug passing through an opening in the first electrode layer within a plurality of first electrode layers, and the sidewall of the first conductive plug contacting the second electrode layer. A plurality of second conductive plugs penetrate the first electrode layer, each second conductive plug passing through an opening in the second electrode layer within the plurality of second electrode layers, and the sidewall of the second conductive plug being in contact with the first electrode layer.

2. The semiconductor structure as described in claim 1, characterized in that, There is a first distance between the opening of the first electrode layer and the sidewall of the first conductive plug, and the dimension of the first distance is greater than 0.

3. The semiconductor structure as described in claim 1, characterized in that, There is a second distance between the opening of the second electrode layer and the sidewall of the second conductive plug, and the dimension of the second distance is greater than 0.

4. The semiconductor structure as described in claim 1, characterized in that, The first electrode layer opening includes a first side parallel to each other along a first direction and a second side parallel to each other along a second direction, the first direction and the second direction being perpendicular. The sidewall of the first compensation part includes a first compensation side and a second compensation side connected to each other. The first compensation side extends along the first direction and its other end is connected to the second side. The second compensation side extends along the second direction and its other end is connected to the first side. The sidewall of the first compensation part protrudes toward the central axis of the first electrode layer opening. A plurality of the first compensation parts are symmetrically distributed along the center of the first electrode layer opening.

5. The semiconductor structure as described in claim 4, characterized in that, The length of the first side is the same as the length of the second side, the length of the first compensation side is the same as the length of the second compensation side, and the ratio of the length of the first compensation side to the length of the first side is in the range of 0.05:1 to 0.25:

1.

6. The semiconductor structure as described in claim 1, characterized in that, The second electrode layer opening has a plurality of second compensation portions, and the sidewalls of the second compensation portions protrude toward the central axis of the second electrode layer opening.

7. The semiconductor structure as described in claim 6, characterized in that, The second electrode layer opening includes a third side parallel to each other along a first direction and a fourth side parallel to each other along a second direction. The sidewall of the second compensation part includes a third compensation side and a fourth compensation side connected to each other. The third compensation side extends along the first direction and its other end is connected to the fourth side. The fourth compensation side extends along the second direction and its other end is connected to the third side. The sidewall of the second compensation part protrudes toward the central axis of the second electrode layer opening. A plurality of second compensation parts are symmetrically distributed along the center of the second electrode layer opening.

8. The semiconductor structure as described in claim 7, characterized in that, The length of the third side is the same as the length of the fourth side, the length of the third compensation side is the same as the length of the fourth compensation side, and the ratio of the length of the third compensation side to the length of the third side is in the range of 0.05:1 to 0.25:

1.

9. The semiconductor structure as described in claim 1, characterized in that, It also includes a first conductive structure located on the first conductive plug and a second conductive structure located on the second conductive plug.

10. A method for forming a semiconductor structure, characterized in that, include: Provide a base; Several overlapping first electrode layers are formed on the substrate; A plurality of first electrode layer openings are formed in each of the first electrode layers, and the projected patterns of the first electrode layer openings in different first electrode layers overlap. Multiple first compensation portions are formed in each of the openings of the first electrode layer. The sidewalls of the first compensation portions protrude toward the central axis of the opening of the first electrode layer. The first compensation portions are used to increase the remaining area left by the first electrode layer. At least one second electrode layer is formed, each second electrode layer is located between two adjacent first electrode layers, and the second electrode layer is insulated from the first electrode layer. Each second electrode layer has a plurality of second electrode layer openings. A plurality of first conductive plugs are formed that penetrate the second electrode layer, each first conductive plug passing through an opening in the first electrode layer within the plurality of first electrode layers, and the sidewall of the first conductive plug being in contact with the second electrode layer. A plurality of second conductive plugs penetrate the first electrode layer, each second conductive plug passing through an opening in the second electrode layer within the plurality of second electrode layers, and the sidewall of the second conductive plug being in contact with the first electrode layer.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, There is a first distance between the opening of the first electrode layer and the sidewall of the first conductive plug, and the dimension of the first distance is greater than 0.

12. The method for forming a semiconductor structure as described in claim 10, characterized in that, There is a second distance between the opening of the second electrode layer and the sidewall of the second conductive plug, and the dimension of the second distance is greater than 0.

13. The method for forming a semiconductor structure as described in claim 10, characterized in that, The first electrode layer opening includes a first side parallel to each other along a first direction and a second side parallel to each other along a second direction, the first direction and the second direction being perpendicular. The sidewall of the first compensation part includes a first compensation side and a second compensation side connected to each other. The first compensation side extends along the first direction and its other end is connected to the second side. The second compensation side extends along the second direction and its other end is connected to the first side. The sidewall of the first compensation part protrudes toward the central axis of the first electrode layer opening. A plurality of the first compensation parts are symmetrically distributed along the center of the first electrode layer opening.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The length of the first side is the same as the length of the second side, the length of the first compensation side is the same as the length of the second compensation side, and the ratio of the length of the first compensation side to the length of the first side is in the range of 0.05:1 to 0.25:

1.

15. The method for forming a semiconductor structure as described in claim 10, characterized in that, Multiple second compensation portions are formed within the opening of the second electrode layer, and the sidewalls of the second compensation portions protrude toward the central axis of the opening of the second electrode layer.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The second electrode layer opening includes a third side parallel to each other along a first direction and a fourth side parallel to each other along a second direction. The sidewall of the second compensation part includes a third compensation side and a fourth compensation side connected to each other. The third compensation side extends along the first direction and its other end is connected to the fourth side. The fourth compensation side extends along the second direction and its other end is connected to the third side. The sidewall of the second compensation part protrudes toward the central axis of the second electrode layer opening. A plurality of second compensation parts are symmetrically distributed along the center of the second electrode layer opening.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The length of the third side is the same as the length of the fourth side, the length of the third compensation side is the same as the length of the fourth compensation side, and the ratio of the length of the third compensation side to the length of the third side is in the range of 0.05:1 to 0.25:

1.

18. The method for forming a semiconductor structure as described in claim 10, characterized in that, It also includes forming a first conductive structure on the first conductive plug and forming a second conductive structure on the second conductive plug.

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