ADC (Analog to Digital Converter) based on multi-bit quantization pipeline structure and capacitance correction

Abstract

The invention belongs to the field of digital analog hybrid integrated circuits, and particularly relates to an ADC based on a multi-bit quantization pipeline structure and capacitance correction. According to the invention, a multi-bit quantization pipeline architecture of a first-stage 2bit / cycle-ADC, an inter-stage amplifier and a second-stage split-type ADC is adopted, and a background correction algorithm with low hardware overhead is added to correct capacitor mismatch; in the first-stage ADC, a grouping shuffling structure is added to realize correction feasibility under the condition of direct current input signals, and meanwhile, exchange capacitors are added between groups to realize correction unification of two groups of capacitors. After the quantization is finished, a dither is added between the two capacitor DAC arrays 100 and 101, so that the correction of the post-stage capacitor weight is realized. According to the method, the gain error is corrected while the correction precision is ensured, the hardware overhead for correcting the inter-stage gain error in the assembly line ADC is saved, and the circuit redundancy degree of a traditional correction mode is reduced.

Description

Technical Field

[0001] The invention belongs to the field of digital analog hybrid integrated circuits, and in particular relates to an ADC based on a multi-bit quantization pipeline structure and capacitance correction. Background Art

[0002] In electronic applications, ADC plays the role of converting analog signals into digital signals. Currently, ADC continues to develop towards high-speed and high-precision applications.

[0003] For high-speed ADC, the fusion architecture can increase the conversion rate of ADC by multiples: for example, the fusion of pipeline ADC and SAR (successive approximation) ADC can increase the conversion rate of ADC by multiples while ensuring the chip area and power consumption; for another example, the fusion of multi-bit quantization ADC, such as 2bit / cycle-ADC, can convert 2-bit results in one comparison cycle of ADC. This type of ADC architecture can speed up ADC very well. However, the use of pipeline ADC will also bring some problems. The most serious one is the problem of inter-stage gain error. The existing correction method generally uses dither injection and secondary quantization for correction.

[0004] In high-precision ADCs, as the number of capacitors increases, the accuracy of the DAC seriously affects the final conversion effect. The capacitors in commonly used capacitive DACs are affected by the process and will have capacitance errors, namely, capacitor mismatch, which will cause the voltage value converted by the capacitive DAC to be inaccurate. Currently, commonly used high-precision ADCs usually use foreground correction to correct capacitor mismatch, that is, before the ADC starts working, capacitor mismatch correction is performed first, and then normal ADC conversion is performed.

[0005] For high-speed and high-precision applications, methods such as foreground correction cannot meet the real-time working characteristics of high-speed ADC. Using background digital correction algorithms can correct the mismatch of capacitors in ADC without affecting the ADC conversion process. However, the hardware overhead of background correction is often much larger than that of foreground correction. This is because most of the existing high-precision correction algorithms rely on a reference ADC, which means that an additional ADC is required to implement the correction, thus occupying a large amount of chip area. Summary of the invention

[0006] In view of the above-mentioned existing problems or deficiencies, in order to solve the problems of capacitor mismatch, relatively insufficient conversion speed and large background correction hardware overhead of the existing high-speed and high-precision ADC, the present invention provides an ADC based on multi-bit quantization pipeline and capacitor correction. The present invention relies on a high-speed fusion architecture (i.e., a multi-bit quantization pipeline architecture) and adds a background correction algorithm with low hardware overhead to correct capacitor mismatch, effectively solving the problem of redundant hardware overhead or speed reduction caused by the traditional correction algorithm correcting capacitor mismatch. In addition, the gain error is corrected at the same time, eliminating the hardware overhead of correcting the inter-stage gain error in the pipeline ADC.

[0007] An ADC based on a multi-bit quantization pipeline structure and capacitance correction includes a first-stage 2bit / cycle-ADC, an interstage amplifier 105 and a second-stage split ADC, such as Figure 1 As shown in the figure, after sampling, the first-stage 2bit / cycle-ADC quantizes the input signal and generates two different quantized residual voltages. The quantized residual voltages are sequentially amplified by the inter-stage amplifier to two identical ADCs in the second-stage split ADC. The second-stage split ADC quantizes the two different amplified residual voltages respectively.

[0008] The first-stage 2bit / cycle-ADC includes a capacitor DAC array 100, a capacitor DAC array 101, a comparator 102, a comparator 103 and a comparator 104. The two capacitor DAC arrays are identical, and the three comparators are also identical. The P terminal of the capacitor DAC array 100 is connected to the positive input terminal of the comparator 102, and the N terminal is connected to the negative input terminals of the comparator 102 and the comparator 103. The P terminal of the capacitor DAC array 101 is connected to the positive input terminals of the comparator 103 and the comparator 104, and the N terminal is connected to the negative input terminal of the comparator 104. The capacitor DAC array 100 and the capacitor DAC array 101 are connected to the input signals VIP and VIN via sampling switches SWSB and SWSA.

[0009] The positive input terminal of the inter-stage amplifier 105 is connected to the P terminal of the capacitor DAC array 100 and the P terminal of the capacitor DAC array 101 via the switch SWA1, and the negative input terminal is connected to the N terminal of the capacitor DAC array 100 and the N terminal of the capacitor DAC array 101 via the switch SWA2 and the switch SWB2; the first-stage 2bit / cycle-ADC quantization residual voltage is amplified and output to the second-stage split ADC.

[0010] The second-stage split ADC includes two identical ADCs SPLIT A and SPLIT B. Figure 1The connection relationship is reflected in a single-ended form; the input end of SPLIT A is connected to the output end of the inter-stage amplifier 105 through the switch SWRA, and the input end of SPLIT B is connected to the output end of the inter-stage amplifier 105 through the switch SWRB; SPLIT A and SPLIT B respectively convert the quantized residual voltage amplified by the inter-stage amplifier 105.

[0011] The present invention can be regarded as having two signal quantization paths, one is the signal quantized by 100, 105 and 106, and the other is the signal quantized by 101, 105 and 107. The two paths sample the same input signal, but the quantization results are different.

[0012] The basic working mode of the present invention is in accordance with the pipeline mode. During the sampling and quantization process of the first-stage 2bit / cycle-ADC, the second-stage split ADC quantizes the residual amplified after the last quantization of the first-stage 2bit / cycle-ADC. When the inter-stage amplifier amplifies the plate voltages converted by 100 and 101, 100 and 101 are in a holding state, and 106 and 107 enter the sampling state in turn.

[0013] The first-stage 2bit / cycle-ADC of the present invention uses two capacitor arrays and does not need to double the capacitor size and add redundant hardware overhead. Since the average of the two-way quantization results will reduce the kT / C noise power by half, the size of each capacitor in the two capacitor arrays in the first-stage 2bit / cycle-ADC only needs to meet the constraint condition of 2 times the sampling thermal noise power. Different from the traditional split-type pipeline ADC, which requires two inter-stage amplifiers, the first-stage 2bit / cycle-ADC only needs one inter-stage amplifier to amplify twice in sequence; at the same time, due to the use of the 2bit / cycle quantization method, the quantization speed of the first stage is doubled. Since the second stage in the pipeline ADC only needs to meet lower precision, the use of the split ADC will slightly increase the overhead, but will not bring the disadvantage of reduced secondary quantization speed.

[0014] In order to solve the problem that the traditional secondary quantization or split pipeline ADC does not have a correction function under the condition of DC signal input, so that the ADC still has a changing quantization codeword under the DC signal input, the first-level 2bit / cycle-ADC capacitor array in the present invention introduces a unit capacitor group and a corresponding shuffling unit. Under the same input voltage, since the quantization capacitors selected to participate are different each time, the quantization residuals are different, and the codewords corresponding to the switching of each quantization capacitor will also be different, thereby realizing background correction under DC signal input. At the same time, since the characteristics of the two capacitor arrays of the 2bit / cycle-ADC are fully utilized, two different quantization residuals and two different quantization codeword matrices can be established for LMS algorithm correction without using methods such as secondary CDAC establishment or secondary quantization.

[0015] Furthermore, the capacitor DAC arrays 100 and 101 each include a set of identical calibration and quantization digital logics, such as Figure 3 As shown (only a single unilateral capacitor DAC array is shown), specifically: the capacitor DAC array includes a high-order unit capacitor array 200, a low-order unit capacitor array 201, a high-order shuffle unit 202, a low-order shuffle unit 203, a capacitor exchange logic 204, a random flip logic 205, a 2bit / cycle successive approximation logic 206 and a shuffle pointer generation logic 207.

[0016] The low-order unit capacitor array 201 is composed of 2 K1 +M1 small unit capacitors of size C, where M1 is a redundant capacitor used to satisfy the mutual replacement condition with the high-order capacitor, and K1 is the number of quantization bits of the low-order unit capacitor array 201; the low-order shuffling unit 203 shuffles the low-order unit capacitor array 201 required for low-order quantization.

[0017] The high-order unit capacitor array 200 consists of 2 K2 -1 size of 2 K1 *C, K2 is the number of quantization bits of the high-order unit capacitor array 200; the high-order shuffling unit 202 shuffles the high-order unit capacitor array 200 required for high-order quantization.

[0018] The low-order shuffle unit 203 selects capacitors in the low-order unit capacitor array 201 and allocates them to the K2+1th to K1+K2th bit quantization according to the shuffle pointer PN2 generated by the shuffle pointer generation logic 207; the high-order shuffle unit 202 selects capacitors in the high-order unit capacitor array 200 and allocates them to the 1st to K2th bit quantization according to the shuffle pointer PN1 generated by the shuffle pointer generation logic 207.

[0019] At the end of quantization, according to the shuffle pointer PN3 generated by the shuffle pointer generation logic 207, the capacitor exchange logic 204 uses the 2 low-order unit capacitor array 201. K1 A small unit capacitor replaces a large unit capacitor in the high-order unit capacitor array 200 (i.e., the voltage switched by the small unit capacitor of the same weight is exchanged with the voltage switched by the large unit capacitor, such as using 2 K1 A small unit capacitor with a lower plate switching a high level replaces a large unit capacitor with a lower plate switching a low level), thereby achieving calibration of the ratio between the large unit capacitor and the small unit capacitor.

[0020] Finally, a capacitor of size C is selected according to the random flip logic 205, and its lower plate voltage is switched, so that the switched voltages of the capacitor DAC arrays 100 and 101 are different; this operation amplifies the voltage difference between the two capacitor DAC arrays, so that the inter-stage gain error between the second-stage split ADC and the first-stage 2bit / cycle-ADC can be calibrated.

[0021] The shuffle pointer generated by the shuffle pointer generation logic 207 points to a certain large (small) unit capacitor as the starting point, and the subsequent capacitor combinations participating in the quantization of each bit are allocated in sequence from this starting point. The corresponding relationship between the shuffle pointer and the high (low) shuffle unit can be obtained by Figure 4 It means that the shuffle pointer generates a starting point pointing to a certain unit capacitor, and the subsequent capacitor combinations participating in the quantization of each bit are allocated in turn.

[0022] Furthermore, the switching timing of the ADC based on the multi-bit quantization pipeline structure and capacitor correction is as follows: Figure 2 As shown, specifically: when sampling starts, SWSA and SWSB are turned on at the same time, and all other switches are turned off, and the input signal is acquired by the first-stage 2bit / cycle-ADC via SWSA and SWSB; after sampling, SWSA and SWSB are turned off, and the first-stage 2bit / cycle-ADC starts quantization; after quantization, the interstage amplifier 105 amplifies the split ADCs SPLIT A and SPLIT B in turn: first, the quantization residual voltage of the capacitor DAC array 100 is amplified to SPLITA by the interstage amplifier 105, at which time SWA1, SWA2 and SWRA are turned on at the same time, and after amplification, SWA1, SWA2 and SWRA are turned off; then, the quantization residual voltage of the capacitor DAC array 101 is amplified to SPLITB by the interstage amplifier 105, at which time SWB1, SWB2 and SWRB are turned on at the same time, and after amplification, SWB1, SWB2 and SWRB are turned off.

[0023] Furthermore, the ADC based on the multi-bit quantization pipeline structure and capacitance correction has a quantization timing as follows: Figure 5As shown, this figure only shows the process and does not represent the actual process time, specifically:

[0024] First, the two capacitor DAC arrays 100 and 101 are sampled. Under the differential signal input, the P-end signal is sampled to the P-end of the capacitor DAC arrays 100 and 101, and the N-end signal is sampled to the N-end of the capacitor DAC arrays 100 and 101; at the same time, the shuffle pointer generation logic generates three shuffle pointers PN1, PN2 and PN3, and the random flip logic generates dither.

[0025] After that, the first-stage 2bit / cycle-ADC starts quantization according to the quantization capacitor selected by the shuffle pointers PN1 and PN2. After quantization, the large unit capacitor in the high-order capacitor group and several small unit capacitors in the low-order capacitor group are exchanged according to PN3, and the voltage switched by a large unit capacitor is replaced by a small unit capacitor.

[0026] Finally, in the capacitor DAC arrays 100 and 101 with correction and quantization digital logic, capacitors are switched according to dither, and different dither voltages are generated in the two capacitor arrays; according to the pipeline mode, during the sampling and quantization process of the first stage, the second stage split ADC quantizes the residual voltage after the last quantization of the first stage 2bit / cycle ADC; next, the inter-stage amplifier amplifies the residual voltage after quantization of 100 and 101, 100 and 101 are in the holding state, and 106 and 107 enter the sampling state in turn. During the amplification process, 106 and 107 are sampled in turn, and after the sampling is completed, both perform quantization operations at the same time.

[0027] Furthermore, the correction algorithm of the ADC based on the multi-bit quantization pipeline structure and capacitance correction relies on the LMS mathematical method. This method has low hardware overhead and is particularly suitable for iterative processing by digital circuits or computers. The basic idea is to calculate the fastest descent direction of the mean square value based on the minimum mean square statistical value criterion, and iterate the weight matrix along the descent direction.

[0028] The entire ADC band correction workflow is as follows Figure 6 As shown in the figure: After the quantization is completed in the first and second stages, the quantization code word D of the unit capacitors of ab or AB is An and D Bn Input to the correction logic, in the correction logic, the error value is obtained by multiplying the quantization code word and the current iteration capacitance weight, and then the iterative step size parameter μ is multiplied with the current quantization code word and the error value to obtain the iterative step STEP of A and B. An and STEP Bn Finally, based on this, update the two-way weights W respectively An and W Bn .

[0029] The correction logic is: the capacitance weights of the large and small units of the first-stage 2bit / cycle-ADC and the capacitance weights of the second-stage split ADC are arranged horizontally to form a matrix, and the k-th iteration results of the two capacitance weights are arranged horizontally into a matrix W kA and W kB The code words corresponding to the lower plate switching of the large and small unit capacitors of the first-stage 2bit / cycle-ADC and the code words of the lower plate switching of the capacitors of the second-stage split ADC are arranged in a matrix, and the code words of the k-th switching of the lower plates of the two capacitors are arranged horizontally as a matrix D kA , D kB , the iteration step parameter is μ, write out the capacitance weight matrix W obtained in each iteration A ′,W B 'as follows:

[0030] (W A ′-W B ′)=(W A -W B )+μ(D kA +D kB ) T [(D kA +D kB )(W A -W B )-2V dither ]

[0031] For the first-stage 2-bit / cycle-ADC, two identical CDACs sample the same input signal. After quantization is completed, the capacitance weights switched by the two CDACs are ideally exactly the same based on the quantization result.

[0032] Therefore, the large and small unit capacitors of all unit capacitor groups of the two CDACs can be uniformly sorted, and the weights of the i-th capacitor are recorded as W ia , W ib , ideally W ia , W ib Equal to the design weight W ia-ideal , W ib-ideal ; The i-th capacitor switching code word of the two CDACs is recorded as D ia , D ib .

[0033] For the unit capacitor group with shuffle, the capacitor weight should correspond to the weight value of each unit capacitor, the switching codeword corresponds to the codeword of each unit capacitor, and the codeword switched according to the dither also corresponds to the switching codeword of the unit capacitor; then ideally D ia , D ib and W ia , Wia The result of multiplication is the same in both paths, that is, the voltage generated by the capacitor DAC on the upper plate is the same. Since the sampled input signal is also the same, the residual voltage error on the two CDACs can be recorded as Δ, recorded as V dither The voltage generated by dither switching, ideally Δ is 2V dither ;

[0034]

[0035] Δ=∑D ia W ia-ideal -∑D ib W in-ideal =2V dither

[0036] Since the capacitor mismatch is not calibrated to the actual value, the mismatch errors of the two capacitors are not the same, and the difference between the current quantization codeword and the current capacitor weight is not 2V. dither , in actual situations, the residual voltage error Δ on the two CDACs is recorded as B;

[0037] B=Δ=∑D ia W ia2 -∑D ib W ib2

[0038] The starting point for the iteration of weight values ​​is a set of design weights W ia-ideal , W ib-ideal , the error between the designed weight and the actual weight with capacitor mismatch is ∈ ia ,∈ ib , after iteration, the real weight W with capacitor mismatch is obtained ia-REAL , W ib-REAL ;

[0039] ΣD ia W ia-REAL =∑D ia W ia-ideal +∑D ia ∈ ia

[0040] ∑D ib W ib-REAL =∑D ib W ib-ideal +∑D ia ∈ ib

[0041] W ia =W ia-REAL +∈ ia

[0042] W ib =W ib-REAL+∈ ib

[0043] B=ΣD ia W ia -ΣD ib W ib =2V dithet +∑D ia ∈ ia -∑D ib ∈ ib

[0044] In order to iterate and obtain the true weight, according to Δ and the current D ia and D ib Modify the current weight value, and the iteration direction is based on the least mean square LMS principle: for a system function matrix X to be solved, if there is a known input matrix A and the result Y satisfying AX = Y, for the system function matrix X after the nth iteration n With AX n =B,BY 2 It is denoted as ε, the iteration step coefficient is denoted as μ, when Y=0, BY is denoted as e, and the iteration direction is obtained as;

[0045]

[0046] Iterate the system function matrix X to be solved according to the iteration direction;

[0047]

[0048] Then the LMS convergence formula is rewritten as a matrix form of capacitor weights and codewords, where Dk ia / b Represents the switching codeword Δout of the i-th bit of the k-th quantization k represents the residual voltage error on the two CDACs for the kth conversion. The matrix containing the weights of the two capacitors is denoted as W, where the weights of the i-th capacitor in the bth path are denoted as W ib , the weights of the i-th capacitor in path a are denoted as W ia :

[0049]

[0050] The weight matrix W is regarded as the system function X, the quantization codeword D is regarded as the input A, and Y is the same voltage difference 2V obtained by the two ADC conversions in an ideal situation. dither , B is the actual voltage difference Δ during the iteration process;

[0051] B=Δout k , X=W,A=Dk,Y=2V dither

[0052] Through this correspondence, the capacitance weight matrix W′ obtained in each iteration can be written as follows;

[0053] W′=W+μDk T (DkW-2V dither ).

[0054] In summary, the present invention proposes a structure based on a multi-bit quantization pipeline ADC, which includes a first-stage 2bit / cycle-ADC, an interstage amplifier for amplifying the residual voltage of two CDAC capacitors, and a second-stage split ADC. In the first-stage 2bit / cycle-ADC, a group shuffle structure is added to realize the feasibility of correction under the condition of a DC input signal, and at the same time, a switching capacitor is added between the groups to realize the correction unification of the two groups of capacitors. After the quantization is completed, a dither is added between the two capacitor DAC arrays 100 and 101 to realize the correction of the weight of the subsequent capacitor. This structure reduces the circuit redundancy of the traditional correction method while ensuring the correction accuracy and quantization speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 It is a schematic diagram of the overall structure of the ADC of the present invention;

[0056] Figure 2 It is the switch timing diagram of the ADC of the present invention;

[0057] Figure 3 It is a structural block diagram of a capacitor DAC array in the first-stage 2bit / cycle-ADC of the present invention;

[0058] Figure 4 A corresponding relationship diagram between the shuffle pointer and the shuffle unit of the present invention;

[0059] Figure 5 It is a calibration flow chart of ADC of the present invention;

[0060] Figure 6 It is the overall working flow diagram of the ADC of the present invention;

[0061] Figure 7 FIG. 4 is a structural block diagram of a capacitor DAC array in an ADC of an embodiment. DETAILED DESCRIPTION

[0062] The present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0063] An ADC based on a multi-bit quantization pipeline structure and capacitance correction, the structure is as follows Figure 1 The overall workflow is as shown in Figure 6 Specifically shown are:

[0064] Step 1: First, during the first-stage 2bit / cycle-ADC sampling process, the shuffle pointer generation logic 207 generates the shuffle pointer required for the first-stage group shuffle, such as Figure 5 As shown. The shuffle pointer can be regarded as a starting point pointing to a certain capacitor, and the subsequent capacitor combinations participating in the quantization of each bit are allocated in sequence, such as Figure 4 shown.

[0065] After entering the quantization stage, according to the shuffle pointers PN1, PN2, 202 and 203, unit capacitors in groups 200 and 201 are randomly selected to participate in the quantization. After the end, according to PN3, a 16C unit capacitor in 200 is replaced by 16 1C unit capacitors in 201 to achieve the calibration and unification of the weights of the high-order capacitor array and the low-order capacitor array. Finally, after the quantization is completed, a reverse dither is added to the A and B capacitor arrays 100 and 101, that is, the lower plate voltage of a unit capacitor in 201 is switched through 205.

[0066] Figure 7 The implementation method of the first-level 8-bit ADC is given as an example, in which the upper four bits and the lower four bits are each in a shuffle unit. When the minimum unit capacitance of the first-level ADC is C, the low-order capacitor group consists of 32 capacitors of size C, and the high-order capacitors consist of 15 capacitors of size 16C. The high-order shuffle unit selects 8, 4, 2, and 1 16C capacitors from the capacitors according to the shuffle pointer and allocates them to the 1st, 2nd, 3rd, and 4th bit quantization. The low-order shuffle unit selects 8, 4, 2, 1, and 1 capacitors of size C according to the shuffle pointer to participate in the 5th, 6th, 7th, and 8th bit quantization (the last capacitor of size 1C does not switch the lower plate voltage). At the end of the quantization, the remaining 16 capacitors are exchanged with the lower plate voltage of a 16C capacitor in the high-order capacitor group, and then a capacitor of size C is selected according to the shuffle pointer to switch its lower plate voltage.

[0067] Step 2: The interstage amplifier 105 sequentially amplifies the upper plate voltages of 100 and 101. After the residual voltage of 100 is amplified to 106, 105 amplifies the residual voltage of 101 to 107. After the amplification is completed, the split ADCs, 106 and 107, independently and simultaneously start the second stage quantization of the residual voltage.

[0068] Step 3: According to the quantization code word D An , D Bn and the current iteration capacitance weight W An and W Bn After multiplication, we get Errn by taking the difference. Then, we convert D An and Errn, D. Bn and Errn are respectively multiplied by the iteration step length μ to obtain two-way iterative step STEP An and STEPBn .

[0069] Step 4: According to STEP An and STEP Bn , update the capacitor weight W An and W Bn .

[0070] Step 5: Repeat steps 1-4 to iterate the capacitance weights. The capacitance weights tend to converge and the ADC performance is significantly improved.

[0071] It can be seen from the above embodiments that the present invention adopts a multi-bit quantization pipeline architecture of a first-stage 2bit / cycle-ADC, an inter-stage amplifier, and a second-stage split ADC, and adds a background correction algorithm with low hardware overhead to correct capacitor mismatch; in the first-stage 2bit / cycle-ADC, a group shuffle structure is added to realize the feasibility of correction under the condition of a DC input signal, and at the same time, a switching capacitor is added between groups to realize the correction unification of the two groups of capacitors. After the quantization is completed, a dither is added between the two capacitor DAC arrays 100 and 101 to realize the correction of the inter-stage gain error. While ensuring the correction accuracy, the present invention corrects the gain error, saves the hardware overhead of correcting the inter-stage gain error in the pipeline ADC, and reduces the circuit redundancy of the traditional correction method.

Claims

1. An ADC based on a multi-bit quantization pipeline structure and capacitance correction, characterized in that: The method comprises a first-stage 2bit / cycle-ADC, an interstage amplifier 105 and a second-stage split ADC; after sampling, the first-stage 2bit / cycle-ADC quantizes the input signal and generates two different quantized residual voltages, and the quantized residual voltages are sequentially amplified by the interstage amplifier to two identical ADCs in the second-stage split ADC, and the second-stage split ADC quantizes the two different amplified residual voltages respectively; The first-stage 2bit / cycle-ADC includes a capacitor DAC array 100, a capacitor DAC array 101, a comparator 102, a comparator 103 and a comparator 104. The two capacitor DAC arrays are exactly the same, and the three comparators are also exactly the same; the P terminal of the capacitor DAC array 100 is connected to the positive input terminal of the comparator 102, and the N terminal is connected to the negative input terminals of the comparator 102 and the comparator 103; the P terminal of the capacitor DAC array 101 is connected to the positive input terminals of the comparator 103 and the comparator 104, and the N terminal is connected to the negative input terminal of the comparator 104; the capacitor DAC array 100 and the capacitor DAC array 101 are connected to the input signals VIP and VIN via sampling switches SWSB and SWSA; The positive input terminal of the inter-stage amplifier 105 is connected to the P terminal of the capacitor DAC array 100 through the switch SWA1, and the P terminal of the capacitor DAC array 101 through the switch SWB1, and the negative input terminal thereof is connected to the N terminal of the capacitor DAC array 100 through the switch SWA2, and the N terminal of the capacitor DAC array 101 through the switch SWB2; the first-stage 2bit / cycle-ADC quantization residual voltage is amplified and output to the second-stage split ADC; The second-stage split ADC includes two identical ADCs SPLIT A and SPLIT B. The input end of SPLIT A is connected to the output end of the inter-stage amplifier 105 via a switch SWRA, and the input end of SPLIT B is connected to the output end of the inter-stage amplifier 105 via a switch SWRB. SPLIT A and SPLIT B respectively convert the quantized residual voltage amplified by the inter-stage amplifier 105.

2. The ADC based on a multi-bit quantization pipeline structure and capacitance correction as claimed in claim 1, characterized in that: The capacitor DAC arrays 100 and 101 each include a set of identical correction and quantization digital logics, specifically: the capacitor DAC array includes a high-order unit capacitor array 200, a low-order unit capacitor array 201, a high-order shuffle unit 202, a low-order shuffle unit 203, a capacitor exchange logic 204, a random flip logic 205, a 2bit / cycle successive approximation logic 206, and a shuffle pointer generation logic 207; The low-order unit capacitor array 201 is composed of 2 K1 +M1 small unit capacitors of size C, where M1 is a redundant capacitor used to satisfy the mutual replacement condition with the high-order capacitor, and K1 is the number of quantization bits of the low-order unit capacitor array 201; The low-order shuffling unit 203 shuffles the low-order unit capacitor array 201 required for low-order quantization; The high-order unit capacitor array 200 consists of 2 K2 -1 size of 2 K1 *C is composed of large unit capacitors, K2 is the number of quantized bits of the high-order unit capacitor array 200; The high-order shuffling unit 202 shuffles the high-order unit capacitor array 200 required for high-order quantization; The low-order shuffle unit 203 selects the capacitors in the low-order unit capacitor array 201 and allocates them to the K2+1th to K1+K2th bit quantization according to the shuffle pointer PN2 generated by the shuffle pointer generation logic 207; The high-order shuffle unit 202 selects capacitors in the high-order unit capacitor array 200 and allocates them to the 1st to K2th quantization bits according to the shuffle pointer PN1 generated by the shuffle pointer generation logic 207; At the end of quantization, according to the shuffle pointer PN3 generated by the shuffle pointer generation logic 207, the capacitor exchange logic 204 uses the 2 low-order unit capacitor array 201. K1 A small unit capacitor replaces a large unit capacitor in the high-order unit capacitor array 200 to achieve calibration of the ratio between the large unit capacitor and the small unit capacitor; Finally, a capacitor of size C is selected according to the random flip logic 205, and its lower plate voltage is switched, so that the switched voltages of the capacitor DAC arrays 100 and 101 are different; this operation amplifies the voltage difference between the two capacitor DAC arrays, so that the inter-stage gain error between the second-stage split ADC and the first-stage 2bit / cycle-ADC can be calibrated; The shuffle pointer generated by the shuffle pointer generation logic 207 points to a certain large / small unit capacitor as a starting point, and the subsequent capacitor combinations participating in each bit quantization are allocated sequentially from the starting point.

3. The ADC based on multi-bit quantization pipeline structure and capacitance correction as claimed in claim 2, characterized in that: The switching sequence is as follows: When sampling starts, SWSA and SWSB are turned on at the same time, and all other switches are turned off. The input signal is acquired by the first-stage 2bit / cycle-ADC via SWSA and SWSB. After sampling, SWSA and SWSB are disconnected, and the first-stage 2bit / cycle-ADC starts quantization; After quantization, the interstage amplifier 105 amplifies the split ADCs SPLIT A and SPLIT B in turn: first, the quantized residual voltage of the capacitor DAC array 100 is amplified to SPLITA by the interstage amplifier 105, at which time SWA1, SWA2 and SWRA are turned on at the same time, and after amplification, SWA1, SWA2 and SWRA are disconnected; then, the quantized residual voltage of the capacitor DAC array 101 is amplified to SPLITB by the interstage amplifier 105, at which time SWB1, SWB2 and SWRB are turned on at the same time, and after amplification, SWB1, SWB2 and SWRB are disconnected.

4. The ADC based on multi-bit quantization pipeline structure and capacitance correction as claimed in claim 1, characterized in that: The specific quantization timing is: First, the two capacitor DAC arrays 100 and 101 are sampled. Under the differential signal input, the P-end signal is sampled to the P-end of the capacitor DAC arrays 100 and 101, and the N-end signal is sampled to the N-end of the capacitor DAC arrays 100 and 101; at the same time, the shuffle pointer generation logic generates three shuffle pointers PN1, PN2 and PN3, and the random flip logic generates dither; Then the first-stage 2bit / cycle-ADC starts quantization according to the quantization capacitor selected by the shuffle pointers PN1 and PN2. After the quantization is completed, the large unit capacitor in the high-order capacitor group and several small unit capacitors in the low-order capacitor group are exchanged according to PN3, and the voltage switched by a large unit capacitor is replaced by a small unit capacitor; Finally, in the capacitor DAC arrays 100 and 101 with correction and quantization digital logic, capacitors are switched according to dither, and different dither voltages are generated in the two capacitor arrays; according to the pipeline mode, during the sampling and quantization process of the first stage, the second stage split ADC quantizes the residual voltage after the last quantization of the first stage 2bit / cycle ADC; next, the inter-stage amplifier amplifies the residual voltage after quantization of 100 and 101, 100 and 101 are in the holding state, and 106 and 107 enter the sampling state in turn. During the amplification process, 106 and 107 are sampled in turn, and after the sampling is completed, both perform quantization operations at the same time.

5. The ADC based on multi-bit quantization pipeline structure and capacitance correction as claimed in claim 1, characterized in that: The specific workflow is: After the quantization is completed in the first and second stages, the quantization code word D of the unit capacitors of ab or AB is An and D Bn Input to the correction logic, in the correction logic, the error value is obtained by multiplying the quantization codeword and the current iteration capacitance weight, and then the iterative step size parameter μ is multiplied with the current quantization codeword and the error value to obtain the iterative step STEP of A and B. An and STEP Bn Finally, based on this, update the two-way weights W respectively An and W Bn ; The correction logic is: the capacitance weights of the large and small units of the first-stage 2bit / cycle-ADC and the capacitance weights of the second-stage split ADC are arranged horizontally to form a matrix, and the k-th iteration results of the two capacitance weights are arranged horizontally into a matrix W kA and W kB The code words corresponding to the lower plate switching of the large and small unit capacitors of the first-stage 2bit / cycle-ADC and the code words of the lower plate switching of the capacitors of the second-stage split ADC are arranged in a matrix, and the code words of the k-th switching of the lower plates of the two capacitors are arranged horizontally as a matrix D kA , D kB , the iteration step parameter is μ, write out the capacitance weight matrix W obtained in each iteration A ′,W B 'as follows: (IN' A -IN B ′)=(In A -IN B )+μ(D kA +D kB ) T [(D kA +D kB )(IN A -IN B )-2V dither ] For the first-stage 2-bit / cycle-ADC, two identical CDACs sample the same input signal, and after quantization, the capacitance weights switched by the two CDACs are ideally exactly the same based on the quantization result; Therefore, the large and small unit capacitors of all unit capacitor groups of the two CDACs can be uniformly sorted, and the weights of the i-th capacitor are recorded as W ia , W ib , ideally W ia , W ib Equal to the design weight W ia-ideal , W ib-ideal ; The i-th capacitor switching code of the two CDACs is recorded as D ia , D ib ; For the unit capacitor group with shuffle, the capacitor weight should correspond to the weight value of each unit capacitor, the switching codeword corresponds to the codeword of each unit capacitor, and the codeword switched according to the dither also corresponds to the switching codeword of the unit capacitor; then ideally D ia , D ib and W ia , W ia The result of multiplication is the same in both paths, that is, the voltage generated by the capacitor DAC on the upper plate is the same. Since the sampled input signal is also the same, the residual voltage error on the two CDACs can be recorded as Δ, recorded as V dither The voltage generated by dither switching, ideally Δ is 2V dither ; Δ=∑D ia IN ia-idedl -∑D ib IN ib-idedl =2V dither Since the capacitor mismatch is not calibrated to the actual value, the mismatch errors of the two capacitors are not the same, and the difference between the current quantization codeword and the current capacitor weight is not 2V. dither , in actual situations, the residual voltage error Δ on the two CDACs is recorded as B; B=Δ=∑D ia W ia2 -∑D ib W ib2 The starting point for the iteration of weight values ​​is a set of design weights W ia-ideal , W ib-ideal , the error between the designed weight and the actual weight with capacitor mismatch is ∈ ia ,∈ ib , after iteration, the real weight W with capacitor mismatch is obtained ia-REAL , W ib-REAL ; ∑D ia IN ia-REAL =∑D ia IN ia-ideal +∑D ia ∈ ia ∑D ib IN ib-REAL =∑D ib IN ib-ideal +∑D ia ∈ ib IN ia =In ia-REAL +∈ ia IN ib =In ib-REAL +∈ ib B=∑D ia W ia -∑D ib W ib =2V dtther +∑D ia ∈ ia -∑D ib ∈ ib In order to iterate and obtain the true weight, according to Δ and the current D ia and D ib Modify the current weight value, and the iteration direction is based on the least mean square LMS principle: for a system function matrix X to be solved, if there is a known input matrix A and the result Y satisfying AX = Y, for the system function matrix X after the nth iteration n With AX n =B,BY 2 It is denoted as ε, the iteration step coefficient is denoted as μ, when Y = 0, BY is denoted as e, and the iteration direction is obtained; Iterate the system function matrix X to be solved according to the iteration direction; Then the LMS convergence formula is rewritten as a matrix form of capacitor weights and codewords, where Dk ia / b Represents the switching codeword Δout of the i-th bit of the k-th quantization k represents the residual voltage error on the two CDACs for the kth conversion. The matrix containing the weights of the two capacitors is denoted as W, where the weights of the i-th capacitor in the bth path are denoted as W ib , the weights of the i-th capacitor in path a are denoted as W ia : The weight matrix W is regarded as the system function X, the quantization codeword D is regarded as the input A, and Y is the same voltage difference 2V obtained by the two ADC conversions in an ideal situation. dither , B is the actual voltage difference Δ during the iteration process; B=Δout k ,X=W,A=Dk,Y=2V dither Through this correspondence, the capacitance weight matrix W′ obtained in each iteration can be written as follows: W′=W+μDk T (DkW-2V dither )。

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