A wide bandgap semiconductor trench gate MOSFET structure and manufacturing method thereof

Abstract

The present invention provides a wide bandgap semiconductor trench gate MOSFET structure and a manufacturing method thereof, wherein the N+ current expansion layer is located in the upper region of the N-epitaxial layer; the P-well region is located on the N+ current expansion layer, and the source N+ region is located on the P-well region; a plurality of trench gate electrodes are arranged at intervals in the horizontal direction, and a first source P+ region is provided between two adjacent trench gate electrodes located in the middle region; the trench gate electrode penetrates the source N+ region, the P-well region and the N+ current expansion layer in the longitudinal direction and extends into the N-epitaxial layer; a second source P+ region is provided at the bottom of the trench gate electrode; a P-type connection region connects a plurality of second source P+ regions in the second direction; an interlayer dielectric layer is provided above the trench gate electrode; an N+ contact region is extended and arranged in the first direction at the first source P+ region, and a Schottky contact region is located above the N+ contact region. The structure can improve the device current density, improve the conduction characteristics of the device, and can also form a mesh P-type region to protect the gate electrode, thereby improving the dynamic reliability of the device gate.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a wide bandgap semiconductor trench gate MOSFET structure and a manufacturing method thereof. Background Art

[0002] At present, silicon carbide (SiC) devices have more advantages than silicon (Si) devices in physical properties such as bandgap width, breakdown field strength, and electron saturation drift velocity. The prepared power devices such as diodes, transistors, and power modules have better electrical properties and can overcome the defects of high power, high voltage, high frequency, high temperature and other application requirements that silicon-based devices cannot meet. It is also one of the breakthrough paths that is expected to surpass Moore's Law. Therefore, it is widely used in new energy fields (photovoltaics, energy storage, charging piles, electric vehicles, etc.).

[0003] There are still several problems in the actual process manufacturing and application of trench gate MOSFET devices made of wide bandgap semiconductor materials: 1) The high electric field in the drift region of the material leads to a high electric field on the gate dielectric layer. This problem is exacerbated at the groove corner, causing the gate dielectric layer to break down quickly under high drain voltage; the tolerance to electrostatic effects in harsh environments and high-voltage spikes in the circuit is poor; 2) Trench MOSFET requires a P-type region to protect the gate groove corner, and the P-type region needs to remain grounded to improve the dynamic characteristics of the device. Therefore, the P-type region will occupy a certain chip area, and the spacing between cells is difficult to reduce after a certain width. New structural design and layout are needed to reduce the cell distance, further improve the device current density, and improve the overall conduction characteristics of the device.

[0004] Therefore, it is necessary to perform new structural design and layout for the trench gate MOSFET device structure. The present invention provides a new wide bandgap semiconductor trench gate MOSFET structure and layout design. Summary of the invention

[0005] Based on the above description, the present invention provides a wide bandgap semiconductor trench gate MOSFET structure and a manufacturing method thereof, which can solve the problem of poor electrostatic effects of MOSFET devices in harsh environments and poor high-voltage spike tolerance in circuits, and can also reduce the cell width at intervals, thereby increasing the device current density and improving the overall conduction characteristics of the device.

[0006] The technical solution of the present invention to solve the above technical problems is as follows:

[0007] In a first aspect, the present invention provides a wide bandgap semiconductor trench gate MOSFET structure, comprising: an N+ substrate, an N-epitaxial layer, an N+ current spreading layer, a P-type connection region, a P-well region, a first source P+ region, a second source P+ region, a source N+ region, a trench gate electrode, an interlayer dielectric layer, an N+ contact region, and a Schottky contact region;

[0008] The N-epitaxial layer is located above the N+ substrate, and the N+ current spreading layer is located in the upper region of the N-epitaxial layer; the P-well region is located on the N+ current spreading layer, and the source N+ region is located on the P-well region;

[0009] There are multiple trench gate electrodes, any of which is extended and arranged along the first direction; multiple trench gate electrodes are arranged at intervals along the second direction, and the first source P+ region is provided between two adjacent trench gate electrodes located in the middle area; any trench gate electrode penetrates the source N+ region, the P-well region and the N+ current expansion layer from top to bottom along the longitudinal direction and extends to the N-epitaxial layer; the second source P+ region is provided at the bottom of any trench gate electrode; the P-type connection region connects multiple second source P+ regions in the second direction; the interlayer dielectric layer is provided above any trench gate electrode;

[0010] The N+ contact region and the first source P+ region are arranged at intervals along the first direction, and the Schottky contact region is located above the N+ contact region, so as to form a junction barrier Schottky diode integrated in the N+ contact region;

[0011] Wherein, the first direction and the second direction are both horizontal transverse directions and are arranged perpendicular to each other.

[0012] Based on the above technical solution, the present invention can also be improved as follows.

[0013] Further, the first source P+ region and the N+ contact region penetrate the source N+ region, the P-well region and the N+ current spreading layer from top to bottom along the longitudinal direction and extend into the N- epitaxial layer;

[0014] The bottoms of the first source P+ region and the second source P+ region are both wrapped by the N-epitaxial layer.

[0015] Furthermore, the horizontal distance between two adjacent trench gate electrodes located in the middle region is defined as L1, and the horizontal distance between two adjacent trench gate electrodes located on both sides is defined as L2; ​​L1 is greater than L2.

[0016] Furthermore, the P-type connection region is used to connect the first source P+ region and the second source P+ region located on both sides of L1 and located on both sides of L2.

[0017] Further, the P-type connection region includes a first P-type connection region and a second P-type connection region;

[0018] The first P-type connection region connects the second source P+ region on both sides of L1 and the first source P+ region in the middle, and the second source P+ region on both sides of one group L2;

[0019] The second P-type connection region connects the second source P+ regions at two sides of another group L2.

[0020] Further, the P-type connection region is an overall P-type connection region;

[0021] The overall P-type connection region penetrates and connects all of the first source P+ region and the second source P+ region.

[0022] Further, the P-type connection region includes a plurality of sub-P-type connection regions;

[0023] The plurality of sub-P-type connection regions are respectively connected to two or more of the second source P+ regions, and one of the sub-P-type connection regions is also connected to the first source P+ region to achieve connection between all the second source P+ regions and the first source P+ region.

[0024] Furthermore, the trench gate electrode includes a gate trench, a gate dielectric layer and gate polysilicon;

[0025] The gate trench penetrates the source N+ region and the P-well region from top to bottom in a vertical direction and extends into the N+ current spreading layer;

[0026] The gate dielectric layer is disposed on the inner wall side of the gate trench, and the gate trench is filled with the gate polysilicon.

[0027] Furthermore, the wide bandgap semiconductor trench gate MOSFET structure also includes an ohmic contact region, a source electrode and a drain electrode;

[0028] The ohmic contact region is located above the source N+ region and the first source P+ region, and the source is located above the ohmic contact region; the interlayer dielectric layer is located above the trench gate electrode, and the Schottky contact region is located in the ohmic contact region; the drain is located at the bottom of the N+ substrate.

[0029] In a second aspect, the present invention further provides a method for manufacturing a wide bandgap semiconductor trench gate MOSFET structure as described in the first aspect, comprising:

[0030] epitaxially growing an N-epitaxial layer and an N-current spreading layer in sequence on the substrate;

[0031] By ion implantation into the P-well region and the source N+ region;

[0032] Forming a first source P+ region and a second source P+ region by P-type ion implantation;

[0033] An N+ contact region is formed by N-type ion implantation; a P-type connection region is formed by P-type ion implantation;

[0034] forming a gate trench by dry etching;

[0035] Performing gate dielectric growth, gate polysilicon growth and etching in the gate trench, and performing interlayer dielectric growth and etching;

[0036] Ohmic contact metal deposition and Schottky metal deposition;

[0037] The wide bandgap semiconductor trench gate MOSFET structure is obtained by depositing and etching the source metal and depositing the drain metal.

[0038] Compared with the prior art, the technical solution of this application has the following beneficial technical effects:

[0039] The wide bandgap semiconductor trench gate MOSFET structure and the manufacturing method thereof provided by the present invention have the following advantages:

[0040] 1. The mesh distribution of the P-type connection area in the layout can ensure that all the first source P+ area and the second source P+ area maintain the ground potential, which can reduce the gate oxide electric field and improve the dynamic reliability of the gate;

[0041] 2. The first source P+ region and the second source P+ region are formed by the same P-type ion implantation process. The traditional process is to form the source P+ region and the P+ masking region at the bottom of the trench by two steps. This process manufacturing method can reduce the process steps and further reduce the process cost.

[0042] 3. By designing trench spacings of different widths and designing different P-type connection areas and source P+ areas between trenches of different widths, the actual effective width of the cell can be further reduced, the cell density of the device can be increased, and the conduction characteristics of the device can be further improved;

[0043] 4. The channels above the P-type connection area can conduct current. Electrons flow downward from the channels on the sidewalls of the trench into the N-current extension area, and then conduct in a direction parallel to the trench, eventually passing downward through the N-epitaxial layer to reach the drain. In other words, in such a trench gate MOSFET structure, a mesh P-type region can be formed to protect the gate, which can also conduct current, further improving the conduction characteristics of the device.

[0044] 5. The JBS diode integrated with the N+ contact region and the Schottky contact region will have a lower reverse conduction voltage drop than the traditional trench MOSFET, and can further improve the dynamic characteristics of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A schematic diagram of the cross-sectional structure at section A of a wide bandgap semiconductor trench gate MOSFET structure provided in Embodiment 1 of the present invention;

[0046] Figure 2 A schematic diagram of the cross-sectional structure at the cross section B of the wide bandgap semiconductor trench gate MOSFET structure provided in Embodiment 1 of the present invention;

[0047] Figure 3 A schematic cross-sectional structure diagram of a wide bandgap semiconductor trench gate MOSFET structure at a cross section C provided in Example 1 of the present invention;

[0048] Figure 4 A schematic diagram of the transverse cross-sectional structure of a wide bandgap semiconductor trench gate MOSFET structure provided in Example 1 of the present invention;

[0049] Figure 5 and Figure 6 Another exemplary schematic diagram of a wide bandgap semiconductor trench gate MOSFET structure provided in Embodiment 1 of the present invention;

[0050] Figure 7 A schematic diagram of the cross-sectional structure at section A of a wide bandgap semiconductor trench gate MOSFET structure provided in Embodiment 2 of the present invention;

[0051] Figure 8 A schematic diagram of a transverse cross-sectional structure of a wide bandgap semiconductor trench gate MOSFET structure provided in Embodiment 3 of the present invention;

[0052] Fig. 9 A schematic diagram of the cross-sectional structure at section A of a wide bandgap semiconductor trench gate MOSFET structure provided in Embodiment 3 of the present invention;

[0053] Fig.10 A schematic diagram of a transverse cross-sectional structure of a wide bandgap semiconductor trench gate MOSFET structure provided in Embodiment 4 of the present invention;

[0054] Fig.11 A schematic diagram of the cross-sectional structure at section A of a wide bandgap semiconductor trench gate MOSFET structure provided in Embodiment 4 of the present invention;

[0055] Fig.12 A schematic diagram of a transverse cross-sectional structure of a wide bandgap semiconductor trench gate MOSFET structure provided in Example 5 of the present invention;

[0056] Fig.13 A schematic diagram of the cross-sectional structure at section A of a wide bandgap semiconductor trench gate MOSFET structure provided in Embodiment 5 of the present invention;

[0057] Fig.14A schematic diagram of a transverse cross-sectional structure of a wide bandgap semiconductor trench gate MOSFET structure provided in Example 6 of the present invention;

[0058] Fig.15 A schematic diagram of a lateral cross-sectional structure of a wide bandgap semiconductor trench gate MOSFET structure provided in Example 7 of the present invention;

[0059] Fig.16 A schematic diagram of a transverse cross-sectional structure of a wide bandgap semiconductor trench gate MOSFET structure provided in Example 8 of the present invention;

[0060] Fig.17 A schematic diagram of the cross-sectional structure at section A of a wide bandgap semiconductor trench gate MOSFET structure provided in Example 8 of the present invention;

[0061] Fig.18 A schematic diagram of a transverse cross-sectional structure of a wide bandgap semiconductor trench gate MOSFET structure provided in Embodiment 9 of the present invention;

[0062] Fig.19 A schematic diagram of a lateral cross-sectional structure of a wide bandgap semiconductor trench gate MOSFET structure provided in Embodiment 10 of the present invention;

[0063] Figures 20 to 23 A schematic diagram of a transverse cross-sectional structure of a wide bandgap semiconductor trench gate MOSFET structure provided in Embodiment 11 of the present invention;

[0064] Fig.24 A schematic flow chart of a method for manufacturing a wide bandgap semiconductor trench gate MOSFET structure provided in Example 12 of the present invention;

[0065] Fig.25 A schematic diagram of the transverse cross-sectional structure of a wide bandgap semiconductor trench gate MOSFET structure provided in Example 13 of the present invention;

[0066] Fig.26 A schematic diagram of the cross-sectional structure at section A of a wide bandgap semiconductor trench gate MOSFET structure provided in Embodiment 13 of the present invention;

[0067] In the accompanying drawings, the components represented by the reference numerals are listed as follows:

[0068] 1. N+ substrate; 2. N- epitaxial layer; 3. N+ current spreading layer; 4. P-well region; 5. Source N+ region; 6. First source P+ region; 7. Second source P+ region; 8. P-type connection region; 9. Trench gate electrode; 901. Gate trench; 902. Gate dielectric layer; 903. Gate polysilicon; 10. Interlayer dielectric layer; 11. Source; 12. Drain; 13. N+ contact region; 14. Schottky contact region; 15. Ohmic contact region. DETAILED DESCRIPTION

[0069] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0070] It will be appreciated that spatial relationship terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It will be appreciated that, in addition to the orientations shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "on" the other elements or features. Therefore, the exemplary terms "on the front side of" and "on the back side of" are only used to define two opposing sides. In addition, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0071] It should be noted that the terms "first", "second" and "third" in the specification, claims and drawings of this application are used to distinguish different objects rather than to limit a specific order.

[0072] In the prior art, in order to better protect the gate oxide layer of the trench MOSFET, especially the bottom and the trench corners, the common device structure of the products of companies in the industry is to use auxiliary P-type injection masking at the bottom or both sides of the trench gate. For example, the product structure of Infineon's silicon carbide trench MOSFET uses a P-type shielding to protect the bottom of the gate trench at the bottom of the trench and one side.

[0073] The defects of the above scheme are: only one side of the bottom of the trench is protected by the P-type shielding area, which makes it difficult to better protect the gate groove corner electric field; further, the P-type masking structure of the existing product will cause a deeper JFET area on the current path, and the masking effect of reducing the trench corner electric field and the device conduction characteristics show a trade-off contradiction; at the same time, due to the design of the P-type ion implantation width of silicon carbide, it is difficult to further reduce the cell pitch, so it is difficult to further improve the device conduction characteristics.

[0074] Based on this, the present invention provides a novel wide bandgap semiconductor trench gate MOSFET structure and a manufacturing method thereof. The following is a further detailed description of the implementation of the present invention in conjunction with the accompanying drawings and embodiments. The following embodiments are used to illustrate the present invention but cannot be used to limit the scope of the present invention.

[0075] Example 1

[0076] This embodiment provides a wide bandgap semiconductor trench gate MOSFET structure, Figure 1 The schematic diagram of the cross section A is shown. Figure 2 The schematic diagram of the cross section B is shown. Figure 3 Shown is a schematic diagram of section C, where section C is the main section, occupying 80%-90% of the chip area, and section A and section B each occupy 5%~10% of the area. While ensuring the normal characteristics of the device, the area of ​​section C can be continuously increased and the areas of section A and section B can be reduced.

[0077] The wide bandgap semiconductor trench gate MOSFET structure includes: an N+ substrate 1, an N-epitaxial layer 2, an N+ current spreading layer 3, a P-type connection region 8, a P-well region 4, a first source P+ region 6, a second source P+ region 7, a source N+ region 5, a trench gate electrode 9, an interlayer dielectric layer 10, an N+ contact region 13 and a Schottky contact region 14.

[0078] The N-epitaxial layer 2 is located above the N+ substrate 1 , and the N+ current spreading layer 3 is located in the upper region of the N-epitaxial layer 2 ; the P-well region 4 is located on the N+ current spreading layer 3 , and the source N+ region 5 is located on the P-well region 4 .

[0079] There are multiple trench gate electrodes 9, and any trench gate electrode 9 is extended along the first direction; multiple trench gate electrodes 9 are arranged at intervals along the second direction, and a first source P+ region 6 is provided between two adjacent trench gate electrodes 9 located in the middle area; any trench gate electrode 9 penetrates the source N+ region 5, the P-well region 4 and the N+ current expansion layer 3 from top to bottom along the longitudinal direction and extends to the N-epitaxial layer 2; a second source P+ region 7 is provided at the bottom of any trench gate electrode 9; the P-type connection region 8 connects multiple second source P+ regions 7 in the second direction; an interlayer dielectric layer 10 is provided above any trench gate electrode 9.

[0080] The N+ contact region 13 and the first source P+ region 6 are arranged at intervals along the first direction, and the Schottky contact region 14 is located above the N+ contact region 13 to form a junction barrier Schottky diode integrated in the N+ contact region 13 .

[0081] Among them, Figure 4 As shown, the first direction and the second direction are both horizontal transverse directions and are arranged perpendicular to each other.

[0082] Specifically, Figure 2 and Figure 3 As shown, there is an N+ contact region between the wider L1 of section B and section C. The P-type region is compounded into an N-type region by an ion implantation concentration greater than that of the P-well, and a Schottky metal is deposited on the N+ contact region, that is, a junction barrier Schottky diode (JBS) is integrated here.

[0083] Among them, Figure 1 and Figure 2 As shown, the first source P+ region 6 and the N+ contact region 13 penetrate the source N+ region 5 , the P-well region 4 and the N+ current spreading layer 3 from top to bottom along the longitudinal direction and extend into the N- epitaxial layer 2 .

[0084] like Figure 1 As shown, the bottoms of the first source P+ region 6 and the second source P+ region 7 are both wrapped by the N-epitaxial layer 2 .

[0085] The wide bandgap semiconductor trench gate MOSFET structure also includes an ohmic contact region 15, a source 11 and a drain 12;

[0086] The ohmic contact region 15 is located above the source N+ region 5 and the first source P+ region 6, and the source 11 is located above the ohmic contact region 15; the interlayer dielectric layer 10 is located above the trench gate electrode 9, and the Schottky contact region 14 is located in the ohmic contact region 15; the drain 12 is located at the bottom of the N+ substrate 1.

[0087] The source 11 is located above the source N+ region 5 and the trench gate electrode 9 , and the interlayer dielectric layer 10 is located in the source 11 ; the drain 12 is located at the bottom of the N+ substrate 1 .

[0088] In an optional embodiment, if Figure 1 As shown, the trench gate electrode 9 includes a gate trench 901 , a gate dielectric layer 902 and a gate polysilicon 903 .

[0089] The gate trench 901 penetrates the source N+ region 5 and the P-well region 4 from top to bottom along the vertical direction and extends into the N+ current spreading layer 3 .

[0090] A gate dielectric layer 902 is disposed on the inner wall side of the gate trench 901 , and the gate trench 901 is filled with gate polysilicon 903 .

[0091] Furthermore, if Figure 1 As shown, the horizontal distance between two adjacent trench gate electrodes 9 located in the middle region is defined as L1, and the horizontal distance between two adjacent trench gate electrodes 9 located on both sides is defined as L2; ​​L1 is greater than L2.

[0092] It should be noted that the trenches in the layout are generally distributed in long strips in the vertical direction. In order to ensure that the horizontal cell distance can be further reduced, the source P+ region is generally not designed in the vertical region where L2 exists. As long as the channels on both sides of L2 do not cause current crowding, the width of this part can be minimized. The width of L1 is greater than that of L2 to facilitate the formation of a square-shaped first source P+ region 6, such as Figure 4 As shown, this area will occupy a certain width, while ensuring that the trenches on both sides of the first source P+ region 6 can still conduct current.

[0093] The P-type connection region 8 is used to connect the first source P+ region 6 and the second source P+ region 7 located on both sides of L1 and both sides of L2.

[0094] The mesh distribution of the P-type connection region 8 in the layout can ensure that all the first source P+ region 6 and the second source P+ region 7 maintain the ground potential. That is, the electrons enter the N-current extension region from the channel on the side wall of the trench downward, and then enter the N-current extension region in a direction parallel to the trench. Figure 3 In the cross-section C region shown, the drain 12 is finally reached through the N-epitaxial layer 2 .

[0095] The P-type connection region 8 may be arranged in a variety of ways. In this embodiment, the P-type connection region 8 includes two types of P-type connection regions 8 : a first P-type connection region 8 and a second P-type connection region 8 .

[0096] like Figure 1 and Figure 4 As shown, the first P-type connection region 8 connects the second source P+ region 7 on both sides of L1 and the first source P+ region 6 in the middle, as well as the second source P+ region 7 on both sides of one group of L2, where "one group" refers to Figure 4 Left side shown.

[0097] The second P-type connection region 8 is connected to the second source P+ region 7 on both sides of another group L2, where "another group" refers to Figure 4 As shown on the right side, of course, those skilled in the art can adaptively change the left-right order according to this description, which can also fall within the protection scope of the embodiment of the present invention.

[0098] The width of the second source P+ region 7 is not less than the width of the gate trench 901. In one example, Figure 4 As shown, the width of the second source P+ region 7 is greater than the width of the gate trench 901; but preferably, as Figure 5 and Figure 6 As shown, the width of the second source P+ region 7 is equal to the trench width. When the width of the second source P+ region 7 is equal to the trench width, the gate trench angle can be better protected, the gate trench angle electric field can be reduced, and the gate dynamic reliability can be improved.

[0099] In this embodiment, the lateral cross-section of the first source P+ region 6 may be in the shape of a square. Figure 4 shown.

[0100] Example 2

[0101] Based on the above-mentioned embodiment 1, the difference lies in that: the P-type connection region includes a plurality of sub-P-type connection regions; the plurality here means two or more, and when there are two, the arrangement method is also different from that of embodiment 1.

[0102] The plurality of sub-P-type connection regions are respectively connected to two or more second source P+ regions, wherein one of the sub-P-type connection regions is also connected to the first source P+ region, so as to realize connection between all the second source P+ regions and the first source P+ region.

[0103] Specific examples include: Figure 7 As shown, it includes three sub-P type connection areas. In cross section A, the middle sub-P type connection area only includes L1 and part of the gate area on both sides thereof, and does not pass through L2. Two sub-P type connection areas are then used to connect the second source P+ areas at the bottom of the gates on both sides of L2.

[0104] Example 3

[0105] Based on the above embodiment 1, the difference lies in that: the P-type connection region is an overall P-type connection region; the overall P-type connection region penetrates and connects all the first source P+ region and the second source P+ region.

[0106] Specific examples include: Figure 8 and Fig. 9 As shown, an overall P-type connection area can connect the second source P+ areas at the bottom of all trenches, including the first source P+ areas, and the P-type connection area is grounded through the first source P+ areas in some areas, thereby improving the gate dynamic reliability of the device.

[0107] Example 4

[0108] Based on the above embodiment 3, Fig.10 and Fig.11 As shown, the wide bandgap semiconductor trench gate MOSFET structure provided by this embodiment has a first source P+ region within the L2 spacing on the left side, and the P-type connection region can connect all the second source P+ regions at the bottom of the trench, and then the P-type connection region is grounded through the first source P+ region within the L1 spacing and the first source P+ region within the L2 spacing, thereby improving the gate dynamic reliability of the device.

[0109] Example 5

[0110] Based on the above embodiment 3, Fig.12 and Fig.13As shown, the wide bandgap semiconductor trench gate MOSFET structure provided by this embodiment has some second source P+ regions wrapping the outer side of the corresponding entire gate electrode. In this example, there is a second source P+ region on the left and right sides respectively wrapping the outer side of the corresponding entire gate electrode. The P-type connection region can connect all the second source P+ regions at the bottom of the trench, and then the P-type connection region is grounded through the first source P+ region within the L1 spacing and the source P+ region outside the trench, thereby improving the gate dynamic reliability of the device.

[0111] Example 6

[0112] On the basis of the above-mentioned Embodiment 2 and Embodiment 3, Fig.14 As shown, in the wide bandgap semiconductor trench gate MOSFET structure provided by this embodiment, the P-type connection region in a partial area can be connected to all the second source P+ regions at the bottom of the trenches, and then the P-type connection region is grounded using the first source P+ region in a partial spacing at the L1 spacing, and the P-type connection region is grounded using the first source P+ region in the entire spacing at the L2 spacing, thereby improving the dynamic reliability of the gate of the device.

[0113] Example 7

[0114] On the basis of the above-mentioned embodiment 6, Fig.15 As shown, in the wide bandgap semiconductor trench gate MOSFET structure provided by this embodiment, the P-type connection region in a partial area can be connected to all the second source P+ regions 7 at the bottom of the trenches, and then the P-type connection region is grounded using the first source P+ region in a partial spacing in the L1 spacing, and a smaller width trench is used in the area where the first source P+ region needs to be injected in the L2 spacing, and then the P-type connection region is grounded using the first source P+ region in the partial spacing, so that current conduction can still be guaranteed within the L2 spacing, and the conduction characteristics of the device are improved by designing different trench widths in different areas.

[0115] Example 8

[0116] On the basis of the above-mentioned embodiment 1, Fig.16 and Fig.17 As shown, in the wide bandgap semiconductor trench gate MOSFET structure provided by this embodiment, the shape of the first source P+ region occupies the entire width of L1, which can better protect the gates on both sides.

[0117] Example 9

[0118] On the basis of the above-mentioned embodiment 1, Fig.18 As shown, in the wide bandgap semiconductor trench gate MOSFET structure provided by this embodiment, the spacing between gates can also be arranged as L2-L1-L1, and a first source P+ region can be formed between two L1s.

[0119] Example 10

[0120] On the basis of the above-mentioned embodiment 9, Fig.19 As shown, in the wide bandgap semiconductor trench gate MOSFET structure provided in this embodiment, the spacing between gates can also be arranged as L2-L1-L1, and a first source P+ region can be formed between two L1s, and the shape of the first source P+ region can also occupy the entire L1 width.

[0121] Embodiment 11

[0122] On the basis of the above-mentioned embodiment 1, Figures 20 to 23 As shown, in the wide bandgap semiconductor trench gate MOSFET structure provided in this embodiment, the shape of the first source P+ region can be a block shape as shown in embodiment 1, or can be a Fig. 20 The triangle shown, Fig.21 The hexagon shown, Fig. 22 The circle shown, Fig.23 The shape of the concentric circles shown may also be a rectangle, an octagon, or the like.

[0123] Example 12

[0124] This embodiment also provides a method for manufacturing a wide bandgap semiconductor trench gate MOSFET structure (using cross section A, cross section B, and cross section C as examples for illustration), see Fig.24 As shown, the operation is as follows:

[0125] Step S1 (cross section A & B): grow an N-epitaxial layer and an N-current spreading layer on a wide bandgap semiconductor material (SiC / GaN / Ga2O3 / C / AlN, etc.) substrate.

[0126] Step S2 (cross section A & B): forming a P-well region and a source N+ region by ion implantation.

[0127] Step S3 (cross section A): forming a plurality of source P+ regions, including a first source P+ region and a second source P+ region, by P-type ion implantation.

[0128] Here, it should be noted that the first source P+ region and the second source P+ region are formed by the same P-type ion implantation process. The traditional process is to form the source P+ region and the P+ masking region at the bottom of the trench through two steps respectively. This process manufacturing method can reduce the process steps and further reduce the process cost.

[0129] Step S4 (cross section B & C): forming an N+ contact region by N-type ion implantation;

[0130] Step S5 (cross section A): forming a P-type connection region by P-type ion implantation.

[0131] Step S6 (cross section A): forming a gate trench by dry etching.

[0132] Step S7 (cross section A): gate dielectric growth, gate polysilicon growth and etching, interlayer dielectric growth and etching.

[0133] Step S8 (cross section A and cross section B): Ohmic contact metal deposition and Schottky metal deposition;

[0134] Step S9 (cross section A and cross section B): source metal deposition and etching, drain metal deposition.

[0135] Example 13

[0136] On the basis of the above-mentioned embodiment 12, Fig.25 and 26 As shown, in the method for manufacturing a wide bandgap semiconductor trench gate MOSFET structure provided by this embodiment, in step S3, the first source P+ region and the second source P+ region can be formed separately, by forming the source P+ region by ion implantation before trench etching, and forming the P+ masking region by ion implantation after trench etching.

[0137] The wide bandgap semiconductor trench gate MOSFET structures provided in the above-mentioned embodiments 1 to 11, and the manufacturing methods provided in embodiments 12 and 13, have the following advantages compared with the prior art:

[0138] 1. The mesh distribution of the P-type connection area in the layout can ensure that all the first source P+ area and the second source P+ area maintain the ground potential, which can reduce the gate oxide electric field and improve the dynamic reliability of the gate;

[0139] 2. The first source P+ region and the second source P+ region are formed by the same P-type ion implantation process. The traditional process is to form the source P+ region and the P+ masking region at the bottom of the trench by two steps. This process manufacturing method can reduce the process steps and further reduce the process cost.

[0140] 3. By designing trench spacings of different widths and designing different P-type connection areas and source P+ areas between trenches of different widths, the actual effective width of the cell can be further reduced, the cell density of the device can be increased, and the conduction characteristics of the device can be further improved;

[0141] 4. The channels above the P-type connection area can conduct current. Electrons flow downward from the channels on the sidewalls of the trench into the N-current extension area, and then conduct in a direction parallel to the trench, eventually passing downward through the N-epitaxial layer to reach the drain. In other words, in such a trench gate MOSFET structure, a mesh P-type region can be formed to protect the gate, which can also conduct current, further improving the conduction characteristics of the device.

[0142] 5. The JBS diode integrated with the N+ contact region and the Schottky contact region will have a lower reverse conduction voltage drop than the traditional trench MOSFET, and can further improve the dynamic characteristics of the device.

[0143] In the description of this specification, the description with reference to the terms "specific example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present invention. In this specification, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and the features of different embodiments or examples, unless they are contradictory.

[0144] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A wide bandgap semiconductor trench gate MOSFET structure, characterized in that: include: N+ substrate, N-epitaxial layer, N+ current spreading layer, P-type connection region, P-well region, first source P+ region, second source P+ region, source N+ region, trench gate electrode, interlayer dielectric layer, N+ contact region and Schottky contact region; The N-epitaxial layer is located above the N+ substrate, and the N+ current spreading layer is located in the upper region of the N-epitaxial layer; the P-well region is located on the N+ current spreading layer, and the source N+ region is located on the P-well region; There are multiple trench gate electrodes, any of which is extended and arranged along the first direction; multiple trench gate electrodes are arranged at intervals along the second direction, and the first source P+ region is provided between two adjacent trench gate electrodes located in the middle area; any trench gate electrode penetrates the source N+ region, the P-well region and the N+ current expansion layer from top to bottom along the longitudinal direction and extends to the N-epitaxial layer; the second source P+ region is provided at the bottom of any trench gate electrode; the P-type connection region connects multiple second source P+ regions in the second direction; the interlayer dielectric layer is provided above any trench gate electrode; The N+ contact region and the first source P+ region are arranged in a spaced relationship along the first direction, and the Schottky contact region is located above the N+ contact region, so as to form a junction barrier Schottky diode integrated in the N+ contact region; Wherein, the first direction and the second direction are both horizontal transverse directions and are arranged perpendicular to each other; The horizontal distance between two adjacent trench gate electrodes located in the middle region is defined as L1, and the horizontal distance between two adjacent trench gate electrodes located on both sides is defined as L2; ​​L1 is greater than L2; The P-type connection region is used to connect the first source P+ region and the second source P+ region located on both sides of L1 and located on both sides of L2; The P-type connection region includes a first P-type connection region and a second P-type connection region; The first P-type connection region connects the second source P+ region on both sides of L1 and the first source P+ region in the middle, and the second source P+ region on both sides of one group L2; The second P-type connection region connects the second source P+ regions at two sides of another group L2.

2. The wide bandgap semiconductor trench gate MOSFET structure according to claim 1, characterized in that: The first source P+ region and the N+ contact region penetrate the source N+ region, the P-well region and the N+ current spreading layer from top to bottom along the longitudinal direction and extend into the N- epitaxial layer; The bottoms of the first source P+ region and the second source P+ region are both wrapped by the N-epitaxial layer.

3. The wide bandgap semiconductor trench gate MOSFET structure according to claim 1, characterized in that: The P-type connection region is an overall P-type connection region; The overall P-type connection region penetrates and connects all of the first source P+ region and the second source P+ region.

4. The wide bandgap semiconductor trench gate MOSFET structure according to claim 1, characterized in that: The P-type connection region includes a plurality of sub-P-type connection regions; The plurality of sub-P-type connection regions are respectively connected to two or more of the second source P+ regions, and one of the sub-P-type connection regions is also connected to the first source P+ region to achieve connection between all the second source P+ regions and the first source P+ region.

5. The wide bandgap semiconductor trench gate MOSFET structure according to claim 1, characterized in that: The trench gate electrode comprises a gate trench, a gate dielectric layer and gate polysilicon; The gate trench penetrates the source N+ region and the P-well region from top to bottom in a vertical direction and extends into the N+ current spreading layer; The gate dielectric layer is disposed on the inner wall side of the gate trench, and the gate trench is filled with the gate polysilicon.

6. The wide bandgap semiconductor trench gate MOSFET structure according to claim 1, characterized in that: The wide bandgap semiconductor trench gate MOSFET structure also includes an ohmic contact region, a source electrode and a drain electrode; The ohmic contact region is located above the source N+ region and the first source P+ region, and the source is located above the ohmic contact region; The interlayer dielectric layer is located above the trench gate electrode, the Schottky contact region is located in the ohmic contact region; and the drain is located at the bottom of the N+ substrate.

7. A method for manufacturing a wide bandgap semiconductor trench gate MOSFET structure as claimed in any one of claims 1 to 6, characterized in that: include: epitaxially growing an N-epitaxial layer and an N-current spreading layer in sequence on the substrate; By ion implantation into the P-well region and the source N+ region; Forming a first source P+ region and a second source P+ region by P-type ion implantation; Forming an N+ contact region by N-type ion implantation; Forming a P-type connection region by P-type ion implantation; forming a gate trench by dry etching; Performing gate dielectric growth, gate polysilicon growth and etching in the gate trench, and performing interlayer dielectric growth and etching; Ohmic contact metal deposition and Schottky metal deposition; The wide bandgap semiconductor trench gate MOSFET structure is obtained by depositing and etching the source metal and depositing the drain metal.

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