Double trench SiC MOSFET device with floating P island and preparation method thereof

Abstract

The present invention discloses a floating P-type island double trench SiC MOSFET device and a preparation method, comprising: a first epitaxial layer, comprising a plurality of spaced floating P-type island structures, the floating P-type island structure being located on a first side of the first epitaxial layer; a second epitaxial layer being stacked with the first side of the first epitaxial layer, the second epitaxial layer comprising a gate trench, the gate trench being located on a side of the second epitaxial layer away from the first epitaxial layer, a gate oxide layer and a gate being arranged in the gate trench; the second epitaxial layer further comprising a plurality of spaced P+ type ring structures, along a first direction, the orthographic projection of the P+ type ring structure overlaps with the orthographic projection of the gate trench, and the orthographic projection of the P+ type ring structure overlaps with the orthographic projection of at least part of the floating P-type island structure. The present invention can not only reduce the on-resistance of the device, but also increase the breakdown voltage of the device.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a floating P-island double-trench SiC MOSFET device and a preparation method thereof. Background Art

[0002] As a typical representative of the third-generation semiconductor materials, SiC material has many advantages such as wide bandgap, high thermal conductivity, high critical electric field, and high electron mobility. The devices made from it are one of the most promising devices at present. They have the characteristics of low impedance, high voltage, high temperature, high frequency, high efficiency, and radiation resistance. Therefore, they are widely used in automotive electronics, photovoltaic inverters, energy storage, aerospace and other fields.

[0003] SiC devices mainly include three series: SiC SBD, SiC MOSFET and SiC IGBT. At present, the market is mainly dominated by the development of SiC SBD and SiC MOSFET, while SiC MOSFET mainly has two development routes: planar type and trench type. Trench type devices include single trench series and double trench series. Among them, trench type devices can use the gate trench to eliminate the JFET effect and reduce the conduction loss of the device. However, in the blocking mode, the high electric field is easy to gather at the bottom corner of the gate trench, which will reduce the withstand voltage of the device and easily cause curvature effect.

[0004] Therefore, there is an urgent need to provide a dual trench SiC MOSFET device to improve the defects of the above-mentioned prior art. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a floating P island double trench SiCMOSFET device and a preparation method. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0006] In a first aspect, the present invention provides a floating P island double trench SiC MOSFET device, comprising:

[0007] The first epitaxial layer includes a plurality of spaced-apart floating P-type island structures, wherein the floating P-type island structures are located on a first side of the first epitaxial layer;

[0008] A second epitaxial layer is stacked with the first side of the first epitaxial layer, the second epitaxial layer includes a gate trench, the gate trench is located on the side of the second epitaxial layer away from the first epitaxial layer, and a gate oxide layer and a gate are arranged in the gate trench; the second epitaxial layer also includes a plurality of P+ type ring structures arranged at intervals, along the first direction, the orthographic projection of the P+ type ring structure overlaps with the orthographic projection of the gate trench, and the orthographic projection of the P+ type ring structure overlaps with the orthographic projection of at least part of the floating P-type island structure;

[0009] The first direction is the thickness direction of the first epitaxial layer.

[0010] In a second aspect, the present invention further provides a method for preparing a floating P island double trench SiC MOSFET device, which is used to prepare the floating P island double trench SiC MOSFET device provided above, comprising:

[0011] providing a substrate;

[0012] Epitaxially growing a first epitaxial layer on a substrate, and forming a plurality of spaced-apart floating P-type island structures on a first side of the first epitaxial layer by using a mask and ion implantation;

[0013] A second epitaxial layer is epitaxially grown on the first epitaxial layer, and a gate trench is formed on the side of the second epitaxial layer away from the first epitaxial layer by using a mask and etching method; ion implantation is performed at the bottom of the gate trench using a mask to form a plurality of spaced-apart P+ type ring structures; a gate oxide layer is grown in the gate trench, and a gate is deposited on the gate oxide layer so that the gate oxide layer and the gate fill the gate trench.

[0014] Beneficial effects of the present invention:

[0015] The present invention provides a floating P-type island double-trench SiC MOSFET device and a preparation method, comprising a first epitaxial layer and a second epitaxial layer located on the first epitaxial layer, wherein a first side of the first epitaxial layer is close to the second epitaxial layer, the first epitaxial layer and the second epitaxial layer jointly form a drift region, a first side of the first epitaxial layer is provided with a plurality of spaced floating P-type island structures, a side of the second epitaxial layer facing away from the first epitaxial layer is provided with a gate trench, a plurality of spaced P+-type ring structures are provided below the gate trench, a gate oxide layer and a gate are provided inside the gate trench, and the gate oxide layer and the gate fill the gate trench; in the present invention, on the one hand, in the first epitaxial layer, a plurality of spaced floating P-type island structures are provided, and ... floating P-type island structures are provided below the gate trench, and a plurality of spaced floating P-type island structures are provided below the gate trench, and a plurality of spaced floating P-type island structures are provided below the gate trench, and a plurality of spaced floating P-type island structures are provided below the gate trench, and a plurality of spaced floating P-type island structures are provided below the gate trench, and a plurality of spaced floating P-type island structures are provided below the gate trench, and a plurality of spaced floating P-type island structures are provided above the gate trench, and a plurality of spaced floating P-type island structures are provided below the gate trench, and a plurality of spaced floating P-type island structures are provided above the gate trench, and a plurality of spaced floating P-type island structures are provided below the gate trench, and a plurality of spaced floating P-type island structures are provided above the gate trench, and a plurality of spaced floating P-type A plurality of floating P-type island structures are arranged on the first side of the epitaxial layer. The floating P-type island structures and the first epitaxial layer form a plurality of laterally arranged PN junctions. The charge balance principle is utilized to optimize the electric field distribution in the drift region, thereby further reducing the on-resistance and improving the breakdown voltage of the device. On the other hand, without adding any process steps or difficulties, a plurality of P+ ring structures are arranged below the gate trench in the second epitaxial layer, which can effectively suppress the electric field aggregation at the bottom corner of the gate trench due to the curvature effect, and the problem of thermal electron instability, thereby reducing the breakdown voltage of the device.

[0016] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 1 is a schematic diagram of a double trench SiC MOSFET device with a floating P island provided in an embodiment of the present invention;

[0018] Figure 2 1 is another schematic diagram of a double trench SiC MOSFET device with a floating P island provided in an embodiment of the present invention;

[0019] Figure 3 1 is another schematic diagram of a double trench SiC MOSFET device with a floating P island provided in an embodiment of the present invention;

[0020] Figure 4 1 is another schematic diagram of a double trench SiC MOSFET device with a floating P island provided in an embodiment of the present invention;

[0021] Figure 5 1 is another schematic diagram of a double trench SiC MOSFET device with a floating P island provided in an embodiment of the present invention;

[0022] Figure 6 1 is another schematic diagram of a double trench SiC MOSFET device with a floating P island provided in an embodiment of the present invention;

[0023] Figure 7 1 is another schematic diagram of a double trench SiC MOSFET device with a floating P island provided in an embodiment of the present invention;

[0024] Figure 8 It is a flow chart of a process for preparing a double-trench SiC MOSFET device with a floating P island provided in an embodiment of the present invention;

[0025] Figure 9a~9g It is a schematic diagram of a process for preparing a double-trench SiC MOSFET device with a floating P island provided in an embodiment of the present invention;

[0026] Fig.10 This is a schematic diagram of the simulation structure of a common double-trench SiC MOSFET device;

[0027] Fig.11 It is a schematic diagram of a simulation structure of a double-trench SiC MOSFET device with a floating P island provided in an embodiment of the present invention;

[0028] Fig.12 It is a schematic diagram comparing the ID-VDS output curves of the device provided by the embodiment of the present invention and the common double trench SiC MOSFET under different VGS;

[0029] Fig.13 It is a schematic diagram comparing the breakdown voltage of the device provided by the embodiment of the present invention and a common double trench SiC MOSFET device;

[0030] Fig.14It is a schematic diagram of a comparison of breakdown voltages under different implantation doses of floating P-type island structures provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0032] See also Figure 1 , Figure 1 1 is a schematic diagram of a double trench SiC MOSFET device with a floating P island provided by an embodiment of the present invention. The double trench SiC MOSFET device with a floating P island provided by the present invention comprises:

[0033] The first epitaxial layer 10 includes a plurality of spaced-apart floating P-type island structures 20 , wherein the floating P-type island structures 20 are located on a first side of the first epitaxial layer 10 ;

[0034] The second epitaxial layer 30 is stacked with the first side of the first epitaxial layer 10, and the second epitaxial layer 30 includes a gate trench 40, and the gate trench 40 is located on the side of the second epitaxial layer 30 away from the first epitaxial layer 10, and a gate oxide layer 50 and a gate 60 are arranged in the gate trench 40; the second epitaxial layer 30 also includes a plurality of P+ type ring structures 80 arranged at intervals, and along the first direction D1, the orthographic projection of the P+ type ring structure 80 overlaps with the orthographic projection of the gate trench 40, and the orthographic projection of the P+ type ring structure 80 overlaps with the orthographic projection of at least part of the floating P-type island structure 20;

[0035] The first direction D1 is the thickness direction of the first epitaxial layer 10 .

[0036] For more details, please see Figure 1As shown, the double trench SiC MOSFET device with floating P island provided in the present embodiment includes a first epitaxial layer 10 and a second epitaxial layer 30 located on the first epitaxial layer 10, the first side of the first epitaxial layer 10 is close to the second epitaxial layer 30, the first epitaxial layer 10 and the second epitaxial layer 30 jointly form a drift region, a first side of the first epitaxial layer 10 is provided with a plurality of floating P-type island structures 20 arranged at intervals, a side of the second epitaxial layer 30 away from the first epitaxial layer 10 is provided with a gate trench 40, a plurality of P+ type ring structures 80 arranged at intervals are provided below the gate trench 40, a gate oxide layer 50 and a gate 60 are provided inside the gate trench 40, and the gate oxide layer 50 and the gate 60 fill the gate trench 40; the present embodiment In the example, on the one hand, a plurality of floating P-type island structures 20 are arranged on the first side of the first epitaxial layer 10, and the floating P-type island structures 20 and the first epitaxial layer 10 form a plurality of laterally arranged PN junctions, and utilize the charge balance principle to optimize the electric field distribution in the drift region, further reduce the on-resistance, and improve the breakdown voltage of the device; on the other hand, without adding any process steps and difficulties, a plurality of P+ type ring structures 80 are arranged below the gate trench 40 in the second epitaxial layer 30, which can effectively suppress the electric field concentration at the bottom corner of the gate trench 40 due to the curvature effect, and easily cause problems such as thermal electron instability, thereby reducing the breakdown voltage of the device.

[0037] It should be noted that Figure 1 The illustrated embodiment only schematically illustrates the shape and structure of each structure included in the device and does not represent its actual size.

[0038] In an optional embodiment of the present invention, see Figure 2 , Figure 2 It is another schematic diagram of a double trench SiC MOSFET device with a floating P island provided in an embodiment of the present invention. Along the second direction D2, from the two sides of the first epitaxial layer 10 to the middle of the first epitaxial layer 10, the distance between adjacent floating P-type island structures 20 gradually decreases, and the second direction D2 intersects with the first direction D1. Optionally, the second direction D2 is perpendicular to the first direction D1.

[0039] For more details, please see Figure 2In this embodiment, the distance between adjacent floating P-type island structures 20 changes gradually, and the distance between adjacent floating P-type island structures 20 gradually decreases from the two sides of the first epitaxial layer 10 to the middle of the first epitaxial layer 10. It can be understood that the number of floating P-type island structures 20 located in the middle area of ​​the first epitaxial layer 10 is large and the density is high; in this way, the number of laterally arranged PN junctions formed by the floating P-type island structure 20 and the first epitaxial layer 10 is more, and the number of PN junctions gathered in the middle area of ​​the first epitaxial layer 10 is more, and combined with the optimization design of other parameters, the charge balance of the first epitaxial layer 10 is achieved, the electric field distribution is optimized, and the on-resistance is further reduced.

[0040] It should be noted that Figure 2 The illustrated embodiment only schematically shows the arrangement relationship of the distance variation between adjacent floating P-type island structures 20 , and does not represent their actual sizes.

[0041] In an optional embodiment of the present invention, please continue to refer to Figure 1 Along the second direction D2, the distances between adjacent floating P-type island structures 20 are equal, the second direction D2 intersects with the first direction D1, and optionally, the second direction D2 is perpendicular to the first direction D1.

[0042] For more details, please see Figure 1 In this embodiment, the distances between adjacent floating P-type island structures 20 are equal. It can be understood that multiple floating P-type island structures 20 are evenly arranged in the first epitaxial layer 10. Through structural design and combined with optimization of other parameters, PN junction charge balance is achieved, thereby reducing the on-resistance of the device.

[0043] It should be noted that Figure 1 The illustrated embodiment only schematically shows an arrangement relationship in which the distances between adjacent floating P-type island structures 20 are equal, and does not represent their actual sizes.

[0044] In an optional embodiment of the present invention, see Figure 3 , Figure 3 It is another schematic diagram of a double-trench SiC MOSFET device with a floating P island provided in an embodiment of the present invention. Along the second direction D2, from the two sides of the first epitaxial layer 10 to the middle of the first epitaxial layer 10, the width of each floating P-type island structure 20 gradually increases, and the second direction D2 intersects with the first direction D1. Optionally, the second direction D2 is perpendicular to the first direction D1.

[0045] For more details, please see Figure 3In this embodiment, the width dimensions of each floating P-type island structure 20 are different. From the two sides of the first epitaxial layer 10 to the middle of the first epitaxial layer 10, the width dimensions of each floating P-type island structure 20 gradually increase. It can be understood that along the second direction D2, the width dimension of the floating P-type island structure 20 located in the middle area of ​​the first epitaxial layer 10 is larger, and the width dimension of the floating P-type island structure 20 located in the two side areas of the first epitaxial layer 10 is smaller; in this way, by combining structural design with optimization of other parameters, the PN junction charge balance is achieved, the epitaxial layer resistance is further reduced, and the device on-resistance is optimized as a whole.

[0046] It should be noted that Figure 3 The illustrated embodiment only schematically shows the size variation of each floating P-type island structure 20 and does not represent its actual size.

[0047] In an optional embodiment of the present invention, please continue to refer to Figure 1 Along the second direction D2, the widths of the floating P-type island structures 20 are equal, the second direction D2 intersects with the first direction D1, and optionally, the second direction D2 is perpendicular to the first direction D1.

[0048] For more details, please see Figure 1 In this embodiment, the sizes of the floating P-type island structures 20 along the second direction D2 are the same. Thus, by combining structural design with optimization of other parameters, the PN junction charge balance is achieved, the epitaxial layer resistance is further reduced, and the device on-resistance is optimized as a whole.

[0049] It should be noted that Figure 1 The illustrated embodiment only schematically shows that the floating P-type island structures 20 have the same size, and does not represent their actual size.

[0050] In an optional embodiment of the present invention, see Figure 4 , Figure 4 It is another schematic diagram of a double-trench SiC MOSFET device with a floating P-type island provided in an embodiment of the present invention. Along the second direction D2, from the two sides of the first epitaxial layer 10 to the middle of the first epitaxial layer 10, the distance between adjacent floating P-type island structures 20 gradually decreases, and the width of each floating P-type island structure 20 gradually increases. The second direction D2 intersects with the first direction D1. Optionally, the second direction D2 is perpendicular to the first direction D1.

[0051] For more details, please see Figure 4On the basis of the change in the distance between adjacent floating P-type island structures 20, the size of each floating P-type island structure 20 along the second direction D2 changes simultaneously. It can be understood that, from the two sides of the first epitaxial layer 10 to the middle of the first epitaxial layer 10, the distance between adjacent floating P-type island structures 20 gradually decreases, and the width size of each floating P-type island structure 20 gradually increases; by combining structural design with optimization of other parameters, the PN junction charge balance is achieved, the epitaxial layer resistance is further reduced, and the device on-resistance is optimized as a whole.

[0052] It should be noted that Figure 4 The illustrated embodiment only schematically shows the width size change of the floating P-type island structure 20 and the distance change between adjacent floating P-type island structures 20 , and does not represent the actual size.

[0053] In an optional embodiment of the present invention, see Figure 5 , Figure 5 It is another schematic diagram of a double-trench SiC MOSFET device with a floating P island provided in an embodiment of the present invention. Along the second direction D2, from the two sides of the second epitaxial layer 30 to the middle of the second epitaxial layer 30, the distance between adjacent P+ type ring structures 80 gradually increases, and the second direction D2 intersects with the first direction D1. Optionally, the second direction D2 is perpendicular to the first direction D1.

[0054] For more details, please see Figure 5 In this embodiment, the distance between adjacent P+ type ring structures 80 changes gradually, and the distance between adjacent P+ type ring structures 80 gradually increases from the two sides of the second epitaxial layer 30 to the middle of the second epitaxial layer 30. It can be understood that the number of P+ type ring structures 80 located in the middle area below the gate trench 40 is relatively small, and the number of P+ type ring structures 80 located below the corner of the gate trench 40 is relatively large. In this way, the electric field concentration phenomenon caused by the curvature effect at the corner of the gate trench 40 can be effectively suppressed, thereby improving the breakdown voltage of the device.

[0055] It should be noted that Figure 5 The illustrated embodiment only schematically illustrates the arrangement relationship of the distance variation between adjacent P+ ring structures 80 , and does not represent their actual sizes.

[0056] In an optional embodiment of the present invention, please continue to refer to Figure 1 , along the second direction D2, the distances between adjacent P+ type ring structures 80 are equal, the second direction D2 intersects the first direction D1, and optionally, the second direction D2 is perpendicular to the first direction D1.

[0057] For more details, please see Figure 1In this embodiment, the distances between adjacent P+ type ring structures 80 are equal. It can be understood that multiple P+ type ring structures 80 are evenly arranged at the bottom of the gate trench 40, which can optimize the electric field concentration phenomenon caused by the curvature effect at the corner of the gate trench 40 and improve the breakdown voltage of the device.

[0058] It should be noted that Figure 1 The illustrated embodiment only schematically shows the arrangement relationship of the P+ type ring structure 80 and does not represent its actual size.

[0059] In an optional embodiment of the present invention, see Figure 6 , Figure 6 It is another schematic diagram of a double-trench SiC MOSFET device with a floating P island provided in an embodiment of the present invention. Along the second direction D2, from the two sides of the second epitaxial layer 30 to the middle of the second epitaxial layer 30, the width of each P+ type ring structure 80 gradually decreases, and the second direction D2 intersects with the first direction D1. Optionally, the second direction D2 is perpendicular to the first direction D1.

[0060] For more details, please see Figure 6 In this embodiment, the width dimensions of each P+ type ring structure 80 are different. From the two sides of the second epitaxial layer 30 to the middle of the second epitaxial layer 30, the width dimensions of each P+ type ring structure 80 gradually decreases. It can be understood that along the second direction D2, the width dimension of the P+ type ring structure 80 located in the middle area of ​​the bottom of the gate trench 40 is smaller, and the width dimension of the P+ type ring structure 80 located below the bottom corner of the gate trench 40 is larger; in this way, the electric field concentration phenomenon caused by the curvature effect at the corner of the gate trench 40 can be effectively suppressed, thereby improving the breakdown voltage of the device.

[0061] It should be noted that Figure 6 The illustrated embodiment merely schematically shows the size variation of each P+ type ring structure 80 , and does not represent its actual size.

[0062] In an optional embodiment of the present invention, please continue to refer to Figure 1 Along the second direction D2, the widths of the P+ type ring structures 80 are equal, the second direction D2 intersects with the first direction D1, and optionally, the second direction D2 is perpendicular to the first direction D1.

[0063] For more details, please see Figure 1 In this embodiment, the sizes of the P+ type ring structures 80 along the second direction D2 are the same, so that the electric field concentration phenomenon caused by the curvature effect at the corner of the gate trench 40 can be optimized and the breakdown voltage of the device can be improved.

[0064] It should be noted that Figure 1The illustrated embodiment merely schematically shows that the sizes of the various P+ type ring structures 80 are the same, and does not represent their actual sizes.

[0065] In an optional embodiment of the present invention, see Figure 7 , Figure 7 It is another schematic diagram of a double-trench SiC MOSFET device with a floating P island provided in an embodiment of the present invention. Along the second direction D2, from the two sides of the second epitaxial layer 30 to the middle of the second epitaxial layer 30, the distance between adjacent P+ type ring structures 80 gradually increases, and the width of each P+ type ring structure 80 gradually decreases. The second direction D2 intersects with the first direction D1. Optionally, the second direction D2 is perpendicular to the first direction D1.

[0066] For more details, please see Figure 7 In this embodiment, based on the change in the distance between adjacent P+ type ring structures 80, the size of each P+ type ring structure 80 along the second direction D2 changes simultaneously. It can be understood that, from the two sides of the second epitaxial layer 30 to the middle of the second epitaxial layer 30, the distance between adjacent P+ type ring structures 80 gradually increases, and the width of each P+ type ring structure 80 gradually decreases; on the one hand, the number of P+ type ring structures 80 located in the middle area below the gate trench 40 is relatively small, and the number of P+ type ring structures 80 located below the corner of the gate trench 40 is relatively large; on the other hand, the width of the P+ type ring structure 80 located in the middle of the bottom of the gate trench 40 is relatively small, and the width of the P+ type ring structure 80 located below the bottom corner of the gate trench 40 is relatively large; in this way, the electric field concentration phenomenon caused by the curvature effect at the corner of the gate trench 40 can be effectively suppressed, thereby improving the breakdown voltage of the device.

[0067] It should be noted that Figure 7 The illustrated embodiment only schematically shows the size change of the P+ type ring structure 80 and the change of the spacing between adjacent P+ type ring structures 80, and does not represent the actual size thereof.

[0068] In an optional embodiment of the present invention, please continue to refer to Figures 1 to 7 The second epitaxial layer 30 also includes a plurality of P+ type regions 90, which are respectively located on both sides of the gate trench 40 along the second direction D2 and are located in the P type body region 70 in the second epitaxial layer 30. The second direction D2 intersects with the first direction D1. Optionally, the second direction D2 is perpendicular to the first direction D1.

[0069] For more details, please see Figures 1 to 7The double trench SiC MOSFET device with floating P island provided in this embodiment also includes a substrate 100, a drain 110, an interlayer dielectric insulating layer 120 and a source trench, wherein the substrate 100 is located on the second side of the first epitaxial layer 10, the first side of the first epitaxial layer 10 is arranged opposite to the second side, the drain 110 is located on the side of the substrate 100 away from the first epitaxial layer 10, the interlayer dielectric insulating layer 120 is located on the upper surface of the gate 60, and the source 130 metal covers the second epitaxial layer 30 and the interlayer dielectric insulating layer 120; the second epitaxial layer 30 also includes a plurality of P+ type regions Domain 90, multiple P+ type regions 90 are respectively located on both sides of the gate trench 40 along the second direction D2, and are located in the P type body region 70 in the second epitaxial layer 30, and an N+ type region 140 is arranged between the P+ type region 90 and the gate trench 40, and the P+ type region 90 and the N+ type region 140 are both located in the P type body region 70 on both sides of the gate trench 40; it should be noted that the P+ type region 90 and the P+ type ring structure 80 are prepared at the same time, so that the device performance is optimized without adding additional process steps, difficulty and cost.

[0070] Based on the same inventive concept, see Figure 8 , Figure 8 1 is a flow chart of a process for preparing a double-trench SiC MOSFET device with a floating P island provided in an embodiment of the present invention. The present invention also provides a method for preparing a double-trench SiC MOSFET device with a floating P island, which is used to prepare a double-trench SiC MOSFET device with a floating P island provided in the above embodiment of the present invention. The embodiments of the device are referred to above and will not be described in detail herein. The preparation method comprises:

[0071] S101, providing a substrate 100;

[0072] S102, epitaxially growing a first epitaxial layer 10 on the substrate 100, and forming a plurality of spaced-apart floating P-type island structures 20 on a first side of the first epitaxial layer 10 by using a mask and ion implantation;

[0073] S103, epitaxially growing a second epitaxial layer 30 on the first epitaxial layer 10, forming a gate trench 40 on the side of the second epitaxial layer 30 away from the first epitaxial layer 10 by using a mask and etching method; using a mask, ion implantation is performed at the bottom of the gate trench 40 to form a plurality of P+ type ring structures 80 arranged at intervals; a gate oxide layer 50 is grown in the gate trench 40, and a gate 60 is deposited on the gate oxide layer 50, so that the gate oxide layer 50 and the gate 60 fill the gate trench 40; specifically comprising:

[0074] S1031, etching to form a source trench on a side of the second epitaxial layer 30 away from the first epitaxial layer 10, wherein the source trench is located on two sides of the second epitaxial layer 30 along the second direction D2;

[0075] S1032, performing ion implantation on both sides of the second epitaxial layer 30 to form a P-type body region 70, and performing ion implantation in the P-type body region 70 to form an N+ type region 140;

[0076] S1033, etching a gate trench 40 in the middle region of the second epitaxial layer 30, performing ion implantation at the bottom of the gate trench 40 to form a plurality of spaced P+ type ring structures 80, and performing ion implantation in the P type body region 70 to form a P+ type region 90; it should be noted that the P+ type ring structure 80 and the P+ type region 90 are prepared simultaneously;

[0077] S1034 , growing a gate oxide layer 50 in the gate trench 40 , and depositing a gate 60 on the gate oxide layer 50 .

[0078] Specifically, the preparation process of the double-trench SiC MOSFET device with a floating P island provided in the present embodiment is as follows: first, a first epitaxial layer 10 is epitaxially grown on a substrate 100, and a plurality of spaced-apart floating P-type island structures 20 are formed by ion implantation on a first side of the first epitaxial layer 10; then, a second epitaxial layer 30 is epitaxially grown on the first epitaxial layer 10, a gate trench 40 is etched on a side of the second epitaxial layer 30 away from the first epitaxial layer 10, and ion implantation is performed at the bottom of the gate trench 40 to form a plurality of spaced-apart P+ type ring structures 80. It should be noted that when ion implantation is performed at the bottom of the gate trench 40, there is no need to increase the implantation on the sidewall of the gate trench 40 to form the P+ type ring structure 80; then, a gate oxide layer 50 is grown in the gate trench 40, and a gate 60 is deposited on the gate oxide layer 50; in this way, the prepared device can not only reduce the on-resistance, but also increase the breakdown voltage.

[0079] It should be noted that the gate 60 of this embodiment is a polysilicon gate.

[0080] In an optional embodiment of the present invention, the P+ type ring structure 80 and the plurality of P+ type regions 90 are prepared simultaneously.

[0081] Specifically, in this embodiment, the P+ type ring structure 80 is prepared while preparing a plurality of P+ type regions 90, which can save process steps, specifically:

[0082] S1. Provide an N+ type high concentration SiC substrate as the overall substrate structure of the device.

[0083] Specifically, the concentration of the substrate 100 may be 1e19 cm-3 to 5e19 cm-3, and the thickness of the substrate 100 may be 175 μm to 200 μm.

[0084] S2 , growing a first epitaxial layer 10 on the substrate 100 , and preparing a floating P-type island structure 20 in the first epitaxial layer 10 .

[0085] Specifically, an N-type epitaxial layer is grown on the substrate 100 as a partial drift region of the device, i.e., the first epitaxial layer 10, whose doping concentration is 1e15cm-3~3e15cm-3, and the thickness of the first epitaxial layer 10 is 6μm~7μm. A mask is set on the N-type epitaxial layer, and ion implantation is performed to form a plurality of floating P-type island structures 20. The dosage of ion implantation to form the floating P-type island structures 20 is determined according to the actual situation, and the purpose is to achieve charge compensation balance, such as Figure 9a shown.

[0086] It should be noted that the spacing between the floating P-type island structures 20 , the size of the floating P-type island structures 20 , and the number of the floating P-type island structures 20 may be set according to actual conditions.

[0087] S3 . Growing a second epitaxial layer 30 on the first epitaxial layer 10 .

[0088] Specifically, a second epitaxial layer 30 is epitaxially grown on the first epitaxial layer 10, the thickness of the second epitaxial layer 30 is less than that of the first epitaxial layer 10, the thickness of the second epitaxial layer 30 is 3μm~4μm, the doping concentration of the second epitaxial layer 30 is greater than that of the first epitaxial layer 10, the doping concentration of the second epitaxial layer 30 is 3.5e15cm-3~6e15cm-3, and the first epitaxial layer 10 and the second epitaxial layer 30 together form a drift region of the device.

[0089] S4 , preparing a source trench in the second epitaxial layer 30 .

[0090] Specifically, along the second direction D2, masks are set on both sides of the second epitaxial layer 30, and plasma etching is used to form source trenches, the source trenches have a depth of 1.3 μm to 1.8 μm, and a width of 1 μm to 1.5 μm. Figure 9b shown.

[0091] S5 , preparing a P-type body region 70 and an N+-type region 140 in the second epitaxial layer 30 .

[0092] Specifically, the etched epitaxial wafer is cleaned to remove the etched particles and surface contaminants; a sacrificial oxide layer is grown on the upper surface of the second epitaxial layer 30 with a thickness of 500Å~800Å, and the sacrificial oxide layer is etched away; a high-temperature aluminum ion implantation is performed in the P-type body region 70 using a mask, and the implantation is performed three times with a dosage of about 1e12cm2~5e12cm2; a nitrogen ion implantation is performed using a mask to form an N+ type region 140 with a dosage of 1e15cm2~3e15cm2, and then an annealing treatment is performed, such as Fig.9c shown.

[0093] S6 , preparing a gate trench 40 in the second epitaxial layer 30 .

[0094] Specifically, a mask is set on the second epitaxial layer 30, and a gate trench 40 is formed by etching, with a depth of 0.8 μm to 1.1 μm and a width of 1 μm to 1.5 μm, and cleaning is performed after etching, such as Figure 9d shown.

[0095] S7 , preparing a P+ type ring structure 80 at the bottom of the gate trench 40 in the second epitaxial layer 30 , and preparing a P+ type region 90 in the P type body region 70 .

[0096] Specifically, using a mask, aluminum ions are implanted at the bottom of the gate trench 40 to form a P+ type ring structure 80, and the dosage can be determined according to the actual situation. Aluminum ions are implanted in the P-type body region 70 to form a P+ type region 90, and the dosage is 1e15cm2~3e15cm2; It should be noted that when ion implantation is performed at the bottom of the gate trench 40, it is not necessary to increase the implantation on the sidewall of the gate trench 40, such as Fig.9e shown.

[0097] It should be noted that the spacing between the P+ type ring structures 80 , the width of the P+ type ring structures 80 , and the number of the P+ type ring structures 80 can be set according to actual conditions.

[0098] Here, the P+ type region 90 and the P+ type ring structure 80 are prepared simultaneously, and the device performance is optimized without adding additional process steps, difficulty and cost.

[0099] S8 , preparing a gate oxide layer 50 and a gate 60 in the gate trench 40 .

[0100] Specifically, a sacrificial oxide layer is diffused and grown in the gate trench 40, with a thickness of 500Å~800Å. After the sacrificial oxide layer is etched away, a gate oxide layer 50 is grown using a furnace thermal oxidation method, and the thickness of the gate oxide layer 50 is 400Å~500Å. A polysilicon gate is deposited on the gate oxide layer 50 with a concentration of 1e19cm-3~5e19cm-3, so that the gate oxide layer 50 and the gate 60 fill the gate trench 40. Figure 9f shown.

[0101] S9, preparing an interlayer dielectric insulating layer 120, a source electrode 130 and a drain electrode 110.

[0102] Specifically, an interlayer dielectric insulating layer 120 is deposited on the gate 60, the gate oxide layer 50 and at least a portion of the N+ region 140 by chemical vapor deposition, a source metal is deposited on the interlayer dielectric insulating layer 120 and the source trench to form a source 130, and a drain metal is deposited on a side of the substrate 100 away from the first epitaxial layer 10 to form a drain 110, as shown in FIG. Figure 9g shown.

[0103] In an optional embodiment of the present invention, the performance of the double trench SiC MOSFET device with floating P island provided in the above embodiment is verified by simulation experiments, specifically:

[0104] See also Fig.10 and Fig.11 , Fig.10 This is a schematic diagram of the simulation structure of a common double-trench SiC MOSFET device. Fig.11 1 is a schematic diagram of a simulation structure of a double-trench SiC MOSFET device with a floating P-type island provided in an embodiment of the present invention. In the embodiment of the present invention, on the one hand, a floating P-type island structure 20 is added to the first epitaxial layer 10, and the electric field distribution in the drift region is optimized by using the lateral charge compensation principle; on the other hand, a P+ type ring structure 80 is added to the bottom of the gate trench 40 to optimize the electric field distribution at the bottom corner of the gate trench 40, as shown in FIG. Fig.11 As shown, Fig.11 The simulation is performed to set up a device with three equally spaced floating P-type island structures 20 and three unequally spaced P+ type ring structures 80. It should be noted that: Fig.10 and Fig.11 X and Y in the figure represent the size in μm.

[0105] See also Fig.12 , Fig.12 It is a schematic diagram comparing the ID-VDS output curves of the device provided by an embodiment of the present invention and a common double trench SiC MOSFET under different VGS. The device proposed by the present invention and the common double trench SiC MOSFET are both 1200V SiC MOSFET devices. The structure of the present invention significantly optimizes the forward output curve, improves the transport capacity of the device, and is more suitable for high current application scenarios.

[0106] As shown in Table 1, Table 1 is a comparison of the on-resistance Rdson parameters of the structure of the present invention and the ordinary dual trench SiC MOSFET under different VGS. It can be seen from the table that when VGS is equal to 15V, the on-resistance of the structure of the present invention is only 14.17mΩ, which is 21.81% lower than that of the ordinary DTMOS; when VGS is equal to 18V, the on-resistance is only 13.66mΩ, which is 18.74% lower than that of the ordinary DTMOS; when VGS is equal to 20V, the on-resistance is only 13.34mΩ, which is 18.47% lower than that of the ordinary DTMOS; it can be seen that the structure of the present invention significantly optimizes the on-resistance and develops in the direction of large current and small internal resistance.

[0107] Table 1 Comparison of on-resistance Rdson parameters of the structure of the present invention and the common double trench SiC MOSFET under different VGS

[0108]

[0109] See also Fig.13 , Fig.13 It is a schematic diagram comparing the breakdown voltage of the device provided by the embodiment of the present invention with that of the ordinary dual trench SiC MOSFET device. The structure of the present invention has a significantly improved breakdown voltage compared with the ordinary DTMOS structure. When the P-ring dose is 1E12 cm2, the BVDSS is increased by about 9.21% compared with the ordinary DTMOS structure. When the P-ring dose is 9E11 cm2, the BVDSS is increased by about 8.29% compared with the ordinary DTMOS structure. When the P-ring dose is 2E12 cm2, the BVDSS is increased by about 7.70% compared with the ordinary DTMOS structure. It can be seen that the structure of the present invention significantly optimizes the breakdown voltage.

[0110] See also Fig.14 , Fig.14 It is a schematic diagram of a breakdown voltage comparison diagram under different implantation doses of the floating P-type island structure 20 provided in an embodiment of the present invention. The P-ring dose is in the range of 7E11cm2 to 3E12cm2. The breakdown voltage of the structure of the present invention is higher than the breakdown voltage of the ordinary DTMOS structure, and the structure of the present invention has a good process window and can cope with process fluctuations well.

[0111] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the term "include", "comprise" or any other variant is intended to cover non-exclusive inclusion, so that the article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the article or device including the elements. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The orientation or position relationship indicated by "up", "down", "left", "right", etc. is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present invention.

[0112] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification.

[0113] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A double trench SiC MOSFET device with a floating P island, characterized in that: include: A first epitaxial layer, comprising a plurality of spaced-apart floating P-type island structures, wherein the floating P-type island structures are located on a first side of the first epitaxial layer and are arranged throughout the first epitaxial layer; A second epitaxial layer is stacked with the first side of the first epitaxial layer, the second epitaxial layer includes a gate trench, the gate trench is located on the side of the second epitaxial layer away from the first epitaxial layer, and a gate oxide layer and a gate are arranged in the gate trench; the second epitaxial layer also includes a plurality of P+ type ring structures arranged at intervals, along the first direction, the orthographic projection of the P+ type ring structure overlaps with the orthographic projection of the gate trench, and the orthographic projection of the P+ type ring structure overlaps with the orthographic projection of at least part of the floating P-type island structure; Along the second direction, from the two sides of the second epitaxial layer to the middle of the second epitaxial layer, the distance between adjacent P+ type ring structures gradually increases, and the width of each P+ type ring structure gradually decreases; The second epitaxial layer further includes a plurality of P+ type regions, the plurality of P+ type regions are respectively located on both sides of the gate trench along the second direction and are located in the P type body region in the second epitaxial layer, and the P+ type ring structure is prepared simultaneously with the plurality of P+ type regions; The first direction is the thickness direction of the first epitaxial layer.

2. The double trench SiC MOSFET device with floating P island according to claim 1, characterized in that: Along a second direction, from the two sides of the first epitaxial layer to the middle of the first epitaxial layer, the distance between adjacent floating P-type island structures gradually decreases, and the second direction intersects with the first direction.

3. The double trench SiC MOSFET device with floating P island according to claim 1, characterized in that: Along a second direction, from the two sides of the first epitaxial layer to the middle of the first epitaxial layer, the width of each of the floating P-type island structures gradually increases, and the second direction intersects with the first direction.

4. The double trench SiC MOSFET device with floating P island according to claim 1, characterized in that: Along the second direction, from the two sides of the first epitaxial layer to the middle of the first epitaxial layer, the distance between adjacent floating P-type island structures gradually decreases, the width of each floating P-type island structure gradually increases, and the second direction intersects with the first direction.

5. A method for preparing a floating P island double trench SiC MOSFET device, used to prepare a floating P island double trench SiC MOSFET device as claimed in any one of claims 1 to 4, characterized in that: include: providing a substrate; Epitaxially growing a first epitaxial layer on the substrate, and forming a plurality of spaced-apart floating P-type island structures on a first side of the first epitaxial layer by using a mask and ion implantation; Epitaxially growing a second epitaxial layer on the first epitaxial layer, and forming a gate trench on a side of the second epitaxial layer away from the first epitaxial layer by using a mask and etching; using a mask, performing ion implantation at the bottom of the gate trench to form a plurality of spaced-apart P+ type ring structures; A gate oxide layer is grown in the gate trench, and a gate is deposited on the gate oxide layer, so that the gate oxide layer and the gate fully fill the gate trench.

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