Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: forming a top groove in a channel lamination layer at two sides of a pseudo gate structure, and enabling the top groove to expose the top of a substrate; doping inversion ions in the substrate exposed out of the top groove, wherein the doping type of the inversion ions is different from the channel conduction type of the MOS transistor; performing first heat treatment for diffusing the inversion ions into the substrate at the bottom of the pseudo gate structure, and forming an initial doped region in the substrate; partial thickness of the substrate at the bottom of the top groove is removed, a bottom groove is formed in the substrate at the bottom of the top groove, and the bottom groove and the top groove located on the bottom groove form a source-drain groove; the residual initial doped region in the edge of the substrate on the side wall of the bottom groove is used as an inversion doped region; and forming a source-drain doped layer in the source-drain groove, wherein the source-drain doped layer is adjacent to the inversion doped region. According to the embodiment of the invention, the performance of the semiconductor structure is optimized.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher component density and higher integration, and semiconductor process nodes are continuously decreasing in accordance with Moore's Law. Transistor size is getting smaller and smaller, and Fin-type field-effect transistor (FinFET) came into being. However, to maintain the original driving current performance, this structure is no longer suitable for smaller nodes. So the all-around gate transistor (Gate-All-Around, GAAFET) appeared. Its control of short channel effects and superior electrical performance make it replace FinFET and become the mainstream at smaller process nodes.

[0003] GAAFET is a four-sided ring gate structure that can better suppress the short channel effect and achieve better electrical performance.

[0004] However, the performance of current semiconductor structures still needs to be improved. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to optimize the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a channel structure layer suspended on the substrate, the channel structure layer including one or more channel layers spaced from bottom to top; a gate structure spanning the channel structure layer, the gate structure filling between the channel layer and the substrate and between adjacent channel layers, the gate structure surrounding the channel layer; a source-drain doping layer located in the channel structure layer on both sides of the gate structure and in a partial thickness of the substrate; an inversion doping region located in the side wall of the substrate adjacent to the source-drain doping layer, the inversion doping region being doped with inversion ions, and the doping type of the inversion ions being different from the doping type of the source-drain doping layer.

[0007] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate for forming a MOS transistor, the substrate comprising a substrate and one or more channel stacks stacked in sequence on the substrate, each channel stack comprising a sacrificial layer and a channel layer on the sacrificial layer; forming a pseudo-gate structure spanning the channel stack; forming a top groove in the channel stack on both sides of the pseudo-gate structure, the top groove exposing the top of the substrate; doping anti-type ions in the substrate exposed by the top groove, the doping type of the anti-type ions being different from the channel conductivity type of the MOS transistor; after doping the anti-type ions in the substrate exposed by the top groove, performing a first heat treatment to diffuse the anti-type ions into the substrate at the bottom of the pseudo-gate structure to form an initial doping region in the substrate; after the first heat treatment, removing part of the thickness of the substrate at the bottom of the top groove, forming a bottom groove in the substrate at the bottom of the top groove, the bottom groove and the top groove on the bottom groove constituting a source-drain groove; the remaining initial doping region in the substrate edge of the sidewall of the bottom groove is used as an anti-type doping region; forming a source-drain doping layer in the source-drain groove, the source-drain doping layer being adjacent to the anti-type doping region.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] The semiconductor structure provided by the embodiment of the present invention is also provided with an inversion doping region, which is located in the side wall of the substrate adjacent to the source-drain doping layer. The inversion doping region is doped with inversion ions, and the doping type of the inversion ions is different from the doping type of the source-drain doping layer. The doping type of the inversion ions in the inversion doping region is different from the doping type of the source-drain doping layer, which can improve the potential barrier of the substrate adjacent to the side wall of the source-drain doping layer, increase the difficulty of the doped ions in the source-drain doping layer to diffuse into the substrate, and correspondingly reduce the probability of the doped ions in the source-drain doping layer to diffuse into the substrate at the bottom of the channel layer, thereby improving the leakage current between the source-drain doping layer and the substrate to improve the short channel effect, thereby optimizing the performance of the semiconductor structure.

[0010] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a top groove is formed in the channel stack on both sides of the pseudo-gate structure, and anti-type ions are doped in the substrate exposed by the top groove, and the doping type of the anti-type ions is different from the channel conductivity type of the MOS transistor. Subsequently, a first heat treatment is performed to diffuse the anti-type ions into the substrate at the bottom of the pseudo-gate structure to form an initial doping region in the substrate; then, a portion of the thickness of the substrate at the bottom of the top groove is removed to form a bottom groove in the substrate at the bottom of the top groove, and the remaining initial doping region in the substrate edge of the sidewall of the bottom groove is used as an anti-type doping region, so that after a source-drain doping layer is formed in the source-drain groove, the source-drain doping layer is adjacent to the anti-type doping region, and the doping type of the anti-type ions in the anti-type doping region is different from the doping type of the source-drain doping layer, which can improve the potential barrier of the substrate adjacent to the sidewall of the source-drain doping layer, increase the difficulty of the doped ions in the source-drain doping layer to diffuse into the substrate, and correspondingly reduce the probability of the doped ions in the source-drain doping layer to diffuse into the substrate at the bottom of the channel layer, thereby improving the leakage current between the source-drain doping layer and the substrate to improve the short channel effect, thereby optimizing the performance of the semiconductor structure.

[0011] In an optional scheme, in the step of doping anti-type ions in the substrate exposed by the top groove, diffusion blocking ions are also doped in the substrate exposed by the top groove. On the one hand, the diffusion blocking ions can slow down the diffusion rate of the anti-type ions during the first heat treatment, thereby reducing the probability of the anti-type ions diffusing into the bottom substrate of the channel layer in a direction parallel to the substrate, so as to concentrate the anti-type ions in the anti-type doping region as much as possible at the edge of the substrate on the side wall of the bottom groove, so as to make the distance between the anti-type doping region and the source and drain doping layer as small as possible, so as to further improve the blocking effect of the anti-type doping region on the doped ions in the source and drain doping layer; on the other hand, after the source and drain doping layer is formed, the diffusion blocking ions can further block the diffusion of the doped ions in the source and drain doping layer into the substrate, thereby further improving the leakage current between the source and drain doping layer and the substrate and improving the short channel effect.

[0012] In an optional scheme, the method for forming a semiconductor structure also includes: after forming the source and drain grooves and before forming the source and drain doping layers in the source and drain grooves, performing a second heat treatment in an inert gas atmosphere, the second heat treatment can repair the lattice damage caused by the step of doping counter ions in the substrate exposed by the top groove, and the damage to the substrate surface during the formation of the bottom groove, thereby improving the interface state of the source and drain groove surface, so as to provide good interface quality for the subsequent formation of the source and drain doping layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figures 1 to 3 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0014] Figure 4is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0015] Figures 5 to 13 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0016] As can be seen from the background technology, the performance of the current semiconductor structure needs to be improved. Now, in combination with a method for forming a semiconductor structure, the reason why the performance of the semiconductor structure needs to be improved is analyzed. Figures 1 to 3 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0017] refer to Figure 1 , providing a base (not shown), including a substrate 31 and one or more channel stacks 11 stacked in sequence on the substrate 31 , each channel stack 11 including a sacrificial layer 12 and a channel layer 13 located on the sacrificial layer 12 .

[0018] refer to Figure 2 , forming a dummy gate structure 15 across the channel stack 11 ; forming source and drain grooves 14 in the channel stack 11 and a partial thickness substrate 31 on both sides of the dummy gate structure 15 .

[0019] refer to Figure 3 , a source-drain doping layer 18 is formed in the source-drain groove 14 .

[0020] Among them, the source-drain doped layer 18 is in direct contact with the substrate 31 on the side wall 19, resulting in a serious leakage current problem between the source-drain doped layer 18 and the substrate 31. In addition, an etching process is usually used to etch the channel stack 11 and a part of the thickness of the substrate 31 on both sides of the dummy gate structure to form the source-drain groove 14. Defects are easily generated on the substrate surface exposed by the source-drain groove 14, and then in the step of forming the source-drain doped layer 18 in the source-drain groove 14, stacking faults are easily generated in the source-drain doped layer 18, resulting in a more serious leakage current problem.

[0021] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, wherein an inversion doping region is also provided, which is located in the side wall of the substrate adjacent to the source and drain doping layer, and the inversion doping region is doped with inversion ions. The doping type of the inversion ions is different from the doping type of the source and drain doping layer. The doping type of the inversion ions in the inversion doping region is different from the doping type of the source and drain doping layer. The potential barrier of the substrate adjacent to the side wall of the source and drain doping layer is increased, and the difficulty of the doped ions in the source and drain doping layer to diffuse into the substrate is increased, and the probability of the doped ions in the source and drain doping layer to diffuse into the substrate at the bottom of the channel layer is correspondingly reduced, thereby improving the leakage current between the source and drain doping layer and the substrate to improve the short channel effect, thereby optimizing the performance of the semiconductor structure.

[0022] In order to solve the technical problem, an embodiment of the present invention also provides a method for forming a semiconductor structure, wherein a top groove is formed in the channel stack on both sides of the pseudo-gate structure, and anti-type ions are doped in the substrate exposed by the top groove, wherein the doping type of the anti-type ions is different from the channel conductivity type of the MOS transistor, and then a first heat treatment is performed to diffuse the anti-type ions into the substrate at the bottom of the pseudo-gate structure to form an initial doping region in the substrate; then, a portion of the thickness of the substrate at the bottom of the top groove is removed to form a bottom groove in the substrate at the bottom of the top groove, and the remaining initial doping region in the substrate edge of the sidewall of the bottom groove is used as an anti-type doping region, so that after a source-drain doping layer is formed in the source-drain groove, the source-drain doping layer is adjacent to the anti-type doping region, and the doping type of the anti-type ions in the anti-type doping region is different from the doping type of the source-drain doping layer, which can improve the potential barrier of the substrate adjacent to the sidewall of the source-drain doping layer, increase the difficulty of the doped ions in the source-drain doping layer to diffuse into the substrate, and correspondingly reduce the probability of the doped ions in the source-drain doping layer to diffuse into the substrate at the bottom of the channel layer, thereby improving the leakage current between the source-drain doping layer and the substrate to improve the short channel effect, thereby optimizing the performance of the semiconductor structure.

[0023] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. Figure 4 , showing a schematic structural diagram of an embodiment of a semiconductor structure of the present invention.

[0024] like Figure 4 As shown, in this embodiment, the semiconductor structure includes: a substrate 100; a channel structure layer 170, suspended on the substrate 100, the channel structure layer 170 includes one or more channel layers 20 arranged in sequence from bottom to top; a gate structure 190, spanning the channel structure layer 170, the gate structure 190 is filled between the channel layer 20 and the substrate 100 and between adjacent channel layers 20, and the gate structure 190 surrounds the channel layer 20; a source-drain doping layer 210, located in the channel structure layer 170 on both sides of the gate structure 190 and a partial thickness of the substrate 100; an inversion doping region (not shown), located in the side wall of the substrate 100 adjacent to the source-drain doping layer 210, the inversion doping region is doped with inversion ions 140, and the doping type of the inversion ions 140 is different from the doping type of the source-drain doping layer 210.

[0025] The substrate 100 is used to provide a process platform for forming a semiconductor structure.

[0026] In this embodiment, the semiconductor structure is a gate all around (GAA) transistor as an example for description. In other embodiments, the semiconductor structure may also be a forksheet transistor or a complementary field effect transistor (CFET).

[0027] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be one or more of other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium arsenide, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

[0028] In this embodiment, the semiconductor structure further includes a well region (not shown), which is located in the substrate 100, and the doping type of the well region is different from the doping type of the source-drain doping layer 210. When an NMOS transistor is formed, the well region is doped with P-type ions; when a PMOS transistor is formed, the well region is doped with N-type ions.

[0029] In this embodiment, the semiconductor structure further includes: an isolation layer (not shown), which is located in the substrate 100 between adjacent device regions and exposes the channel structure layer 170. The isolation layer is used to achieve isolation between adjacent devices.

[0030] In this embodiment, the isolation layer is a shallow trench isolation structure. The material of the isolation layer may include one or more of silicon oxide, silicon oxynitride and silicon nitride.

[0031] In this embodiment, the channel structure layer 170 includes a plurality of channel layers 20 as an example for description, and the plurality of channel layers 20 are stacked and arranged on the substrate 100 in a direction perpendicular to the surface of the substrate 100. In other embodiments, based on actual process requirements, the number of the channel layer can also be one.

[0032] Specifically, the channel layer 20 is used to form a conductive channel of a MOS transistor.

[0033] In this embodiment, an NMOS transistor is formed, and the material of the channel layer 20 is the same as that of the substrate 100, both of which are silicon. In other embodiments, when a PMOS transistor is formed, in order to improve the performance of the PMOS transistor, a silicon germanium channel technology may be used, that is, the material of the channel layer is silicon germanium.

[0034] In other embodiments, based on actual process requirements, other materials may be selected for the channel layer.

[0035] When the device is working, the gate structure 190 is used to control the opening and closing of the conductive channel. Specifically, in this embodiment, the gate structure 190 is formed on the isolation layer.

[0036] In this embodiment, the portion of the gate structure 190 located between the substrate 100 and the channel layer 20 or between adjacent channel layers 20 is the first portion 191 ; the portion of the gate structure 190 spanning the channel structure layer 170 is the second portion 192 .

[0037] In this embodiment, the gate structure 190 is a metal gate structure, and the gate structure 190 includes a gate dielectric layer (not shown), a work function layer (not shown) located on the gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer and filling the through groove and the gate opening.

[0038] The gate dielectric layer is used to achieve electrical isolation between the work function layer and the gate electrode layer and the conductive channel. The material of the gate dielectric layer includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3 and Al2O3.

[0039] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3. In other embodiments, the gate dielectric layer may also include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer.

[0040] The work function layer is used to adjust the work function of the gate structure 190, and then adjust the threshold voltage of the field effect transistor. When forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum or titanium carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride and tantalum carbide.

[0041] The gate electrode layer is used as an external electrode for electrically connecting the gate structure 190 to an external circuit. The material of the gate electrode layer is a conductive material, such as W, Al, Cu, Ag, Au, Pt, Ni or Ti.

[0042] In this embodiment, the semiconductor structure further includes: a gate spacer 125 located on the sidewall of the second portion 192 and used to protect the sidewall of the gate structure 190 .

[0043] In this embodiment, the material of the gate spacer 125 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric or ultra-low-k dielectric material, and the gate spacer 125 is a single-layer or stacked structure. As an example, the gate spacer 125 is a single-layer structure, and the material of the gate spacer 125 is silicon nitride.

[0044] In this embodiment, the semiconductor structure further includes: an inner sidewall 180 , which is located between the first portion 191 and the source-drain doped layer 210 along the extension direction of the channel layer 20 .

[0045] In this embodiment, the inner sidewall 180 is used to achieve isolation between the source-drain doped layer 210 and the gate structure 190 , and also increases the distance between the source-drain doped layer 210 and the gate structure 190 , which is beneficial to reducing the parasitic capacitance between the source-drain doped layer 210 and the gate structure 190 .

[0046] In this embodiment, the material of the inner sidewall 180 is an insulating material to achieve isolation between the source-drain doped layer 210 and the gate structure 190, thereby reducing the parasitic capacitance between the source-drain doped layer 210 and the gate structure 190. In this embodiment, the material of the inner sidewall 180 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material or ultra-low-k dielectric material.

[0047] The source-drain doped layer 210 is used as a source or a drain of the MOS transistor. When the MOS transistor is working, the source-drain doped layer 210 is used to provide a carrier source.

[0048] In this embodiment, the material of the source-drain doping layer 210 includes a stress layer doped with ions. When the all-around gate transistor is a P-type MOS transistor, the material of the stress layer is Si or SiGe, and the doping ions in the source-drain doping layer 210 are P-type ions; when the all-around gate transistor is an N-type MOS transistor, the material of the stress layer is Si or SiC, and the doping ions in the source-drain doping layer 210 are N-type ions.

[0049] In the present embodiment, the source-drain doping layer 210 is located at a depth in the substrate 100 that is the same as the doping height of the inversion doping region, thereby enabling the inversion doping region to be distributed over the entire side wall of the substrate 100 adjacent to the source-drain doping layer 210, thereby enhancing the effect of the inversion doping region in reducing the probability of doping ions in the source-drain doping layer 210 diffusing into the side wall of the substrate 100, and further optimizing the performance of the semiconductor structure.

[0050] It should be noted that the depth of the source-drain doping layer 210 in the substrate 100 should not be too small or too large. If the depth of the source-drain doping layer 210 in the substrate 100 is too small, it is easy to cause the height of the inversion doping region distributed in the substrate 100 adjacent to the source-drain doping layer 210 to be too small, which in turn easily causes the inversion doping region to be used to reduce the diffusion probability of the doped ions in the source-drain doping layer 210 into the side wall of the substrate 100. The effect is not significant; if the depth of the source-drain doping layer 210 in the substrate 100 is too large, it is easy to have an adverse effect on the short channel effect. For this reason, in this embodiment, the depth of the source-drain doping layer 210 in the substrate 100 is 10nm to 30nm.

[0051] The source-drain doping layer 210 is adjacent to the inversion doping region. The doping type of the inversion ions 140 in the inversion doping region is different from the doping type of the source-drain doping layer 210. This can increase the potential barrier of the substrate 100 adjacent to the side wall of the source-drain doping layer 210, increase the difficulty of the doped ions in the source-drain doping layer 210 diffusing into the substrate 100, and correspondingly reduce the probability of the doped ions in the source-drain doping layer 210 diffusing into the substrate 100 at the bottom of the channel layer 20, thereby improving the leakage current between the source-drain doping layer 210 and the substrate 100 to improve the short channel effect, thereby optimizing the performance of the semiconductor structure.

[0052] The doping type of the counter ion 140 is different from the channel conductivity type of the MOS transistor, thereby increasing the counter doping concentration in the substrate 100. Specifically, the doping type of the counter ion 140 is the same as the doping type of the well region. In this embodiment, when an NMOS transistor is formed, the counter ion 140 is a P-type ion, such as a boron ion; when a PMOS transistor is formed, the counter ion 140 is an N-type ion, such as a phosphorus ion.

[0053] It should be noted that the doping concentration of the anti-type ions 140 in the anti-doping region should not be too low or too high. If the doping concentration of the anti-type ions 140 in the anti-doping region is too low, it is easy to cause the anti-doping region to have an insignificant effect on reducing the probability of doping ions in the source and drain doping layers diffusing into the substrate 100; if the doping concentration of the anti-type ions 140 in the anti-doping region is too high, it is easy to increase the probability of the anti-type ions 140 diffusing into the channel layer 20, thereby easily increasing the probability of causing adverse effects on the carrier mobility in the channel region when the device is working. To this end, in this embodiment, when an NMOS transistor is formed, the counter ion 140 is a P-type ion, and the doping concentration of the counter ion 140 in the inversion doping region is 1e19 atoms per cubic centimeter to 1e20 atoms per cubic centimeter; when a PMOS transistor is formed, the counter ion 140 is an N-type ion, and the doping concentration of the counter ion 140 in the inversion doping region is 1e19 atoms per cubic centimeter to 1e20 atoms per cubic centimeter.

[0054] It should be noted that, in this embodiment, the inversion doping region is also doped with diffusion blocking ions.

[0055] The step of forming the inversion doping region includes ion doping the substrate 100 at the bottom of the top groove and performing a first heat treatment to diffuse the inversion ions 140 into the substrate 100 at the bottom of the channel layer 20. On the one hand, the diffusion blocking ions can slow down the diffusion rate of the inversion ions 140 during the first heat treatment, thereby reducing the probability of the inversion ions 140 diffusing into the interior of the substrate 100 at the bottom of the channel layer 20 in a direction parallel to the substrate 100, so as to concentrate the inversion ions 140 in the inversion doping region at the edge of the substrate 100 at the side wall of the bottom groove as much as possible, so as to minimize the distance between the inversion doping region and the source-drain doping layer 210, so as to further improve the blocking effect of the inversion doping region on the doped ions in the source-drain doping layer 210. On the other hand, the diffusion blocking ions can also further block the diffusion of the doped ions in the source-drain doping layer 210 into the substrate 100, thereby further improving the leakage current between the source-drain doping layer 210 and the substrate 100 and improving the short channel effect.

[0056] In this embodiment, the diffusion blocking ions include ions of group IV elements. Group IV element ions have four valence electrons, and will not form additional electrons or holes, and thus will not affect the doping concentration and doping profile of the counter ions 140 of the substrate 100, and can also reduce the impact on the electrical performance of the device; and the group IV element ions are easy to diffuse, move and fill into the lattice vacancies in the substrate 100 during the first heat treatment, and thus can play a role in blocking the counter ions 140, and correspondingly can reduce the probability of the counter ions 140 diffusing to the inside of the substrate 100 at the bottom of the channel layer 20 in a direction parallel to the substrate 100, and further play a role in blocking the diffusion of the doped ions in the source and drain doping layer 210 into the substrate 100.

[0057] As an example, the group IV element ions include carbon ions, silicon ions or germanium ions. In this embodiment, the group IV element ions are carbon ions as an example for explanation. Carbon ions are relatively small in size, which is conducive to reducing the difficulty of filling lattice vacancies.

[0058] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer (not shown) located on the substrate 100 at the side of the gate structure 190 and covering the source-drain doped layer 210. Specifically, in this embodiment, the interlayer dielectric layer is located on the isolation layer and covers the source-drain doped layer 210.

[0059] The interlayer dielectric layer is used to cover the source-drain doped layer 210 and protect the source-drain doped layer 210. The interlayer dielectric layer is also used to achieve electrical isolation between adjacent devices. The material of the interlayer dielectric layer includes one or more of silicon oxide and silicon nitride. As an example, the material of the interlayer dielectric layer is silicon nitride.

[0060] The semiconductor structure may be formed by the method for forming a semiconductor structure provided by an embodiment of the present invention, or may be formed by other methods.

[0061] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 5 to 13 The following is a schematic diagram of the structure corresponding to each step of the method for forming a semiconductor structure in accordance with an embodiment of the present invention. The method for forming a semiconductor structure in accordance with the present embodiment is described in detail in conjunction with the accompanying drawings.

[0062] refer to Figures 5 and 6 , providing a substrate for forming a MOS transistor, the substrate comprising a substrate 100 and one or more sequentially stacked channel stacks 110 located on the substrate 100 , each channel stack 110 comprising a sacrificial layer 10 and a channel layer 20 located on the sacrificial layer 10 .

[0063] The substrate is used to provide a process platform for subsequent process steps. In this embodiment, the formation of a gate-all-around (GAA) transistor is used as an example for explanation. In other embodiments, the formation method can also be used to form a forksheet transistor or a complementary field effect transistor (CFET).

[0064] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be one or more of other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide, or indium arsenide, and the substrate may also be other types of substrates such as a silicon on insulator substrate or a germanium on insulator substrate.

[0065] The channel stack 110 provides a process basis for subsequently forming the channel layer 20 with suspended spacing.

[0066] In this embodiment, the number of the channel stacks 110 is multiple as an example for description, and the stacking direction of the multiple channel stacks 110 on the substrate 100 is perpendicular to the surface of the substrate 100. Specifically, the number of the channel stacks 110 is three. In other embodiments, the number of the channel stacks can also be two, four, etc. In other embodiments, based on actual process requirements, the number of the channel stacks can also be only one.

[0067] Specifically, the channel layer 20 is used to form a conductive channel of the MOS transistor, and the sacrificial layer 10 is used to support the channel layer 20, thereby providing a process basis for the subsequent realization of the spaced suspended arrangement of the channel layer 20. The sacrificial layer 10 is also used to occupy a spatial position for the subsequent formation of a gate structure.

[0068] In this embodiment, the formation of an NMOS transistor is taken as an example for explanation. The material of the channel layer 20 is the same as that of the substrate 100 , both of which are silicon; and the material of the sacrificial layer 10 is silicon germanium.

[0069] In the subsequent process of removing the sacrificial layer 10, the etching selectivity of silicon germanium and silicon is relatively high. Therefore, by setting the material of the sacrificial layer 10 to silicon germanium and the material of the channel layer 20 to silicon, the effect of the removal process of the sacrificial layer 10 on the channel layer 20 can be effectively reduced, thereby improving the quality of the channel layer 20, which is beneficial to improving device performance.

[0070] In other embodiments, when forming a PMOS transistor, in order to improve the performance of the PMOS transistor, a silicon germanium channel technology may be used, that is, the material of the channel layer is silicon germanium, and the material of the sacrificial layer is silicon. In other embodiments, based on actual process requirements, other materials may be selected for the channel layer and the sacrificial layer.

[0071] It should be noted that, in this embodiment, a well region (not shown) is also formed in the substrate 100 and the channel layer 106, and the doping type of the well region is different from the channel conductivity type of the MOS transistor. When an NMOS transistor is formed, the well region is doped with P-type ions; when a PMOS transistor is formed, the well region is doped with N-type ions.

[0072] As an example, the step of providing a substrate includes:

[0073] like Figure 5 As shown, a substrate 100 is provided; a well region (not shown) is formed in the substrate 100, and the doping type of the well region is different from the channel conductivity type of the MOS tube.

[0074] As an example, the step of forming a well region in the substrate 100 includes: performing ion doping treatment on the substrate 100 ; and performing heat treatment on the substrate 100 to form a well region in the substrate 100 .

[0075] As an example, an ion implantation process is used to perform ion doping treatment on the substrate 100 .

[0076] As an example, an annealing process is used to heat-treat the substrate 100. For example, a rapid thermal annealing process is used to heat-treat the substrate 100.

[0077] like Figure 6 As shown, one or more stacked channel stacks 110 are formed on a substrate 100 .

[0078] As an example, the step of forming one or more stacked channel stacks 110 on the substrate 100 includes: forming one or more stacked channel material stacks (not shown) on the substrate 100, each channel material stack including a sacrificial material layer and a channel material layer located on the sacrificial material layer; performing patterning on the channel material stack, and the remaining channel material stack is used as the channel stack 110.

[0079] In a specific implementation, in the step of patterning the channel material stack, a portion of the thickness of the substrate 100 may also be patterned so that the substrate 100 of the adjacent device region is surrounded by a trench. The trench is used to define the isolation region between adjacent devices so as to provide a spatial position for forming an isolation layer in the trench.

[0080] Correspondingly, in this embodiment, the step of providing a substrate may further include: forming an isolation layer (not shown) in the trench, wherein the isolation layer exposes the channel stack 110 .

[0081] The isolation layer is used to isolate adjacent devices. In this embodiment, the isolation layer is a shallow trench isolation structure. The material of the isolation layer may include one or more of silicon oxide, silicon oxynitride and silicon nitride.

[0082] refer to Figure 7 , forming a dummy gate structure 120 across the channel stack 110 .

[0083] The dummy gate structure 120 is used to pre-occupy a space position for the subsequent formation of a gate structure. Specifically, in this embodiment, the dummy gate structure 120 is formed on the isolation layer and across the channel stack 110 , and covers part of the top and part of the sidewall of the channel stack 110 .

[0084] In this embodiment, the dummy gate structure 120 includes a dummy gate oxide layer 121 and a dummy gate layer 122 located on the dummy gate oxide layer 121 .

[0085] In this embodiment, the material of the dummy gate oxide layer 121 includes one or more of silicon oxide and silicon oxynitride. In this embodiment, the material of the dummy gate layer 122 includes polysilicon or amorphous silicon.

[0086] In a specific implementation, a dummy gate mask layer (not shown) is further formed on the top of the dummy gate layer 122 . The dummy gate mask layer is used as an etching mask for patterning the dummy gate material layer to form the dummy gate structure 120 .

[0087] As an example, the material of the dummy gate mask layer is silicon nitride.

[0088] In this embodiment, after forming the dummy gate structure 120, the method for forming a semiconductor structure further includes: forming a gate sidewall 125 on the sidewall of the dummy gate structure 120. The gate sidewall 125 is used together with the dummy gate layer 122 and the dummy gate mask layer as an etching mask for subsequent formation of source and drain grooves to define the formation position of the source and drain doping layer, and the gate sidewall 125 is also used to protect the dummy gate layer 122 and the sidewall of the subsequent gate structure.

[0089] The material of the gate spacer 125 is an insulating dielectric material. In this embodiment, the material of the gate spacer 125 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric or ultra-low-k dielectric material, and the gate spacer 125 is a single-layer or stacked structure. As an example, the gate spacer 125 is a single-layer structure, and the material of the gate spacer 125 is silicon nitride.

[0090] refer to Figure 8 A top groove 130 is formed in the channel stack 110 on both sides of the dummy gate structure 120, and the top groove 130 exposes the top of the substrate 100. By forming the top groove 130 and exposing the top of the substrate 100, counter ions 140 can be doped in the substrate 100 exposed by the top groove 130 later.

[0091] Moreover, after the initial doping region is subsequently formed in the substrate 100, part of the thickness of the substrate 100 at the bottom of the top groove 130 is removed to form a bottom groove. The top groove is used to provide a process basis for the subsequent formation of the bottom groove, and is also used to form a source and drain groove together with the subsequent bottom groove, so that the source and drain grooves provide a spatial position for the subsequent formation of the source and drain doping layer.

[0092] As an example, the step of forming the top recess 130 includes: using an anisotropic dry etching process to etch the channel stack 110 exposed by the dummy gate structure 120 to form the top recess 130 .

[0093] The anisotropic dry etching process has anisotropic etching characteristics, which is beneficial to improving the profile control of the top groove 130. The dry etching process has high etching accuracy and fast etching rate. The dry etching process is easy to achieve a higher etching selectivity ratio, which is beneficial to reducing the probability of damage to other film layer structures in the process of forming the top groove 130.

[0094] refer to Fig. 9 , counter ions 140 are doped into the substrate 100 exposed by the top groove 130 , and the doping type of the counter ions 140 is different from the channel conductivity type of the MOS transistor.

[0095] By doping the substrate 100 exposed by the top groove 130 with counter ions 140 so as to perform a first heat treatment later, the counter ions 140 are diffused into the substrate 100 at the bottom of the pseudo gate structure 120, and an initial doping region is formed in the substrate 100. Then, after a portion of the thickness of the substrate 100 at the bottom of the top groove 130 is removed to form a bottom groove, the remaining initial doping region at the edge of the substrate 100 at the side wall of the bottom groove can be used as an counter doping region.

[0096] The doping type of the counter ions 140 is different from the channel conductivity type of the MOS transistor, thereby increasing the counter doping concentration in the substrate 100. Specifically, the doping type of the counter ions 140 is the same as the doping type of the well region.

[0097] In this embodiment, when an NMOS transistor is formed, the counter ions 140 are P-type ions, such as boron ions; when a PMOS transistor is formed, the counter ions 140 are N-type ions, such as phosphorus ions.

[0098] As an example, an ion implantation process is used to dope the counter ions 140 in the substrate 100 exposed by the top groove 130. The ion implantation process can easily control the ion doping concentration and doping depth in the substrate 100 by controlling the energy and dose of the ion implantation and the implantation angle, thereby easily making the doping concentration, doping depth and doping profile of the counter ions 140 in the substrate 100 meet the process requirements.

[0099] It should be noted that, in the step of doping the anti-type ions 140 in the substrate 100 exposed by the top groove 130 by using the ion implantation process, the energy of the ion implantation should not be too small or too large. If the energy of the ion implantation is too small, it is easy to cause the doping depth of the anti-type ions 140 in the substrate 100 to be too small. After the partial thickness of the substrate 100 at the bottom of the top groove 130 is removed to form the bottom groove, it is easy to cause the anti-type doping region to be not completely distributed on the entire side wall of the bottom groove, thereby easily reducing the effect of the anti-type doping region for reducing the diffusion probability of the doping ions in the source and drain doping layer into the substrate 100; if the energy of the ion implantation is too large, it is easy to increase the ion implantation damage to the substrate 100.

[0100] To this end, in this embodiment, in the step of doping counter ions in the substrate 100 exposed by the top groove 130 using an ion implantation process, when an NMOS transistor is formed, the counter ions are P-type ions, and the implantation energy is 5KeV to 20KeV; when a PMOS transistor is formed, the counter ions are N-type ions, and the implantation energy is 5KeV to 20KeV.

[0101] It should also be noted that, in the step of doping the anti-type ions 140 in the substrate 100 exposed by the top groove 130 by using the ion implantation process, the implantation dose of the anti-type ions 140 should not be too small or too large. If the implantation dose of the anti-type ions is too small, it is easy to cause the subsequent doping concentration of the anti-type ions 140 in the anti-type doping region to be too low, and then it is easy to cause the anti-type doping region to be used for reducing the diffusion probability of the doped ions in the source and drain doping layer into the substrate 100. The effect is not obvious; if the implantation dose of the anti-type ions 140 is too large, it is easy to cause the doping concentration of the anti-type ions 140 in the subsequent initial anti-type doping region to be too high, and in the subsequent step of performing the first heat treatment, it is easy to increase the probability of the anti-type ions 140 diffusing into the channel layer 20, and then it is easy to increase the probability of causing adverse effects on the carrier mobility in the channel region when the device is working. To this end, in this embodiment, when an NMOS transistor is formed, the counter ion 140 is a P-type ion, and the implantation dose is 5e12 atoms per square centimeter to 2e13 atoms per square centimeter; when a PMOS transistor is formed, the counter ion 140 is an N-type ion, and the implantation dose is 5e12 atoms per square centimeter to 2e13 atoms per square centimeter.

[0102] It should also be noted that, in the step of doping the counter ions 140 in the substrate 100 exposed by the top groove 130 using the ion implantation process, the implantation angle of the counter ions 140 should not be too large, otherwise it is easy to increase the risk of implanting the counter ions 140 into the channel layer 20. For this reason, in this embodiment, the implantation angle is 0° to 5°.

[0103] In this embodiment, the implantation angle refers to the angle between the ion implantation direction and the surface normal of the substrate 100 .

[0104] It should also be noted that, in the present embodiment, in the step of doping the counter ions 140 in the substrate 100 exposed by the top groove 130 , diffusion blocking ions are also doped in the substrate 100 exposed by the top groove 130 .

[0105] On the one hand, the diffusion blocking ions can slow down the diffusion rate of the anti-type ions 140 during the first heat treatment, thereby reducing the probability of the anti-type ions 140 diffusing into the bottom substrate 100 of the channel layer 20 in a direction parallel to the substrate 100, so as to concentrate the anti-type ions 140 in the anti-type doping region as much as possible at the substrate edge of the bottom groove side wall, and make the distance between the anti-type doping region and the source-drain doping layer as small as possible, so as to further improve the blocking effect of the anti-type doping region on the doped ions in the source-drain doping layer; on the other hand, after the source-drain doping layer is formed, the diffusion blocking ions can further block the diffusion of the doped ions in the source-drain doping layer into the substrate 100, thereby further improving the leakage current between the source-drain doping layer and the substrate 100 and improving the short channel effect.

[0106] In this embodiment, the diffusion blocking ions include ions of group IV elements. Group IV element ions have four valence electrons, and will not form additional electrons or holes, and thus will not affect the doping concentration and doping profile of the counter ions 140 of the substrate 100, and can also reduce the impact on the electrical performance of the device; and the group IV element ions are easy to diffuse, move and fill into the lattice vacancies in the substrate 100 during the subsequent first heat treatment, and thus can play a role in blocking the counter ions 140, and correspondingly can reduce the probability of the counter ions 140 diffusing to the inside of the substrate 100 at the bottom of the channel layer 20 in a direction parallel to the substrate 100, and further play a role in blocking the diffusion of doped ions in the source and drain doping layers into the substrate.

[0107] As an example, the Group IV element ions include carbon ions, silicon ions, or germanium ions.

[0108] In this embodiment, the IV group element ions are carbon ions as an example for illustration. Carbon ions are relatively small in size, which is conducive to reducing the difficulty of filling lattice vacancies.

[0109] Similarly, in this embodiment, in the step of doping the counter ions 140 in the substrate 100 exposed by the top groove 130 by using the ion implantation process, the diffusion barrier ions are doped in the substrate 100 exposed by the top groove 130 by using the ion implantation process.

[0110] It should be noted that, in the step of doping diffusion barrier ions in the substrate 100 exposed by the top groove 130 using the ion implantation process, the implantation energy of the diffusion barrier ions should not be too small or too large. If the implantation energy of the diffusion barrier ions is too small, it is easy to cause the implantation depth of the diffusion barrier ions in the substrate 100 to be too small, and thus it is easy to reduce the blocking effect of the diffusion barrier ions on the counter ions 140; if the implantation energy of the diffusion barrier ions is too large, it is easy to increase the implantation damage caused by the ion implantation to the substrate 100. For this reason, in this embodiment, the diffusion barrier ions include carbon ions, and the implantation energy is 2KeV to 10KeV.

[0111] It should also be noted that in the step of doping diffusion-blocking ions in the substrate 100 exposed by the top groove 130 using the ion implantation process, the implantation dose of the diffusion-blocking ions should not be too small or too large. If the implantation dose of the diffusion-blocking ions is too small, it is easy to cause the concentration of the diffusion-blocking ions in the substrate 100 to be too low, and thus it is easy to cause the diffusion-blocking ions to have an insignificant blocking effect on the counter ions 140; if the implantation dose of the diffusion-blocking ions is too large, it is also easy to increase the risk of ion implantation causing implantation damage to the substrate 100. For this reason, in this embodiment, the diffusion-blocking ions include carbon ions, and the implantation dose is 1e14 atoms per square centimeter to 5e14 atoms per square centimeter.

[0112] It should also be noted that, in the step of doping diffusion barrier ions in the substrate 100 exposed by the top groove 130 using an ion implantation process, the implantation angle of the diffusion barrier ions should not be too large, otherwise it is easy to increase the probability of implanting the diffusion barrier ions into the channel layer 20. For this purpose, the diffusion barrier ions include carbon ions, and the implantation angle is 0° to 5°.

[0113] refer to Fig.10 After counter ions 140 are doped into the substrate 100 exposed by the top groove 130 , a first heat treatment 200 is performed to diffuse the counter ions 140 into the substrate 100 at the bottom of the dummy gate structure 120 , thereby forming an initial doping region (not shown) in the substrate 100 .

[0114] The first heat treatment 200 is performed to diffuse the counter ions 140 into the substrate 100 at the bottom of the dummy gate structure 120 to form an initial doping region, so that after a portion of the thickness of the substrate 100 at the bottom of the top groove is subsequently removed to form a bottom groove, a portion of the initial doping region can still be retained within the edge of the substrate 100 at the sidewall of the bottom groove as an inverted doping region. The first heat treatment 200 is also used to activate the counter ions 140 and repair lattice damage caused to the substrate 100.

[0115] It should be noted that in the step of performing the first heat treatment 200, the temperature of the first heat treatment 200 should not be too low or too high. If the temperature of the first heat treatment 200 is too low, it is easy to cause the diffusion rate of the counter ions 140 to be too slow, and it is also easy to reduce the activation effect on the impurity ions; if the temperature of the first heat treatment 200 is too high, it is easy to cause the diffusion rate of the counter ions 140 to be too fast, and it is easy to increase the probability of the counter ions 140 diffusing into the channel layer 20. For this reason, in this embodiment, the temperature of the first heat treatment 200 is 800°C to 1100°C.

[0116] It should also be noted that the process time of the first heat treatment 200 should not be too short or too long. If the process time of the first heat treatment 200 is too short, it is easy to cause the diffusion distance of the counter ions 140 to be too small, and it is also easy to reduce the activation effect on the impurity ions; if the process time of the first heat treatment 200 is too long, it is easy to increase the probability of the counter ions 140 diffusing into the channel layer 20. For this reason, in this embodiment, the process time of the first heat treatment 200 is 0.2 minutes to 2 minutes.

[0117] In this embodiment, an annealing process is used to perform the first heat treatment 200. As an example, a rapid thermal annealing process is used to perform the first heat treatment 200.

[0118] refer to Fig.11After the first heat treatment 200, part of the thickness of the substrate 100 at the bottom of the top groove 130 is removed, and a bottom groove 150 is formed in the substrate 100 at the bottom of the top groove 130. The bottom groove 150 and the top groove 130 located on the bottom groove 150 constitute a source-drain groove 160; the remaining initial doped region in the edge of the substrate 100 at the side wall of the bottom groove 150 is used as an inversion doped region (not shown).

[0119] The source-drain grooves 160 are used to provide a space for the subsequent formation of source-drain doping layers.

[0120] In this embodiment, a portion of the thickness of the substrate 100 at the bottom of the top groove 130 is removed to form a bottom groove 150, and the remaining initial doped region in the edge of the substrate 100 at the side wall of the bottom groove 150 is used as an inversion doped region, so that after a source-drain doped layer is subsequently formed in the source-drain groove 160, the source-drain doped layer is adjacent to the inversion doped region, and the doping type of the inversion ions in the inversion doped region is different from the doping type of the source-drain doped layer, which can improve the potential barrier of the substrate 100 adjacent to the side wall of the source-drain doped layer, increase the difficulty of the doped ions in the source-drain doped layer to diffuse into the substrate 100, and correspondingly reduce the probability of the doped ions in the source-drain doped layer to diffuse into the substrate 100 at the bottom of the channel layer 20, thereby improving the leakage current between the source-drain doped layer and the substrate 100 to improve the short channel effect, thereby optimizing the performance of the semiconductor structure.

[0121] In the present embodiment, in the step of removing a portion of the thickness of the substrate 100 at the bottom of the top groove 130 and forming a bottom groove 150 in the substrate 100 at the bottom of the top groove 130, the thickness of the removed substrate 100 is the same as the doping depth of the initial doping region, thereby ensuring that after removing a portion of the thickness of the substrate 100 at the bottom of the top groove 130, the inverted doping region can be distributed on the entire side wall of the bottom groove 150, thereby enhancing the effect of the inverted doping region for reducing the probability of doping ions in the source and drain doping layers diffusing into the side walls of the substrate 100, thereby further optimizing the performance of the semiconductor structure.

[0122] It should be noted that the depth of the bottom groove 150 should not be too small or too large. If the depth of the bottom groove 150 is too small, it is easy to cause the height of the inversion doping region retained on the side wall of the bottom groove 150 to be too small, which in turn easily causes the inversion doping region to be used to reduce the diffusion probability of the doped ions in the source and drain doping layer into the side wall of the substrate 100. The effect is not significant; if the depth of the bottom groove 150 is too large, it is easy to cause the depth of the source and drain doping layer subsequently formed in the source and drain groove to be too deep, which is easy to have an adverse effect on the short channel effect. For this reason, in this embodiment, the depth of the bottom groove 150 is 10nm to 30nm.

[0123] In this embodiment, the step of forming the bottom groove 150 includes: using an anisotropic dry etching process to etch a portion of the thickness of the substrate 100 at the bottom of the top groove 130 to form the bottom groove 150 .

[0124] The anisotropic dry etching process has anisotropic etching characteristics, which is beneficial to improving the profile control of the bottom groove 150. The dry etching process has high etching accuracy and fast etching rate. The dry etching process is easy to achieve a higher etching selectivity ratio, which is beneficial to reduce the probability of damage to other film layer structures in the process of forming the bottom groove 150 and accurately control the depth of the bottom groove 150.

[0125] It should be noted that the reference Fig.12 In this embodiment, the method for forming a semiconductor structure further includes: after forming the source-drain grooves 160 , performing a second heat treatment 300 in an inert gas atmosphere.

[0126] A second heat treatment 300 is performed in an inert gas atmosphere to repair the interface state on the surface of the source-drain groove 160 and the lattice damage generated in the substrate 100, thereby providing a good interface state for the subsequent formation of a source-drain doping layer in the source-drain groove 160, thereby correspondingly improving the formation quality of the source-drain doping layer, and repairing the defects in the lattice at the bottom of the source-drain doping layer, which is beneficial to improving the problem of stacking fault defects in the source-drain doping layer, further improving the leakage current problem between the source-drain doping layer and the substrate 100, and optimizing the performance of the semiconductor structure.

[0127] In this embodiment, the step of performing the second heat treatment 300 in an inert gas atmosphere includes: performing the second heat treatment 300 in a deuterium and inert gas atmosphere.

[0128] Deuterium or inert gas combines more stably with the interface dangling bonds, thereby inhibiting the formation of unstable chemical bonds with hydrogen, and then passivating the interface state. Then, by performing the second heat treatment 300 in the deuterium and inert gas atmosphere, the interface state at the bottom and side wall surface of the source / drain groove 160 can be repaired.

[0129] Specifically, in this embodiment, deuterium and an inert gas are introduced into the reaction chamber to perform the second heat treatment 300 .

[0130] It should be noted that the gas flow rate of the second heat treatment 300 should not be too small or too large. If the gas flow rate of the second heat treatment 300 is too small, the efficiency of the interface repair is easily reduced; if the gas flow rate of the second heat treatment 300 is too large, the probability of uneven interface repair is easily increased. For this reason, in the step of performing the second heat treatment 300, the total flow rate of deuterium and inert gas is 2slm (standard litre per minute, a flow rate of 1L / min under standard conditions) to 20slm in this embodiment.

[0131] It should also be noted that the process temperature of the second heat treatment 300 should not be too low or too high. If the process temperature of the second heat treatment 300 is too low, the efficiency of interface repair and lattice damage repair is easily reduced; if the process temperature of the second heat treatment 300 is too high, the probability of diffusion of doped ions in the semiconductor structure is easily increased. For this reason, in this embodiment, the process temperature of the second heat treatment 300 is 400°C to 700°C.

[0132] It should also be noted that the process time of the second heat treatment 300 should not be too short or too long. If the process time of the second heat treatment 300 is too short, it is easy to cause insufficient repair of interface states and lattice damage; if the process time of the second heat treatment 300 is too long, it is easy to increase the probability of diffusion of doped ions in the semiconductor structure and it is also easy to waste working hours. For this reason, the process time of the second heat treatment 300 is 1 minute to 30 minutes.

[0133] refer to Fig.13 A source-drain doping layer 210 is formed in the source-drain groove 160, and the source-drain doping layer 210 is adjacent to the inversion doping region. The source-drain doping layer 210 is used as a source or drain of the MOS transistor. When the MOS transistor is working, the source-drain doping layer 210 is used to provide a carrier source.

[0134] The source-drain doping layer 210 is adjacent to the inversion doping region. The doping type of the inversion ions 140 in the inversion doping region is different from the doping type of the source-drain doping layer 210. This can increase the potential barrier of the substrate 100 adjacent to the side wall of the source-drain doping layer 210, increase the difficulty of the doped ions in the source-drain doping layer 210 diffusing into the substrate 100, and correspondingly reduce the probability of the doped ions in the source-drain doping layer 210 diffusing into the substrate 100 at the bottom of the channel layer 20, thereby improving the leakage current between the source-drain doping layer 210 and the substrate 100 to improve the short channel effect, thereby optimizing the performance of the semiconductor structure.

[0135] In this embodiment, an epitaxial process is adopted to form the stress layer, and ions are self-doped in situ during the process of forming the stress layer. The stress layer doped with ions is used as the source-drain doping layer 210 .

[0136] Specifically, based on the substrate 100 at the bottom and sidewall of the source-drain groove 160 and the channel layer 20 exposed by the source-drain groove 160, epitaxial growth is performed to form the source-drain doped layer 210. The interface state on the substrate surface is repaired, so that the epitaxial quality of the source-drain doped layer 210 is good, and the leakage current problem between the source-drain doped layer 210 and the substrate 100 is improved.

[0137] Among them, when the fully enclosed gate transistor is a P-type MOS transistor, the material of the stress layer is Si or SiGe, and the doped ions in the source and drain doping layer 210 are P-type ions; when the fully enclosed gate transistor is an N-type MOS transistor, the material of the stress layer is Si or SIC, and the doped ions in the source and drain doping layer 210 are N-type ions.

[0138] In this embodiment, the method for forming a semiconductor structure also includes: after performing the second heat treatment 300 and before forming the source and drain doping layers, transversely etching a portion of the sacrificial layer 10 exposed on the sidewalls of the source and drain grooves 160 in a direction parallel to the substrate 100 and perpendicular to the extension direction of the dummy gate structure 120 to form an inner groove (not shown), the inner groove is surrounded by the adjacent channel layer 20 and the remaining sacrificial layer 10, or the inner groove is surrounded by the substrate 100, the channel layer 20 adjacent to the substrate 100 and the remaining sacrificial layer 10; forming an inner sidewall 180 in the inner groove.

[0139] Specifically, the inner groove provides a spatial position for forming the inner sidewall. In this embodiment, the process of laterally etching the part of the sacrificial layer 10 exposed by the sidewall of the source-drain groove 160 includes an isotropic etching process. The isotropic etching process has the characteristics of isotropic etching, and it is easy to achieve a large etching selectivity, so that the part of the sacrificial layer 10 exposed along the sidewall of the source-drain groove 160 can be laterally etched, which is conducive to reducing the difficulty of etching the sacrificial layer 10 and reducing the probability of damage to other film structures.

[0140] Subsequently, a source-drain doped layer is formed in the source-drain groove 160, and a gate structure is formed at the position of the pseudo-gate structure 120 and the sacrificial layer 10. The inner sidewall 180 is used to achieve isolation between the source-drain doped layer and the gate structure, and also to increase the distance between the source-drain doped layer and the gate structure, which is beneficial to reducing the parasitic capacitance between the source-drain doped layer and the gate structure.

[0141] In this embodiment, the material of the inner sidewall 180 is an insulating material to achieve isolation between the source and drain doping layers and the gate structure. In this embodiment, the material of the inner sidewall 180 includes silicon nitride, silicon oxide, silicon oxynitride, low-k dielectric material or ultra-low-k dielectric material.

[0142] In this embodiment, the method for forming a semiconductor structure also includes: after forming the source-drain doping layer 210, forming an interlayer dielectric layer (not shown) on the substrate 100 on the side of the dummy gate structure 120, the interlayer dielectric layer covers the source-drain doping layer 210 and exposes the top of the dummy gate structure 111; removing the dummy gate structure 120, forming a gate opening (not shown) in the interlayer dielectric layer, exposing the channel stack 110; removing the sacrificial layer 10 exposed by the gate opening, forming a through groove (not shown), the through groove is connected to the gate opening; filling the gate opening and the through groove with a gate structure 190, the gate structure 190 surrounds the channel layer 20.

[0143] The interlayer dielectric layer is used to cover the source-drain doped layer 210, and plays a role in protecting the source-drain doped layer 210 when the gate opening is subsequently formed. The interlayer dielectric layer is also used to achieve electrical isolation between adjacent devices. The material of the interlayer dielectric layer includes one or more of silicon oxide and silicon nitride. As an example, the material of the interlayer dielectric layer is silicon nitride.

[0144] Specifically, in this embodiment, the interlayer dielectric layer is formed on the isolation layer and covers the source-drain doped layer 210 .

[0145] The gate opening and the through groove are used to provide a spatial location for forming a gate structure.

[0146] After removing the sacrificial layer, one or more channel layers 20 are suspended and arranged at intervals, so that the subsequent gate structure can surround the channel layer 20. Among them, one or more channel layers 20 that are suspended and arranged at intervals in sequence are used to form a channel structure layer 170.

[0147] When the device is operating, the gate structure 190 is used to control the opening and closing of the conductive channel.

[0148] In this embodiment, the portion of the gate structure 190 located between the substrate 100 and the channel layer 20 or between adjacent channel layers 20 is the first portion 191 ; the portion of the gate structure 190 spanning the channel structure layer 170 is the second portion 192 .

[0149] In this embodiment, the gate structure 190 is a metal gate structure, and the gate structure 190 includes a gate dielectric layer (not shown), a work function layer (not shown) located on the gate dielectric layer, and a gate electrode layer (not shown) located on the work function layer and filling the through groove and the gate opening.

[0150] The gate dielectric layer is used to achieve electrical isolation between the work function layer and the gate electrode layer and the conductive channel. The material of the gate dielectric layer includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3 and Al2O3.

[0151] In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k dielectric material. The material of the high-k gate dielectric layer can be selected from ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3. In other embodiments, the gate dielectric layer may also include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer.

[0152] The work function layer is used to adjust the work function of the gate structure 190, and then adjust the threshold voltage of the field effect transistor. When forming an NMOS transistor, the work function layer is an N-type work function layer, and the material of the work function layer includes one or more of titanium aluminide, tantalum carbide, aluminum or titanium carbide; when forming a PMOS transistor, the work function layer is a P-type work function layer, and the material of the work function layer includes one or more of titanium nitride, tantalum nitride, titanium carbide, tantalum silicon nitride, titanium silicon nitride and tantalum carbide.

[0153] The gate electrode layer is used as an external electrode for electrically connecting the gate structure 190 to an external circuit. The material of the gate electrode layer is a conductive material, such as W, Al, Cu, Ag, Au, Pt, Ni or Ti.

[0154] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A channel structure layer is suspended on the substrate, and the channel structure layer includes one or more channel layers sequentially arranged from bottom to top; A gate structure, spanning the channel structure layer, the gate structure is filled between the channel layer and the substrate and between adjacent channel layers, and the gate structure surrounds the channel layer; Source and drain doping layers are located in the channel structure layer on both sides of the gate structure and in a portion of the thickness of the substrate; The inversion doping region is located in the side wall of the substrate adjacent to the source-drain doping layer. The inversion doping region is doped with inversion ions, and the doping type of the inversion ions is different from the doping type of the source-drain doping layer.

2. The semiconductor structure according to claim 1, wherein: The inversion doping region is also doped with diffusion blocking ions.

3. The semiconductor structure according to claim 2, wherein: The diffusion barrier ions include ions of group IV elements.

4. The semiconductor structure according to claim 3, characterized in that The group IV element ions include carbon ions, silicon ions or germanium ions.

5. The semiconductor structure according to claim 1, wherein: The source-drain doping layer is located in the substrate at a depth of 10 nm to 30 nm.

6. The semiconductor structure according to claim 1, wherein: When an NMOS transistor is formed, the counter ions are P-type ions, and the doping concentration of the counter ions in the inversion doping region is 1e19 atoms per cubic centimeter to 1e20 atoms per cubic centimeter; when a PMOS transistor is formed, the counter ions are N-type ions, and the doping concentration of the counter ions in the inversion doping region is 1e19 atoms per cubic centimeter to 1e20 atoms per cubic centimeter.

7. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate for forming a MOS transistor, the substrate comprising a substrate and one or more sequentially stacked channel stacks located on the substrate, each of the channel stacks comprising a sacrificial layer and a channel layer located on the sacrificial layer; forming a dummy gate structure across the channel stack; forming a top groove in the channel stack at both sides of the dummy gate structure, wherein the top groove exposes the top of the substrate; doping counter-type ions in the substrate exposed by the top groove, wherein the doping type of the counter-type ions is different from the channel conductivity type of the MOS transistor; After doping the substrate exposed by the top groove with counter ions, performing a first heat treatment to diffuse the counter ions into the substrate at the bottom of the pseudo gate structure to form an initial doping region in the substrate; After the first heat treatment, a part of the thickness of the substrate at the bottom of the top groove is removed to form a bottom groove in the substrate at the bottom of the top groove, wherein the bottom groove and the top groove located on the bottom groove constitute a source-drain groove; and the remaining initial doping region in the substrate edge of the side wall of the bottom groove is used as an inversion doping region; A source-drain doping layer is formed in the source-drain groove, and the source-drain doping layer is adjacent to the inversion doping region.

8. The method for forming a semiconductor structure according to claim 7, wherein: In the step of doping the substrate exposed by the top groove with counter ions, diffusion blocking ions are also doped in the substrate exposed by the top groove.

9. The method for forming a semiconductor structure according to claim 8, wherein: The diffusion barrier ions include ions of group IV elements.

10. The method for forming a semiconductor structure according to claim 9, wherein: The group IV element ions include carbon ions, silicon ions or germanium ions.

11. The method for forming a semiconductor structure according to claim 8, wherein: An ion implantation process is used to dope diffusion barrier ions into the substrate exposed by the top groove.

12. The method for forming a semiconductor structure according to claim 11, wherein: The process parameters of the ion implantation include: the diffusion barrier ions include carbon ions, the implantation energy is 2KeV to 10KeV, the implantation dose is 1e14 atoms per square centimeter to 5e14 atoms per square centimeter, and the implantation angle is 0° to 5°.

13. The method for forming a semiconductor structure according to claim 7, wherein: An ion implantation process is used to dope the substrate exposed by the top groove with counter ions.

14. The method for forming a semiconductor structure according to claim 13, wherein: The process parameters of the ion implantation include: when forming an NMOS transistor, the counter ions are P-type ions, the implantation energy is 5KeV to 20KeV, the implantation dose is 5e12 atoms per square centimeter to 2e13 atoms per square centimeter, and the implantation angle is 0° to 5°; when forming a PMOS transistor, the counter ions are N-type ions, the implantation energy is 5KeV to 20KeV, the implantation dose is 5e12 atoms per square centimeter to 2e13 atoms per square centimeter, and the implantation angle is 0° to 5°.

15. The method for forming a semiconductor structure according to claim 7, wherein: The method for forming a semiconductor structure further includes: performing a second heat treatment in an inert gas atmosphere after forming the source-drain grooves and before forming source-drain doping layers in the source-drain grooves.

16. The method for forming a semiconductor structure according to claim 15, wherein: The step of performing the second heat treatment in an inert gas atmosphere includes performing the second heat treatment in an atmosphere of deuterium and inert gas.

17. The method for forming a semiconductor structure according to claim 16, wherein: The process parameters of the second heat treatment include: a total flow rate of deuterium and inert gas of 2 slm to 20 slm, a process temperature of 400° C. to 700° C., and a process time of 1 minute to 30 minutes.

18. The method for forming a semiconductor structure according to claim 7, wherein: The step of forming the top groove includes: using an anisotropic dry etching process to etch the channel stack exposed by the pseudo gate structure to form the top groove; the step of forming the bottom groove includes: using an anisotropic dry etching process to etch a partial thickness of the substrate at the bottom of the top groove to form the bottom groove.

19. The method for forming a semiconductor structure according to claim 7, wherein: A partial thickness of the substrate at the bottom of the top groove is removed, and in the step of forming a bottom groove in the substrate at the bottom of the top groove, the thickness of the removed substrate is the same as the doping depth of the initial doping region.

20. The method for forming a semiconductor structure according to claim 7, wherein: The method for forming the semiconductor structure also includes: after forming the source-drain doping layer, removing the dummy gate structure to form a gate opening to expose the channel stack; removing the sacrificial layer exposed by the gate opening to form a through groove, wherein the through groove is connected to the gate opening; and filling the gate opening and the through groove with a gate structure, wherein the gate structure surrounds the channel layer.

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