Back contact battery, manufacturing method thereof and photovoltaic module
By adopting aluminum doped low -temperature technology in the P area of the TBC battery, instead of traditional high -temperature phosphorus doping technology, and using a pupa -containing plasma, it solves the problem of high costs of the TBC battery P zone. Improvement of conversion efficiency.
Patent Information
- Application Number
- CN202411480179.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-22
- Publication Date
- 2025-01-21
AI Technical Summary
In the P-zone process of TBC batteries, the phosphorus-doped semiconductor layer needs to be produced through high-temperature processes, resulting in higher process costs.
The method of using aluminum doping is used to make the first half of the conductor doping layer under low temperature annealing conditions, replacing the traditional phosphorus doped semiconductor layer, and using aluminum -containing conductive plasma to make the grid line to reduce the contact resistance.
It effectively reduces production costs, reduces heat loss and deformation of materials, improves the stability and controllability of the production process, and improves the photoelectric conversion efficiency of back-contact cells.
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Figure CN119342927A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of photovoltaic technology, and in particular to a back-contact cell and a manufacturing method thereof, and a photovoltaic module. Background Art
[0002] The interdigitated back contact (IBC) cell and the tunnel oxide passivated contact (TOPcon) cell can be stacked to form a TBC cell. The TBC cell includes the tunnel oxide passivated contact of the TOPCon cell and the P and N regions arranged in interdigitated patterns on the back of the IBC cell.
[0003] At present, the P-zone process of TBC batteries uses a phosphorus-doped semiconductor layer. However, the phosphorus-doped semiconductor layer needs to be produced through a high-temperature process, and the process cost is relatively high. Summary of the invention
[0004] Based on this, it is necessary to provide a back contact cell and a manufacturing method thereof, and a photovoltaic module to address the problem of high process cost of the P region of TBC cells in the prior art.
[0005] In order to achieve the above objectives, in a first aspect, the present disclosure provides a method for manufacturing a back contact battery, comprising:
[0006] providing a substrate;
[0007] forming a first semiconductor intrinsic layer on the back side of the substrate;
[0008] forming a first material layer on a side of the first semiconductor intrinsic layer away from the substrate, wherein the first material layer includes aluminum;
[0009] Annealing the first material layer and the first semiconductor intrinsic layer under a first temperature condition, so that the aluminum element in the first material layer diffuses into the first semiconductor intrinsic layer to form a first semiconductor doping layer, and the first temperature ranges from 200° C. to 600° C.;
[0010] A conductive paste containing aluminum element is printed on a side of the first semiconductor doping layer away from the substrate to form a first gate line, wherein the first gate line is connected to the first semiconductor doping layer.
[0011] Optionally, the first material layer is an aluminum oxide layer.
[0012] Optionally, the first material layer is formed only on one side of the first semiconductor intrinsic layer in the first region of the back side, and after annealing the first material layer and the first semiconductor intrinsic layer, the first semiconductor doping layer is formed in the first region.
[0013] Optionally, after forming the first semiconductor doping layer, the first semiconductor doping layer except the first region on the back side is etched away.
[0014] Optionally, the manufacturing method further includes:
[0015] forming a second semiconductor doping layer in a second region between the first regions, the first semiconductor doping layer and the second semiconductor doping layer being alternately arranged on the back side of the substrate, and the second semiconductor doping layer being doped with N-type conductive type doping ions;
[0016] A back passivation anti-reflection layer is formed, wherein the back passivation anti-reflection layer covers the first semiconductor doping layer and the second semiconductor doping layer on a side away from the substrate; wherein the first gate line is formed on a side of the back passivation anti-reflection layer away from the first semiconductor doping layer, and at least a portion of the first gate line penetrates the back passivation anti-reflection layer and contacts the first semiconductor doping layer;
[0017] A second gate line is formed on a side of the back passivation anti-reflection layer away from the second semiconductor doping layer, and at least a portion of the second gate line penetrates the back passivation anti-reflection layer and contacts the second semiconductor doping layer.
[0018] Optionally, the manufacturing method comprises:
[0019] forming a second tunneling layer, a second semiconductor intrinsic layer and a phosphosilicate glass layer in sequence on the back side of the substrate;
[0020] Laser processing the phosphosilicate glass layer, so that phosphorus ions in the phosphosilicate glass layer diffuse into the second semiconductor intrinsic layer to form a second semiconductor doped layer;
[0021] Etching and removing the phosphosilicate glass layer, the second semiconductor doping layer and the second tunneling layer outside the second region to expose the back side of the first region;
[0022] forming a first tunneling layer and the first semiconductor intrinsic layer in sequence on the back side of the substrate, and etching and removing the first tunneling layer and the first semiconductor intrinsic layer outside the first region;
[0023] forming the first material layer, wherein the first material layer covers the first semiconductor intrinsic layer and the second semiconductor doping layer;
[0024] Annealing the first material layer and the first semiconductor intrinsic layer under a first temperature condition to form the first semiconductor doping layer;
[0025] A back passivation anti-reflection layer is formed, wherein the back passivation anti-reflection layer covers a surface of the first semiconductor doping layer and the second semiconductor doping layer on a side away from the substrate, and the back passivation anti-reflection layer includes the first material layer.
[0026] Optionally, the manufacturing method comprises:
[0027] forming a second tunneling layer, a second semiconductor intrinsic layer and a phosphosilicate glass layer in sequence on the back side of the substrate;
[0028] Laser processing the phosphosilicate glass layer, so that phosphorus ions in the phosphosilicate glass layer diffuse into the second semiconductor intrinsic layer to form a second semiconductor doped layer;
[0029] Etching and removing the phosphosilicate glass layer, the second semiconductor doping layer and the second tunneling layer outside the second region to expose the back side of the first region;
[0030] forming a first tunneling layer, a first semiconductor intrinsic layer and a first material layer in sequence on the back side of the substrate;
[0031] Annealing the first material layer and the first semiconductor intrinsic layer under a first temperature condition to form a first semiconductor doping layer;
[0032] Etching and removing the first material layer, the first semiconductor intrinsic layer, and the first tunneling layer outside the first region;
[0033] A back passivation anti-reflection layer is formed, wherein the back passivation anti-reflection layer covers a surface of the first semiconductor doping layer and the second semiconductor doping layer which is away from the substrate.
[0034] Optionally, the manufacturing method comprises:
[0035] forming a tunneling layer and the first semiconductor intrinsic layer in sequence on the back side of the substrate;
[0036] forming a phosphosilicate glass layer, wherein the phosphosilicate glass layer covers the first semiconductor intrinsic layer in the second region;
[0037] Laser processing the phosphosilicate glass layer, so that phosphorus ions in the phosphosilicate glass layer diffuse into the first semiconductor intrinsic layer, and form a second semiconductor doping layer in the second region;
[0038] forming a first material layer, wherein the first material layer covers the first semiconductor intrinsic layer in the first region;
[0039] Annealing the first material layer and the first semiconductor intrinsic layer under a first temperature condition to form the first semiconductor doping layer in the first region;
[0040] Etching and removing the first semiconductor intrinsic layer and the tunneling layer outside the first region and the second region;
[0041] A back passivation anti-reflection layer is formed, wherein the back passivation anti-reflection layer covers a surface of the first semiconductor doping layer and the second semiconductor doping layer which is away from the substrate.
[0042] In a second aspect, the present disclosure provides a back-contact battery, comprising:
[0043] substrate;
[0044] A first semiconductor doping layer, disposed on the back side of the substrate, wherein the first semiconductor doping layer is doped with aluminum;
[0045] A second semiconductor doping layer is provided on the back side of the substrate, the first semiconductor doping layer and the second semiconductor doping layer are alternately arranged on the back side of the substrate, and the second semiconductor doping layer is doped with N-type conductive type doping ions;
[0046] A back-side passivation anti-reflection layer, covering a surface of the first semiconductor doping layer and the second semiconductor doping layer away from the substrate;
[0047] A first gate line is disposed on a side of the back passivation anti-reflection layer away from the first semiconductor doping layer, at least a portion of the first gate line penetrates the back passivation anti-reflection layer and contacts the first semiconductor doping layer, and a material of the first gate line includes aluminum;
[0048] The second gate line is arranged on a side of the back passivation anti-reflection layer away from the second semiconductor doping layer, and at least a portion of the second gate line penetrates the back passivation anti-reflection layer and contacts the second semiconductor doping layer.
[0049] In a third aspect, the present disclosure provides a photovoltaic module, including a back-contact cell obtained by the method for manufacturing a back-contact cell as described in the first aspect, or including the back-contact cell as described in the second aspect.
[0050] In the back-contact cell and its manufacturing method, and photovoltaic module disclosed in the present invention, the P region uses aluminum doping to manufacture the first semiconductor doping layer to replace the traditional phosphorus-doped semiconductor layer. The aluminum doping source can form the first semiconductor doping layer under low-temperature annealing conditions, which has low equipment requirements and can effectively reduce production costs. Low-temperature manufacturing can also reduce heat loss and deformation of materials, and improve the stability and controllability of the manufacturing process; aluminum doping changes the energy band structure of the semiconductor, and the passivation performance of the first semiconductor doping layer is better; at the same time, this embodiment uses a conductive paste containing aluminum elements to manufacture the first gate line, which can reduce the contact resistance between the first gate line and the first semiconductor doping layer and improve the conductivity of the P region, which is beneficial to improving the photoelectric conversion efficiency of the back-contact cell. BRIEF DESCRIPTION OF THE DRAWINGS
[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0052] Figure 1 is a process flow chart of a method for manufacturing a back contact battery provided in one embodiment;
[0053] Figure 2 A schematic diagram of a structure from forming a second semiconductor doping layer in a second region to forming a first semiconductor intrinsic layer in a first region provided in an embodiment;
[0054] Figure 3 It is a schematic diagram of a structure of forming a first material layer, forming a first semiconductor doping layer, forming a first gate line, and a second gate line provided in an embodiment;
[0055] Figure 4 A schematic diagram of a structure from forming a second semiconductor doping layer in the second region to forming a first semiconductor doping layer on the back side provided in another embodiment;
[0056] Figure 5 A schematic diagram of a structure in which the first material layer, the first semiconductor doping layer and the first tunneling layer outside the first region are removed by etching to form a first gate line and a second gate line provided in another embodiment;
[0057] Figure 6 A schematic diagram of a structure from forming a first semiconductor intrinsic layer to forming a first material layer in a first region provided in another embodiment;
[0058] Figure 7 A schematic diagram of a structure from forming a first semiconductor doping layer in a first region to forming a first gate line and a second gate line provided in another embodiment;
[0059] Figure 8 A schematic diagram of the structure of a back contact battery provided in one embodiment;
[0060] Fig. 9 A schematic diagram of the structure of a back contact battery provided in another embodiment.
[0061] Description of reference numerals:
[0062] 10. substrate; 10a. front side; 10b. back side; 11. tunneling layer; 111. first tunneling layer; 211. second tunneling layer; 121. first semiconductor intrinsic layer; 131. first semiconductor doped layer; 141. first gate line; 150. back side passivation anti-reflection layer; 151. first passivation anti-reflection layer; 152. second passivation anti-reflection layer; 221. second semiconductor intrinsic layer; 231. second semiconductor doped layer; 241. second gate line; 250. front side passivation anti-reflection layer; 251. third passivation anti-reflection layer; 252. fourth passivation anti-reflection layer; 20. first material layer; 40. phosphosilicate glass layer; A1. first region; A2. second region. DETAILED DESCRIPTION
[0063] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0064] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0065] The inventor of the present application has found through research that the P-region process of the TBC battery uses a phosphorus-doped semiconductor layer. In the relevant scheme, a low pressure chemical vapor deposition process (LPCVD) is usually used to deposit a tunneling oxide layer and an amorphous silicon layer, and then the amorphous silicon layer is doped by phosphorus diffusion to obtain a phosphorus-doped semiconductor layer in the P region, or a plasma enhanced chemical vapor deposition process (PECVD) is used to make a tunneling oxide layer and an in-situ doped phosphorus-doped semiconductor layer. However, the process temperatures of phosphorus diffusion doping amorphous silicon layer and PECVD to make in-situ doped phosphorus-doped semiconductor layer are both greater than 900°C, which has high requirements on equipment. High temperature easily leads to damage to the life of the furnace tube and high production costs.
[0066] According to an exemplary embodiment, the present disclosure provides a method for manufacturing a back contact battery, such as Figure 1 As shown, the method for manufacturing a back contact battery comprises the following steps:
[0067] Step S10: providing a substrate 10;
[0068] Step S20: forming a first semiconductor intrinsic layer 121 on the back side 10 b of the substrate 10 ;
[0069] Step S30: forming a first material layer 20 on a side of the first semiconductor intrinsic layer 121 away from the substrate 10, wherein the first material layer 20 includes aluminum elements;
[0070] Step S40: annealing the first material layer 20 and the first semiconductor intrinsic layer 121 at a first temperature, so that the aluminum element in the first material layer 20 diffuses into the first semiconductor intrinsic layer 121 to form a first semiconductor doping layer 131, and the first temperature ranges from 200° C. to 600° C.;
[0071] Step S50 : printing a conductive paste containing aluminum element on a side of the first semiconductor doping layer 131 away from the substrate 10 to form a first gate line 141 , wherein the first gate line 141 is connected to the first semiconductor doping layer 131 .
[0072] In the manufacturing method of the back contact battery of this embodiment, the P region adopts aluminum doping to manufacture the first semiconductor doping layer 131 to replace the traditional phosphorus doped semiconductor layer. The aluminum doping source can form the first semiconductor doping layer 131 under the condition of low temperature annealing, which has low equipment requirements and can effectively reduce the production cost. The low temperature manufacturing can also reduce the heat loss and deformation of the material, and improve the stability and controllability of the manufacturing process; aluminum doping changes the energy band structure of the semiconductor, the minority carrier (electron) lifetime of the first semiconductor doping layer 131 is about 5000us, while the minority carrier (electron) lifetime of the boron doped semiconductor layer is about 3000us, and the passivation performance of the first semiconductor doping layer 131 is better; at the same time, this embodiment adopts a conductive paste containing aluminum element to manufacture the first gate line 141, which can reduce the contact resistance between the first gate line 141 and the first semiconductor doping layer 131, improve the conductivity of the P region, and is beneficial to improving the photoelectric conversion efficiency of the back contact battery.
[0073] In step S10, referring to Figure 2 , Figure 3 , or refer to Figure 4 , Figure 5 , or refer to Figure 6 , Figure 7 As shown, the substrate 10 may be a silicon substrate, a germanium substrate or a sapphire substrate, etc. The substrate includes a front side and a back side arranged opposite to each other. The substrate may be an N-type semiconductor substrate or a P-type semiconductor substrate. The N-type semiconductor substrate is doped with an N-type doping element, and the N-type doping element may be any one of the V-group elements such as phosphorus (P), bismuth (Bi), antimony (Sb) or arsenic (As). The P-type semiconductor substrate is doped with a P-type element, and the P-type doping element may be any one of the III-group elements such as boron (B), aluminum (Al), gallium (Ga) or indium (In).
[0074] In some embodiments, the back side 10b of the substrate 10 is polished to remove the damaged layer on the back side 10b of the substrate 10, and a pyramid structure is formed on the front side 10a of the substrate 10 to increase the photoelectric conversion area of the back contact cell, which is beneficial to improving the photoelectric conversion efficiency of the back contact cell.
[0075] In step S20, referring to Figure 2 , Figure 3 , or refer to Figure 4 , Figure 5 , or refer to Figure 6 , Figure 7 As shown, before forming the first semiconductor intrinsic layer 121 on the back side 10b of the substrate 10, the substrate 10 may be oxidized by wet oxidation or thermal oxidation technology to form a tunneling layer 11 on the back side 10b of the substrate 10. The first tunneling layer 111 is specifically a silicon oxide layer.
[0076] Then, an atomic layer deposition process (ALD) or a chemical vapor deposition process (CVD) may be used to deposit a first semiconductor intrinsic layer 121 on a side of the tunneling layer 11 away from the substrate 10. In this embodiment, the first semiconductor intrinsic layer 121 includes poly.
[0077] In this embodiment, alternating first regions A1 and second regions A2 are defined on the back side 10b of the substrate 10, the first regions A1 being P regions, and the second regions A2 being N regions. In some examples, the tunneling layer 11 and the first semiconductor intrinsic layer 121 only cover the first regions A1 of the substrate 10; in other examples, the tunneling layer 11 and the first semiconductor intrinsic layer 121 cover the entire back side 10b of the substrate 10.
[0078] In step S30, referring to Figure 2 , Figure 3 , or refer to Figure 4 , Figure 5 , or refer to Figure 6 , Figure 7 As shown, ALD or CVD may be used to deposit and form the first material layer 20 on a side of the first semiconductor intrinsic layer 121 away from the tunneling layer 11 , and the first material layer 20 includes aluminum.
[0079] In this embodiment, the material of the first material layer 20 may include aluminum oxide.
[0080] In some examples, a mask may be used to allow the first material layer 20 to grow only in the first region A1 and cover the first semiconductor intrinsic layer 121 in the first region A1 ; in other examples, the first material layer 20 may completely cover the first semiconductor intrinsic layer 121 on the back side 10 b of the substrate 10 .
[0081] In step S40, referring to Figure 2 , Figure 3 , or refer to Figure 4 , Figure 5 , or refer to Figure 6 , Figure 7 As shown, a thermal annealing treatment is performed on the structure after the tunneling layer 11, the first semiconductor intrinsic layer 121 and the first material layer 20 are formed. The temperature of the thermal annealing treatment is a first temperature so that the aluminum element in the first material layer 20 diffuses into the first semiconductor intrinsic layer 121 to form a first semiconductor doped layer 131 doped with aluminum. The first semiconductor doped layer 131 has a P-type conductivity type.
[0082] The first temperature ranges from 200°C to 600°C. For example, the first temperature may be 200°C, 250°C, 300°C, 350°C, 400°C, 450°C, 500°C, 550°C or 600°C.
[0083] For example, the thermal annealing process may be performed in a heating furnace tube.
[0084] In some embodiments, the first material layer 20 is formed only on one side of the first semiconductor intrinsic layer 121 in the first area A1 of the back side 10 b , and after annealing the first material layer 20 and the first semiconductor intrinsic layer 121 , the first semiconductor doping layer 131 is formed in the first area A1 .
[0085] In some other embodiments, after forming the first semiconductor doping layer 131, the first semiconductor doping layer 131 outside the first region A1 of the back side 10b is removed by etching. Only the first semiconductor doping layer 131 in the first region A1 is retained, and the first semiconductor doping layers 131 are arranged at intervals on the back side 10b of the substrate 10.
[0086] In step S50, referring to Figure 2 , Figure 3 , or refer to Figure 4 , Figure 5 , or refer to Figure 6 , Figure 7As shown, before forming the first gate line 141, a back passivation anti-reflection layer 150 is formed to cover the surface of the first semiconductor doping layer 131 away from the substrate 10. The material of the back passivation anti-reflection layer 150 can be one of silicon oxide, aluminum oxide, silicon nitride or silicon oxynitride. The back passivation anti-reflection layer 150 can be a single-layer structure or a multi-layer structure. For a multi-layer structure, the materials of different layers can be different from each other, or the materials of a part of the number of layers can be the same and different from the materials of other layers.
[0087] Conductive paste is screen-printed on one side of the back passivation anti-reflection layer 150 away from the first semiconductor intrinsic layer 121 . The conductive paste contains aluminum element. For example, the conductive paste can be aluminum paste, silver aluminum paste or aluminum copper paste.
[0088] The conductive paste is dried to form the first gate line 141 , and then the first gate line 141 is irradiated with a laser so that at least a portion of the first gate line 141 penetrates the back passivation anti-reflection layer 150 to directly contact and connect with the first semiconductor doping layer 131 .
[0089] In this embodiment, aluminum doping is used to form the first semiconductor doping layer 131, and a conductive paste containing aluminum elements is used to make the first gate line 141. Both the first semiconductor doping layer 131 and the first gate line 141 contain aluminum elements, which can reduce the contact resistance between the first semiconductor doping layer 131 and the first gate line 141, improve the overall performance of the back contact battery, and help improve the photoelectric conversion efficiency.
[0090] In some embodiments, reference Figure 2 , Figure 3 , or refer to Figure 4 , Figure 5 , or refer to Figure 6 , Figure 7 As shown, the manufacturing method also includes:
[0091] Step S60: A second semiconductor doping layer 231 is formed in the second area A2 between the first areas A1, the first semiconductor doping layer 131 and the second semiconductor doping layer 231 are alternately arranged on the back side 10b of the substrate 10, and the second semiconductor doping layer 231 is doped with N-type conductive type doping ions. The second semiconductor doping layer 231 is doped with N-type conductive ions, such as phosphorus ions.
[0092] A semiconductor intrinsic layer and a phosphosilicate glass layer 40 may be sequentially formed on the back surface 10 b of the substrate 10 , and the phosphosilicate glass layer 40 is irradiated with laser to dope the semiconductor intrinsic layer to form a second semiconductor doping layer 231 .
[0093] Specifically, the step of forming the second semiconductor doping layer 231 can be performed before forming the first semiconductor intrinsic layer 121, or, after forming the first semiconductor intrinsic layer 121 and before forming the first material layer 20, the first semiconductor intrinsic layer 121 in the second area A2 is doped to form the second semiconductor doping layer 231.
[0094] In some embodiments, the first region A1 and the second region A2 are spaced apart on the back side 10b of the substrate 10. After alternating first semiconductor doping layers 131 and second semiconductor doping layers 231 are respectively formed on the back side 10b of the substrate 10, the film layer between the first region A1 and the second region A2 is etched to expose the back side 10b of the substrate 10 between the first region A1 and the second region A2, so that the adjacent first semiconductor doping layers 131 and second semiconductor doping layers 231 are disconnected, which is beneficial to reduce leakage of the back contact battery and reduce hot spot problems.
[0095] In some embodiments, reference Figure 2 , Figure 3 , or refer to Figure 4 , Figure 5 , or refer to Figure 6 , Figure 7 As shown, the manufacturing method also includes:
[0096] Step S70: forming a back passivation anti-reflection layer 150, wherein the back passivation anti-reflection layer 150 covers the surface of the first semiconductor doping layer 131 and the second semiconductor doping layer 231 on the side away from the substrate 10; wherein the first gate line 141 is formed on the side of the back passivation anti-reflection layer 150 away from the first semiconductor doping layer 131, and at least a portion of the first gate line 141 penetrates the back passivation anti-reflection layer 150 and contacts the first semiconductor doping layer 131.
[0097] ALD or CVD deposition can be used to form the back passivation anti-reflection layer 150. For example, the back passivation anti-reflection layer 150 can be a multilayer structure of a silicon nitride layer and an aluminum oxide layer. In this way, the back passivation anti-reflection layer 150 has high light transmittance, taking into account the passivation effect and light transmittance of the back contact cell, which is conducive to improving the photoelectric conversion efficiency of the back contact cell and improving the cell performance.
[0098] In this embodiment, the back passivation anti-reflection layer 150 includes a first passivation anti-reflection layer 151 and a second passivation anti-reflection layer 152 sequentially stacked on the back side 10b, wherein the first passivation anti-reflection layer 151 is a silicon oxide layer, and the second passivation anti-reflection layer 152 is an aluminum oxide layer.
[0099] In some embodiments, the first material layer 20 is an aluminum oxide layer, and after forming the first semiconductor doping layer 131, the first material layer 20 is retained as a back passivation anti-reflection layer 150. The back passivation anti-reflection layer 150 includes the first material layer 20 and the second passivation anti-reflection layer 152 sequentially stacked on the back side 10b. In some other embodiments, after forming the first semiconductor doping layer 131, the first material layer 20 can be etched and removed.
[0100] In some embodiments, reference Figure 2 , Figure 3 , or refer to Figure 4 , Figure 5 , or refer to Figure 6 , Figure 7 As shown, the manufacturing method also includes:
[0101] Step S80 : forming a second gate line 241 on a side of the back passivation anti-reflection layer 150 away from the second semiconductor doping layer 231 , wherein at least a portion of the second gate line 241 penetrates the back passivation anti-reflection layer 150 and contacts the second semiconductor doping layer 231 .
[0102] Conductive paste is screen-printed on one side of the back passivation anti-reflection layer 150 away from the second semiconductor doping layer 231 to form a second gate line 241. After the conductive paste is dried, laser irradiation is performed to form a second gate line 241 that penetrates at least a portion of the back passivation anti-reflection layer 150, and the second gate line 241 contacts the second semiconductor doping layer 231. In this embodiment, silver paste is used to form the second gate line 241 to reduce the contact resistance between the second gate line 241 and the second semiconductor doping layer 231, thereby improving the overall performance of the back contact battery.
[0103] In other embodiments, in order to save process steps and manufacturing costs, the conductive paste used to make the second gate line 241 can be the same conductive paste used to make the first gate line 141, such as aluminum paste, silver aluminum paste or aluminum copper paste.
[0104] In some embodiments, reference Figure 2 , Figure 3 , or refer to Figure 4 , Figure 5 , or refer to Figure 6 , Figure 7As shown, the manufacturing method also includes etching to remove the film layer deposited on the front side 10a of the substrate 10, exposing the front side 10a of the substrate 10, and depositing a front passivation anti-reflection layer 250 on the front side 10a of the substrate 10. The material of the front passivation anti-reflection layer 250 can be one of silicon oxide, aluminum oxide, silicon nitride or silicon oxynitride. The front passivation anti-reflection layer 250 can be a single-layer structure or a multi-layer structure. For example, the front passivation anti-reflection layer 250 can include a stacked third passivation anti-reflection layer 251 and a fourth passivation anti-reflection layer 252, the third passivation anti-reflection layer 251 is a silicon oxide layer, and the fourth passivation anti-reflection layer 252 is a silicon nitride layer. In this way, it is beneficial to improve the photoelectric conversion efficiency of the back contact battery and improve the battery performance.
[0105] Based on the description of the above embodiments, more specific embodiments are proposed below for detailed description.
[0106] According to an exemplary embodiment, this exemplary embodiment provides a method for manufacturing a back-contact battery. The process of the method for manufacturing a back-contact battery of this exemplary embodiment is as follows: Figure 2 , Figure 3 The method for manufacturing a back contact battery of this exemplary embodiment includes the following steps:
[0107] Step S101: providing a substrate 10; in this embodiment, the substrate 10 is a silicon substrate, and the substrate 10 has a P-type conductivity;
[0108] Step S102: forming a second tunneling layer 211, a second semiconductor intrinsic layer 221 and a phosphosilicate glass layer 40 in sequence on the back side 10b of the substrate 10; in this embodiment, the second tunneling layer 211 is a silicon oxide layer, and the second semiconductor intrinsic layer 221 is a poly layer.
[0109] Step S103: laser processing the phosphosilicate glass layer 40, so that phosphorus ions in the phosphosilicate glass layer 40 diffuse into the second semiconductor intrinsic layer 221, forming a second semiconductor doping layer 231;
[0110] Step S104: etching and removing the phosphosilicate glass layer 40, the second semiconductor doping layer 231 and the second tunneling layer 211 outside the second area A2 to expose the back side of the first area A1;
[0111] Step S105: A first tunneling layer 111 and a first semiconductor intrinsic layer 121 are sequentially formed on the back side 10b of the substrate 10, and the first tunneling layer 111 and the first semiconductor intrinsic layer 121 outside the first area A1 are etched and removed; wherein the first tunneling layer 111 is a silicon oxide layer, and the first semiconductor intrinsic layer 121 is a poly layer. In this embodiment, after etching the first semiconductor intrinsic layer 121 and the first tunneling layer 111, the back side 10b between the first area A1 and the second area A2 is textured to form a velvet surface, so as to increase the photoelectric conversion area of the back contact battery.
[0112] Step S106: forming a first material layer 20, the first material layer 20 covers the first semiconductor intrinsic layer 121 and the second semiconductor doping layer 231; the first material layer 20 also covers the back surface 10b between the first area A1 and the second area A2,
[0113] Step S107: annealing the first material layer 20 and the first semiconductor intrinsic layer 121 under a first temperature condition to form a first semiconductor doping layer 131; in this embodiment, the first temperature ranges from 200° C. to 600° C., and the aluminum element in the first material layer 20 diffuses into the first semiconductor intrinsic layer 121, and the first semiconductor doping layer 131 is doped with aluminum element;
[0114] Step S108: forming a back passivation anti-reflection layer 150, the back passivation anti-reflection layer 150 covers the first semiconductor doping layer 131 and the second semiconductor doping layer 231 away from the substrate 10, and the back passivation anti-reflection layer 150 includes a first material layer 20; in this embodiment, a second passivation anti-reflection layer 152 is deposited to cover the first material layer 20, and the first material layer 20 and the second passivation anti-reflection layer 152 together serve as the back passivation anti-reflection layer 150. The second passivation anti-reflection layer 152 may be a silicon nitride layer.
[0115] Step S109: forming a first gate line 141 and a second gate line 241, wherein at least a portion of the first gate line 141 penetrates the back passivation anti-reflection layer 150 and is connected to the first semiconductor doping layer 131, and at least a portion of the second gate line 241 penetrates the back passivation anti-reflection layer 150 and is in contact with the second semiconductor doping layer 231; in this embodiment, a conductive paste containing aluminum is printed on a side of the back passivation anti-reflection layer 150 away from the first semiconductor doping layer 131, and is dried to form the first gate line 141, and a laser is irradiated to the first gate line 141 so that at least a portion of the first gate line 141 penetrates the back passivation anti-reflection layer 150 and is connected to the first semiconductor doping layer 131; silver paste is printed on a side of the back passivation anti-reflection layer 150 away from the second semiconductor doping layer 231, and is dried to form the second gate line 241, and a laser is irradiated to the second gate line 241 so that at least a portion of the second gate line 241 penetrates the back passivation anti-reflection layer 150 and is in contact with the second semiconductor doping layer 231.
[0116] According to an exemplary embodiment, this exemplary embodiment provides a method for manufacturing a back-contact battery. The process of the method for manufacturing a back-contact battery of this exemplary embodiment is as follows: Figure 4 , Figure 5 The method for manufacturing a back contact battery of this exemplary embodiment includes the following steps:
[0117] Step S201: providing a substrate 10; in this embodiment, the substrate 10 is a silicon substrate, and the substrate 10 has a P-type conductivity;
[0118] Step S202: forming a second tunneling layer 211, a second semiconductor intrinsic layer 221 and a phosphosilicate glass layer 40 in sequence on the back side 10b of the substrate 10; in this embodiment, the second tunneling layer 211 is a silicon oxide layer, and the second semiconductor intrinsic layer 221 is a poly layer.
[0119] Step S203: laser processing the phosphosilicate glass layer 40, so that phosphorus ions in the phosphosilicate glass layer 40 diffuse into the second semiconductor intrinsic layer 221 to form a second semiconductor doping layer 231;
[0120] Step S204: etching and removing the phosphosilicate glass layer 40, the second semiconductor doping layer 231 and the second tunneling layer 211 outside the second area A2 to expose the back side of the first area A1;
[0121] Step S205: A first tunneling layer 111, a first semiconductor intrinsic layer 121 and a first material layer 20 are sequentially formed on the back side 10b of the substrate 10; wherein the first tunneling layer 111 is a silicon oxide layer; the first semiconductor intrinsic layer 121 is a poly layer; the first material layer 20 includes aluminum elements, and in this embodiment, the first material layer 20 is a silicon oxide layer.
[0122] Step S206: annealing the first material layer 10 and the first semiconductor intrinsic layer 121 under a first temperature condition to form a first semiconductor doped layer 131; the aluminum element in the first material layer 20 diffuses into the first semiconductor intrinsic layer 121 to form an aluminum-doped first semiconductor doped layer 131. In this embodiment, the first temperature ranges from 200° C. to 600° C.;
[0123] Step S207: Etching and removing the first material layer 20, the first semiconductor intrinsic layer 121 and the first tunneling layer 111 outside the first area A1; in this embodiment, after etching the first material layer 20, the first semiconductor intrinsic layer 121 and the first tunneling layer 111, the back side 10b between the first area A1 and the second area A2 is exposed, and the back side 10b between the first area A1 and the second area A2 is textured to form a velvet surface, so as to increase the photoelectric conversion area of the back contact battery.
[0124] Step S208: forming a back passivation anti-reflection layer 150, the back passivation anti-reflection layer 150 covers the first semiconductor doping layer 131, the second semiconductor doping layer 231 on the side away from the substrate 10; in this embodiment, the first passivation anti-reflection layer 151 and the second passivation anti-reflection layer 152 are sequentially deposited to form the back passivation anti-reflection layer 150, the back passivation anti-reflection layer 150 covers the surface of the first material layer 20 on the side away from the first semiconductor doping layer 131, the surface of the phosphosilicate glass layer 40 on the side away from the second semiconductor doping layer 231, and the back side 10b between the first area A1 and the second area A2. The first passivation anti-reflection layer 151 is a silicon oxide layer, and the second passivation anti-reflection layer 152 is an aluminum oxide layer.
[0125] Step S209: forming a first gate line 141 and a second gate line 241, wherein at least a portion of the first gate line 141 penetrates the back passivation anti-reflection layer 150 and is connected to the first semiconductor doping layer 131, and at least a portion of the second gate line 241 penetrates the back passivation anti-reflection layer 150 and is in contact with the second semiconductor doping layer 231. In this embodiment, an aluminum-containing paste is printed on a side of the back passivation anti-reflection layer 150 away from the first semiconductor doping layer 131, and a silver paste is printed on a side of the back passivation anti-reflection layer 150 away from the second semiconductor doping layer 231, and the conductive paste is dried to form the first gate line 141 and the second gate line 241, and a laser is irradiated on the first gate line 141 so that at least a portion of the first gate line 141 penetrates the back passivation anti-reflection layer 150 and the first material layer 20 and is connected to the first semiconductor doping layer 131, and a laser is irradiated on the second gate line 241 so that at least a portion of the second gate line 241 penetrates the back passivation anti-reflection layer 150 and the phosphosilicate glass layer 40 and is in contact with the second semiconductor doping layer 231.
[0126] According to an exemplary embodiment, this exemplary embodiment provides a method for manufacturing a back-contact battery. The process of the method for manufacturing a back-contact battery of this exemplary embodiment is as follows: Figure 6 , Figure 7 The method for manufacturing a back contact battery of this exemplary embodiment includes the following steps:
[0127] Step S301: providing a substrate 10; in this embodiment, the substrate 10 is a silicon substrate, and the substrate 10 has a P-type conductivity;
[0128] Step S302: forming a tunneling layer 11 and a first semiconductor intrinsic layer 121 in sequence on the back side 10 b of the substrate 10 ; in this embodiment, the tunneling layer 11 is a silicon oxide layer, and the first semiconductor intrinsic layer 121 is a poly layer.
[0129] Step S303: forming a phosphosilicate glass layer 40, the phosphosilicate glass layer 40 covers the first semiconductor intrinsic layer 121 in the second area A2; in this embodiment, a mask layer may be formed on the side of the first semiconductor intrinsic layer 121 away from the substrate 10, the mask layer covers the first semiconductor intrinsic layer 121 in the first area A1 and exposes the first semiconductor intrinsic layer 121 in the second area A2. Then, the phosphosilicate glass layer 40 is deposited, the phosphosilicate glass layer 40 covers the first semiconductor intrinsic layer 121 in the second area A2.
[0130] Step S304: laser processing the phosphosilicate glass layer 40, so that phosphorus ions in the phosphosilicate glass layer 40 diffuse into the first semiconductor intrinsic layer 121, and form a second semiconductor doping layer 231 in the second area A2;
[0131] Step S305: forming a first material layer 20, the first material layer 20 covers the first semiconductor intrinsic layer 121 in the first area A1; the first material layer 20 includes aluminum elements; in this embodiment, the first material layer 20 is a silicon oxide layer;
[0132] Step S306: annealing the first material layer 20 and the first semiconductor intrinsic layer 121 at a first temperature to form a first semiconductor doped layer 131 in the first region A1; in this embodiment, the first material layer 20 and the first semiconductor intrinsic layer 121 are annealed at the first temperature to diffuse the aluminum element in the first material layer 20 into the first semiconductor intrinsic layer 121 to form an aluminum-doped first semiconductor doped layer 131, and the first temperature ranges from 200° C. to 600° C.;
[0133] Step S307: etching and removing the first semiconductor intrinsic layer 121 and the tunneling layer 11 outside the first area A1 and the second area A2; in this embodiment, the back surface 10b between the first area A1 and the second area A2 is textured to form a textured surface to increase the photoelectric conversion area of the back contact battery.
[0134] Step S308: forming a back passivation anti-reflection layer 150, the back passivation anti-reflection layer 150 covers the surface of the first semiconductor doping layer 131 and the second semiconductor doping layer 231 away from the substrate 10; in this embodiment, the back passivation anti-reflection layer 150 includes a stacked silicon nitride layer and an aluminum oxide layer; in this embodiment, the back passivation anti-reflection layer 150 includes a first passivation anti-reflection layer 151 and a second passivation anti-reflection layer 152, the first passivation anti-reflection layer 151 is a silicon oxide layer, and the second passivation anti-reflection layer 152 is an aluminum oxide layer.
[0135] Step S309: forming a first gate line 141 and a second gate line 241, wherein at least a portion of the first gate line 141 penetrates the back passivation anti-reflection layer 150 and is connected to the first semiconductor doping layer 131, and at least a portion of the second gate line 241 penetrates the back passivation anti-reflection layer 150 and is in contact with the second semiconductor doping layer 231. In this embodiment, at least a portion of the first gate line 141 penetrates the back passivation anti-reflection layer 150 and the first material layer and is connected to the first semiconductor doping layer 131, and at least a portion of the second gate line 241 penetrates the back passivation anti-reflection layer 150 and the phosphosilicate glass layer 40 and is in contact with the second semiconductor doping layer 231.
[0136] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.
[0137] According to an exemplary embodiment, a back contact battery is provided. Figure 8 , Fig. 9As shown, the back contact battery includes a substrate 10, a first semiconductor doping layer 131, a second semiconductor doping layer 231, a back passivation anti-reflection layer 150, a first gate line 141 and a second gate line 241; the first semiconductor doping layer 131 is arranged on the back side 10b of the substrate 10, and the first semiconductor doping layer 131 is doped with aluminum; the second semiconductor doping layer 231 is arranged on the back side 10b of the substrate 10, the first semiconductor doping layer 131 and the second semiconductor doping layer 231 are alternately arranged on the back side 10b of the substrate 10, and the second semiconductor doping layer 231 is doped with N-type conductive type doping ions; the back passivation anti-reflection layer 150 is 50 covers the surface of the first semiconductor doping layer 131 and the second semiconductor doping layer 231 away from the substrate 10; the first gate line 141 is arranged on the side of the back passivation anti-reflection layer 150 away from the first semiconductor doping layer 131, at least a part of the first gate line 141 penetrates the back passivation anti-reflection layer 150 and contacts the first semiconductor doping layer 131, and the material of the first gate line 141 includes aluminum; the second gate line 241 is arranged on the side of the back passivation anti-reflection layer 150 away from the second semiconductor doping layer 231, at least a part of the second gate line 241 penetrates the back passivation anti-reflection layer 150 and contacts the second semiconductor doping layer 231. The material of the first gate line 141 may include aluminum material, silver-aluminum material, aluminum-copper material, etc.
[0138] In the back contact battery of the present embodiment, the P region adopts an aluminum-doped first semiconductor doping layer 131 to replace the traditional phosphorus-doped semiconductor layer. The first semiconductor doping layer 131 is manufactured under low-temperature annealing conditions, which has low equipment requirements and can effectively reduce production costs. Low-temperature manufacturing can also reduce heat loss and deformation of materials, and improve the product yield and structural stability of the back contact battery; the minority carrier (electron) lifetime of the first semiconductor doping layer 131 is about 5000us, while the minority carrier (electron) lifetime of the boron-doped semiconductor layer is about 3000us, and the passivation performance of the first semiconductor doping layer 131 is better; at the same time, the first gate line 141 includes a conductive paste containing aluminum elements, which can reduce the contact resistance between the first gate line 141 and the first semiconductor doping layer 131 and improve the conductivity of the P region, which is beneficial to improving the photoelectric conversion efficiency of the back contact battery.
[0139] In some embodiments, the second semiconductor doping layer 231 may be doped with phosphorus ions.
[0140] The back passivation anti-reflection layer 150 can be a multilayer structure of a silicon nitride layer and an aluminum oxide layer. In this way, the back passivation anti-reflection layer 150 has high light transmittance, taking into account the passivation effect and light transmittance of the back contact cell, which is beneficial to improving the photoelectric conversion efficiency of the back contact cell and improving the cell performance.
[0141] In one example, if Figure 8As shown, the back passivation anti-reflection layer 150 includes a first material layer 20 and a second passivation anti-reflection layer 152 sequentially stacked on the back side 10b. The first material layer 20 is an aluminum oxide layer, which is a doping source layer for making the first semiconductor doping layer 131, and the second passivation anti-reflection layer 152 is a silicon oxide layer or a silicon nitride layer.
[0142] In another example, Fig. 9 As shown, the back passivation anti-reflection layer 150 includes a first passivation anti-reflection layer 151 and a second passivation anti-reflection layer 152 sequentially stacked on the back surface 10b. The first passivation anti-reflection layer 151 is a silicon oxide layer, and the second passivation anti-reflection layer 152 is an aluminum oxide layer.
[0143] In some examples, such as Fig. 9 As shown, a first material layer 20 is further disposed between the first semiconductor doping layer 131 and the back passivation anti-reflection layer 150, and the first material layer 20 is an aluminum oxide layer. At least a portion of the first gate line 141 penetrates the first material layer 20 and contacts the first semiconductor doping layer 131. The first material layer 20 can further enhance the passivation effect of the P region.
[0144] A phosphosilicate glass layer 40 is further disposed between the second semiconductor doping layer 231 and the back passivation anti-reflection layer 150 . At least a portion of the second gate line 241 penetrates the phosphosilicate glass layer 40 and contacts the second semiconductor doping layer 231 .
[0145] like Figure 8 , Fig. 9 As shown, the front side 10a of the substrate 10 is provided with a front passivation anti-reflection layer 250. The front passivation anti-reflection layer 250 includes a stacked silicon oxide layer and a silicon nitride layer. The front passivation anti-reflection layer 250 has high light transmittance, taking into account the passivation effect and transmittance of the back contact battery, which is beneficial to improving the photoelectric conversion efficiency of the back contact battery and improving the battery performance.
[0146] In some embodiments, Figure 8 , Fig. 9 As shown, the front side 10a of the substrate 10 has a pyramid structure to increase the light-receiving surface of the back contact cell, which is beneficial to improving the photoelectric conversion efficiency of the back contact cell.
[0147] In some embodiments, Figure 8 , Fig. 9 As shown, the back side 10 b of the substrate 10 between the first semiconductor doping layer 131 and the second semiconductor doping layer 231 has a pyramid structure, which is beneficial to improving the photoelectric conversion efficiency of the back contact cell.
[0148] According to an exemplary embodiment, a photovoltaic module is provided. The photovoltaic module includes a back-contact cell obtained by the method for manufacturing the back-contact cell in the above embodiment, or includes the back-contact cell in the above embodiment.
[0149] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0150] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.
Claims
1. A method for manufacturing a back contact battery, characterized in that: include: providing a substrate; forming a first semiconductor intrinsic layer on the back side of the substrate; forming a first material layer on a side of the first semiconductor intrinsic layer away from the substrate, wherein the first material layer includes aluminum; Annealing the first material layer and the first semiconductor intrinsic layer under a first temperature condition, so that the aluminum element in the first material layer diffuses into the first semiconductor intrinsic layer to form a first semiconductor doping layer, and the first temperature ranges from 200° C. to 600° C.; A conductive paste containing aluminum element is printed on a side of the first semiconductor doping layer away from the substrate to form a first gate line, wherein the first gate line is connected to the first semiconductor doping layer.
2. The method for manufacturing a back contact battery according to claim 1, characterized in that: The first material layer is an aluminum oxide layer.
3. The method for manufacturing a back contact battery according to claim 1, characterized in that: The first material layer is formed only on one side of the first semiconductor intrinsic layer in the first region of the back side, and after annealing the first material layer and the first semiconductor intrinsic layer, the first semiconductor doping layer is formed in the first region.
4. The method for manufacturing a back contact battery according to claim 1, characterized in that: After forming the first semiconductor doping layer, the first semiconductor doping layer except the first region on the back side is removed by etching.
5. The method for manufacturing a back contact battery according to claim 3 or 4, characterized in that: The production method further comprises: forming a second semiconductor doping layer in a second region between the first regions, the first semiconductor doping layer and the second semiconductor doping layer being alternately arranged on the back side of the substrate, and the second semiconductor doping layer being doped with N-type conductive type doping ions; A back passivation anti-reflection layer is formed, wherein the back passivation anti-reflection layer covers the first semiconductor doping layer and the second semiconductor doping layer on a side away from the substrate; wherein the first gate line is formed on a side of the back passivation anti-reflection layer away from the first semiconductor doping layer, and at least a portion of the first gate line penetrates the back passivation anti-reflection layer and contacts the first semiconductor doping layer; A second gate line is formed on a side of the back passivation anti-reflection layer away from the second semiconductor doping layer, and at least a portion of the second gate line penetrates the back passivation anti-reflection layer and contacts the second semiconductor doping layer.
6. The method for manufacturing a back contact battery according to claim 1, characterized in that: The production method comprises: forming a second tunneling layer, a second semiconductor intrinsic layer and a phosphosilicate glass layer in sequence on the back side of the substrate; Laser processing the phosphosilicate glass layer, so that phosphorus ions in the phosphosilicate glass layer diffuse into the second semiconductor intrinsic layer to form a second semiconductor doped layer; Etching and removing the phosphosilicate glass layer, the second semiconductor doping layer and the second tunneling layer outside the second region to expose the back side of the first region; forming a first tunneling layer and the first semiconductor intrinsic layer in sequence on the back side of the substrate, and etching and removing the first tunneling layer and the first semiconductor intrinsic layer outside the first region; forming the first material layer, wherein the first material layer covers the first semiconductor intrinsic layer and the second semiconductor doping layer; Annealing the first material layer and the first semiconductor intrinsic layer under a first temperature condition to form the first semiconductor doping layer; A back passivation anti-reflection layer is formed, wherein the back passivation anti-reflection layer covers a surface of the first semiconductor doping layer and the second semiconductor doping layer on a side away from the substrate, and the back passivation anti-reflection layer includes the first material layer.
7. The method for manufacturing a back contact battery according to claim 1, characterized in that: The production method comprises: forming a second tunneling layer, a second semiconductor intrinsic layer and a phosphosilicate glass layer in sequence on the back side of the substrate; Laser processing the phosphosilicate glass layer, so that phosphorus ions in the phosphosilicate glass layer diffuse into the second semiconductor intrinsic layer to form a second semiconductor doped layer; Etching and removing the phosphosilicate glass layer, the second semiconductor doping layer and the second tunneling layer outside the second region to expose the back side of the first region; forming a first tunneling layer, a first semiconductor intrinsic layer and a first material layer in sequence on the back side of the substrate; Annealing the first material layer and the first semiconductor intrinsic layer under a first temperature condition to form a first semiconductor doping layer; Etching and removing the first material layer, the first semiconductor intrinsic layer, and the first tunneling layer outside the first region; A back passivation anti-reflection layer is formed, wherein the back passivation anti-reflection layer covers a surface of the first semiconductor doping layer and the second semiconductor doping layer which is away from the substrate.
8. The method for manufacturing a back contact battery according to claim 1, characterized in that: The production method comprises: forming a tunneling layer and the first semiconductor intrinsic layer in sequence on the back side of the substrate; forming a phosphosilicate glass layer, wherein the phosphosilicate glass layer covers the first semiconductor intrinsic layer in the second region; Laser processing the phosphosilicate glass layer, so that phosphorus ions in the phosphosilicate glass layer diffuse into the first semiconductor intrinsic layer, and form a second semiconductor doping layer in the second region; forming a first material layer, wherein the first material layer covers the first semiconductor intrinsic layer in the first region; Annealing the first material layer and the first semiconductor intrinsic layer under a first temperature condition to form the first semiconductor doping layer in the first region; Etching and removing the first semiconductor intrinsic layer and the tunneling layer outside the first region and the second region; A back passivation anti-reflection layer is formed, wherein the back passivation anti-reflection layer covers a surface of the first semiconductor doping layer and the second semiconductor doping layer which is away from the substrate.
9. A back contact battery, characterized in that: include: substrate; A first semiconductor doping layer, disposed on the back side of the substrate, wherein the first semiconductor doping layer is doped with aluminum; A second semiconductor doping layer is provided on the back side of the substrate, the first semiconductor doping layer and the second semiconductor doping layer are alternately arranged on the back side of the substrate, and the second semiconductor doping layer is doped with N-type conductive type doping ions; A back-side passivation anti-reflection layer, covering a surface of the first semiconductor doping layer and the second semiconductor doping layer away from the substrate; A first gate line is disposed on a side of the back passivation anti-reflection layer away from the first semiconductor doping layer, at least a portion of the first gate line penetrates the back passivation anti-reflection layer and contacts the first semiconductor doping layer, and a material of the first gate line includes aluminum; The second gate line is arranged on a side of the back passivation anti-reflection layer away from the second semiconductor doping layer, and at least a portion of the second gate line penetrates the back passivation anti-reflection layer and contacts the second semiconductor doping layer.
10. A photovoltaic module, characterized in that: A back contact battery obtained by the method for manufacturing a back contact battery as described in any one of claims 1 to 8, or a back contact battery as described in claim 9.