Dual in-line power module

Abstract

A power module is provided with a substrate, a power device and a housing. The power device is mounted on a device pad of the substrate and is arranged to provide a power circuit having a first input, a second input and at least one output. First and second power terminals provide the first and second inputs of the power circuit. At least one output power terminal provides the at least one output. The housing encloses the substrate, the power device, and parts of the first and second input power terminals and the at least one output power terminal.

Description

[0001] Related applications

[0002] This application is based on and claims the priority benefit of U.S. Patent Application No. 17 / 736,487, filed May 4, 2022. This application claims the priority and benefit thereof, in whole or in part, of the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to power modules for high-power applications. Background Technology

[0004] In high-power applications, multiple components, either all or part of a circuit, are typically encapsulated in electronic modules. These modules, often called power modules, are housed in molded housings made of thermoplastic, epoxy, or similar materials, which encapsulate the components and the circuit board or substrate on which they are mounted. Input / output connections for the power modules are provided by terminal assemblies extending from the housing for incorporation and connection to other systems. Such systems may include electric vehicles, power conversion, and control systems. Summary of the Invention

[0005] The power module has a substrate, a power device, and a housing. The power device is mounted on device pads on the substrate and is arranged to provide a power circuit having a first input, a second input, and at least one output. First and second power terminals provide first and second inputs to the power circuit. At least one output power terminal provides at least one output. The housing surrounds the substrate, the power device, portions of the first and second input power terminals, and at least one output power terminal.

[0006] In one embodiment, a housing surrounds a substrate, a plurality of power devices, and portions thereof, including a first input power terminal, a second input power terminal, and at least one output power terminal, wherein at least one first input power terminal, at least one second input power terminal, and at least one output power terminal extend from a first side of the housing. The at least one first input power terminal may provide a first V- terminal and a second V- terminal extending from the first side of the housing. The at least one second input power terminal may provide a first V+ terminal and a second V+ terminal extending from the first side of the housing. The first V+ terminal and the second V+ terminal may be located between the first V- terminal and the second V- terminal. The at least one output power terminal may be located between the first V+ terminal and the second V+ terminal.

[0007] The at least one output power terminal may provide: a first output power terminal providing a first output of the power circuit, a second output power terminal providing a second output of the power circuit, and a third output power terminal providing a third output of the power circuit.

[0008] The plurality of signal terminals can provide multiple control signals to the power circuit, wherein portions of the plurality of signal terminals extend from a second side of the housing, the second side being opposite to its first side. The plurality of signal terminals may include a first plurality of gate signal terminals providing gate control signals to the gates of a first group of the plurality of power devices and a second plurality of gate signal terminals providing gate control signals to the gates of a second group of the plurality of power devices.

[0009] The plurality of signal terminals may further include a first plurality of source-Kelvin signal terminals providing source-Kelvin control signals to the sources of a first group of power devices, and a second plurality of source-Kelvin signal terminals providing source-Kelvin control signals to the sources of a second group of the power devices. Each of the first plurality of gate signal terminals may be adjacent to a corresponding source-Kelvin signal terminal of the first plurality of source-Kelvin signal terminals, and each of the second plurality of gate signal terminals may be adjacent to a corresponding source-Kelvin signal terminal of the second plurality of source-Kelvin signal terminals. Additional terminals may be used for various types of sensors to monitor temperature, current, voltage, etc.

[0010] The pin headers of the first and second plurality of gate terminals for adjacent pairs and the first and second pairs of source-Kelvin signal terminals may be offset from each other. Each of at least one first input power terminal, at least one second input power terminal, and at least one output power terminal may have a first pin header and a second pin header offset from the first pin header.

[0011] The substrate may provide at least one jumper pad, a first bonding line, and a second bonding line. The first bonding line may extend from at least one of a plurality of signal terminals to at least one jumper pad, and the second bonding line may extend from at least one jumper pad to a power circuit.

[0012] The at least one first input power terminal and / or the at least one second input power terminal are directly mechanically coupled to the substrate. The at least one output power terminal may not be directly mechanically coupled to the substrate, wherein a bonding wire couples the at least one output power terminal to the power circuit. At least one of the plurality of signal terminals may be directly mechanically coupled to the substrate, and at least another of the plurality of signal terminals may be directly coupled to the power circuit via a bonding wire, while the other signal terminals are not.

[0013] In the selected embodiment, thermal pads are disposed on the bottom side of the substrate, wherein the thermal pads are exposed through the housing. The power circuit is a three-phase circuit, a full-bridge circuit, a half-bridge circuit, etc. Temperature circuits may be disposed on the substrate.

[0014] The slot may be recessed into one or more sides of the housing for attaching the power module to another device. A creepage extender may be provided on at least one of the top and bottom sides of the housing. One or more slots may be provided on a first side of the housing between adjacent ones of at least one first input power terminal, at least one second input power terminal, or at least one output power terminal to reduce creepage.

[0015] In one embodiment, the power module comprises a substrate, a power device, and a housing. The power device is mounted on device pads on the substrate and is arranged to provide power circuitry having a first input, a second input, and at least one output. First and second power terminals provide first and second inputs to the power circuitry. At least one output power terminal provides at least one output. The housing surrounds portions of the substrate, the power device, the first and second input power terminals, and at least one output power terminal, wherein at least one of the at least first input power terminal and / or at least one of the at least second input power terminals is directly mechanically coupled to the substrate. At least one first input power terminal and at least one second input power terminal are directly mechanically coupled to the substrate.

[0016] At least one of the plurality of signal terminals may also be directly mechanically coupled to the substrate, and at least another of the plurality of signal terminals may be coupled to the power circuit via a bonding wire.

[0017] Based on the above, this disclosure relates to a compact, high-voltage, high-current, low-inductance power module designed for next-generation silicon carbide (SiC) and other material system power devices and power electronics applications. It utilizes a novel layout of a power substrate that combines size and cost optimization.

[0018] This design is characterized by scalability and modularity. The layout can be widened and lengthened to (1) accommodate larger devices or (2) place more devices side-by-side. Essentially, the package concept can be scaled up or down to meet power handling needs without sacrificing any performance benefits offered by the package. These packages are also arranged in direct parallel, increasing the converter current and / or forming topologies such as half-bridge and full-bridge (often used for DC-DC power conversion) and three-phase circuits (for motor drives and inverters).

[0019] After reading the following detailed description in conjunction with the accompanying drawings, those skilled in the art will understand the scope of this disclosure and implement its additional aspects. Attached Figure Description

[0020] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several aspects of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0021] Figure 1A A schematic diagram of a three-phase circuit is shown.

[0022] Figure 1B The temperature circuit is shown.

[0023] Figure 2 This is an isometric view of the top side of a power module according to a first embodiment of the present disclosure.

[0024] Figure 3 This is an isometric view of the bottom side of a power module according to a first embodiment of the present disclosure.

[0025] Figure 4 This is a top plan view of a power module according to a first embodiment of the present disclosure.

[0026] Figure 5 , Figure 6 and Figure 7 This is a corresponding side view of the power module according to the first embodiment of this disclosure.

[0027] Figure 8 This is a bottom plan view of a power module according to a first embodiment of the present disclosure.

[0028] Figure 9 , Figure 10 and Figure 11 These are a top plan view, a top isometric view, and a side plan view of a power module without a housing or bonding wires according to a first embodiment of the present disclosure.

[0029] Figure 12 , Figure 13 and Figure 14 These are a top plan view, a top isometric view, and a side plan view of a power module without a housing but having a bonding wire according to a first embodiment of the present disclosure.

[0030] Figure 15 and Figure 16 Terminal pins according to two embodiments of the present disclosure are shown.

[0031] Figure 17 and Figure 18 These are bottom plan views and bottom isometric views of a power module without a housing according to a first embodiment of the present disclosure.

[0032] Figure 19 This is an exploded view of the first embodiment of this disclosure.

[0033] Figure 20 An exemplary power circuit for a first embodiment of this disclosure is shown.

[0034] Figure 21 An exemplary signal loop according to a first embodiment of the present disclosure is shown.

[0035] Figure 22 An exemplary implementation of a power module when used with larger power devices is shown.

[0036] Figure 23 An exemplary implementation of a power module when used with smaller power devices is shown.

[0037] Figure 24 An exemplary implementation of a power module used with parallel power devices is shown.

[0038] Figure 25 An exemplary implementation of a power module is shown, in which certain available locations of power devices are not used. Detailed Implementation

[0039] The embodiments described below provide the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practice. When reading the following description in conjunction with the accompanying drawings, those skilled in the art will understand the concepts of this disclosure and will recognize that applications of these concepts are not specifically described herein. It should be understood that these concepts and applications fall within the scope of this disclosure and the appended claims.

[0040] It will be understood that while the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items.

[0041] It will be understood that when an element, such as a layer, region, or substrate, is referred to as being "on" or extending "on" another element, the element may be directly on or directly extending onto the other element, or intermediate elements may be present. Conversely, when an element is referred to as being "directly on" or "directly extending onto" another element, no intermediate elements are present. Similarly, it will be understood that when an element, such as a layer, region, or substrate, is referred to as being "on" or extending "on" another element, the element may be directly on or directly extending onto the other element, or intermediate elements may be present. Conversely, when an element is referred to as being "directly on" or "directly extending onto" another element, no intermediate elements are present. It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, the element may be directly connected to or coupled to the other element, or intermediate elements may be present. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, no intermediate elements are present.

[0042] Relative terms (such as "below" or "above" or "upper" or "lower" or "horizontal" or "vertical") may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as shown in the figures. It will be understood that these terms, and those mentioned above, are intended to include different orientations of the device other than those depicted in the figures.

[0043] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” also include the plural forms. It should be further understood that, when used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” specify the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof.

[0044] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should be further understood that terms used herein shall be interpreted as having the same meaning as they have in the context of this specification and the relevant field, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0045] This disclosure relates to power modules used in high-power applications. Power modules may comprise one or more power semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), diodes, etc., arranged in various circuit topologies. Typical circuit topologies include, but are not limited to, single-switch, half-H-bridge, full-H-bridge, and three-phase switching circuits, often referred to as six-phase packages.

[0046] For the following discussion, a three-phase circuit is used to facilitate an understanding of the packaging concepts disclosed herein. Figure 1A An exemplary three-phase circuit according to an embodiment of the present disclosure is shown. Those skilled in the art will recognize that other circuits, such as half-bridge circuits, full-bridge circuits, etc., can be used. For this example, it is assumed that transistors Q1-Q6 are power silicon carbide (SiC) MOSFETs, each having a drain (D), gate (GX), source (S), and source-Kelvin (KX) terminal. For the embodiment described below, transistors Q1-Q6 are vertical N-channel MOSFETs, wherein the drain contact is at the bottom of the device, and the source, gate, and source-Kelvin contacts are at the top of the device.

[0047] Each high-side transistor Q1, Q3, Q5 is connected in series with its corresponding low-side transistor Q2, Q4, Q6. The drain D of high-side transistors Q1, Q3, Q5 is coupled to the V+ terminal, and the source S of low-side transistors Q2, Q4, Q6 is coupled to the V- terminal. For the first branch of the three-phase circuit, the source S of high-side transistor Q1 is coupled to the drain D of low-side transistor Q2 to provide the first output, referred to as terminal U. For the second branch of the three-phase circuit, the source S of high-side transistor Q3 is coupled to the drain D of low-side transistor Q4 to provide the second output, referred to as terminal V. For the third branch of the three-phase circuit, the source S of high-side transistor Q5 is coupled to the drain D of low-side transistor Q6 to provide the third output, referred to as terminal W. Each of transistors Q1-Q6 also has independent gate terminals G1-G6 (typically GX) and source-Kelvin signal terminals K1-K6 (typically KX).

[0048] Diodes D1-D6 can be coupled between the drain and source of the corresponding transistors Q1-Q6. In each case, the anode of diodes D1-D6 is coupled to the source of the corresponding transistor Q1-Q6, and the cathode of diodes D1-D6 is coupled to the drain of the transistor Q1-Q6. Diodes D1-D6 can be standalone devices or integrated into the package of transistors Q1-Q6.

[0049] like Figure 1B As shown, additional circuitry (e.g., temperature circuitry 16 for sensing the temperature of internal devices) can be associated with a three-phase circuit and can be as simple as a thermistor, a negative temperature coefficient (NTC) device, or a resistance temperature detector (RTD) with terminals TEMP1 and TEMP2. In such an implementation, the resistance of the thermistor or RTD will change with temperature and is measurable across terminals TEMP1 and TEMP2. Thermistors will typically have a negative temperature coefficient because their resistance is negatively correlated with temperature, while RTDs will typically have a positive temperature coefficient because their resistance is positively correlated with temperature. Additional circuitry, such as current sensing, can be introduced using functional elements and dedicated pins.

[0050] Figures 2 to 8 These are different isometric views and plan views of the power module 10 according to the first embodiment, which provides for implementing different power circuits (such as...). Figure 1A and Figure 1B The electronic components required for the three-phase circuit and temperature circuit 16). Figure 2 and Figure 3 It is a top isometric view and a bottom isometric view. Figure 4 This is the top plan view. Figure 5 , Figure 6 and Figure 7 These are the side view and the end view, respectively. Figure 8 This is a bottom plan view. The power module 10 has a housing 12, which may include thermal pads 14, the thermal pads being... Figure 3 and Figures 5 to 8 As can be seen in the figures. While housing 12 can be molded as described below, other types of housings are also envisioned, such as housings having one or more manufactured or pre-formed components. Thermal pads 14 are electrically isolated from any internal circuitry and facilitate heat transfer from power module 10 to the environment, heat sink structure, etc. (not shown). Other reference features in these figures are further described below after the internal architecture of power module 10 is described.

[0051] Figures 9 to 11 Various isometric and planar views of the internal architecture of the power module 10 are shown, in which the housing 12 and the bonding line BW (or similar interconnect) are removed to show the various components of the internal architecture more clearly. Figures 12 to 14 Different isometric and planar views of the internal architecture of the power module 10 are shown, wherein the bonding line BW is positioned appropriately for an implementation of the three-phase circuit. The following description initially refers to... Figures 9 to 11 The junction line BW is not shown, and the discussion then transitions to the point where the connection provided by the junction line BW is addressed. Figures 12 to 14 The junction line BW is generally labeled, but note that the connection provided by all shown junction lines BW is clearly described. Figure 17 and Figure 18 This is a planar and isometric view of the top side of the power module 10, with the housing 12 removed.

[0052] refer to Figures 9 to 11 The core of the internal architecture is the substrate S, on which multiple conductive device pads 18, 20, 22, 24, 26, and 28 are formed. Thermal pads 14 are formed on the opposite side, as shown below. Figure 11 As best shown in the diagram. The device pads 18-28 and thermal pad 14 can be formed of any conductive material such as copper. For Figure 1A In this three-phase circuit, high-side transistors Q1, Q3, and Q5 are mounted on elongated device pads 18, which extend along the side adjacent to the power terminals V-, V+, U, V, and W. Low-side transistor Q2 is located on device pad 20. Low-side transistor Q6 is located on device pad 24. Low-side transistor Q4 is located on device pad 22. Temperature circuit 16 is located on device pad 26, which is formed on the substrate and, in this embodiment, between device pads 20 and 22. Each of device pads 18-26 is electrically isolated from the other device pads.

[0053] In one embodiment, the drain D of each transistor Q1-Q6 is directly attached to the corresponding device pads 18-24 to form a mechanical and electrical connection between the transistors Q1-Q6 and the device pads 18-24. Temperature circuit 16 can be mechanically and electrically connected to device pad 26 in a similar manner.

[0054] Each terminal can be separated into power terminals and signal terminals. As described above, the power terminals include power terminals V+, V-, U, V, and W. The signal terminals include signal terminals G1-G6, K1-K6, TEMP1, and TEMP2. While each of these terminals can take any shape required to work with the intended application, those shown are adapted to be soldered, crimped, or snapped into corresponding holes in a printed circuit board (not shown). As shown, the DC input power terminals V- and V+ and the AC output power terminals U, V, and W extend from the first side of the power module 10. The signal terminals G1-G6, K1-K6, TEMP1, and TEMP2 extend from the second side of the power module 10, wherein the first side of the power module 10 is opposite to the second side of the power module 10.

[0055] At opposite ends on the first side of the power module 10 are two power terminals V-. Each of these power terminals V- extends to the opposite end of an elongated jumper pad J9. Each power terminal V- has a pair of power pins P- and a branch L- extending from the power pins P- to the jumper pad J9. In this embodiment, the power terminals V- are directly mechanically attached to the substrate via the jumper pad J9. Most (if not all) of the branches L- of the power terminals V- are disposed together with the housing 12, wherein the power pins P- extend to the outside of the housing 12 and are rotated approximately 90 degrees toward the top side of the power module 10.

[0056] Power terminals V+ are positioned along a first side of power module 10 between power terminals V-, wherein each power terminal V+ is adjacent to a corresponding power terminal V-. Power terminals V+ extend to opposite ends of device pads 18, such that transistors Q1, Q3, Q5 and diodes D1, D3, and D5 are positioned between power terminals V+ on device pads 18. Each power terminal V+ has a pair of power pins P+ and a branch L+ extending from the power pins P+ to the device pads 18. Most (if not all) of the branches L+ of the power terminals V+ are disposed together with housing 12, wherein the power pins P+ extend to the outside of housing 12 and are rotated approximately 90 degrees toward the top side of power module 10. In this embodiment, power terminals V+ are directly and mechanically attached to the substrate via device pads 18.

[0057] Each power terminal U, V, W is located between power terminals V+ along the first side of power module 10. Each power terminal U, V, W has a pair of power pins PU, PV, PW and branches LU, LV, LW. Branches LU, LV, LW do not directly contact any pads on the substrate S. Instead, a set of bonding wires BW is used to facilitate electrical connection.

[0058] Now for reference Figures 12 to 14 This includes bonding lines BW. For the power terminal U, the first set of bonding lines BW extends from branch LU of the power terminal U to the source pad SP on top of transistor Q1 and to jumper pad J3, which is an extension of device pad 20 and electrically connected to device pad 20. The second set of bonding lines BW extends from branch LU to the anode on top of diode D1 and to jumper pad J3. In this way, the first and second sets of bonding lines BW connect the source of transistor Q1 to the drain of transistor Q2, the anode of diode D1, and the power terminal U.

[0059] For the power terminal V, the second set of bonding lines BW extends from branch LV of the power terminal V to the source pad SP on top of transistor Q3 and then to jumper pad J4, which is an extension of device pad 22 and is electrically connected to device pad 22. The second set of bonding lines BW extends from branch LU to the anode on top of diode D3 and then to jumper pad J4. Therefore, the first and second sets of bonding lines BW connect the source of transistor Q3 to the drain of transistor Q4, the anode of diode D3, and the power terminal V.

[0060] For the power terminal W, the third set of bonding lines BW extends from branch LW of the power terminal W to the source pad SP on top of transistor Q5 and then to jumper pad J6, which is an extension of device pad 24 and electrically connected to device pad 24. The second set of bonding lines BW extends from branch LU to the anode on top of diode D5 and then to jumper pad J6. Thus, the first and second sets of bonding lines BW connect the source of transistor Q5 to the drain of transistor Q6, the anode of diode D3, and the power terminal W.

[0061] Signal terminal G1 is electrically coupled to the gate pad GP of transistor Q1 via a first bonding line BW extending from signal terminal G1 to jumper pad J1 and a second bonding line BW extending from jumper pad J1 to gate pad GP of transistor Q1. The first bonding line BW is coupled to branch LG1 of signal terminal G1 at a point opposite to the point of signal pin PG1.

[0062] Signal terminal K1 is electrically coupled to the source pad SP of transistor Q1 via a first bonding line BW extending from signal terminal K1 to jumper pad J2 and a second bonding line BW extending from jumper pad J2 to source pad SP of transistor Q1. The first bonding line BW is coupled to branch LK1 of signal terminal K1 at a point opposite to the point of signal pin PK1.

[0063] Signal terminal K2 is coupled to the source pad SP of transistor Q2 via a first bonding line BW. An additional bonding line BW is used to couple the source pad SP of transistor Q2 to a jumper pad J9, which is coupled to the V- terminal. In this embodiment, these additional bonding lines BW may have an intermediate connection to the anode of diode D2, located on device pad 20, such that the cathode is electrically coupled to device pad 20. The first bonding line BW is coupled to a branch LK2 of signal terminal K2 at a point opposite to the point of signal pin PK2. Signal terminal G2 is coupled to the gate pad GP of transistor Q2 via a second bonding line BW. The second bonding line BW is coupled to a branch LG2 of signal terminal G2 at a point opposite to the point of signal pin PG2.

[0064] As shown in the figure, the temperature circuit 16 can be a vertically oriented semiconductor mounted on and electrically contacting the device pad 26. The signal terminal TEMP1 is coupled to the top contact of the temperature circuit 16 via a first bonding wire BW. The first bonding wire BW is coupled to a branch LT1 of the signal terminal TEMP1 at a point opposite to the point of the signal pin PT1. The signal terminal TEMP2 extends to and is directly coupled to the device pad 26 without using the bonding wire BW. Therefore, the signal terminal TEMP2 is directly and mechanically attached to the substrate via the device pad 26.

[0065] Signal terminal G3 extends to and is directly coupled to device pad 28 without using bonding wire BW. Therefore, signal terminal G3 is directly and mechanically attached to the substrate via device pad 28. Bonding wire is used to couple device pad 28 to the gate pad GP of transistor Q3. Signal terminal K3 is electrically coupled to the source pad SP of transistor Q3 via a first bonding wire BW extending from signal terminal K3 to jumper pad J5 and a second bonding wire BW extending from jumper pad J5 to source pad SP of transistor Q3. The first bonding wire BW is coupled to a branch LK3 of signal terminal K3 at a point opposite to the point of signal pin PK3.

[0066] Signal terminal K4 is coupled to the source pad SP of transistor Q4 via a first bonding line BW. An additional bonding line BW is used to couple the source pad SP of transistor Q4 to jumper pad J9, which is coupled to the V- terminal. In this embodiment, these additional bonding lines may have an intermediate connection to the anode of diode D4, located on device pad 22, such that the cathode is electrically coupled to device pad 22. The first bonding line BW is coupled to a branch LK4 of signal terminal K4 at a point opposite to the point of signal pin PK4. Signal terminal G4 is coupled to the gate pad GP of transistor Q4 via a second bonding line BW. The second bonding line BW is coupled to a branch LG4 of signal terminal G4 at a point opposite to the point of signal pin PG4.

[0067] Signal terminal G5 is electrically coupled to the gate pad GP of transistor Q5 via a first bonding line BW extending from signal terminal G5 to jumper pad J8 and a second bonding line BW extending from jumper pad J8 to gate pad GP of transistor Q5. The first bonding line BW is coupled to branch LG5 of signal terminal G5 at a point opposite to the point of signal pin PG5.

[0068] Signal terminal K5 is electrically coupled to the source pad SP of transistor Q5 via a first bonding line BW extending from signal terminal K5 to jumper pad J7 and a second bonding line BW extending from jumper pad J7 to source pad SP of transistor Q5. The first bonding line BW is coupled to a branch LK5 of signal terminal K5 at a point opposite to the point of signal pin PK5.

[0069] Signal terminal K6 is coupled to the source pad SP of transistor Q6 via a first bonding line BW. An additional bonding line BW is used to couple the source pad SP of transistor Q6 to jumper pad J9, which is directly coupled to the V- terminal. In this embodiment, these additional bonding lines may have an intermediate connection to the anode of diode D6, located on device pad 24, such that the cathode is electrically coupled to device pad 24. The first bonding line BW is coupled to a branch LK6 of signal terminal K6 at a point opposite to the point of signal pin PK6. Signal terminal G6 is coupled to the gate pad GP of transistor Q6 via the first bonding line BW. The first bonding line BW is coupled to a branch LG6 of signal terminal G6 at a point opposite to the point of signal pin PG6.

[0070] In the illustrated embodiment, the pins P-, P+, U, V, W of the respective power terminals V-, V+, U, V, W each have staggered double-pin headers. For higher power devices, additional power terminals may be used for power terminals V-, V+, U, V, W. The first pin header of each power terminal V-, V+, U, V, W is linearly aligned with the first pin headers of other power terminals V-, V+, U, V, W, and the second pin header of each terminal is linearly aligned with the second pin headers of other power terminals V-, V+, U, V, W.

[0071] Unlike the power terminals V-, V+, U, V, W, in the illustrated embodiment, signal terminals G1-G6, K1-K6, TEMP1, and TEMP2 are each end-capped with a single pin. Adjacent pairs of signal terminals are configured such that the pins used for these signal terminals are staggered. As shown, the pins for signal terminals G1, K2, TEMP1, K4, G3, G6, and K5 are linearly aligned with each other, while signal terminals K1, G2, TEMP2, G4, K3, K6, and G5 are linearly aligned with each other but staggered from signal terminals G1, K2, TEMP1, K4, G3, G6, and K5. Staggering is defined as falling into at least two different planes parallel to the sides of the housing 12 from which each terminal extends. In alternative embodiments, the pins may all be aligned or staggered in a manner different from that shown.

[0072] Figure 15 and Figure 16 Two exemplary pin configurations are shown for any of the various pins described above (P+, P-, PU, ​​PV, PW, PG1-PG6, PK1-PK6). Figure 15 Pin P1 has a linear body B, which narrows to become a linear head H1, which is configured to be inserted into a corresponding hole in a printed circuit board, etc., and is soldered to facilitate mechanical and electrical connection between the printed circuit board and the head H1. Figure 16 Pin P2 has a crimp head H2 at the end of linear body B. The crimp head H2 is designed to compress radially upon insertion into the corresponding hole in the printed circuit board (PCB) to provide a solderless mechanical and electrical connection between the PCB and head H1. Once inserted, the crimp head applies outward radial pressure to hold the crimp head H2 in the corresponding hole. Various crimp head styles can be used depending on the metal thickness and insertion process. For example... Figures 9 to 14 As shown, pin P1 will typically have a bend of approximately 90 degrees (i.e., 80-100 degrees). The bend is not in... Figure 15 and Figure 16 The diagram below shows the linear bodies and configurations of the heads H1 and H2 for better illustration.

[0073] like Figure 17 and Figure 18As shown, the lower surface of substrate S includes a large thermal pad 14 that covers most of substrate S and is intended to be directly attached to a heat sink, cold plate, or similar heat removal device. This attachment can be formed by bolting using a thermal interface material, metal sintering (silver, copper, or other metals), welding, conductive adhesive, fusion, or other thermally conductive attachments. Other embodiments of the design can be attached to a gap base plate in a similar manner, which can then be bolted or fused to a cooling plate.

[0074] Now for reference Figure 19 An exploded view of the power module 10. Starting from the bottom of the figure, the drain pads of transistors Q1-Q6 and the temperature circuit 16 are electrically and mechanically attached to device pads 18-26 on the substrate S using device attachment material 40. Device attachment material 40 can be solder, adhesive, sintered metal, laser welded, ultrasonic welded, etc., providing mechanical structure, high current interconnection, and high thermal conductivity. Power terminals V+, V-, U, V, W, signal terminals G1-G6, K1-K6, and temperature circuit signal terminals TEMP1, TEMP2 can be formed from a single lead frame 44. As detailed above, bonding wire BW is used to enable... Figure 1A and Figure 1B The lead frame 44 is a metal contact strip used for high-current external connections and internal interconnections. Arbitrary contacts are bonded together on a single sheet, typically with multiple products per sheet, and processed as an array before forming and splitting. The bonding wires BW can be large-diameter wires ultrasonically or thermoelectrically bonded, capable of supporting relatively high-current electrical interconnections.

[0075] The housing 12 can be formed using transfer or injection molding processes to provide mechanical structure and high voltage isolation. The housing 12 encapsulates the internal components of the power module 10. The molding compound used for the housing 12 can be a transfer or compression molding epoxy molding compound (EMC) capable of providing mechanical structure, high voltage isolation, matching coefficient of thermal expansion (CTE), and low humidity absorption.

[0076] like Figure 3 and Figure 8As shown, the thermal pads 14 on the back of the power module 10 are exposed and not covered by the housing material. During manufacturing, the epoxy resin used for the housing 12 may seep into the thermal pads 14 and leave a small amount of residue. To ensure that the molding compound or other sealant does not cover the outer surface of the thermal pads 14, press pins can be used to apply pressure to the edges or other surfaces of the substrate S to enhance the seal against the molding tool. These pins retract as the material cures and may leave traces 42 in the compound. Ejector pins are used to release the product from the mold and will also leave small marks. The number and location of the press pins and ejector pins will vary depending on the design implementation, as more or fewer of these components may be required as the width of the module varies.

[0077] Gap and creepage are critical aspects of high-voltage products. A gap is the shortest direct path through air between conductors at different voltage potentials. Creepage is the shortest direct path along a surface between them. Meeting safety standards is challenging and often inconsistent with manufacturing processes (tooling, epoxy flow, etc.) and product dimensions (coverage area and power density). For small transfer-molded packages, especially low-profile and high-voltage SiC-based products, achieving a proper balance between module size and voltage safety is essential.

[0078] For creepage, slots 46 and / or elongated edges 48 can be formed in the housing 12 to increase the surface distance between voltage nodes provided by various signal and power terminals, such as... Figure 2 , Figure 3 and Figure 4 and Figure 8 As shown in the diagram. Creepage between signal terminals G1-G6, K1-K6, power terminals V+, V-, U, V, W, and / or thermal pads 14 can be addressed in a first manner by adding elongated edges 48 and ridges to the surface of the compound or by placing elongated grooves between voltage nodes. Specific features will depend on the dimensions and voltage rating of a given embodiment of the design.

[0079] like Figure 8As shown, slots 46 can be placed between each group of adjacent signal terminals G1 / K1 to G6 / K6 and on either side of a pair of TEMP1 / TEMP2 signal terminals. Additional slots 46 can be placed between adjacent power terminals among the power terminals V1-, V+, U, V, and W. Mounting slots 52 on opposite non-terminal sides of the housing are also shown. These mounting slots 52 allow the power module 10 to be securely attached to a PCB or other structure using bolts, screws, or other fasteners. Mounting slots 52 can also serve as creepage extenders. In the illustrated embodiment, transistors Q1-Q6 are placed in a row on corresponding device pads 18, 20, 22, and 24 based on their switching positions. The overall layout, length, width, aspect ratio, and number of transistors for each switching position can be parametrically varied to amplify or reduce the desired output power of the power module 10. Transistors Q1-Q6 and any other devices may be attached by: (1) metal sintering (silver, copper, or other metals), (2) soldering, (3) conductive adhesive, or (4) other conductive and thermally conductive attachment. Depending on the sensor technology or nature of temperature circuit 16, a temperature sensor (represented by temperature circuit 16) may be included on and placed on the illustrated isolation device pad 26 or directly adjacent to one of transistors Q1-Q6. The illustrated temperature sensors are generally attached to transistors Q1-Q6 in a similar manner. Depending on the attachment method and material compatibility, the substrate metal for device pads 18-26 may be wholly or partially plated with silver, nickel, nickel / gold, or the like.

[0080] A reference can be added to aid in the automated picking and placement of transistors Q1-Q6 and / or any other included components, as well as for subsequent process steps that require determining their relative positions. References can be provided through partial plating, etched features or edges, laser-marked symbols, or other visually distinguishable features that can be recognized by a machine vision system.

[0081] Typically, power modules contain two types of electrical circuits: power circuits and signal circuits. The power circuit is a high-voltage, high-current path between the power terminals V+ and V- and through transistors Q1-Q6. It delivers power to the load via the drain (or collector) and source (or emitter) of transistors Q1-Q6, where the load is connected to the three-phase circuit terminals U, V, and W. The signal circuit is a low-voltage, low-current path through the gates G1-G6 (or bases) and sources (or emitters) of transistors Q1-Q6. The gate-source (or base-emitter) signal path actuates transistors Q1-Q6 to effectively turn them on or off. The signal circuit may also require source-Kelvin connections K1-K6 of transistors Q1-Q6.

[0082] The power circuit operates effectively between the power terminals V+ and V-. The power terminals V+ and V- are typically connected in parallel with a large capacitor across a DC power source (such as a battery). Figure 20 An exemplary power circuit for the power module 10 shown is illustrated. Figure 20 An exemplary power commutation circuit for the three-phase implementation described above is shown. The internal and external layout allows power to efficiently enter and exit the power module 10 and has effective flux cancellation. Power (1) flows in through the power terminal V+, (2) flows downward to the device pad 18 of the substrate S, (3) flows to the drain D of the high-side transistors Q1, Q3, Q5, (4) flows upward through the high-side transistors Q1, Q3, Q5 to the corresponding source pad SP, (5) flows via the bonding line BW and jumper pads J3, J4, J6 to the corresponding device pads 20, 22, 24 of the substrate S, (6) flows to the drain D of the corresponding low-side transistors Q2, Q4, Q6, (7) flows upward through the low-side transistors Q2, Q4, Q6 to the corresponding source pad SP, (8) flows via the bonding line BW to the jumper pad J9, and (9) flows directly to the power terminal V-. For each output, daisy-chained bonding wires BW are used to couple the power terminals U, V, and W to the source pads SP of the high-side transistors Q1, Q3, and Q5, respectively. For each parallel device, the loop is well balanced. The low profile, compact module size, flux cancellation, and balanced loop of power module 10 result in very low loop inductance and clean, efficient switching.

[0083] The signal loop at each transistor location preferably provides low impedance to minimize voltage stress on the device gate during switching. While these can be buffered or reduced by adding resistors, this typically comes at the cost of increased complexity, higher cost, and slower switching speeds. To improve switching performance, the power loop and signal loop can be largely (if not completely) independent of each other to achieve low switching losses with fast, well-controlled dynamic characteristics.

[0084] In some implementations, any drain-source (or collector-emitter) and gate-source (or gate-emitter) loops share the same connection at the source (or emitter) of each of the individual transistors Q1-Q6. If the power path is coupled into the signal path, additional power is introduced through positive or negative feedback. Typically, negative feedback introduces additional losses when the power path coupling conflicts with the control signal. Essentially, the power path coupling attempts to turn the transistor off while the control signal attempts to turn it on. Positive feedback typically causes instability because the power path coupling amplifies the control signal until the transistor is damaged. Ultimately, any significant coupling between the power and signal paths leads to degraded switching quality, slower switching speeds, increased losses, and potential damage.

[0085] Therefore, one way to improve switching quality is to ensure independent power and control loops. Power source connections have separate paths from signal source connections (called source Kelvin), ensuring that one does not overlap or interfere with the other. The closer the individual connections of transistors Q1-Q6 are to each other, the better the switching performance.

[0086] Figure 21 The internal signal loops for the high-side and low-side positions are shown. Here, the gate signal uses one of two general paths. The first is a through path, which is used for the signal loops associated with signal terminals G2, G4, and G6, where a single bonding wire connects the corresponding signal terminals G2, G4, and G6 to the gate pads GP of transistors Q2, Q4, and Q6. The second path uses jumpers and multiple bonding wires. Signal terminal G1 is connected to the gate pad GP via jumper pad J1 and two bonding wires. Signal terminal G5 is connected to the gate pad GP via jumper pad J8 and two bonding wires. Signal terminal G3 is slightly different in that it is directly connected to device pad 26 and bonding wire BW connects device pad 26 to the gate pad GP of transistor Q3.

[0087] The return path for the Kelvin-source signals follows a similar route. The first is a straight-through path, used for the signal loops associated with signal terminals K2, K4, and K6, where a single bonding wire connects the corresponding signal terminals K2, K4, and K6 to the source pads SP of transistors Q2, Q4, and Q6. The second path uses jumpers and multiple bonding wires. Signal terminal K1 is connected to the source pad SP via jumper pad J2 and two bonding wires. Signal terminal K3 is connected to the source pad SP via jumper pad J5 using two bonding wires. Signal terminal K5 is connected to the source pad SP via jumper pad J7 using two bonding wires.

[0088] The illustrated implementation provides a true Kelvin-source implementation where the power and signal loops are completely independent. In some implementations, transistor devices can be connected in parallel to increase the output current. When connected in parallel, further problems arise regarding transconductance mismatch between the transistor devices. Transconductance is essentially the current gain of a device—the relationship between the output current and the input voltage. During switching, the input voltage increases, resulting in a corresponding increase in the output current. If a transconductance difference exists between the paralleled transistor devices (common in silicon carbide, SiC, and power devices), they will each have slightly different conduction characteristics. With different currents flowing through each device, they will have slightly different voltages across them. This voltage mismatch will result in a 'balancing current' flowing between the devices during switching.

[0089] The balancing current will preferentially follow the path of least impedance, which can pass through the signal loop rather than the power loop. If the balancing current flows through the signal loop, it will affect the switching quality. Introducing such a high, uncontrolled current through the signal loop can also cause reliability issues, as the signal loop is not designed to carry high currents. For these parallel devices, jumper wires (BW) can be connected between their source pads (SP) to create a very low impedance path for these balancing currents.

[0090] Modularity is a beneficial feature of the concept described in this paper. For example... Figure 22 and Figure 23 As shown, within a given coverage area, transistors Q1-Q6 and / or other devices of different sizes can be combined. For a given coverage area, Figure 22 transistors Q1-Q6 compared to Figure 23 The smaller, lower-power transistors Q1-Q6 are much larger and have higher power. This flexibility allows designers to optimize device size and operating parameters for a given system and operating conditions. Because device size is typically related to the total cost of power module 10, using appropriately sized devices is key to cost reduction.

[0091] In some implementations, the substrate S can be widened to accommodate multiple parallel devices, thereby increasing power handling capability. Figure 24 and Figure 25 This shows complete filling (where all possible areas are filled) Figure 24 ) or fill down ( Figure 25 (where the selected possible locations are not filled) is an option. This is a useful technique for adjusting the device area for a given application, with the added benefit of not having to develop or manufacture new custom devices. Depending on the bonding pad layout, different device sizes, and larger or smaller numbers of parallel devices, more implementations and combinations with different device rotations are envisioned.

[0092] In addition to its high modularity, the layout of the power module 10 can be easily scaled to be as compact as possible for the required device size and count. This parametric scalability gives product designers numerous variables to adjust for streamlined thermal performance and product dimensions to achieve the desired electrical performance parameters.

[0093] As the power module 10 is scaled up or down, the internal layout is scaled accordingly. Since the current will vary based on the total device area, wider electrical paths are dynamically scaled to properly carry current without excessive resistive losses. Scaling the electrical paths helps ensure that the effective current path to each device is effectively balanced. In some cases, as the size is scaled, the width of the power terminals and the number of power connection lines can be increased or decreased as needed or desired.

[0094] The concepts disclosed herein provide an optimized three-phase package design for a next-generation power module 10. A modular layout is possible, where multiple device regions can be fully or partially filled within the same structure. A scalable layout supports multiple optimized products by simply increasing or decreasing the length and width to achieve the desired power device area and / or size. The layout can be optimized for high current by grouping power and signal terminals. Through-hole edges can be used in the power terminal regions, rather than relying on voltage isolation.

[0095] This architecture provides a logic flow of power with minimal or reduced power loop inductance, resulting in clean, efficient switching. It offers a low-inductance structure with minimal voltage overshoot to facilitate higher bus voltages and higher voltage operation. The layout also supports two or more power devices in parallel at each switching location, while providing nearly identical power loop inductance for each device.

[0096] Signal and power terminals can be arranged and organized using DC input connections (on one side), AC output connections (on the other side), and signal contacts (grouped by potential). A dual DC input terminal arrangement achieves uniform power distribution and low-inductance connections to external buses. This internal layout can be configured to minimize bonding line distances through direct bonding from the terminals to the device pads.

[0097] The concepts presented in this paper also provide options for forming electrical connections from power terminals to the power substrate via wire bonding or direct soldering. Interleaved power and signal terminals provide voltage isolation gaps between different signal and power terminals. Through-hole power and signal terminals allow for regularly spaced pin pitches for head units, PCBs, etc.

[0098] This architecture provides a true Kelvin implementation for the signal loop, resulting in clean and efficient switching. Integrated temperature sensors and similar circuitry can be placed near power devices. Temperature sensors or similar circuitry can be placed on isolated substrate traces (for non-isolated vertical sensors) or on the same traces as the devices (for laterally isolated sensors). There is an option to detect overcurrent events using an overcurrent / desaturation signal pin.

[0099] This architecture reduces costs by minimizing the number of unique components used, minimizing the area of ​​the power substrate, maximizing the utilization of the semiconductor area, and using leadframe volume handling, transfer molding, and production automation.

[0100] Power module 10 may have molded voltage creepage extenders on the top and bottom sides of the package. Power module 10 may also have power terminals configured for soldering, connection to a headstock, clamping or soldering to a wire, laser welding, or integration with press-fit contacts for solderless connections. Signal terminals may be configured for soldering, connection to a headstock, clamping or soldering to a wire, laser welding, or integration with press-fit contacts for solderless connections. Exposed thermal pads on the back of power module 10 may be configured for permanent silver sintering, copper sintering, or direct soldering to a cold plate or heat sink. Edge notches of the molding compound for housing 12 may serve as bolt holes, allowing direct, non-permanent bolting to a cold plate or heat sink using thermal interface materials, thermal gap pads, phase change materials, or the like.

[0101] The concepts provided above solve one, some, or all of the problems described above to provide a unique and novel power module 10. Those skilled in the art will recognize improvements and modifications to this disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein.

Claims

1. A power module, comprising: A substrate, the substrate including a bottom side and a top side, the top side including a plurality of device pads; Multiple power devices are mounted on multiple device pads and arranged to provide a power circuit having a first input, a second input, and at least one output, the multiple power devices including multiple high-side power devices and multiple low-side power devices; At least one first input power terminal, the at least one first input power terminal providing the first input to the power circuit; At least one second input power terminal, the at least one second input power terminal providing the second input to the power circuit; At least one output power terminal, the at least one output power terminal providing the at least one output to the power circuit; A housing for the substrate, the plurality of power devices, and the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal, wherein the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal extend from a first side of the housing; and Multiple signal terminals provide multiple control signals to the power circuit, wherein portions of the multiple signal terminals extend from a second side of the housing, the second side being opposite to the first side of the housing. The at least one first input power terminal includes a first V- terminal and a second V- terminal extending from the first side of the housing, and the at least one second input power terminal includes a first V+ terminal and a second V+ terminal extending from the first side of the housing. Wherein, the first V+ terminal and the second V+ terminal are located between the first V- terminal and the second V- terminal, and the at least one output power terminal is located between the first V+ terminal and the second V+ terminal. Furthermore, the plurality of device pads include: First device pad, on which the plurality of high-side power devices are located; Multiple second device pads, each second device pad including a low-side power device; and The third device pad, which contains a temperature circuit, is located between the two second device pads.

2. The power module of claim 1, wherein, The at least one output power terminal includes: a first output power terminal providing a first output of the power circuit, a second output power terminal providing a second output of the power circuit, and a third output power terminal providing a third output of the power circuit.

3. The power module of claim 1, wherein, The plurality of signal terminals include: a first plurality of gate signal terminals and a second plurality of gate signal terminals, wherein the first plurality of gate signal terminals provide gate control signals to the gates of a first group of the plurality of power devices, and the second plurality of gate signal terminals provide gate control signals to the gates of a second group of the plurality of power devices.

4. The power module according to claim 3, wherein, The plurality of signal terminals further includes: a first plurality of source-Kelvin signal terminals and a second plurality of source-Kelvin signal terminals, wherein the first plurality of source-Kelvin signal terminals provide source-Kelvin control signals to the sources of the first group of the plurality of power devices, and the second plurality of source-Kelvin signal terminals provide source-Kelvin control signals to the sources of the second group of the plurality of power devices.

5. The power module according to claim 4, wherein, Each of the first plurality of gate signal terminals is adjacent to a corresponding source-Kelvin signal terminal among the first plurality of source-Kelvin signal terminals, and each of the second plurality of gate signal terminals is adjacent to a corresponding source-Kelvin signal terminal among the second plurality of source-Kelvin signal terminals.

6. The power module according to claim 5, wherein, The pins of the first plurality of gate signal terminals and the second plurality of gate signal terminals are staggered from each other to the adjacent pairs of the first source-Kelvin signal terminals and the second source-Kelvin signal terminals.

7. The power module according to claim 6, wherein, Each of the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal has a first pin header and a second pin header offset from the first pin header.

8. The power module according to claim 1, wherein: The substrate includes at least one jumper pad, a first bonding line, and a second bonding line; and The first bonding line extends from at least one of the plurality of signal terminals to the at least one jumper pad, and the second bonding line extends from the at least one jumper pad to the power circuit.

9. The power module according to claim 1, wherein, The at least one first input power terminal or the at least one second input power terminal is directly mechanically coupled to the substrate.

10. The power module according to claim 1, wherein, The at least one first input power terminal and the at least one second input power terminal are directly mechanically coupled to the substrate.

11. The power module according to claim 10, wherein, The at least one output power terminal is not directly mechanically coupled to the substrate, and a bonding wire couples the at least one output power terminal to the power circuit.

12. The power module according to claim 11, wherein, At least one of the plurality of signal terminals is directly mechanically coupled to the substrate, and at least another of the plurality of signal terminals is coupled to the power circuit via a bonding wire.

13. The power module according to claim 1, wherein, At least one of the plurality of signal terminals is directly mechanically coupled to the substrate, and at least another of the plurality of signal terminals is coupled to the power circuit via a bonding wire.

14. The power module according to claim 1, further comprising: A thermal pad is located on the bottom side of the substrate, wherein the thermal pad is exposed through the housing.

15. The power module according to claim 1, wherein, The power circuit is a three-phase circuit.

16. The power module according to claim 1, wherein, The slot is recessed into one or more sides of the housing for attaching the power module to another device.

17. The power module according to claim 1, wherein, Each of the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal is end-capped with at least one linear pin, which is configured to be soldered to another device.

18. The power module according to claim 1, wherein, The creepage extender is disposed on at least one of the top side and the bottom side of the housing.

19. The power module according to claim 1, wherein, In the first side of the housing, at least one slot is disposed between adjacent ones of the at least one first input power terminal, the at least one second input power terminal, or the at least one output power terminal.

20. The power module according to claim 1, wherein, The temperature circuit is mounted on the substrate.

21. The power module according to claim 1, wherein, Each of the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal has a first pin header and a second pin header offset from the first pin header.

22. A power module, comprising: A substrate, the substrate including a bottom side and a top side, the top side having a plurality of device pads; Multiple power devices are mounted on multiple device pads and arranged to provide a power circuit having a first input, a second input, and at least one output, the multiple power devices including multiple high-side power devices and multiple low-side power devices; At least one first input power terminal, the at least one first input power terminal providing the first input to the power circuit; At least one second input power terminal, the at least one second input power terminal providing the second input to the power circuit; At least one output power terminal, the at least one output power terminal providing the at least one output to the power circuit; A housing, the housing being a portion of the substrate, the plurality of power devices, and the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal; as well as Multiple signal terminals provide multiple control signals to the power supply circuit. These signal terminals include multiple gate signal terminals and multiple source-Kelvin signal terminals. Each gate signal terminal is adjacent to a corresponding source-Kelvin signal terminal. The pins of adjacent pairs of gate and source-Kelvin signal terminals are staggered. Wherein, the at least one first input power terminal includes a first V- terminal and a second V- terminal extending from a first side of the housing, and the at least one second input power terminal includes a first V+ terminal and a second V+ terminal extending from the first side of the housing. Furthermore, the plurality of device pads include: First device pad, on which the plurality of high-side power devices are located; Multiple second device pads, each second device pad including a low-side power device; and The third device pad, which contains a temperature circuit, is located between the two second device pads.

23. The power module according to claim 22, wherein, The at least one first input power terminal and the at least one second input power terminal are directly mechanically coupled to the substrate.

24. The power module according to claim 23, wherein, The at least one output power terminal is not directly mechanically coupled to the substrate, and a bonding wire couples the at least one output power terminal to the power circuit.

25. The power module according to claim 24, wherein, At least one of the plurality of signal terminals is directly mechanically coupled to the substrate, and at least another of the plurality of signal terminals is coupled to the power circuit via a bonding wire.

26. The power module according to claim 22, wherein, The at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal extend from a first side of the housing, and portions of the plurality of signal terminals extend from a second side of the housing, the second side being opposite to the first side of the housing.

27. The power module according to claim 26, wherein, At least one of the plurality of signal terminals is directly mechanically coupled to the substrate, and at least another of the plurality of signal terminals is coupled to the power circuit via a bonding wire.

28. A power module, comprising: A substrate, the substrate including a bottom side and a top side, the top side having a plurality of device pads; Multiple power devices are mounted on multiple device pads and arranged to provide a power circuit having a first input, a second input, and at least one output, the multiple power devices including multiple high-side power devices and multiple low-side power devices; At least one first input power terminal, the at least one first input power terminal providing the first input to the power circuit; At least one second input power terminal, the at least one second input power terminal providing the second input to the power circuit; At least one output power terminal, the at least one output power terminal providing the at least one output to the power circuit; as well as A housing for the substrate, the plurality of power devices, and the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal, wherein each of the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal has a first pin and a second pin offset from the first pin. Wherein, the at least one first input power terminal includes a first V- terminal and a second V- terminal extending from a first side of the housing, and the at least one second input power terminal includes a first V+ terminal and a second V+ terminal extending from the first side of the housing. Wherein, the first pin headers of the at least one first input power terminal, the first pin headers of the at least one second input power terminal, and the first pin headers of the at least one output power terminal are linearly aligned in a first plane, and Wherein, the second pin of the at least one first input power terminal, the second pin of the at least one second input power terminal, and the second pin of the at least one output power terminal are linearly aligned in a second plane offset from the first plane. Furthermore, the plurality of device pads include: First device pad, on which the plurality of high-side power devices are located; Multiple second device pads, each second device pad including a low-side power device; and The third device pad, which contains a temperature circuit, is located between the two second device pads.

29. A power module, comprising: A substrate, the substrate including a bottom side and a top side, the top side including a plurality of device pads; Multiple power devices are mounted on multiple device pads and arranged to provide a power circuit having a first input, a second input, and at least one output, the multiple power devices including multiple high-side power devices and multiple low-side power devices; At least one first input power terminal, the at least one first input power terminal providing the first input to the power circuit; At least one second input power terminal, the at least one second input power terminal providing the second input to the power circuit; At least one output power terminal, the at least one output power terminal providing the at least one output to the power circuit; as well as A housing for the substrate, the plurality of power devices, and the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal, wherein the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal extend from a first side of the housing; The at least one first input power terminal includes a first V- terminal and a second V- terminal extending from the first side of the housing, and the at least one second input power terminal includes a first V+ terminal and a second V+ terminal extending from the first side of the housing. Wherein, the first V+ terminal and the second V+ terminal are located between the first V- terminal and the second V- terminal, and the at least one output power terminal is located between the first V+ terminal and the second V+ terminal. Furthermore, the plurality of device pads include: First device pad, on which the plurality of high-side power devices are located; Multiple second device pads, each second device pad including a low-side power device; and The third device pad, which contains a temperature circuit, is located between the two second device pads.

30. A power module, comprising: A substrate, the substrate including a bottom side and a top side, the top side including a plurality of device pads; Multiple power devices are mounted on multiple device pads and arranged to provide a power circuit having a first input, a second input, and at least one output, the multiple power devices including multiple high-side power devices and multiple low-side power devices; At least one first input power terminal, the at least one first input power terminal providing the first input to the power circuit; At least one second input power terminal, the at least one second input power terminal providing the second input to the power circuit; At least one output power terminal, the at least one output power terminal providing the at least one output to the power circuit; as well as A housing for the substrate, the plurality of power devices, and the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal, wherein the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal extend from a first side of the housing; Each of the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal has a first pin, a second pin, and a power leg extending from the first pin and the second pin. The at least one first input power terminal includes a first V- terminal and a second V- terminal extending from the first side of the housing, and the at least one second input power terminal includes a first V+ terminal and a second V+ terminal extending from the first side of the housing. Furthermore, the plurality of device pads include: First device pad, on which the plurality of high-side power devices are located; Multiple second device pads, each second device pad including a low-side power device; and The third device pad, which contains a temperature circuit, is located between the two second device pads.

31. The power module according to claim 30, wherein, For each of the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal: The second pin is offset from the first pin.

32. A power module, comprising: A substrate, the substrate including a bottom side and a top side, the top side including a plurality of device pads; Multiple power devices are mounted on multiple device pads and arranged to provide a power circuit having a first input, a second input, and at least one output, the multiple power devices including multiple high-side power devices and multiple low-side power devices; At least one first input power terminal, the at least one first input power terminal providing the first input to the power circuit; At least one second input power terminal, the at least one second input power terminal providing the second input to the power circuit; At least one output power terminal, the at least one output power terminal providing the at least one output to the power circuit; as well as A housing for the substrate, the plurality of power devices, and the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal, wherein the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal extend from a first side of the housing; Each of the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal is terminated with at least one linear pin, the at least one linear pin being configured to be soldered to another device. The at least one first input power terminal includes a first V- terminal and a second V- terminal extending from the first side of the housing, and the at least one second input power terminal includes a first V+ terminal and a second V+ terminal extending from the first side of the housing. Wherein, the first V+ terminal and the second V+ terminal are located between the first V- terminal and the second V- terminal, and the at least one output power terminal is located between the first V+ terminal and the second V+ terminal. Furthermore, the plurality of device pads include: First device pad, on which the plurality of high-side power devices are located; Multiple second device pads, each second device pad including a low-side power device; and The third device pad, which contains a temperature circuit, is located between the two second device pads.

33. A power module, comprising: A substrate, the substrate including a bottom side and a top side, the top side including a plurality of device pads; Multiple power devices are mounted on multiple device pads and arranged to provide a power circuit having a first input, a second input, and at least one output, the multiple power devices including multiple high-side power devices and multiple low-side power devices; At least two first input power terminals, wherein the at least one first input power terminal provides the first input to the power circuit; At least two second input power terminals, wherein the at least one second input power terminal provides the second input to the power circuit; At least one output power terminal, the at least one output power terminal providing the at least one output to the power circuit; as well as A housing for the substrate, the plurality of power devices, and the at least two first input power terminals, the at least two second input power terminals, and the at least one output power terminal, wherein the at least two first input power terminals, the at least two second input power terminals, and the at least one output power terminal extend from a first side of the housing; A creepage extender is provided on at least one of the top and bottom sides of the housing. Specifically, on the first side of the housing, at least one slot is disposed between adjacent ones of the at least two input power terminals, the at least two second input power terminals, and the at least one output power terminal. Each of the at least two first input power terminals, the at least two second input power terminals, and the at least one output power terminal has a first pin header and a second pin header, and The at least one first input power terminal includes a first V- terminal and a second V- terminal extending from the first side of the housing, and the at least one second input power terminal includes a first V+ terminal and a second V+ terminal extending from the first side of the housing. Furthermore, the plurality of device pads include: First device pad, on which the plurality of high-side power devices are located; Multiple second device pads, each second device pad including a low-side power device; and The third device pad, which contains a temperature circuit, is located between the two second device pads.

34. A power module, comprising: A substrate, the substrate including a bottom side and a top side, the top side including a plurality of device pads; Multiple power devices are mounted on multiple device pads and arranged to provide a power circuit having a first input, a second input, and at least one output, the multiple power devices including multiple high-side power devices and multiple low-side power devices; At least one first input power terminal, the at least one first input power terminal providing the first input to the power circuit; At least one second input power terminal, the at least one second input power terminal providing the second input to the power circuit; At least one output power terminal, the at least one output power terminal providing the at least one output to the power circuit; as well as A housing for the substrate, the plurality of power devices, and the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal, wherein the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal extend from a first side of the housing; Each of the at least one first input power terminal, the at least one second input power terminal, and the at least one output power terminal has a first pin header and a second pin header offset from the first pin header. The at least one first input power terminal includes a first V- terminal and a second V- terminal extending from the first side of the housing, and the at least one second input power terminal includes a first V+ terminal and a second V+ terminal extending from the first side of the housing. Wherein, the at least one first input power terminal and the at least one second input power terminal are directly mechanically coupled to the substrate, and In this embodiment, the at least one output power terminal is not directly mechanically coupled to the substrate, and a bonding wire couples the at least one output power terminal to the power circuit. Furthermore, the plurality of device pads include: First device pad, on which the plurality of high-side power devices are located; Multiple second device pads, each second device pad including a low-side power device; and The third device pad, which contains a temperature circuit, is located between the two second device pads.

35. A device package, comprising: A substrate, the substrate including a bottom side and a top side, the top side including a plurality of device pads; Multiple power devices are arranged on multiple device pads to provide a power circuit having a first input terminal, a second input terminal, and at least one output terminal, the multiple power devices including multiple high-side power devices and multiple low-side power devices; Multiple signal terminals provide multiple control signals to the power circuit; as well as A housing, comprising portions for the plurality of signal terminals and the plurality of power devices; In this configuration, the pin tips of adjacent pairs of the plurality of signal terminals are staggered. The device package further includes power terminals providing a first input and a second input to the power circuit, the power terminals including a first V- terminal, a second V- terminal, a first V+ terminal, and a second V+ terminal. Wherein, the first V+ terminal and the second V+ terminal are located between the first V- terminal and the second V- terminal. Furthermore, the plurality of device pads include: First device pad, on which the plurality of high-side power devices are located; Multiple second device pads, each second device pad including a low-side power device; and The third device pad, which contains a temperature circuit, is located between the two second device pads.

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