Method for preparing ferroelectric thin film and application thereof
By using a single-element-oxidation-state preparation method, the stability problem of traditional ferroelectric thin films in high-temperature self-aligned processes has been solved, and the performance of ferroelectric thin films at high temperatures has been optimized, making them suitable for microelectronic devices such as ferroelectric random access memory and ferroelectric field-effect transistors.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
- Filing Date
- 2024-10-17
- Publication Date
- 2026-07-31
AI Technical Summary
Traditional ferroelectric thin film preparation techniques are incompatible with self-aligned processes, and high-temperature treatments damage the structure of the ferroelectric oxide layer, affecting ferroelectric properties.
The method of preparing ferroelectric alloy layer by depositing hafnium and zirconium by magnetron sputtering, controlling the oxygen content, oxidizing to form ferroelectric oxide layer, and forming ferroelectric orthorhombic phase by rapid thermal annealing.
The thermal annealing temperature was lowered to ensure the stability of the ferroelectric thin film in the high-temperature self-alignment process and to optimize the ferroelectric properties.
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Figure CN119351965B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the semiconductor field, specifically to a method for preparing and applying a ferroelectric thin film. Background Technology
[0002] Ferroelectric materials have been widely used in non-volatile semiconductor devices. Hafnium oxide (HfO2)-based ferroelectric materials have attracted extensive research and attention due to their high scalability, good compatibility with complementary metal-oxide-semiconductor (CMOS), and high performance in small-size thin films. Among them, HfO2-based ferroelectric materials have shown good performance in non-volatile memories such as ferroelectric random access memory (FeRAM) and ferroelectric field-effect transistor (FeFET) devices.
[0003] However, the ferroelectric stability of HfO2-based ferroelectric materials often presents a mismatch with the fabrication processes of non-volatile semiconductor devices. For example, the self-alignment technique in the fabrication of ferroelectric field-effect transistors (FeFETs) is a widely used technique in microelectronics. It utilizes certain parts of the transistor structure (such as the gate) as a mask to automatically align other parts (such as the source and drain) in subsequent process steps, thereby reducing alignment errors and improving device performance and reliability. However, the self-alignment process typically involves diffusion of the active region at high temperatures (1000°C). High temperatures can damage the internal structure of the ferroelectric oxide film, thus affecting ferroelectricity. Therefore, traditional ferroelectric thin film fabrication techniques cannot directly realize the self-alignment process for FeFETs.
[0004] Therefore, designing a method for preparing ferroelectric thin films that is compatible with both the stability of ferroelectric materials and the high-temperature processing of semiconductors has profound practical significance. Summary of the Invention
[0005] In view of the above, in order to solve at least one technical problem mentioned in the related art and other aspects, this disclosure proposes a method for preparing a ferroelectric thin film, comprising: providing a first stress layer; depositing elemental hafnium and elemental zirconium on the first stress layer by magnetron sputtering to form a ferroelectric alloy layer; oxidizing the ferroelectric alloy layer, using the heat released during the oxidation process to generate crystal defects and phase transformation stress in the ferroelectric alloy layer to form a ferroelectric oxide layer; patterning the ferroelectric oxide layer, depositing stress material in the patterned area of the ferroelectric oxide layer to form a second stress layer; and finally performing rapid thermal annealing on the composite layer formed by the first stress layer, the ferroelectric alloy layer, and the second stress layer to promote the transformation of the crystal phase of the ferroelectric alloy layer into a ferroelectric orthorhombic phase, thereby obtaining a ferroelectric thin film.
[0006] According to embodiments of this disclosure, in the magnetron sputtering process, the sputtering ratio of hafnium to zirconium is 2:1.
[0007] According to embodiments of this disclosure, in the magnetron sputtering process, the sputtering gas atmosphere is a mixture of argon and oxygen, wherein the flux of argon is 40 sccm and the flux of oxygen is 0.6 sccm.
[0008] According to embodiments of this disclosure, in the oxidation treatment, the oxidation temperature is 300-400°C and the oxidation time is 3 hours.
[0009] According to embodiments of this disclosure, the deposition method of the first stress layer and the second stress layer includes any one of ion beam sputtering, DC sputtering, and reactive sputtering.
[0010] According to embodiments of this disclosure, in the ion beam sputtering process, the sputtering atmosphere is a mixture of argon and nitrogen gas, the beam voltage is 700-900V, the beam current is 40-60mA, and the accelerating voltage is 150-170V.
[0011] According to embodiments of this disclosure, the first stress layer and the second stress layer have a symmetrical structure, and the stress material includes at least one selected from titanium nitride, tungsten, tungsten nitride, high-conductivity silicon, indium, tungsten, tungsten dioxide, platinum, and palladium.
[0012] According to embodiments of this disclosure, in rapid thermal annealing, the annealing atmosphere is nitrogen, the annealing temperature is 500-600°C, and the annealing time is 30s-1min.
[0013] According to embodiments of this disclosure, the patterning process includes: applying a resist to the ferroelectric oxide layer, exposing it, and developing it to obtain a patterned area of the ferroelectric oxide layer.
[0014] In another aspect of this disclosure, an application of the aforementioned fabrication method in a microelectronic device is also proposed, wherein the microelectronic device includes any one of a ferroelectric capacitor, a ferroelectric transistor, and a ferroelectric random access memory.
[0015] According to embodiments of this disclosure, unlike the preparation processes of depositing hafnium and zirconium oxides in related technologies, this disclosure deposits elemental hafnium and elemental zirconium to form a ferroelectric alloy layer. The advantage of depositing elemental materials is that it allows for more precise control of the oxygen content in the ferroelectric thin film during subsequent oxidation. By adjusting the oxidation conditions (such as oxygen partial pressure, temperature, and time), fine control of the stoichiometry of the ferroelectric thin film components can be achieved, thereby optimizing the ferroelectric properties of the film. During oxidation, the continuous release of heat induces defects and transformation stresses in the ferroelectric alloy layer. In subsequent hot annealing, these defects and transformation stresses are eliminated through atomic rearrangement and diffusion, while simultaneously forming ferroelectric domains. Using the ferroelectric thin film preparation method proposed in this disclosure, since the oxidation process has partially "preheated" the ferroelectric alloy layer, and the oxide film contains numerous defects and stresses, the energy required for the hot annealing process is relatively low, thus reducing the annealing temperature. Attached Figure Description
[0016] Figure 1 This is a flowchart of the preparation method of ferroelectric thin films in the embodiments of this disclosure;
[0017] Figure 2 This is a cross-sectional view of the device during the fabrication process of the ferroelectric capacitor in Embodiment 1 of this disclosure, wherein a is a cross-sectional view of the substrate, b is a cross-sectional view after the deposition of the first stress layer, c is a cross-sectional view after the deposition of the ferroelectric alloy layer, and d is a cross-sectional view after the deposition of the second stress layer.
[0018] Explanation of reference numerals in the attached figures
[0019] The meanings of the reference numerals in the attached figures are as follows:
[0020] 201-Substrate; 202-First stress layer; 203-Ferroelectric alloy layer; 204-Second stress layer. Detailed Implementation
[0021] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.
[0022] The endpoints and any values of the ranges disclosed in this disclosure are not limited to the precise ranges or values, and such ranges or values should be understood to include values close to such ranges or values. For numerical ranges, the endpoint values of the various ranges, the endpoint values of the various ranges and individual point values, and individual point values can be combined with each other to obtain one or more new numerical ranges, which should be regarded as specifically disclosed in this disclosure.
[0023] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.
[0024] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.
[0025] It should be noted that, unless otherwise defined, the technical or scientific terms used in this disclosure should have the ordinary meaning understood by a person with ordinary skill in the art to which this disclosure pertains. Where the terms "first," "second," etc., are used throughout, they are used only to distinguish similar objects and should not be construed as indicating or implying their relative importance, order of precedence, or implicitly specifying the number of technical features indicated. It should be understood that the data described by "first," "second," etc., can be interchanged where appropriate.
[0026] To make the objectives, technical solutions, and advantages of this disclosure clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure.
[0027] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.
[0028] Throughout the accompanying drawings, identical elements are represented by the same or similar reference numerals. Conventional structures or configurations have been omitted where they may cause confusion in understanding this disclosure. Furthermore, the shapes, dimensions, and positional relationships of the components in the drawings do not reflect their actual size, scale, or actual positional relationships. Additionally, any reference symbols enclosed in parentheses should not be construed as limiting this disclosure.
[0029] Similarly, to simplify this disclosure and aid in understanding one or more of the various aspects of the disclosure, in the above description of exemplary embodiments of the present disclosure, various features of the present disclosure are sometimes grouped together in a single embodiment, figure, or description thereof. The use of terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refers to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of the present disclosure. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0030] Furthermore, the technical solutions of the various embodiments can be combined with each other, but only if they are based on the ability of a person skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed in this disclosure.
[0031] In the process of implementing this disclosure, it was discovered that the self-alignment step in CMOS processes typically requires high temperatures (>1000°C) to ensure that impurity elements can effectively diffuse into the semiconductor material to form the desired PN junction or other structures. This high-temperature processing is an indispensable part of CMOS processes. Traditional ferroelectric oxide thin films possess specific crystal structures and chemical compositions, which determine their ferroelectric properties. However, high-temperature processing can destroy this delicate crystal structure, leading to a decrease or even loss of the film's ferroelectric properties. Therefore, ferroelectric oxide thin films are unstable at high temperatures. In summary, to overcome this technical challenge, it is necessary to develop new ferroelectric thin film fabrication techniques or improve existing CMOS processes. This disclosure reduces the ferroelectric annealing temperature by designing the ferroelectric thin film fabrication process as a single-element oxidation state. Simultaneously, the self-alignment process can be performed in the more stable oxidation state stage, followed by thermal annealing to induce ferroelectric phase formation, thus avoiding the influence of high temperatures on the ferroelectric phase material.
[0032] Figure 1 This is a flowchart of the preparation method of ferroelectric thin films in the embodiments of this disclosure.
[0033] This disclosure proposes a method for preparing ferroelectric thin films, such as... Figure 1 As shown, it includes:
[0034] Step S101: Provide the first stress layer;
[0035] Step S102: Hafnium and zirconium are deposited on the first stress layer by magnetron sputtering to form a ferroelectric alloy layer;
[0036] Step S103: Oxidize the ferroelectric alloy layer, and use the heat released during the oxidation process to generate crystal defects and phase transformation stress in the ferroelectric alloy layer to form a ferroelectric oxide layer.
[0037] Step S104: Pattern the ferroelectric oxide layer and deposit stress material in the patterned area of the ferroelectric oxide layer to form a second stress layer;
[0038] Step S105: Perform rapid thermal annealing on the composite layer formed by the first stress layer, the ferroelectric alloy layer, and the second stress layer to promote the transformation of the crystalline phase of the ferroelectric alloy layer into the ferroelectric orthorhombic phase, thereby obtaining a ferroelectric thin film.
[0039] According to embodiments of this disclosure, unlike the preparation processes of depositing hafnium and zirconium oxides in related technologies, this disclosure deposits elemental hafnium and elemental zirconium to form a ferroelectric alloy layer. The advantage of depositing elemental materials is that it allows for more precise control of the oxygen content in the ferroelectric thin film during subsequent oxidation. By adjusting the oxidation conditions (such as oxygen partial pressure, temperature, and time), fine control of the stoichiometry of the ferroelectric thin film components can be achieved, thereby optimizing the ferroelectric properties of the film. During oxidation, the continuous release of heat induces defects and transformation stresses in the ferroelectric alloy layer. In subsequent hot annealing, these defects and transformation stresses are eliminated through atomic rearrangement and diffusion, while simultaneously forming ferroelectric domains. Using the ferroelectric thin film preparation method proposed in this disclosure, since the oxidation process has partially "preheated" the ferroelectric alloy layer, and the oxide film contains numerous defects and stresses, the energy required for the hot annealing process is relatively low, thus reducing the annealing temperature.
[0040] According to an embodiment of this disclosure, in the magnetron sputtering process of step S102, the sputtering ratio of hafnium to zirconium is 2:1.
[0041] According to embodiments of this disclosure, the component ratio of the two elements in the ferroelectric alloy can be controlled by controlling the sputtering ratio of hafnium and zirconium. Controlling the ratio of hafnium and zirconium is beneficial for designing the subsequent oxidation degree, thereby obtaining a ferroelectric thin film with good ferroelectric properties.
[0042] According to an embodiment of this disclosure, in the magnetron sputtering process of step S102, the sputtering gas atmosphere is a mixture of argon and oxygen, wherein the flux of argon is 40 sccm and the flux of oxygen is 0.6 sccm.
[0043] According to embodiments of this disclosure, the addition of trace amounts of oxygen during the sputtering of elemental materials in the magnetron sputtering process is to achieve specific coating effects and performance requirements of this disclosure, rather than simply causing oxidation. By precisely controlling the sputtering process parameters and the oxygen content in the sputtering gas atmosphere, hafnium-zirconium ferroelectric alloy layers with excellent ferroelectric properties can be obtained.
[0044] According to an embodiment of this disclosure, in the oxidation treatment of step S103, the oxidation temperature is 300-400°C and the oxidation time is 3 hours.
[0045] According to embodiments of this disclosure, in the method for preparing ferroelectric thin films proposed in this disclosure, an elemental thin film is first deposited. During the subsequent oxidation process, the elemental thin film reacts with oxygen to form an oxide. The oxidation process itself is an exothermic reaction, releasing a certain amount of heat. Therefore, the oxidation temperature does not need to be too high.
[0046] According to embodiments of this disclosure, the first stress layer and the second stress layer have a symmetrical structure, and the stress material includes at least one of titanium nitride, tungsten, high-conductivity silicon, indium, platinum and palladium.
[0047] According to embodiments of this disclosure, during the thermal annealing process in step S105, stress accumulates within the ferroelectric oxide layer. This stress may originate from factors such as thin film deposition or lattice mismatch during the fabrication process of the ferroelectric oxide layer. The stress layers on the upper and lower surfaces of the ferroelectric oxide layer provide a mechanism to manage stress, optimize interface properties, and ensure the structural stability of the ferroelectric phase. Simultaneously, the symmetrical structure of the first and second stress layers ensures that the stress received by the upper and lower surfaces of the ferroelectric oxide layer is the same, guaranteeing stability.
[0048] According to embodiments of this disclosure, in steps S101 and S104, the deposition method of the first stress layer and the second stress layer includes any one of ion beam sputtering, DC sputtering, and reactive sputtering.
[0049] According to embodiments of this disclosure, in steps S101 and S104, in the ion beam sputtering process, the sputtering atmosphere is a mixture of argon and nitrogen gas, the beam current voltage is 700-900V, for example, 700V, 750V, 800V, 850V, 900V, etc., the beam current is 40-60mA, for example, 40mA, 45mA, 50mA, 55mA, 60mA, etc., and the accelerating voltage is 150-170V, for example, 150V, 155V, 160V, 165V, 170V, etc.
[0050] According to an embodiment of this disclosure, in the rapid thermal annealing process of step S105, the annealing atmosphere is nitrogen, the annealing temperature is 500-600℃, for example, it can be 500℃, 510℃, 520℃, 530℃, 540℃, 550℃, 560℃, 570℃, 580℃, 590℃, 600℃, etc., and the annealing time is 30s-1min, for example, it can be 30s, 30s, 30s, 1min, etc.
[0051] According to embodiments of this disclosure, the patterning process includes: applying a resist to the ferroelectric oxide layer, exposing it, and developing it to obtain a patterned area of the ferroelectric oxide layer.
[0052] According to an embodiment of this disclosure, in step S104, after the second stress layer is formed, it is also necessary to clean it to remove the photoresist and excess deposited stress material.
[0053] In some specific embodiments, a first stress layer is deposited on a substrate, which can be made of a semiconductor material, such as a substrate made solely of silicon or silicon oxide, or a multilayer substrate composed of silicon and silicon oxide. When silicon is used as the substrate, the substrate thickness can be 500 μm; when a multilayer substrate composed of silicon and silicon oxide is used, the silicon thickness in the substrate can be 500 μm, and the silicon hydride thickness can be 300 nm.
[0054] In another aspect of this disclosure, an application of the aforementioned fabrication method in a microelectronic device is also proposed, wherein the microelectronic device includes any one of a ferroelectric capacitor, a ferroelectric transistor, and a ferroelectric random access memory.
[0055] According to embodiments of this disclosure, when the aforementioned method for preparing a ferroelectric thin film is applied to a ferroelectric capacitor, the first stress layer can be a first electrode, and the second stress layer can be a second electrode; when the aforementioned method for preparing a ferroelectric thin film is applied to a ferroelectric transistor, the first stress layer can be a semiconductor layer, a bottom electrode, or a gate electrode, and the second stress layer can be a metal layer, a top electrode, or an insulating layer. A ferroelectric random access memory typically consists of a field-effect transistor and a ferroelectric capacitor.
[0056] It should be noted that the described embodiments are merely some, not all, of the embodiments disclosed herein. Other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without inventive effort are all within the scope of protection of this disclosure.
[0057] Example 1
[0058] Taking the fabrication process of a ferroelectric capacitor as an example, the following explanation is provided:
[0059] Figure 2 These are cross-sectional structural diagrams of the device during the fabrication process of the ferroelectric capacitor in Embodiment 1 of this disclosure, wherein (a) is a cross-sectional structural diagram of the substrate, (b) is a cross-sectional structural diagram after the deposition of the first stress layer, (c) is a cross-sectional structural diagram after the deposition of the ferroelectric alloy layer, and (d) is a cross-sectional structural diagram after the deposition of the second stress layer.
[0060] A substrate 201 is formed using silicon (Si) as the substrate material, and TiN is used as the first electrode 202 and the second electrode 204. The first electrode 202 and the second electrode 204 are prepared by ion beam sputtering, and a metal alloy layer 203 is prepared by magnetron sputtering.
[0061] Titanium nitride (TiN) target material is sputtered on substrate 201 under the conditions of beam voltage of 800V, beam current of 50mA, accelerating voltage of 160V, and gas of argon (Ar) and nitrogen (N2) to obtain first electrode 202. The flow rate of argon (Ar) is 8sccm and the flow rate of nitrogen (N2) is 5sccm. The thickness of the prepared first electrode 202 is not less than 10nm.
[0062] First, Hf and Zr targets with a purity of over 99% were selected. The Hf and Zr targets were then mounted on a magnetron sputtering coating machine. Using an AC power supply, the sputtering power of the Hf and ZrO2 targets was set. The Hf to Zr composition ratio was maintained at approximately 2:1 by adjusting the power of the two targets, resulting in a ferroelectric alloy layer 203 with a thickness of 10 nm. The amount of Ar introduced was 40 sccm, and the amount of O2 introduced was 0.6 sccm.
[0063] The obtained substrate 201-first electrode 202-ferroelectric alloy layer 203 structure was oxidized in an oxygen (O2) atmosphere at 400°C for 3 hours to obtain a fully oxidized ferroelectric oxide layer.
[0064] A negative adhesive is coated on the ferroelectric oxide layer, which can be baked at 150°C for 2 minutes, exposed, baked at 120°C for 2 minutes, immersed in developer for 45 seconds, and then rinsed with deionized water and dried.
[0065] Under conditions of 800V beam voltage, 50mA beam current, 160V accelerating voltage, and argon (Ar) and nitrogen (N2) gases, a second electrode 204 was obtained by sputtering a titanium nitride (TiN) target onto a ferroelectric oxide layer. The thickness of the second electrode 204 was not less than 10nm. The flow rate of argon (Ar) was 8sccm, and the flow rate of nitrogen (N2) was 5sccm.
[0066] The ferroelectric capacitor with capacitor substrate layer 201, first electrode 202, oxide thin film layer 203 and second electrode 204 obtained above was immersed in acetone solution until the photoresist and excess metal were removed; then it was immersed in anhydrous ethanol to remove acetone; and then rinsed with deionized water and dried.
[0067] Finally, the rinsed and dried ferroelectric capacitor was annealed in a nitrogen (N2) atmosphere at 600°C for 30 seconds to obtain a ferroelectric capacitor with ferroelectric properties.
[0068] The specific embodiments described above further illustrate the purpose, technical solutions, and beneficial effects of this disclosure. It should be understood that the above descriptions are merely specific embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.
Claims
1. A method for preparing a ferroelectric thin film, comprising: Provide the first stress layer; Hafnium and zirconium are deposited on the first stress layer by magnetron sputtering to form a ferroelectric alloy layer. The sputtering ratio of hafnium to zirconium is 2:
1. In the magnetron sputtering process, the sputtering gas atmosphere is a mixture of argon and oxygen, wherein the flux of argon is 40 sccm and the flux of oxygen is 0.6 sccm. The ferroelectric alloy layer is oxidized, and the heat released during the oxidation process generates crystal defects and phase transformation stress in the ferroelectric alloy layer to form a ferroelectric oxide layer. The ferroelectric oxide layer is patterned, and stress material is deposited in the patterned area of the ferroelectric oxide layer to form a second stress layer; The composite layer formed by the first stress layer, the ferroelectric alloy layer, and the second stress layer is subjected to rapid thermal annealing to induce the crystal phase of the ferroelectric alloy layer to transform into a ferroelectric orthorhombic phase, thereby obtaining a ferroelectric thin film.
2. The production method according to claim 1, wherein, In the oxidation process, the oxidation temperature is 300-400℃ and the oxidation time is 3h.
3. The production method according to claim 1, wherein, The deposition methods for the first stress layer and the second stress layer include any one of ion beam sputtering, DC sputtering, and reactive sputtering.
4. The production method according to claim 3, wherein In the ion beam sputtering process, the sputtering atmosphere is a mixture of argon and nitrogen, the beam voltage is 700-900V, the beam current is 40-60mA, and the accelerating voltage is 150-170V.
5. The production method according to claim 1, wherein The first stress layer and the second stress layer have a symmetrical structure, and the stress material includes at least one of titanium nitride, tungsten, high-conductivity silicon, indium, platinum and palladium.
6. The production method according to claim 1, wherein In the rapid thermal annealing process, the annealing atmosphere is nitrogen, the annealing temperature is 500-600℃, and the annealing time is 30s-1min.
7. The production method according to claim 1, wherein The patterning process includes coating, exposing, and developing the ferroelectric oxide layer to obtain a patterned area of the ferroelectric oxide layer.
8. Use of a preparation method as claimed in any one of claims 1 to 7 in a microelectronic device, wherein The microelectronic device includes any one of ferroelectric capacitors, ferroelectric transistors, and ferroelectric random access memory.