Network card management method and device, storage medium and program product

Abstract

This application provides a network interface card (NIC) management method and apparatus, storage medium, and program product, relating to the computer field. The method includes: configuring an arbitration chip for the serial communication bus I2C and configuring a logic chip; using the arbitration chip to sort and send first management information and second management information to the target NIC; when the logic chip on the second adapter board receives a first power-on management signal sent by a complex programmable logic device (CPLD) of the first motherboard or a second power-on management signal sent by the CPLD of the second motherboard, sending the first power-on management signal or the second power-on management signal to the target NIC; when the logic chip receives a first power-off management signal sent by the CPLD of the first motherboard and a second power-off management signal sent by the CPLD of the second motherboard, sending the target power-off management signal to the target NIC; using the above solution, the problem of ineffective NIC management is solved.

Description

Technical Field

[0001] This application relates to the field of computers, specifically to a network interface card (NIC) management method and apparatus, storage medium, and program product. Background Technology

[0002] A network interface card (NIC) is an internal or external device used to connect a computer to a local area network (LAN) or wide area network (WAN), enabling data transmission via Ethernet or wireless networks. NIC management is crucial because it directly impacts a computer's network connectivity and communication performance. Network connectivity is a key component for data exchange between a computer and external networks, and the NIC is the hardware device that enables this connection.

[0003] Currently, the common approach to network card management is to use the embedded management controller (BMC) on the motherboard of the device containing the network card to transmit network card information (such as temperature, operating status, etc.) with the network card via the serial communication bus I2C, thereby controlling the network card. The complex programmable logic device (CPLD) on the motherboard is used to manage the power-on and power-off of the network card through the power-on and power-off signal transmission channel.

[0004] However, when using the network card management method provided in the above-mentioned related technologies, if there are multiple motherboards in the device, all motherboards need to monitor the network card through I2C and manage the power-on and power-off of the network card through the power-on and power-off signal transmission channel. This may cause conflicts between the management of the network card by multiple motherboards, which may lead to technical problems such as the inability to effectively manage the network card. Summary of the Invention

[0005] This application provides a method and apparatus for managing network interface cards (NICs), a storage medium, and a program product to at least solve the technical problem of the inability to effectively manage NICs.

[0006] According to one embodiment of this application, a network interface card (NIC) management method is provided, comprising: configuring an arbitration chip for serial communication bus I2C on a first adapter board and configuring a logic chip on a second adapter board; when the arbitration chip on the first adapter board receives first management information sent by the embedded management system (BMC) on the first motherboard and second management information sent by the BMC on the second motherboard via I2C, sorting the first and second management information using the arbitration chip, and sending the first and second management information to the target NIC according to the sorting order between the first and second management information, wherein, when the target NIC receives the first management information, it will execute a management operation matching the first management information, and when the target NIC receives the second management information, it will execute a management operation matching the second management information. The matching management operations are as follows: When the logic chip on the second adapter board receives a first power-on management signal sent by the complex programmable logic device (CPLD) of the first motherboard or a second power-on management signal sent by the CPLD of the second motherboard through the power-on / off signal transmission channel, the logic chip sends the first power-on management signal or the second power-on management signal to the target network card. Upon receiving the first power-on management signal or the second power-on management signal, the target network card will perform a power-on operation. When the logic chip receives a first power-off management signal sent by the CPLD of the first motherboard or a second power-off management signal sent by the CPLD of the second motherboard through the power-on / off signal transmission channel, the logic chip sends a target power-off management signal to the target network card. Upon receiving the target power-off management signal, the target network card will perform a power-off operation.

[0007] According to another embodiment of this application, a network interface card (NIC) management device is provided, comprising: a configuration unit configured to configure an arbitration chip for a serial communication bus (I2C) on a first adapter board and a logic chip on a second adapter board; and a first transmission unit configured to, when the arbitration chip on the first adapter board receives first management information sent by an embedded management system (BMC) on a first motherboard and second management information sent by a BMC on a second motherboard via I2C, sort the first management information and the second management information using the arbitration chip, and send the first management information and the second management information to a target NIC according to the sorting order between them, wherein, when the target NIC receives the first management information, it will execute a management operation matching the first management information, and when the target NIC receives the second management information, it will execute a management operation matching the second management information. The management operation matched by the management information; the second sending unit, used to send the first power-on management signal or the second power-on management signal to the target network card when the logic chip on the second adapter board receives the first power-on management signal sent by the complex programmable logic device CPLD of the first motherboard or the second power-on management signal sent by the CPLD of the second motherboard through the power-on / off signal transmission channel, wherein the target network card will perform a power-on operation upon receiving the first power-on management signal or the second power-on management signal; and when the logic chip receives the first power-off management signal sent by the CPLD of the first motherboard and the second power-off management signal sent by the CPLD of the second motherboard through the power-on / off signal transmission channel, the logic chip will send the target power-off management signal to the target network card, wherein the target network card will perform a power-off operation upon receiving the target power-off management signal.

[0008] According to yet another embodiment of this application, a computer-readable storage medium is also provided, wherein a computer program is stored therein, and the computer program is configured to perform the steps in any of the above method embodiments when it is run.

[0009] According to yet another embodiment of this application, an electronic device is also provided, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0010] According to yet another embodiment of this application, a computer program product is also provided, including a computer program that, when executed by a processor, implements the steps of the methods described in various embodiments of this application.

[0011] According to the embodiments provided in this application, an arbitration chip for the serial communication bus I2C is configured on the first adapter board, and a logic chip is configured on the second adapter board. When the arbitration chip on the first adapter board receives first management information sent by the embedded management system (BMC) on the first motherboard and second management information sent by the BMC on the second motherboard via I2C, it sorts the first and second management information using the arbitration chip and sends them to the target network card according to their order. Specifically, when the target network card receives the first management information, it executes a management operation matching the first management information; when the target network card receives the second management information, it executes a management operation matching the second management information. The management operation matched by the information; when the logic chip on the second adapter board receives a first power-on signal sent by the complex programmable logic device CPLD of the first motherboard or a second power-on signal sent by the CPLD of the second motherboard through the power-on / off signal transmission channel, the logic chip sends the first power-on signal or the second power-on signal to the target network card, wherein the target network card will perform a power-on operation upon receiving the first power-on signal or the second power-on signal; when the logic chip receives a first power-off signal sent by the CPLD of the first motherboard and a second power-off signal sent by the CPLD of the second motherboard through the power-on / off signal transmission channel, the logic chip sends a target power-off signal to the target network card, wherein the target network card will perform a power-off operation upon receiving the target power-off signal. In other words, using the embodiments of this application, on the one hand, a first adapter board is configured between the motherboard and the network card, and an I2C arbitration chip is configured on the first adapter board. The I2C arbitration chip is used to coordinate the management information sent by the first motherboard and the second motherboard, ensuring that the management information sent by the first motherboard and the second motherboard can be transmitted to the target network card in an orderly manner. On the other hand, a second adapter board is configured between the motherboard and the network card, and a logic chip is configured on the second adapter board. The logic chip is used to determine whether to control the target network card to perform power-on / off operations based on the power-on / off signals sent by the first motherboard and the second motherboard and predetermined processing logic, thereby avoiding conflicts between the power-on / off signals sent by different motherboards. In other words, by using the embodiments of this application, the conflict between multiple motherboards in managing the network card is avoided through the above two aspects, solving the technical problem that the network card management methods provided by related technologies cannot effectively manage the network card, and achieving the technical effect of improving the management effect of the network card. Attached Figure Description

[0012] Figure 1 This is a flowchart of a network interface card (NIC) management method according to an embodiment of this application;

[0013] Figure 2This is a flowchart of a network interface card (NIC) management method according to an embodiment of this application;

[0014] Figure 3 This is a flowchart of another network interface card (NIC) management method according to an embodiment of this application;

[0015] Figure 4 This is a schematic diagram of a network interface card (NIC) management method according to an embodiment of this application;

[0016] Figure 5 A structural block diagram of a network interface card (NIC) management device according to an embodiment of this application. Detailed Implementation

[0017] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0018] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0019] As an optional solution, the specific steps of the above network card management method are as follows: Figure 1 The following are included:

[0020] S102, an arbitration chip for the serial communication bus I2C is configured on the first adapter board, and a logic chip is configured on the second adapter board;

[0021] S104, when the arbitration chip on the first adapter board receives the first management information sent by the embedded manager BMC on the first motherboard and the second management information sent by the BMC on the second motherboard via I2C, the arbitration chip sorts the first management information and the second management information and sends the first management information and the second management information to the target network card according to the sorting order between the first management information and the second management information. When the target network card receives the first management information, it will execute the management operation matching the first management information. When the target network card receives the second management information, it will execute the management operation matching the second management information.

[0022] S106, when the logic chip on the second adapter board receives a first power-on signal sent by the complex programmable logic device (CPLD) of the first motherboard or a second power-on signal sent by the CPLD of the second motherboard through the power-on / off signal transmission channel, the logic chip sends the first power-on signal or the second power-on signal to the target network card. Upon receiving the first power-on signal or the second power-on signal, the target network card performs a power-on operation. When the logic chip receives a first power-off signal sent by the CPLD of the first motherboard or a second power-off signal sent by the CPLD of the second motherboard through the power-on / off signal transmission channel, the logic chip sends a target power-off signal to the target network card. Upon receiving the target power-off signal, the target network card performs a power-off operation.

[0023] It should be noted that the above-described network interface card (NIC) management method can be applied to, but is not limited to, NIC management scenarios. The first and second adapter boards described above can be, but are not limited to, configured between the target NIC and the first and second motherboards.

[0024] Optionally, in this embodiment, the aforementioned I2C can be, but is not limited to, a data path used to instruct the BMC to obtain network card information. The BMC uses I2C to request network card information from the target network card, such as the target network card manufacturer, the target network card's uptime, the target network card's temperature, etc., in order to monitor and manage the target network card.

[0025] Furthermore, in this embodiment, the aforementioned power-on / off signal transmission channel may be used, but is not limited to, for transmitting power-on / off signals, wherein the power-on signal is used to control the target network card to start, and the power-off signal is used to control the target network card to stop operating.

[0026] It should be noted that the aforementioned Complex Programmable Logic Device (CPLD) is used to implement various digital logic functions, including combinational and sequential logic. It can be used to construct digital circuits such as counters, registers, state machines, and microprocessors. The logic chip described above can be, but is not limited to, a CPLD or other chips with similar functions; this embodiment does not impose any limitations on this.

[0027] Optionally, the arbitration chip for the aforementioned serial communication bus I2C can be, but is not limited to, the 9641 chip or other chips with I2C arbitration function. In this embodiment, no limitation is made on this. The aforementioned 9641 chip is a dedicated I2C arbitration chip, which can allow two groups of I2C to arbitrate bus control on their own. The motherboard BMC that wins bus control accesses the network card first. After the bus is idle, the other motherboard BMC gains bus control and then accesses the network card I2C device.

[0028] Furthermore, the aforementioned logic chip can be used, but is not limited to, to indicate chips pre-programmed with power-on / off logic. Specifically, the power-on signal uses OR logic, meaning that if one motherboard wants to power on the network card, the network card performs the power-on action, and upon completion, returns a power-on success signal to both motherboards. Based on this, it can be achieved that if one motherboard wants to power on, the smart network card will also power on, functioning as a normal network card. The power-off signal uses AND logic, meaning that when the motherboards are powered off, the smart network card will only power off if both motherboards are powered off. This ensures that both motherboards can connect to and manage the network card, while avoiding conflicts in network card control caused by different power-on / off states.

[0029] It should be noted that the above-mentioned sorting of the first and second management information using an arbitration chip, and sending the first and second management information to the target network card according to their sorting order, may include, but is not limited to: sorting the first and second management information according to the reception time of the first and second management information using the arbitration chip, obtaining sorted first and second management information, wherein the management information with the earlier reception time has a higher sorting order; and sending the first and second management information to the target network card according to their sorting order.

[0030] In addition to determining the order in which the first and second management information are sent to the target network card based on the time when the management information is received, other strategies can also be used to determine the order in which the first and second management information are sent to the target network card, such as the type of management information, the priority of management information, the priority of the motherboard, etc. Among these, management information with higher priority will be sent first, and management information sent by the motherboard with higher motherboard priority will be sent first.

[0031] It should be noted that, in this embodiment, before the logic chip sends the first power-on signal or the second power-on signal to the target network card, it may include, but is not limited to: when the CPLD of the first motherboard receives a boot command for the first motherboard, sending the first power-on management signal to the logic chip through the power-on / off signal transmission channel; when the CPLD of the second motherboard receives a boot command for the second motherboard, sending the second power-on management signal to the logic chip through the power-on / off signal transmission channel.

[0032] Optionally, in this embodiment, before the logic chip sends the target power-down signal to the target network card after receiving the first power-down signal sent by the CPLD of the first motherboard and the second power-down signal sent by the CPLD of the second motherboard through the power-up / down signal transmission channel, it may include, but is not limited to: when the CPLD of the first motherboard receives a power-off command for the first motherboard, sending the first power-down management signal to the logic chip through the power-up / down signal transmission channel; and when the CPLD of the second motherboard receives a power-off command for the second motherboard, sending the second power-down management signal to the logic chip through the power-up / down signal transmission channel.

[0033] According to the embodiments provided in this application, an arbitration chip for the serial communication bus I2C is configured on the first adapter board, and a logic chip is configured on the second adapter board. When the arbitration chip on the first adapter board receives first management information sent by the embedded management system (BMC) on the first motherboard and second management information sent by the BMC on the second motherboard via I2C, it sorts the first and second management information using the arbitration chip and sends them to the target network card according to their order. Specifically, when the target network card receives the first management information, it executes a management operation matching the first management information; when the target network card receives the second management information, it executes a management operation matching the second management information. The management operation matched by the information; when the logic chip on the second adapter board receives a first power-on signal sent by the complex programmable logic device CPLD of the first motherboard or a second power-on signal sent by the CPLD of the second motherboard through the power-on / off signal transmission channel, the logic chip sends the first power-on signal or the second power-on signal to the target network card, wherein the target network card will perform a power-on operation upon receiving the first power-on signal or the second power-on signal; when the logic chip receives a first power-off signal sent by the CPLD of the first motherboard and a second power-off signal sent by the CPLD of the second motherboard through the power-on / off signal transmission channel, the logic chip sends a target power-off signal to the target network card, wherein the target network card will perform a power-off operation upon receiving the target power-off signal. In other words, using the embodiments of this application, on the one hand, a first adapter board is configured between the motherboard and the network card, and an I2C arbitration chip is configured on the first adapter board. The I2C arbitration chip is used to coordinate the management information sent by the first motherboard and the second motherboard, ensuring that the management information sent by the first motherboard and the second motherboard can be transmitted to the target network card in an orderly manner. On the other hand, a second adapter board is configured between the motherboard and the network card, and a logic chip is configured on the second adapter board. The logic chip is used to determine whether to control the target network card to perform power-on / off operations based on the power-on / off signals sent by the first motherboard and the second motherboard and predetermined processing logic, thereby avoiding conflicts between the power-on / off signals sent by different motherboards. In other words, by using the embodiments of this application, the conflict between multiple motherboards in managing the network card is avoided through the above two aspects, solving the technical problem that the network card management methods provided by related technologies cannot effectively manage the network card, and achieving the technical effect of improving the management effect of the network card.

[0034] As an optional solution, the arbitration chip is used to sort the first management information and the second management information, and then the first management information and the second management information are sent to the target network card according to their sorting order.

[0035] S1, using the arbitration chip to sort the first management information and the second management information according to the reception time of the first management information and the reception time of the second management information, to obtain the sorted first management information and the second management information. Among them, the management information with the earlier reception time is ranked earlier in the sorted first management information and the second management information.

[0036] S2, according to the sorting order between the first management information and the second management information, sends the first management information and the second management information to the target network card.

[0037] For example, assuming the arbitration chip receives the first management information at 12:00 and the second management information at 12:00:01, the arbitration chip will sort the first and second management information and send the first management information first. After the target network card has processed the first management information, the second management information will be sent to the target network card so that the target network card can process the second management information.

[0038] It should be noted that the above example is an optional example provided to facilitate the explanation of the above network card management method, and there is no limitation on the specific implementation of the above network card management method.

[0039] In this embodiment, an arbitration chip sorts the first and second management information according to their reception times, resulting in sorted first and second management information. The management information with earlier reception times is ranked higher. Then, the first and second management information are sent to the target network card according to their sorting order. In other words, by configuring a first adapter board between the motherboard and the network card and utilizing the arbitration chip on the first adapter board to send earlier-sent management information to the target network card for processing, this ensures that information is processed in its original sending order, thus avoiding problems caused by incorrect ordering. Furthermore, this sorting mechanism optimizes the information processing flow, preventing delays in system operation due to processing later-arriving information, thereby improving overall system efficiency. Moreover, the sorting function of the arbitration chip reduces the information processing burden on the target network card, as it can receive information sequences already sorted in the correct order without requiring complex sorting algorithms within the network card. This not only simplifies the design and implementation of network cards, but may also improve their processing efficiency and response speed.

[0040] As an optional solution, the above-mentioned network interface card (NIC) management methods also include:

[0041] When the CPLD of the first motherboard receives a boot command for the first motherboard, it sends a first power-on signal to the logic chip through the power-on / off signal transmission channel; when the target network card successfully performs a power-on operation based on the received first power-on signal, it sends a first power-on prompt message to the logic chip to indicate successful power-on; when the logic chip receives the first power-on prompt message, it sends the first power-on prompt message to the CPLD of the first motherboard through the power-on / off signal transmission channel; when the CPLD of the first motherboard receives the first power-on prompt message, it boots up the first motherboard.

[0042] When the CPLD of the second motherboard receives a boot command for the second motherboard, it sends a second power-on signal to the logic chip through the power-on / off signal transmission channel. When the target network card successfully performs a power-on operation based on the received second power-on signal, it sends a second power-on prompt message to the logic chip to indicate successful power-on. When the logic chip receives the second power-on prompt message, it sends the second power-on prompt message to the CPLD of the second motherboard through the power-on / off signal transmission channel. When the CPLD of the second motherboard receives the second power-on prompt message, it boots up the second motherboard.

[0043] In this embodiment, when the CPLD of the first motherboard receives a boot command for the first motherboard, it sends a first power-on signal to the logic chip through the power-on / off signal transmission channel. When the target network card successfully performs a power-on operation based on the received first power-on signal, it sends a first power-on prompt message to the logic chip to indicate successful power-on. When the logic chip receives the first power-on prompt message, it sends the first power-on prompt message to the CPLD of the first motherboard through the power-on / off signal transmission channel. When the CPLD of the first motherboard receives the first power-on prompt message, it boots the first motherboard. When the CPLD of the second motherboard receives a boot command for the second motherboard, it sends a second power-on signal to the logic chip through the power-on / off signal transmission channel. When the target network card successfully performs a power-on operation based on the received second power-on signal, it sends a second power-on prompt message to the logic chip to indicate successful power-on. When the logic chip receives the second power-on prompt message, it sends the second power-on prompt message to the CPLD of the second motherboard through the power-on / off signal transmission channel. When the CPLD of the second motherboard receives the second power-on prompt message, it boots the second motherboard. In other words, by using the embodiments of this application, the startup process of the first motherboard, the second motherboard, and the target network card can be precisely controlled by the logic chip as an intermediate controller, ensuring accurate transmission and reception of signals between the logic chip and the motherboard, thereby achieving precise control over the power-on operation of the motherboard and the target network card.

[0044] As an optional solution, the above-mentioned network interface card (NIC) management methods also include:

[0045] When the CPLD of the first motherboard receives a power-off command for the first motherboard, it sends the first power-down signal to the logic chip through the power-on / off signal transmission channel; when the CPLD of the second motherboard receives a power-off command for the second motherboard, it sends the second power-down signal to the logic chip through the power-on / off signal transmission channel.

[0046] If the target network card successfully performs a power-down operation based on the received target power-down signal, a power-down prompt message is sent to the logic chip to indicate that the power-down is successful. If the logic chip receives the power-down prompt message, it sends the power-down prompt message to the CPLD of the first motherboard and the CPLD of the second motherboard through the power-up and power-down signal transmission channel.

[0047] When the CPLD of the first motherboard receives a power-down prompt, the first motherboard is powered off; when the CPLD of the second motherboard receives a power-down prompt, the second motherboard is powered off.

[0048] In this embodiment, when the CPLD of the first motherboard receives a power-off command for the first motherboard, it sends a first power-down signal to the logic chip through the power-on / off signal transmission channel; when the CPLD of the second motherboard receives a power-off command for the second motherboard, it sends a second power-down signal to the logic chip through the power-on / off signal transmission channel; when the target network card successfully performs a power-down operation according to the received target power-down signal, it sends a power-down prompt message to the logic chip to indicate successful power-down; when the logic chip receives the power-down prompt message, it sends the power-down prompt message to the CPLD of the first motherboard and the CPLD of the second motherboard through the power-on / off signal transmission channel; when the CPLD of the first motherboard receives the power-down prompt message, it powers off the first motherboard; when the CPLD of the second motherboard receives the power-down prompt message, it powers off the second motherboard. In other words, by using this embodiment, with the logic chip as an intermediate controller, the power-down process of the first motherboard, the second motherboard, and the target network card can be precisely controlled, ensuring accurate transmission and reception of signals between the logic chip and the motherboard, thereby achieving precise control of the power-down operation of the motherboard and the target network card.

[0049] As an optional solution, the above-mentioned network interface card (NIC) management methods also include:

[0050] Configure the LAN switch chip on the third adapter board.

[0051] When the LAN switch chip on the third adapter board receives the first request information sent by the BMC of the first motherboard through the first interface connected to the out-of-band management network channel, the LAN switch chip sends the first request information to the target network card.

[0052] When the target network card receives the first request information, it sends the first network card information requested by the first request information to the LAN switch chip, so that the LAN switch chip sends the first network card information to the BMC of the first motherboard through the out-of-band management network channel.

[0053] When the LAN switch chip on the third adapter board receives the second request information sent by the BMC of the second motherboard through the second interface connected to the out-of-band management network channel, the LAN switch chip sends the second request information to the target network card.

[0054] When the target network card receives the second request information, it sends the second network card information requested by the second request information to the LAN switch chip, so that the LAN switch chip sends the second network card information to the BMC of the second motherboard through the out-of-band management network channel.

[0055] Optionally, the aforementioned LAN switch chip is used to manage and control the transmission of data in the network. The LAN switch chip may, but is not limited to, be configured with multiple interfaces connected to the motherboard and one or more interfaces connected to the target network card, so as to ensure that the request information sent by multiple motherboards can be sent to the target network card through the LAN switch chip.

[0056] It should be noted that in some embodiments, the first adapter board, the second adapter board, and the third adapter board may be, but are not limited to, the same adapter board, or they may be different adapter boards. This embodiment does not impose any limitations on this.

[0057] Furthermore, in this embodiment, the aforementioned out-of-band management network channel may be used, but is not limited to, to indicate the transmission of network signals. Network signals are abbreviations for various network signals, including, but not limited to, NCSI, RGMII, MDI, etc. Network signals that can be directly interconnected with the network card, such as NCSI and MDI, are output by the LAN switch chip. This enables the two motherboard BMCs to manage the network card out of band through network signals.

[0058] It should be noted that, in this embodiment, the aforementioned first request information may be, but is not limited to, network signals used to indicate network information for obtaining network card information, such as network card health status information. Similarly, the aforementioned second request information may be, but is not limited to, network signals used to indicate network information for obtaining network card information, such as network card health status information. This embodiment does not impose any limitations on this.

[0059] In this embodiment of the application, a LAN switch chip is configured on a third adapter board. When the LAN switch chip on the third adapter board receives a first request message from the BMC of the first motherboard via a first interface connected to the out-of-band management network channel, it sends the first request message to the target network card. Upon receiving the first request message, the target network card sends the requested first network card information to the LAN switch chip, so that the LAN switch chip sends the first network card information to the BMC of the first motherboard via the out-of-band management network channel. Similarly, when the LAN switch chip on the third adapter board receives a second request message from the BMC of the second motherboard via a second interface connected to the out-of-band management network channel, it sends the second request message to the target network card. Upon receiving the second request message, the target network card sends the requested second network card information to the LAN switch chip, so that the LAN switch chip sends the second network card information to the BMC of the second motherboard via the out-of-band management network channel. In other words, using the embodiments of this application, the LAN switch chip can receive and forward request information sent by the BMC (Baseboard Management Controller). Regardless of whether the information comes from the first motherboard or the second motherboard, it can accurately send the information to the target network card, and then the target network card returns the response information to the corresponding BMC, thus realizing efficient and accurate information transmission.

[0060] As an optional solution, the above-mentioned network interface card (NIC) management methods also include:

[0061] The CPU of the first motherboard sends a first data transmission request to the target network card through the first network card data channel. When the target network card receives the first data transmission request, it will encapsulate the first data carried in the first data transmission request and transmit the encapsulated first data to the first address carried in the first data transmission request.

[0062] It should be noted that the aforementioned first network card data channel may, but is not limited to, be used to indicate a PCIex8, which provides a transmission channel for information between the CPU and the network card, thereby successfully sending the data to be sent by the motherboard or successfully transmitting the data received by other devices through the network card to the motherboard.

[0063] The CPU of the second motherboard sends the second data transmission request to the target network card through the second network card data channel. When the target network card receives the second data transmission request, it will encapsulate the second data carried in the second data transmission request and transmit the encapsulated second data to the second address carried in the second data transmission request.

[0064] It should be noted that the aforementioned first network card data channel can be used, but is not limited to, to instruct another PCIe x8 to provide a transmission channel for information between the CPU and the network card, thereby successfully sending the data to be sent by the motherboard or successfully transmitting data received by other devices through the network card to the motherboard.

[0065] The CPU of the first motherboard sends a first clock signal to the target network card through a first clock signal channel. When the target network card receives the first clock signal, it will synchronize the clock information of the target network card based on the clock information carried in the first clock signal.

[0066] Optionally, in this embodiment, the aforementioned first clock signal channel may, but is not limited to, being used to indicate a link for transmitting clock signals between the CPU of the first motherboard and the target network card. The aforementioned first clock signal is a synchronization signal used to control the timing operations within the network card chip. The clock signal is typically generated by the CPU; this signal is a periodic pulse wave with a very high frequency (e.g., hundreds of megahertz or gigahertz) to ensure correct data transmission and processing. Further, the aforementioned clock information may, but is not limited to, indicating the aforementioned pulse wave; this embodiment does not impose any limitations on this.

[0067] The CPU of the second motherboard sends the second clock signal to the target network card through the second clock signal channel. When the target network card receives the second clock signal, it will synchronize the clock information of the target network card based on the clock information carried in the second clock signal.

[0068] It should be noted that, in this embodiment, the aforementioned second clock signal channel may, but is not limited to, be used to indicate a link for transmitting clock signals between the CPU of the second motherboard and the target network card. The aforementioned second clock signal is also a synchronization signal used to control the timing operations within the network card chip. The clock signal is typically generated by the CPU; this signal is a periodic pulse wave with a very high frequency (e.g., hundreds of megahertz or gigahertz) used to ensure correct data transmission and processing.

[0069] The CPU of the first motherboard sends a first reset signal to the target network card through the first reset signal channel. When the target network card receives the first reset signal, it will reset the target network card to its initial state based on the first reset signal.

[0070] Optionally, in this embodiment, the first reset signal channel may be, but is not limited to, a link between the CPU of the first motherboard and the target network card for transmitting a reset signal. The first reset signal is a control signal used to reset the network card device to its initial state.

[0071] The CPU of the second motherboard sends a second reset signal to the target network card through the second reset signal channel. When the target network card receives the second reset signal, it will reset the target network card to its initial state based on the second reset signal.

[0072] Optionally, in this embodiment, the second reset signal channel may be, but is not limited to, used as a link between the CPU of the second motherboard and the target network card to transmit a reset signal. The second reset signal is also a control signal used to reset the network card device to its initial state.

[0073] Optionally, in some embodiments, in addition to the first motherboard and the second motherboard described above, more motherboards may be configured, but not limited to, to enable multiple motherboards to manage the target network card. Taking the configuration of three motherboards as an example, the network card management method may, but is not limited to, also include:

[0074] An arbitration chip for the serial communication bus I2C is configured on the first adapter board, a logic chip is configured on the second adapter board, and a LAN switch chip is configured on the third adapter board.

[0075] When the arbitration chip on the first adapter board receives the first management information sent by the embedded manager BMC on the first motherboard, the second management information sent by the BMC on the second motherboard, and the third management information sent by the BMC on the third motherboard via I2C, the arbitration chip sorts the first, second, and third management information and sends them to the target network card according to the sorting order of the first, second, and third management information. When the target network card receives the first management information, it will execute the management operation matching the first management information; when the target network card receives the second management information, it will execute the management operation matching the second management information; and when the target network card receives the third management information, it will execute the management operation matching the third management information.

[0076] When the logic chip on the second adapter board receives a first power-on management signal from the complex programmable logic device (CPLD) of the first motherboard, a second power-on management signal from the CPLD of the second motherboard, or a third power-on management signal from the CPLD of the third motherboard via the power-on / off signal transmission channel, the logic chip sends the first power-on management signal or the second power-on management signal to the target network card. Upon receiving the first power-on management signal or the second power-on management signal, the target network card will perform a power-on operation. When the logic chip receives a first power-off management signal from the CPLD of the first motherboard, a second power-off management signal from the CPLD of the second motherboard, and a third power-off management signal from the CPLD of the third motherboard via the power-on / off signal transmission channel, the logic chip sends a target power-off management signal to the target network card. Upon receiving the target power-off management signal, the target network card will perform a power-off operation.

[0077] When the LAN switch chip on the third adapter board receives the first request information sent by the BMC of the first motherboard through the first interface connected to the out-of-band management network channel, the LAN switch chip sends the first request information to the target network card.

[0078] When the target network card receives the first request information, it sends the first network card information requested by the first request information to the LAN switch chip, so that the LAN switch chip sends the first network card information to the BMC of the first motherboard through the out-of-band management network channel;

[0079] When the LAN switch chip on the third adapter board receives the second request information sent by the BMC of the second motherboard through the second interface connected to the out-of-band management network channel, the LAN switch chip sends the second request information to the target network card.

[0080] When the target network card receives the second request information, it sends the second network card information requested by the second request information to the LAN switch chip, so that the LAN switch chip sends the second network card information to the BMC of the second motherboard through the out-of-band management network channel.

[0081] When the LAN switch chip on the third adapter board receives the third request information sent by the BMC of the third motherboard through the third interface connected to the out-of-band management network channel, the LAN switch chip sends the third request information to the target network card.

[0082] When the target network card receives the third request information, it sends the second network card information requested by the third request information to the LAN switch chip, so that the LAN switch chip sends the third network card information to the BMC of the third motherboard through the out-of-band management network channel.

[0083] Alternatively, as an optional example, it can be, but is not limited to, by means of, such as Figure 2 The following steps are shown as an example to explain the power-on control of the target network card:

[0084] Execute steps S202 to S204: Step S202: After the server motherboard is powered on and running, the user issues a power-on command to a certain motherboard. At this time, the motherboard CPLD first sends a PWREN signal to the smart network card. The PWREN signal is used to indicate the power-on enable signal. Step S204: The adapter board or gate or CPLD pulls up the PWREN signal output to the network card.

[0085] Next, step S206 is executed, where the motherboard CPLD determines whether the PWRON signal output by the network card is high;

[0086] If the result is high, proceed to step S208 to confirm that the network card has completed the power-on process; then proceed to steps S210 to S212: Step S210, the motherboard performs the power-on process; Step S212, after the motherboard is powered on, it accesses and manages the smart network card through the BMC's I2C or network interface.

[0087] If it is low, then continue to wait;

[0088] Alternatively, as another alternative example, it can be, but is not limited to, by means of, such as Figure 3The following steps are shown as an example to explain the power-down control of the target network card:

[0089] In step S302, at a certain moment, a motherboard performs a shutdown action, which lowers the PWREN signal to the network card.

[0090] Next, step S304 is executed, where the adapter board CPLD or OR gate determines the high or low level of the PWREN signal output to the network card based on the high or low level of the PWREN signal output from another motherboard.

[0091] If the output of the other motherboard is high, then execute step S306-1 to keep the output to the network card at a high level;

[0092] If the other motherboard output is low, then step S306-2 is executed to pull the PWREN signal to the network card low; then step S308 is executed to perform the network card shutdown action.

[0093] The method embodiments provided in this application may be, but are not limited to, as follows: Figure 4 Execute in the architecture shown, such as Figure 4 As shown, the architecture includes: MB0 (i.e., the first motherboard mentioned above), MB1 (i.e., the second motherboard mentioned above), SmartNIC (i.e., the target network card mentioned above), adapter board 402, 9641 / MUX chip (i.e., the arbitration chip mentioned above) configured on the adapter board, logic chip / CPLD, and LAN switch chip.

[0094] Specifically, such as Figure 4 As shown, the Smart NIC's PCIe signal consists of a set of ×8 signals sent by the CPU on MB0 and a set of ×8 signals sent by the CPU on MB1; the Smart NIC's Clock signal consists of a set of CLK_0 signals sent by the CPU on MB0 and a set of CLK_1 signals sent by the CPU on MB1; the Smart NIC's Reset signal consists of a set of Reset_0 signals sent by the CPU on MB0 and a set of Reset_1 signals sent by the CPU on MB1.

[0095] Furthermore, the I2C signal on the adapter board can achieve the function of two sets of I2C accessing the network card without conflict by adding a 9641 chip or a MUX chip. The 9641 chip is a dedicated I2C arbitration chip, which can allow the two sets of I2C to arbitrate the bus control right themselves. The motherboard BMC that wins the bus control right accesses the network card first. After that, when the bus is idle, the other motherboard BMC wins the bus control right and then accesses the network card I2C device.

[0096] The aforementioned Network signals are used to indicate various network signal names, including but not limited to NCSI, RGMII, and MDI. The NCSI / Network_0 signal of MB0 and the NCSI / Network_1 signal of MB1 are uniformly connected to the LAN switch chip of the third adapter board. The LAN switch chip outputs network signals that can be directly interconnected with the network card, such as NCSI and MDI. This enables the two motherboard BMCs to manage the network card out of band through network signals.

[0097] PWREN / PWROK (i.e., power-on enable and power-on completion indicators), when connected to the second adapter board, can be connected to a logic chip or CPLD. The PWREN signal performs an OR operation, meaning that if one motherboard wants to power on the network card, the network card performs the power-on action. After power-on, it returns a PWROK signal, which is simultaneously sent to both motherboards, performing an AND operation. Based on this, it can achieve the function of a smart network card powering on when one motherboard wants to power on, realizing normal network card functionality; when the motherboard is powered off, the smart network card will only power off when both motherboards are powered off. This ensures that both motherboards can connect to, access, and manage the network card, and avoids conflicts in network card control caused by different power-on / off states. Specifically, the BMC of MB0 sends PWRPN_0 and PWROK_0 signals, while the BMC of MB1 sends PWRPN_1 and PWROK_1 signals.

[0098] This embodiment also provides a network interface card (NIC) management device, which is used to implement the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0099] Figure 5 This is a structural block diagram of a network interface card (NIC) management device according to an embodiment of this application, such as... Figure 5 As shown, the device includes:

[0100] Configuration unit 502 is used to configure the arbitration chip of serial communication bus I2C on the first adapter board and to configure the logic chip on the second adapter board.

[0101] The first transmitting unit 504 is configured to, when the arbitration chip on the first adapter board receives first management information sent by the embedded manager BMC on the first motherboard and second management information sent by the BMC on the second motherboard via I2C, sort the first management information and the second management information using the arbitration chip, and send the first management information and the second management information to the target network card according to the sorting order between the first management information and the second management information. When the target network card receives the first management information, it will execute the management operation matching the first management information. When the target network card receives the second management information, it will execute the management operation matching the second management information.

[0102] The second transmitting unit 506 is configured to, when the logic chip on the second adapter board receives a first power-on management signal sent by the complex programmable logic device (CPLD) of the first motherboard or a second power-on management signal sent by the CPLD of the second motherboard through the power-on / off signal transmission channel, transmit the first power-on management signal or the second power-on management signal to the target network card, wherein the target network card will perform a power-on operation upon receiving the first power-on management signal or the second power-on management signal; and when the logic chip receives a first power-off management signal sent by the CPLD of the first motherboard and a second power-off management signal sent by the CPLD of the second motherboard through the power-on / off signal transmission channel, transmit the target power-off management signal to the target network card, wherein the target network card will perform a power-off operation upon receiving the target power-off management signal.

[0103] As an optional solution, the first sending unit includes: a sorting processing module, used to sort the first management information and the second management information according to the reception time of receiving the first management information and the reception time of receiving the second management information using an arbitration chip, to obtain sorted first management information and second management information, wherein the management information with the earlier reception time in the sorted first management information and second management information has a higher sorting order; and a sending module, used to send the first management information and the second management information to the target network card according to the sorting order between the first management information and the second management information.

[0104] As an optional solution, the above-mentioned device further includes: a first startup unit, configured to, upon receiving a startup command for the first motherboard, send a first power-on management signal to a logic chip via a power-on / off signal transmission channel; upon the target network card successfully performing a power-on operation based on the received first power-on management signal, send a first power-on prompt message to the logic chip to indicate successful power-on; upon receiving the first power-on prompt message, the logic chip sends the first power-on prompt message to the CPLD of the first motherboard via the power-on / off signal transmission channel; upon the CPLD of the first motherboard receiving the first power-on prompt message, start the first motherboard; and a second startup unit, configured to, upon receiving a startup command for the second motherboard, send a second power-on management signal to the logic chip via a power-on / off signal transmission channel; upon the target network card successfully performing a power-on operation based on the received second power-on management signal, send a second power-on prompt message to the logic chip to indicate successful power-on; upon receiving the second power-on prompt message, the logic chip sends the second power-on prompt message to the CPLD of the second motherboard via the power-on / off signal transmission channel; upon the CPLD of the second motherboard receiving the second power-on prompt message, start the second motherboard.

[0105] As an optional solution, the above-mentioned device further includes: a third transmitting unit, configured to transmit a first power-down management signal to a logic chip through a power-up / down signal transmission channel when the CPLD of the first motherboard receives a power-down command for the first motherboard; and to transmit a second power-down management signal to a logic chip through a power-up / down signal transmission channel when the CPLD of the second motherboard receives a power-down command for the second motherboard; a fourth transmitting unit, configured to transmit a power-down prompt message to the logic chip to indicate successful power-down when the target network card successfully performs a power-down operation according to the received target power-down management signal; and to transmit the power-down prompt message to the CPLD of the first motherboard and the CPLD of the second motherboard through the power-up / down signal transmission channel when the logic chip receives the power-down prompt message; and a power-down processing unit, configured to power off the first motherboard when the CPLD of the first motherboard receives the power-down prompt message; and to power off the second motherboard when the CPLD of the second motherboard receives the power-down prompt message.

[0106] As an optional solution, the above-mentioned device further includes: a first configuration unit, configured to configure a LAN switch chip on a third adapter board; a fifth sending unit, configured to send the first request information to a target network card when the LAN switch chip on the third adapter board receives a first request information sent by the BMC of the first motherboard through a first interface connected to an out-of-band management network channel; a sixth sending unit, configured to send the first network card information requested by the first request information to the LAN switch chip when the target network card receives the first request information, so that the LAN switch chip sends the first network card information to the BMC of the first motherboard through the out-of-band management network channel; a seventh sending unit, configured to send the second request information to a target network card when the LAN switch chip on the third adapter board receives a second request information sent by the BMC of the second motherboard through a second interface connected to an out-of-band management network channel; and an eighth sending unit, configured to send the second network card information requested by the second request information to the LAN switch chip when the target network card receives the second request information, so that the LAN switch chip sends the second network card information to the BMC of the second motherboard through the out-of-band management network channel.

[0107] As an optional solution, the above-mentioned device further includes: a ninth transmitting unit, configured to send a first data transmission request to a target network card via a first network card data channel, wherein, upon receiving the first data transmission request, the target network card encapsulates the first data carried in the first data transmission request and transmits the encapsulated first data to the first address carried in the first data transmission request; a tenth transmitting unit, configured to send a second data transmission request to the target network card via a second network card data channel, wherein, upon receiving the second data transmission request, the target network card encapsulates the second data carried in the second data transmission request and transmits the encapsulated second data to the second address carried in the second data transmission request; and an eleventh transmitting unit, configured to send a first clock signal to the target network card via a first clock signal channel, wherein, upon receiving the second data transmission request, the target network card encapsulates the second data carried in the second data transmission request and transmits the encapsulated second data to the second address carried in the second data transmission request; and an eleventh transmitting unit, configured to send a first clock signal to the target network card via a first clock signal channel, wherein, upon receiving the first data transmission request, the target network card encapsulates the first .... Upon receiving the first clock signal, the clock information of the target network card is synchronized based on the clock information carried in the first clock signal; the twelfth sending unit is used to send the second clock signal to the target network card through the second clock signal channel, wherein, upon receiving the second clock signal, the clock information of the target network card is synchronized based on the clock information carried in the second clock signal; the thirteenth sending unit is used to send the first reset signal to the target network card through the first reset signal channel, wherein, upon receiving the first reset signal, the target network card is reset to its initial state based on the first reset signal; the fourteenth sending unit is used to send the second reset signal to the target network card through the second reset signal channel, wherein, upon receiving the second reset signal, the target network card is reset to its initial state based on the second reset signal.

[0108] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0109] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0110] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0111] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when run.

[0112] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0113] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0114] In one exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0115] Embodiments of this application also provide a computer program product, including a non-volatile computer-readable storage medium storing the computer program product, wherein the computer program, when executed by a processor, implements the steps of the methods described in various embodiments of this application.

[0116] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0117] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0118] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A method for managing a network interface card (NIC), characterized in that, include: An arbitration chip for the serial communication bus I2C is configured on the first adapter board, and a logic chip is configured on the second adapter board. When the arbitration chip on the first adapter board receives first management information sent by the embedded manager BMC on the first motherboard and second management information sent by the BMC on the second motherboard via I2C, the arbitration chip sorts the first management information and the second management information and sends them to the target network card according to the sorting order between the first management information and the second management information. When the target network card receives the first management information, it will perform a management operation matching the first management information. When the target network card receives the second management information, it will perform a management operation matching the second management information. When the logic chip on the second adapter board receives a first power-on signal from the complex programmable logic device (CPLD) of the first motherboard or a second power-on signal from the CPLD of the second motherboard via the power-on / off signal transmission channel, the logic chip transmits the first power-on signal or the second power-on signal to the target network card. Specifically, the CPLD of the first motherboard, upon receiving a boot command for the first motherboard, transmits the first power-on signal to the logic chip on the second adapter board via the power-on / off signal transmission channel. The target network card, upon successfully performing a power-on operation based on the received first power-on signal, sends a first power-on notification message to the logic chip indicating successful power-on. The logic chip, upon receiving the first power-on notification message, transmits the first power-on notification message to the CPLD of the first motherboard via the power-on / off signal transmission channel. The CPLD of the first motherboard, upon receiving the first power-on notification message, also boots the first motherboard. The CPLD of the second motherboard is used to send the second power-on signal to the logic chip through the power-on / off signal transmission channel when it receives a boot command for the second motherboard. The target network card is also used to send a second power-on prompt message to the logic chip when it successfully executes the power-on operation based on the received second power-on signal. The logic chip is also used to send the second power-on prompt message to the CPLD of the second motherboard through the power-on / off signal transmission channel when it receives the second power-on prompt message. The CPLD of the second motherboard is also used to start the second motherboard when it receives the second power-on prompt message. When the logic chip receives the first power-off signal sent by the CPLD of the first motherboard and the second power-off signal sent by the CPLD of the second motherboard through the power-on / off signal transmission channel, it uses the logic chip to send a target power-off signal to the target network card. The target network card will perform a power-off operation when it receives the target power-off signal.

2. The network interface card (NIC) management method according to claim 1, characterized in that, The step of sorting the first management information and the second management information using the arbitration chip, and sending the first management information and the second management information to the target network card according to the sorting order between them, includes: The arbitration chip is used to sort the first management information and the second management information according to the reception time of the first management information and the reception time of the second management information, so as to obtain the sorted first management information and the second management information. In the sorted first management information and the second management information, the management information with the earlier reception time is ranked earlier. The first management information and the second management information are sent to the target network card according to the sorting order between them.

3. The network card management method according to any one of claims 1 to 2, characterized in that, The method further includes: When the CPLD of the first motherboard receives a power-off command for the first motherboard, it sends the first power-down signal to the logic chip through the power-on / off signal transmission channel; when the CPLD of the second motherboard receives a power-off command for the second motherboard, it sends the second power-down signal to the logic chip through the power-on / off signal transmission channel. When the target network card successfully performs the power-down operation according to the received target power-down signal, a power-down prompt message is sent to the logic chip to indicate that the power-down is successful; when the logic chip receives the power-down prompt message, it sends the power-down prompt message to the CPLD of the first motherboard and the CPLD of the second motherboard through the power-up and power-down signal transmission channel. When the CPLD of the first motherboard receives the power-down prompt, the first motherboard is powered off; when the CPLD of the second motherboard receives the power-down prompt, the second motherboard is powered off.

4. The network interface card (NIC) management method according to any one of claims 1 to 2, characterized in that, The method further includes: Configure a LAN switch chip on the third adapter board; When the LAN switch chip on the third adapter board receives the first request information sent by the BMC of the first motherboard through the first interface connected to the out-of-band management network channel, the LAN switch chip sends the first request information to the target network card. When the target network card receives the first request information, it sends the first network card information requested by the first request information to the LAN switch chip, so that the LAN switch chip sends the first network card information to the BMC of the first motherboard through the out-of-band management network channel; When the LAN switch chip on the third adapter board receives the second request information sent by the BMC of the second motherboard through the second interface connected to the out-of-band management network channel, the LAN switch chip sends the second request information to the target network card. When the target network card receives the second request information, it sends the second network card information requested by the second request information to the LAN switch chip, so that the LAN switch chip sends the second network card information to the BMC of the second motherboard through the out-of-band management network channel.

5. The network interface card (NIC) management method according to any one of claims 1 to 2, characterized in that, The method further includes: The CPU of the first motherboard sends a first data transmission request to the target network card through the first network card data channel. When the target network card receives the first data transmission request, it will encapsulate the first data carried in the first data transmission request and transmit the encapsulated first data to the first address carried in the first data transmission request. The CPU of the second motherboard sends a second data transmission request to the target network card through the second network card data channel. When the target network card receives the second data transmission request, it will encapsulate the second data carried in the second data transmission request and transmit the encapsulated second data to the second address carried in the second data transmission request. The CPU of the first motherboard sends a first clock signal to the target network card through a first clock signal channel. When the target network card receives the first clock signal, it will synchronize the clock information of the target network card based on the clock information carried in the first clock signal. The CPU of the second motherboard sends a second clock signal to the target network card through a second clock signal channel. When the target network card receives the second clock signal, it will synchronize the clock information of the target network card based on the clock information carried in the second clock signal. The CPU of the first motherboard sends a first reset signal to the target network card through a first reset signal channel. When the target network card receives the first reset signal, it will reset the target network card to its initial state based on the first reset signal. The CPU of the second motherboard sends a second reset signal to the target network card through the second reset signal channel. When the target network card receives the second reset signal, it will reset the target network card to its initial state based on the second reset signal.

6. A network interface card (NIC) management device, characterized in that, include: A configuration unit is used to configure the arbitration chip of the serial communication bus I2C on the first adapter board and to configure the logic chip on the second adapter board. The first sending unit is configured to, when the arbitration chip on the first adapter board receives first management information sent by the embedded manager BMC on the first motherboard and second management information sent by the BMC on the second motherboard via I2C, sort the first management information and the second management information using the arbitration chip, and send the first management information and the second management information to the target network card according to the sorting order between the first management information and the second management information. Specifically, when the target network card receives the first management information, it will execute a management operation matching the first management information; when the target network card receives the second management information, it will execute a management operation matching the second management information. The second transmitting unit is configured to, when the logic chip on the second adapter board receives a first power-on signal from the complex programmable logic device (CPLD) of the first motherboard or a second power-on signal from the CPLD of the second motherboard via a power-on / off signal transmission channel, transmit the first power-on signal or the second power-on signal to the target network card using the logic chip. Specifically, the CPLD of the first motherboard, upon receiving a boot command for the first motherboard, transmits the first power-on signal to the logic chip on the second adapter board via the power-on / off signal transmission channel. The target network card, upon successfully performing a power-on operation based on the received first power-on signal, sends a first power-on prompt message indicating successful power-on to the logic chip. The logic chip, upon receiving the first power-on prompt message, transmits the first power-on prompt message to the CPLD of the first motherboard via the power-on / off signal transmission channel. The CPLD of the first motherboard, upon receiving the first power-on prompt message, initiates the power-on process. The first motherboard; the CPLD of the second motherboard is used to send the second power-on signal to the logic chip through the power-on / off signal transmission channel when a boot command for the second motherboard is received. The target network card is also used to send a second power-on prompt message to the logic chip when the power-on operation is successfully executed according to the received second power-on signal. The logic chip is also used to send the second power-on prompt message to the CPLD of the second motherboard through the power-on / off signal transmission channel when it receives the second power-on prompt message. The CPLD of the second motherboard is also used to start the second motherboard when it receives the second power-on prompt message. When the logic chip receives the first power-off signal sent by the CPLD of the first motherboard and the second power-off signal sent by the CPLD of the second motherboard through the power-on / off signal transmission channel, the logic chip sends a target power-off signal to the target network card. The target network card will perform a power-off operation when it receives the target power-off signal.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method according to any one of claims 1 to 5.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 5.

9. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 5.

Images