A storage device

Abstract

The application discloses a storage device. The storage device comprises a storage array, a burn-in storage circuit, a command decoder and a processing circuit. The burn-in storage circuit, the command decoder and the storage array are coupled to the processing circuit. The word line mapping addresses stored in the burn-in storage circuit comprise at least two types of word line mapping addresses. Each type of word line mapping address corresponds to a type of redundant word line group. The number of redundant word lines in each type of redundant word line group is different. The processing circuit generates a corresponding redundant word line enable signal to drive the redundant word line in the at least one redundant word line group corresponding to the matched at least one word line mapping address to replace the normal word line corresponding to the word line addressing address in response to the matching of the word line addressing address and the at least one word line mapping address. The application improves the efficiency and flexibility of the storage chip repair.

Description

Technical Field

[0001] The disclosed embodiments of this application relate to the field of semiconductor memory technology, and more specifically, to a memory device. Background Technology

[0002] If a Dynamic Random Access Memory (DRAM) has damaged word lines (WLs) or bit lines (BLs) (e.g., short circuits or open circuits), these WLs and BLs need to be replaced with redundant WLs / BLs. Those skilled in the art will understand that, due to manufacturing process factors, when one word line (WL) is damaged, one or more adjacent word lines (WLs) are also highly likely to be damaged. Therefore, for replacement efficiency, manufacturers typically replace multiple adjacent word lines (WLs) simultaneously, such as replacing 8 WLs, 4 WLs, or 2 WLs simultaneously, etc., when performing redundant replacement of word lines (WLs). However, existing simultaneous replacement methods require pre-setting the number of word lines (WLs) to be replaced simultaneously, and then performing the pre-set number of word lines (WLs) for simultaneous replacement. Once the number of word lines (WLs) to be replaced simultaneously is set, it is difficult to modify later. Therefore, this simultaneous replacement method is very inflexible and has many problems. For example, while performing simultaneous replacement of 2 word lines (WLs) improves the repair efficiency of the memory chip compared to replacing a single word line (WL), its repair efficiency is still relatively low and cannot meet the needs of high-performance memory chips. Performing simultaneous replacement of 8 word lines (WLs) has a higher repair efficiency, but sometimes the number of adjacent word lines (WLs) that need redundant replacement is less than 8, or even much less than 8. For example, if only 3 adjacent WLs need redundant replacement, it can still only perform simultaneous replacement of 8 word lines (WLs), thus greatly wasting word line and redundant word line resources and causing a waste of memory chip area. Summary of the Invention

[0003] According to embodiments of this application, this application proposes a storage device to solve the problem of the single word line replacement method mentioned above, and to improve the efficiency and flexibility of chip repair.

[0004] This application discloses a storage device, comprising: a storage array including a general-purpose storage array and a redundant storage array, wherein redundant word lines in the redundant storage array are used to map and replace general-purpose word lines in the general-purpose storage array, so that redundant storage cells in the redundant storage array map and replace damaged general-purpose storage cells in the general-purpose storage array; a programming storage circuit configured to store at least one word line mapping address, wherein each word line mapping address corresponds to a redundant word line of a redundant word line group; a command decoder configured to generate a corresponding word line addressing address in response to a user instruction; and a processing circuit coupled to the programming storage circuit, the command decoder, and the storage array. An array; wherein the processing circuit is configured to receive the word line addressing address and the word line mapping address; in response to the word line addressing address matching at least one of the word line mapping addresses, generate a corresponding redundant word line enable signal to drive the redundant word line mapping in at least one redundant word line group corresponding to the matched at least one word line mapping address to replace a group of ordinary word lines corresponding to the word line addressing address; wherein the word line mapping address stored in the programming memory circuit includes at least two types of word line mapping addresses, each type of word line mapping address corresponds to a type of redundant word line group, and the number of redundant word lines in the various types of redundant word line groups is different.

[0005] The beneficial effects of the present application are as follows: The storage device includes a storage array, a programming storage circuit, a command decoder, and a processing circuit. The processing circuit is coupled to the programming storage circuit, the command decoder, and the storage array. Among them, the word line mapping addresses stored in the programming storage circuit include at least two types of word line mapping addresses. Each type of word line mapping address corresponds to a type of redundant word line group, and the number of redundant word lines in various types of redundant word line groups is different. Furthermore, the processing circuit will generate corresponding redundant word line enable signals to drive the redundant word lines in at least one redundant word line group corresponding to the matched at least one word line mapping address to map and replace a group of normal word lines corresponding to the word line addressing address in response to the word line addressing address matching at least one word line mapping address, thereby improving the efficiency and flexibility of storage chip repair. Further, when a part of the first type of redundant word lines (M) in the first type of redundant word line group is also damaged, an embodiment of the present invention uses the second type of redundant word lines in the second type of redundant word line group to replace part of the first type of redundant word lines (N) to map and replace the normal word lines corresponding to the word line addressing address, without occupying an additional group of the first type of redundant word line group (M, where N < M), thereby saving redundant word line resources; in addition, even if N ≥ M, when a part of the first type of redundant word lines (M) in the first type of redundant word line group is damaged, an embodiment of the present invention can also use the second type of redundant word lines (N) in the second type of redundant word line group to replace the first type of redundant word lines to map and replace the normal word lines corresponding to the word line addressing address, avoiding the situation where replacement cannot be achieved when the first type of redundant word lines in the first type of redundant word line group are exhausted. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present application will be further described below in conjunction with the drawings and embodiments. In the drawings:

[0007] Figure 1 is a schematic structural diagram of a storage device according to an embodiment of the present application;

[0008] Figure 2 is a schematic diagram of a storage device according to another embodiment of the present application;

[0009] Figure 3 is a schematic diagram of a storage device according to another embodiment of the present application;

[0010] Figure 4 is a schematic diagram of a storage device according to another embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0011] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0012] In this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Additionally, the character " / " generally indicates that the preceding and following related objects are in an "or" relationship. Furthermore, "many" in this application means two or more. Moreover, the term "at least one" in this application means any combination of at least two of any one or more of a plurality of objects. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C. Furthermore, the terms "first," "second," and "third" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0013] To enable those skilled in the art to better understand the technical solution of this application, the technical solution of this application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0014] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a storage device according to an embodiment of this application. The storage device 10 includes a storage array 11, a programming storage circuit 12, a command decoder 13, and a processing circuit 14. The storage device 10 may be a dynamic random access memory (DRAM). The storage device 10 can be applied to electronic devices including storage systems, graphics systems, computing systems, or mobile systems. For example, the electronic device may include a data storage device, a memory controller, a cache memory, etc.

[0015] Specifically, the storage array 11 includes a general storage array 111 and a redundant storage array 112. The general storage array 111 includes multiple general word lines WL, multiple general bit lines BL, and multiple general storage cells. By performing row addressing operations on the general word lines WL and / or column addressing operations on the general bit lines BL, the corresponding general storage cell is selected to perform memory operations, such as read, write, and erase operations.

[0016] The redundant storage array 112 includes multiple redundant word lines and multiple redundant storage cells. The redundant word lines in the redundant storage array 112 can be used to map and replace ordinary word lines in the ordinary storage array 111, so that the redundant storage cells in the redundant storage array 112 can replace damaged ordinary storage cells in the ordinary storage array 111. In other words, when a damaged ordinary word line appears in the ordinary storage array 111, the redundant word lines in the redundant storage array 112 can be used for redundant replacement.

[0017] The programming memory circuit 12 is configured to store at least one word line mapping address Efsadd, wherein each word line mapping address Efsadd corresponds to a redundant word line in a redundant word line group. The programming memory circuit 12 stores at least one word line mapping address Efsadd, which can be the address of a faulty word line discovered during pre-shipment testing of the DRAM. Each word line mapping address Efsadd can correspond to a redundant word line in a redundant word line group, and the simultaneous mapping and replacement of multiple redundant word lines in its corresponding redundant word line group is performed through the word line mapping address Efsadd. For example, if a redundant word line group corresponding to a certain word line mapping address Efsadd includes 8 redundant word lines, then when that word line mapping address Efsadd is selected, the 8 redundant word lines in its corresponding redundant word line group are simultaneously mapped and replaced with 8 ordinary word lines.

[0018] Command decoder 13 is configured to generate a corresponding word line address in response to a user instruction. Specifically, when a user issues a user instruction, command decoder 13 can generate a corresponding word line address RA and a word line addressing operation trigger signal Act_en. The word line addressing operation trigger signal Act_en is used to trigger the back-end circuitry (e.g., the back-end processing circuitry 14) to perform a word line addressing operation. The word line address RA can be the word line address that the user wants to access.

[0019] Processing circuit 14 is coupled to programming and storage circuit 12, command decoder 13, and storage array 11. Processing circuit 14 is configured to receive word line addressing address RA and word line mapping address Efsadd, and to receive the word line addressing operation trigger signal Act_en sent by command decoder 13. In response to word line addressing address RA matching at least one word line mapping address Efsadd, processing circuit 14 determines whether the word line addressing address is a faulty word line address. Further, if word line addressing address RA matches at least one word line mapping address Efsadd, a corresponding redundant word line enable signal is generated to drive the redundant word line mapping in at least one redundant word line group corresponding to the matched at least one word line mapping address Efsadd to replace a group of ordinary word lines corresponding to word line address RA. In other words, when the processing circuit 14 matches at least one word line mapping address Efsadd according to the word line addressing address RA, it means that a group of ordinary word lines WL corresponding to the word line addressing address RA is faulty or damaged, and the group of ordinary word lines WL corresponding to the word line addressing address RA needs to be replaced. The replacement object is the redundant word line in the at least one redundant word line group corresponding to the matched at least one word line mapping address Efsadd.

[0020] In this application, the word line mapping address Efsadd stored in the programming memory circuit 12 includes at least two types of word line mapping addresses, such as two-word line mapping addresses, four-word line mapping addresses, eight-word line mapping addresses, etc., wherein a two-word line mapping address can be understood as a word line mapping address in which two word lines are replaced together, a four-word line mapping address can be understood as a word line mapping address in which four word lines are replaced together, and an eight-word line mapping address can be understood as a word line mapping address in which eight word lines are replaced together.

[0021] The number of redundant word lines in the redundant word line group corresponding to each type of word line mapping address is different from the number of redundant word lines in the redundant word line group corresponding to other types of word line mapping addresses. For example, the number of redundant word lines in the redundant word line group corresponding to a two-word line mapping address is 2, the number of redundant word lines in the redundant word line group corresponding to a four-word line mapping address is 4, and the number of redundant word lines in the redundant word line group corresponding to an eight-word line mapping address is 8. The number of redundant word lines in the redundant word line groups corresponding to these addresses is not the same.

[0022] In some embodiments, such as Figure 1 As shown, the processing circuit 14 includes an address matching circuit 141, which is coupled to the programming and storage circuit 12 and the command decoder 13.

[0023] The address matching circuit 141 is configured to cache the word line mapping address Efsadd from the programming memory circuit 12, receive the word line addressing address RA from the command decoder 13, and compare the word line addressing address RA and the word line mapping address Efsadd to determine whether the word line addressing address RA matches at least one of the word line mapping addresses Efsadd.

[0024] Specifically, the address matching circuit 141 may also include a latch unit for buffering or temporarily storing the word line mapping address Efsadd from the programming memory circuit 12, so as to compare it one by one with the word line addressing address RA corresponding to the user instruction to determine whether word line redundancy replacement is required. Furthermore, the address matching circuit 141 also receives the word line addressing address RA and the word line addressing operation trigger signal Act_en from the command decoder 13, and performs a word line addressing operation based on the word line addressing operation trigger signal Act_en; wherein, the word line addressing operation first compares the word line addressing address RA and the word line mapping address Efsadd to determine whether word line redundancy replacement is required. In response to a match between at least one of the word line addressing address RA and the word line mapping address Efsadd, it is determined that word line redundancy replacement is required.

[0025] Furthermore, such as Figure 1 As shown, in some embodiments, the processing circuit 14 further includes a redundant word line decoding circuit 142, which is coupled to an address matching circuit 141.

[0026] Specifically, the address matching circuit 141 determines that the word line addressing address RA matches at least one word line mapping address Efsadd, meaning that the address matching circuit 141 determines that word line redundancy replacement is required. Therefore, the redundant word line decoding circuit 142 is selected. Based on the at least one word line mapping address Efsadd that matches the word line addressing address RA, the redundant word line decoding circuit 142 generates a corresponding redundant word line enable signal RWL_en to drive the redundant word lines in at least one redundant word line group corresponding to the matched at least one word line mapping address Efsadd to replace a group of ordinary word lines corresponding to the word line addressing address RA. In other words, when the address matching circuit 141 determines that the word line addressing address RA matches at least one word line mapping address Efsadd, then a group of word lines corresponding to the word line addressing address RA is faulty or damaged and needs to be replaced redundantly. The redundant word line decoding circuit 142 generates a corresponding redundant word line enable signal RWL_en and replaces a group of ordinary word lines corresponding to the word line addressing address RA. The replacement object is the redundant word line in the at least one redundant word line group corresponding to the at least one word line mapping address Efsadd that matches the word line addressing address RA.

[0027] In some embodiments, such as Figure 1As shown, the processing circuit 14 also includes a common word line decoding circuit 143, which is coupled to an address matching circuit 141.

[0028] When the address matching circuit 141 determines that the word line addressing address RA and the word line mapping address Efsadd do not match, that is, when word line redundancy replacement is not required, the ordinary word line decoding circuit 143 is selected and receives the word line addressing address RA from the command decoder 13. Based on the word line addressing address RA, it generates the corresponding ordinary word line enable signal WL_en to drive the ordinary word line corresponding to the word line addressing address RA and complete the relevant operations of ordinary word line addressing.

[0029] In other words, in this application, the address matching circuit 141 issues a selection signal Select based on the matching result between the word line addressing address RA and the word line mapping address Efsadd, thereby selecting either the ordinary word line decoding circuit 143 or the redundant word line decoding circuit 142. When the address matching circuit 141 determines that at least one of the word line addressing address RA and the word line mapping address Efsadd matches, the address matching circuit 141 selects the redundant word line decoding circuit 142 to perform redundant mapping replacement of word lines based on the word line mapping address Efsadd; when the address matching circuit 141 determines that neither the word line addressing address RA nor the word line mapping address Efsadd matches, the address matching circuit 141 selects the ordinary word line decoding circuit 143 to perform ordinary word line addressing operation based on the word line addressing address RA.

[0030] In summary, in this application, since the word line mapping address Efsadd stored in the programming memory circuit 12 includes at least two types of word line mapping addresses, and the number of redundant word lines in the redundant word line group corresponding to one type of word line mapping address is different from the number of redundant word lines in the redundant word line group corresponding to another type of word line mapping address, when the word line addressing address RA matches one type of word line mapping address Efsadd (e.g., an 8-word line mapping address), simultaneous redundancy replacement of 8 word lines can be performed; when the word line addressing address RA matches another type of word line mapping address Efsadd (e.g., a 2-word line mapping address), simultaneous redundancy replacement of 2 word lines can be performed; when the word line addressing address RA matches multiple different types of word line mapping addresses, mixed redundancy replacement of multiple different types of word line mapping addresses can be performed (explained in detail later). Therefore, the storage device 10 of this application has great flexibility when performing word line redundancy replacement operation. It can flexibly configure the type of word line mapping address according to actual needs to perform different types of word line redundancy replacement, which can not only provide repair efficiency, but also avoid wasting word line and redundant word line resources.

[0031] For ease of understanding, such as Figure 2-4 As shown, Figure 2-4 This is a schematic diagram of a storage device according to another embodiment of this application. In this embodiment, the application is specifically explained by way of example.

[0032] In this embodiment, the working principle of this application is described using the example of word line mapping addresses Efsadd stored in the programming memory circuit 12, which include two types of word line mapping addresses. Of course, those skilled in the art will understand that the word line mapping addresses Efsadd stored in the programming memory circuit 12 in this application are not limited to two types of word line mapping addresses, but may also include three types of word line mapping addresses, four types of word line mapping addresses, etc. This application does not limit this, as long as it conforms to the working principle described in this application.

[0033] Specifically, the word line mapping address Efsadd stored in the programming and storage circuit 12 includes a first type of word line mapping address and a second type of word line mapping address. The first type of word line mapping address corresponds to a first type of redundant word line group containing M redundant word lines, and the second type of word line mapping address corresponds to a second type of redundant word line group containing N redundant word lines. M and N are natural numbers, and M is not equal to N. In this embodiment, M = 8, N = 2, the first type of word line mapping address corresponds to a first type of redundant word line group containing 8 redundant word lines (i.e., 8 redundant word lines constitute one redundant word line group's word line mapping address), and the second type of word line mapping address corresponds to a second type of redundant word line group containing 2 redundant word lines (i.e., 2 redundant word lines constitute one redundant word line group's word line mapping address). It is understood that in other embodiments, the first type of word line mapping address and the second type of word line mapping address can also be other types of word line mapping addresses, such as 16-word line mapping addresses, 4-word line mapping addresses, etc.

[0034] like Figure 3 As shown, the address matching circuit 141 includes a first address matching circuit 1411 and a second address matching circuit 1412. The first address matching circuit 1411 can be used to match a first type of address, i.e., a first type address matching circuit. The second address matching circuit 1412 is used to match a second type of address, i.e., a second type address matching circuit. The redundant word line decoding circuit 142 includes a first redundant word line decoding circuit 1421 and a second redundant word line decoding circuit 1422. The first redundant word line decoding circuit 1421 can be a first type of redundant word line decoding circuit, and the second redundant word line decoding circuit 1422 can be a second type of redundant word line decoding circuit.

[0035] Specifically, when the address matching circuit 1411 determines that the word line addressing address RA matches the first type word line mapping address Efsadd, the address matching circuit 1411 selects the first redundant word line decoding circuit 1421 to perform redundant mapping replacement of the word line based on the first type word line mapping address Efsadd. When the address matching circuit 1412 determines that the word line addressing address RA matches the second type word line mapping address Efsadd, the address matching circuit 1412 selects the second redundant word line decoding circuit 1422 to perform redundant mapping replacement of the word line based on the second type word line mapping address Efsadd.

[0036] like Figure 4 As shown, the programming and storage circuit 12 includes a first programming unit 121 and a second programming unit 122, wherein the first programming unit 121 programs a first type of word line mapping address (e.g., ...). Figure 4 Efsadd shown <RA<14:3> The second programming unit 122 has a second type of word line mapping address (e.g., G<1:0>, flag>) programmed in it. Figure 4 Efsadd shown <RA<14:1> The first type of redundant word line group corresponding to the first type of word line mapping address includes M redundant word lines. In this embodiment, M=8, that is, the first type of redundant word line group includes 8 redundant word lines, which are used to implement the redundancy replacement of 8 word lines; the second type of redundant word line group corresponding to the second type of word line mapping address includes N redundant word lines. In this embodiment, N=2, that is, the second type of redundant word line group includes 2 redundant word lines, which are used to implement the redundancy replacement of 2 word lines.

[0037] Address matching circuit 141 receives word line addressing address RA<14:0> transmitted from command decoder 13 and determines whether word line addressing address RA<14:0> matches the cached word line mapping address.

[0038] Correspondingly, the redundant word line decoding circuit 142 includes a plurality of first latch units 14211 and a plurality of second latch units 14221 (exemplary, Figure 4Only one first latch unit 14211 and one first latch unit 14211 are shown in the figure (but the invention is not limited thereto), wherein each first latch unit 14211 is used to generate a corresponding redundant word line enable signal RWL_en to drive the matching first type word line mapping address Efsadd. <RA<14:3> The eight redundant word lines in the first type of redundant word line group corresponding to the flag> are mapped to replace a set of ordinary word lines corresponding to the word line addressing address RA<14:0>. Each second latch unit 14221 is used to generate the corresponding redundant word line enable signal RWL_en to drive the matching second type of word line mapping address Efsadd. <RA<14:1> The two redundant word lines in the second type of redundant word line group corresponding to the flag> are mapped to replace the set of ordinary word lines corresponding to the word line addressing address RA<14:0>.

[0039] Those skilled in the art will understand that a word-line addressed address is composed of multiple address signals. For example, in this application, a word-line addressed address may include a-bit address signals, which can be denoted as RA. <a-1:0>This refers to the address signal from bit 0 to bit a-1, where a is a preset value. In this embodiment, a = 15, so the word line addressing signal can be recorded as RA<(15-1=14):0>, that is, RA<14:0>.

[0040] The word-line mapped address Efsadd also includes multiple address signals, but the number of bits in its address signals is less than that of the word-line addressed address. It corresponds to the word-line addressed address RA. <a-1:0>The high-order address signal of the same number of bits. For example, a first-type word-line mapped address includes (ab) bits of high-order address signal, which can be written as Efsadd. <RA <a-1:b>>, where RA <a-1:b>Corresponding word line address RA <a-1:0>The high-order address signals from bit b to bit a-1 (a total of ab bits).

[0041] Therefore, during the comparison and judgment, when the word line address RA... <a-1:0>The high-order address signals from bit b to bit a-1 are respectively mapped to the first type word line address Efsadd. <RA <a-1:b>When the high-order address signals of bits (ab) in the > are consistent, then the word line addressing address RA <a-1:0>Mapped address Efsadd with first type word line <RA <a-1:b>>Match. Word line addressing address RA <a-1:0>The position address signals from bit 0 to bit (b-1) in the data do not need to be compared again.

[0042] Word line address RA <a-1:0>The position address signal from bit 0 to bit (b-1) in the array corresponds to 2 b One ordinary word line; due to the word line address RA <a-1:0>The positional address signals from bit 0 to bit (b-1) in the first type word line do not need to be mapped to the address Efsadd. <RA <a-1:b>>Compare and determine, that is, the first type word line mapping address Efsadd <RA <a-1:b>The corresponding first type of redundant word line group includes M=2 b One redundant word line, which executes M=2 b 2 redundant word lines b Redundant replacement of ordinary word lines. In this embodiment, b = 3, therefore the first type of word line mapping address can be recorded as Efsadd. <RA<14:3> > It compares the 3rd to 14th high-order address signals in the word line addressing address RA<14:0>, that is, the first address matching circuit 1411 determines whether the 3rd to 14th high-order address signals in the 15-bit address signal RA<14:0> of the word line addressing address match the first type word line mapping address Efsadd. <RA<14:3> The 12-bit high-order address signal is consistent with that in the >.

[0043] To determine whether the word line addressing address RA<14:0> is mapped to the first type word line address Efsadd <RA<14:3> > Match; if a match is found, then execute M=2 3 2 redundant word lines 3 Redundant replacement of a regular character line, i.e., redundant replacement of the 8-character line.

[0044] In addition, the first type word line mapping address may also include a 1-bit first identifier signal flag, then the first type word line mapping address can be recorded as Efsadd. <RA <a-1:b>The first flag signal is used to characterize whether the current first-type redundant word line group corresponding to the first-type word line mapping address is damaged. For example, the first-type redundant word line group includes 8 redundant word lines. However, if 6 of the redundant word lines in the current first-type redundant word line group corresponding to the first-type word line mapping address are also faulty, then the current first-type redundant word line group can be defined as damaged. Otherwise, even if the 8-word-line redundant word lines are replaced with 8-word-line ordinary word lines, 6 of the replaced 8 redundant word lines will still be faulty, and the repair will be of little significance.

[0045] Those skilled in the art will understand that, in some embodiments, the first flag signal is used to indicate that when the current first type redundant word line group corresponding to the first type word line mapping address is damaged, the next first type redundant word line group is sequentially assigned to the first type word line mapping address, and the next first type redundant word line group is used as the corresponding first type redundant word line group to perform the mapping replacement of M redundant word lines.

[0046] Correspondingly, the second type word line mapped address may include (ac) bits of high-order address signal and 1 bit of second identifier signal, which can be recorded as Efsadd <RA <a-1:c>,flag>。RA <a-1:c>>Corresponding word line address RA <a-1:0>The high-order address signals from bit c to bit a-1 (a total of ac bits).

[0047] During the comparison and judgment, when the word line address RA <a-1:0>The high-order address signals from bit c to bit a-1 are respectively mapped to the second type word line address Efsadd. <RA <a-1:c>When the high-order address signal of the (ac) bit in the word line addressing is consistent, then the word line addressing address RA <a-1:0>Mapped address Efsadd with first type word line <RA <a-1:c>>Match. Word line addressing address RA <a-1:0>The positional address signals from bit 0 to bit (c-1) do not need to be compared again. Type II word line mapped address Efsadd <RA <a-1:c>The corresponding second type of redundant word line group includes N=2 c One redundant word line, which executes N=2 c 2 redundant word lines c Redundant replacement of ordinary character lines.

[0048] In this embodiment, c = 1, therefore the second type word line mapping address can be recorded as Efsadd. <RA<14:1> The flag> is compared with the high-order address signals of bits 1 to 14 in the word line addressing address RA<14:0>. That is, the second address matching circuit 1412 determines whether the high-order address signals of bits 1 to 14 in the 15-bit address signal of the word line addressing address RA<14:0> match the second type word line mapping address Efsadd. <RA<14:1> The 14-bit high-order address signal in > is consistent to determine whether the word line addressing address RA<14:0> is consistent with the second type word line mapping address Efsadd. <RA<14:1> > Match; if a match is found, then execute N=2 1 2 redundant word lines 1 Redundant replacement of one ordinary character line, that is, redundant replacement of two character lines.

[0049] The second flag signal is used to indicate whether the current second-type redundant word line group corresponding to the second-type word line mapping address is damaged; if it is damaged, the next group of second-type redundant word line groups is assigned to the second-type word line mapping address in sequence, and the N redundant word lines in the next group of second-type redundant word line groups are replaced for redundancy.

[0050] Please refer to the following: Figure 2-4 The address matching circuit 141 is used to determine the word line addressing address RA. <a-1:0>Does it match the word line mapping address Efsadd cached in the programming memory circuit 12?

[0051] When the word line addresses the address RA <a-1:0>Matches a first-type word-line mapped address, for example, word-line addressed address RA. <a-1:0>The cached first type word line mapping address Efsadd <RA <a-1:b>,flag>(for example, Figure 4 Efsadd shown <RA<14:3> During the matching process (G<1:0>, flag>, where G<1:0> will be described later), the first address matching circuit 1411 selects the first redundant word line decoding circuit 1421, and the first latch unit 14211 receives all the first type word line mapping addresses Efsadd. <RA <a-1:b>,flag>.

[0052] The first redundant word line decoding circuit 1421 receives the word line address RA. <a-1:0>And each of them is mapped to the first type word line address Efsadd temporarily stored in each first latch unit 14211. <RA <a-1:b>The comparison is performed based on the first type word line mapping address Efsadd, which is matched with the flag. <RA <a-1:b>The location of the first latch unit 14211 stored in the flag (each first latch unit 14211 further includes M latches, each latch corresponds to one redundant word line enable signal RWL_en), generates the corresponding M redundant word line enable signals RWL_en, to drive the matched first type word line mapping address Efsadd <RA <a-1:b>The M redundant word lines in the first type of redundant word line group corresponding to flag> are mapped to the replacement word line address RA. <a-1:0>The corresponding set of ordinary character lines.

[0053] In this embodiment, M=8, a=15, b=3, therefore, the above is a redundant replacement of the figure-eight line.

[0054] Similarly, when the word line addresses the address RA <a-1:0>Matches a second-type word-line mapped address, for example, word-line addressed address RA. <a-1:0>The cached second type word line mapping address Efsadd <RA <a-1:c>,flag>(for example, Figure 4 Efsadd shown <RA<14:1> When matching (flag>), the second address matching circuit 1412 selects the second redundant word line decoding circuit 1422, and the second latch unit 14221 receives all the second type word line mapping addresses Efsadd. <RA <a-1:c>The second redundant word line decoding circuit 1422 receives the word line address RA. <a-1:0>And each one is mapped to the second type word line mapping address Efsadd temporarily stored in each second latch unit 14221. <RA <a-1:c>The comparison, flag> is based on the matching second-type word line mapping address Efsadd. <RA <a-1:c>The location of the second latch unit 14221 stored in the flag (each second latch unit 14221 includes N latches, and each latch corresponds to one redundant word line enable signal RWL_en) is used to generate the corresponding N redundant word line enable signals RWL_en to drive the matched second type word line mapping address Efsadd. <RA <a-1:c>The N redundant word lines in the second type of redundant word line group corresponding to flag> are mapped to replace the word line addressing address RA. <a-1:0>The corresponding set of ordinary character lines.

[0055] In this embodiment, N=2, a=15, c=1, therefore, the above is a redundant replacement of the 2-word line.

[0056] Furthermore, those skilled in the art will understand that the redundant word lines in the redundant memory array 112 may also be damaged during the manufacturing process, and may require redundancy replacement, i.e., redundant replacement of the redundant word lines. Therefore, in this application, the word line addressing address RA... <a-1:0>It may match more than one word line mapping address Efsadd.

[0057] Specifically, word-line addressing address RA <a-1:0>It may match not only a first-type word-line mapped address, but also at least one second-type word-line mapped address; for example, word-line addressed address RA. <a-1:0>high level <a-1:b>The first type word line mapping address Efsadd of a certain first latch unit 14211 cache <RA <a-1:b>,flag>(for example, Figure 4 Efsadd shown <RA<14:3> The expression (,G<1:0>,flag>) matches, and the word line address RA is also correct. <a-1:0>high level <a-1:c>The second type word line mapping address Efsadd of a certain second latch unit 14221 cache <RA <a-1:c>,flag>(for example, Figure 4 Efsadd shown <RA<14:1> ,flag>) match.

[0058] Those skilled in the art will understand that the first type word line mapping address Efsadd <RA <a-1:b>The address signal in ,flag> is RA <a-1:b>This corresponds to the address signals from bit b to bit a-1 in the word line addressing signal, for example, in this embodiment, Figure 4 The first type word line mapping address Efsadd shown <RA<14:3> ,G<1:0>,flag>, its address signal is RA<14:3>, which corresponds to the address signals of bits 3 to 14 in the word line addressing signal.

[0059] Type 2 word line mapping address Efsadd <RA <a-1:c>The address signal in ,flag> is RA <a-1:c>This corresponds to the address signals from bit c to bit a-1 in the word line addressing signal, for example, in this embodiment, Figure 4 The second type word line mapping address Efsadd shown <RA<14:1> The address signal of ,flag> is RA<14:1>, which corresponds to the address signals of bits 1 to 14 in the word line addressing signal.

[0060] When performing a matching judgment, the address matching circuit 141 only needs the first type word line mapped address Efsadd. <RA <a-1:b>,flag>Middle and high address signal RA <a-1:b>AND word line addressing signal RA <a-1:0>If they match, it is assumed that the word line addressing signal and the first type of word line mapping address Efsadd are consistent. <RA <a-1:b>,flag> matches; similarly, as long as the second type word line mapping address Efsadd <RA <a-1:c>The high-order address signal RA in the flag> <a-1:c>AND word line addressing signal RA <a-1:0>If they are consistent, then the word line addressing signal RA is considered to be consistent. <a-1:0>Mapped address Efsadd with type 2 word line <RA <a-1:c>The flag> match. Therefore, when the address matching circuit 141 performs the matching judgment, it may encounter word-line addressed address RA. <a-1:0>That is, the address Efsadd mapped to the first type word line. <RA <a-1:b>The flag matches, and also matches the second type word line mapping address Efsadd. <RA <a-1:c>,flag> Matching.

[0061] Specifically, in response to word-line address RA <a-1:0>Both the address mapped to the first type word line are Efsadd <RA <a-1:b>The flag matches, and also matches the second type word line mapping address Efsadd. <RA <a-1:c>If the flag matches, the first address matching circuit 1411 selects (or enables) the first redundant word line decoding circuit 1421 and outputs all first type word line mapping addresses Efsadd. <RA <a-1:b>,flag> and the second type word line mapping address Efsadd <RA <a-1:c>,flag> to redundant word line decoding circuit 142.

[0062] The redundant word line decoding circuit 142 is based on word line addressing address RA. <a-1:0>Type 1 word line mapping address Efsadd <RA <a-1:b>,flag> and the second type word line mapping address Efsadd <RA <a-1:c>The flag> generates the corresponding redundant word line enable signal RWL_en to drive the matched first type word line mapping address Efsadd. <RA <a-1:c>The M redundant word lines in the first type of redundant word line group corresponding to flag> are mapped to the replacement word line address RA. <a-1:0>The corresponding set of ordinary word lines, and the matching second type word line mapping address Efsadd <RA <a-1:c>The N redundant word lines in the second type of redundant word line group corresponding to flag> are mapped to replace the N redundant word lines in one group of the first type of redundant word line group, where N is less than M.

[0063] In this embodiment, based on the matched first type word line mapping address Efsadd <RA<14:3> ,G<1:0>,flag>, using the matched first type word line mapping address Efsadd <RA<14:3> The 8 redundant word lines in the first type of redundant word line group corresponding to G<1:0>,flag> are mapped to replace a group of 8 ordinary word lines corresponding to the word line addressing address RA<14:0>, performing 8-word line redundancy replacement; and based on the matching second type of word line mapping address Efsadd <RA<14:1> ,flag>, using the matched second type word line mapping address Efsadd <RA<14:1> The two redundant word lines in the second type of redundant word line group corresponding to flag> are mapped to replace the two redundant word lines in the first type of redundant word line group.

[0064] In other words, of the eight redundant word lines in the first type of redundant word line group, six may be good, while two adjacent redundant word lines may be damaged. Therefore, during redundancy replacement, of the eight ordinary word lines corresponding to the word line address RA<14:0>, six ordinary word lines are mapped to the six good redundant word lines in the first type of redundant word line group, and two ordinary word lines are mapped to the two redundant word lines in the second type of redundant word line group.

[0065] In this application, the first type word line mapped address may further include at least one set of (bc)-bit redundant word line replacement signals G. <b-c-1:0>Then the first type word line mapping address can be recorded as <RA <a-1:b> ,G <b-c-1:0>,flag>, for example Figure 4 Efsadd shown <RA<14:3> ,G<1:0>,flag>.

[0066] Among them, the first type word line mapping address <RA <a-1:b> ,G <b-c-1:0>The first type of redundant word line group corresponding to ,flag> can be divided into 2 (b-c) There are N=2 redundant word line subgroups. c The redundant word lines of the above (bc) bits are replaced by the signal G. <b-c-1:0>This is used to indicate a corresponding redundant word line subgroup in the first type of redundant word line group, where the redundant word lines may be faulty and need to be mapped and replaced by other redundant word lines.

[0067] In this embodiment, if b = 3, then the first type redundant word line group corresponding to the first type word line mapping address includes 8 redundant word lines; if c = 1, then the second type redundant word line group corresponding to the second type word line mapping address includes 2 redundant word lines.

[0068] Therefore, when bc = 2, the redundant word line replacement signal can be recorded as G<1:0>, a 2-bit signal. The 8 redundant word lines in the first type of redundant word line group can be divided into 2... 2 There are four redundant word line subgroups; each redundant word line subgroup consists of two adjacent redundant word lines.

[0069] When G<1:0>=00, it can indicate the first redundant word line subgroup in the first type of redundant word line group, where the redundant word lines may be faulty, that is, the 0th and 1st redundant word lines need to be replaced by other redundant word lines.

[0070] When G<1:0>=01, it can indicate the second redundant word line subgroup in the first type of redundant word line group, where the redundant word lines may be faulty, that is, the second and third redundant word lines need to be replaced by other redundant word lines.

[0071] When G<1:0>=10, it can indicate the third redundant word line subgroup in the first type of redundant word line group, where the redundant word lines may be faulty, that is, the 4th and 5th redundant word lines, which need to be replaced by other redundant word lines.

[0072] When G<1:0>=11, it can indicate the fourth redundant word line subgroup in the first type of redundant word line group, where the redundant word lines may be faulty, that is, the 6th and 7th redundant word lines, which need to be replaced by other redundant word lines.

[0073] In this embodiment, in response to the word line addressing address RA<14:0> matching the first type of word line mapping address Efsadd <RA<14:3> ,G<1:0>,flag> and the second type word line mapping address Efsadd <RA<14:1> ,flag>, and the first type word line mapping address Efsadd <RA<14:3> The flag also includes redundant word line replacement signals G<1:0>, then the first type of word line mapping address Efsadd is matched. <RA<14:3> The redundant word lines in the first type of redundant word line group corresponding to G<1:0>,flag> are used to map and replace a group of 8 ordinary word lines corresponding to the word line addressing address RA<14:0>, and the matched second type of word line mapping address Efsadd <RA<14:1> The redundant word lines in the second type of redundant word line group corresponding to flag> are used to map and replace the redundant word lines in the redundant word line subgroup indicated by the redundant word line replacement signal G<1:0> in the first type of redundant word line group.

[0074] Understandably, in response to word line addressing address RA<14:0> matching the first type word line mapping address Efsadd <RA<14:3> The first type word line mapping address also includes a (bc) bit redundant word line replacement signal G<1:0>. The first redundant word line decoding circuit 1421 masks the redundant word line enable signals of the (bc=2) bit redundant word line replacement signals in the redundant word line subgroup indicated by the (bc=2) bit redundant word line replacement signals in the first type redundant word line group, and generates a matching first type word line mapping address Efsadd. <RA<14:3> The redundant word line enable signal for the remaining 6 redundant word lines out of the 8 redundant word lines in the first type of redundant word line group, G<1:0>, flag>; in response to the word line addressing address RA<14:0> matching the second type of word line mapping address Efsadd <RA<14:1> The second redundant word line decoding circuit 1422 drives two redundant word lines in the second type redundant word line group corresponding to the matched second type word line mapping address. For example, the matched first type word line mapping address Efsadd <RA<14:3> The first type of redundant word line group corresponding to `G<1:0>,flag>` includes eight redundant word lines: RDN10, RDN11, RDN12, RDN13, RDN14, RDN15, RDN16, and RDN17. Among them, redundant word lines RDN16 and RDN17 are damaged and need to be replaced; the matching second type of word line mapping address is `Efsadd`. <RA<14:1> The second type of redundant word line group corresponding to flag> includes two redundant word lines: RDN26 and RDN27. Therefore, when performing redundancy replacement on the eight ordinary word lines WL0, WL11, WL12, WL13, WL14, WL15, WL16, and WL17 corresponding to the word line address RA<14:0>, the six redundant word lines RDN10, RDN11, RDN12, RDN13, RDN14, and RDN15 in the first type of redundant word line group are mapped to replace WL0, WL11, WL12, WL13, WL14, and WL15 in the eight ordinary word lines, respectively; G<1:0>=11, indicating the redundant word lines RDN16 and RDN17 in the fourth group of redundant word line subgroups, that is, the mapping jumps to RDN26 and RDN27 in the second type of redundant word line group, and these two redundant word lines are used to map and replace WL16 and WL17 in the eight ordinary word lines.

[0075] The above embodiment uses the first type word line mapping address Efsadd <RA<14:3> The working principle of this application is illustrated by using a set of redundant word line replacement signals G<1:0> as an example, where the word line addressing address matches a first-type word line mapping address and a second-type word line mapping address. However, those skilled in the art will understand that the first-type word line mapping address may also include multiple sets of redundant word line replacement signals G1<1:0>, G2<1:0>, etc., meaning that redundant word lines in multiple redundant word line subgroups within the first-type redundant word line group corresponding to the first-type word line mapping address are respectively replaced by redundant word lines in multiple second-type redundant word line groups corresponding to multiple second-type word line mapping addresses. For example, the 8 redundant word lines in the first-type redundant word line group are divided into 4 redundant word line groups. If 4 redundant word lines in 2 of the redundant word line groups are damaged, they are replaced by redundant word lines in the 2 second-type redundant word line groups corresponding to the 2 second-type word line mapping addresses.

[0076] Furthermore, in some embodiments, such as Figure 4 As shown, the programming and storage circuit 12 further includes a bit line programming unit 123, wherein at least one bit line mapped address Efsadd (e.g., ...) is programmed in the bit line programming unit 123. Figure 4 Efsadd shown <CA<9:3> The bit line mapping address Efsadd can be the address of a faulty bit line found during testing before the DRAM leaves the factory. Each bit line mapping address Efsadd can correspond to a redundant bit line in a redundant bit line group. By using the bit line mapping address Efsadd, the simultaneous mapping and replacement of multiple redundant bit lines in its corresponding redundant bit line group can be performed.

[0077] Correspondingly, the processing circuit 14 also includes a bit line latch unit 144. The bit line latch unit 144 is used to cache the bit line mapping address programmed by the bit line programming unit 123. Furthermore, the bit line latch unit 144 also receives the bit line addressing address CA<9:3> transmitted from the command decoder 13, and compares the bit line addressing address CA<9:3> with the bit line mapping address Efsadd. <CA<9:3> The flag determines whether the bit-line addressing address CA<9:3> matches the cached bit-line mapping address Efsadd. <CA<9:3> The flag> match, where the bit-line address CA can be the bit-line address that the user wants to access, and determines the bit-line address CA<9:3> and the cached bit-line mapping address Efsadd. <CA<9:3> Match the flag and generate the corresponding redundant bit line enable signal RBL_en.

[0078] In summary, the storage device 10 of the present application includes a storage array 11, a programming storage circuit 12, a command decoder 13, and a processing circuit 14. The processing circuit 14 is coupled to the programming storage circuit 12, the command decoder 13, and the storage array 11. Among them, the word line mapping addresses stored in the programming storage circuit 12 include at least two types of word line mapping addresses. Each type of word line mapping address corresponds to a type of redundant word line group, and the number of redundant word lines in various types of redundant word line groups is different. Furthermore, the processing circuit 14 can generate corresponding redundant word line enable signals in response to the word line addressing address matching at least one word line mapping address, so as to drive the redundant word lines in at least one redundant word line group corresponding to the matched at least one word line mapping address to map and replace a group of normal word lines corresponding to the word line addressing address. Therefore, the present application improves the efficiency and flexibility of storage chip repair.

[0079] Furthermore, when some of the first type of redundant word lines (M) in the first type of redundant word line group are also damaged, in an embodiment of the present invention, the second type of redundant word lines in the second type of redundant word line group are used to replace some of the first type of redundant word lines (N) to map and replace the normal word lines corresponding to the word line addressing address, without occupying an additional group of the first type of redundant word line group (M, where N < M), thus saving redundant word line resources. In addition, even if N ≥ M, when some of the first type of redundant word lines (M) in the first type of redundant word line group are damaged, in an embodiment of the present invention, the second type of redundant word lines (N) in the second type of redundant word line group can also be used to replace the first type of redundant word lines to map and replace the normal word lines corresponding to the word line addressing address, so as to avoid the situation where replacement cannot be achieved when the first type of redundant word lines in the first type of redundant word line group are exhausted.

[0080] The descriptions of the above embodiments tend to emphasize the differences between the embodiments. Their similarities can be referred to each other. For the sake of brevity, they will not be elaborated herein.

[0081] In several embodiments provided by the present application, it should be understood that the disclosed methods and related devices can be implemented in other ways. For example, the above-described related device embodiments are merely illustrative. For example, the division of modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication disconnection between each other can be through some interfaces. The indirect coupling or communication disconnection of devices or units can be in electrical, mechanical or other forms.

[0082] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0083] Those skilled in the art will readily recognize that numerous modifications and variations can be made to the apparatus and method while maintaining the teachings of this application. Therefore, the above disclosure should be considered limited only by the scope of the appended claims. < / a-1:b> < / a-1:b>

Claims

1. A storage device, characterized in that, include: A storage array includes a normal storage array and a redundant storage array, wherein redundant word lines in the redundant storage array are used to map and replace normal word lines in the normal storage array, so that redundant storage cells in the redundant storage array map and replace damaged normal storage cells in the normal storage array. The redundant storage array includes a first type of redundant word line group and a second type of redundant word line group, wherein the number of redundant word lines in the first type of redundant word line group and the second type of redundant word line group are different and both are greater than 1. The programming memory circuit is configured to store at least one word line mapping address, wherein each word line mapping address corresponds to a redundant word line of a redundant word line group; The command decoder is configured to generate corresponding word-line addressing addresses in response to user commands. A processing circuit is coupled to the programming and storage circuit, the command decoder, and the storage array; wherein the processing circuit is configured to receive the word line addressing address and the word line mapping address; in response to the word line addressing address matching at least one of the word line mapping addresses, generate a corresponding redundant word line enable signal to drive the redundant word line mapping in at least one redundant word line group corresponding to the matched at least one word line mapping address to replace a group of ordinary word lines corresponding to the word line addressing address; The word line mapping addresses stored in the programming and storage circuit include a first type of word line mapping address and a second type of word line mapping address, which correspond to the first type of redundant word line group and the second type of redundant word line group, respectively. Each word line mapping address includes an identification signal, which is used to characterize whether the first or second type redundant word line group currently allocated to the first or second type word line mapping address is damaged. If damaged, the next group of the first or second type redundant word line group will be allocated sequentially. The first type word line mapping address further includes a redundant word line replacement signal. In response to the word line addressing address matching a first type word line mapping address and a second type word line mapping address, and the first type word line mapping address further including the redundant word line replacement signal, the redundant word lines in the first type redundant word line group corresponding to the matched first type word line mapping address are driven to map and replace a group of ordinary word lines corresponding to the word line addressing address. The redundant word lines in the second type redundant word line group corresponding to the matched second type word line mapping address are used to map and replace the redundant word lines in the redundant word line subgroup indicated by the redundant word line replacement signal in the first type redundant word line group.

2. The storage device according to claim 1, characterized in that, The processing circuit includes: An address matching circuit is coupled to the programming memory circuit and the command decoder, wherein the address matching circuit is configured to cache the word line mapping address from the programming memory circuit, receive the word line addressing address from the command decoder, and compare the word line addressing address and the word line mapping address to determine whether the word line addressing address matches at least one of the word line mapping addresses.

3. The storage device according to claim 2, characterized in that, The processing circuit further includes: A redundant word line decoding circuit, coupled to the address matching circuit, wherein, in response to the address matching circuit determining that the word line addressing address matches at least one of the word line mapping addresses, the redundant word line decoding circuit is selected and receives the matched at least one word line mapping address from the address matching circuit, and generates a corresponding redundant word line enable signal based on the matched at least one word line mapping address to drive the redundant word line mapping in at least one of the redundant word line groups corresponding to the matched at least one word line mapping address to replace a group of ordinary word lines corresponding to the word line addressing address.

4. The storage device according to claim 1, characterized in that, The word line mapping addresses stored in the programming and storage circuit include at least a plurality of first-type word line mapping addresses and a plurality of second-type word line mapping addresses. Each first-type word line mapping address corresponds to a first-type redundant word line group, which includes M redundant word lines. Each second-type word line mapping address corresponds to a second-type redundant word line group, which includes N redundant word lines. M and N are natural numbers, and M is not equal to N.

5. The storage device according to claim 4, characterized in that, In response to the word line addressing address matching a first type word line mapping address, the address matching circuit outputs the matching first type word line mapping address to the redundant word line decoding circuit; The redundant word line decoding circuit generates a corresponding redundant word line enable signal based on the matched first type word line mapping address, so as to drive M of the redundant word lines in the first type redundant word line group corresponding to the matched first type word line mapping address to replace a group of ordinary word lines corresponding to the word line addressing address. or In response to the word line addressing address matching a second type word line mapping address, the address matching circuit outputs the matching second type word line mapping address to the redundant word line decoding circuit; The redundant word line decoding circuit generates a corresponding redundant word line enable signal based on the matched second type word line mapping address, so as to drive N redundant word lines in the second type redundant word line group corresponding to the matched second type word line mapping address to replace a group of ordinary word lines corresponding to the word line addressing address. or In response to the word line address matching a first type word line mapping address and a second type word line mapping address, the address matching circuit outputs the matched first type word line mapping address and second type word line mapping address to the redundant word line decoding circuit; The redundant word line decoding circuit generates a corresponding redundant word line enable signal based on the matched first type word line mapping address and the second type word line mapping address. This signal drives M redundant word lines in the first type redundant word line group corresponding to the matched first type word line mapping address to replace a group of ordinary word lines corresponding to the word line address. It also drives N redundant word lines in the second type redundant word line group corresponding to the matched second type word line mapping address to replace N redundant word lines in the corresponding first type redundant word line group, where N is less than M.

6. The storage device according to claim 4, characterized in that, The word line addressing address includes a bit address signal; The first type of word line mapping address includes (ab) bits of high-order address signal and 1 bit of first identifier signal, wherein each first type of word line mapping address corresponds to a first type of redundant word line group, and the first type of redundant word line group includes M=2 b The redundant word lines, wherein the first identification signal indicates whether a group of redundant word lines of the first type corresponding to the first type word line mapping address is damaged; in response to the address signal of the a-bit address signal of the word line addressing address being consistent with the high-bit address signal of the (ab)-bit address signal of the first type word line mapping address, the word line addressing address is matched with the first type word line mapping address. The second type of word line mapping address includes (ac) bits of high-order address signal and 1 bit of second identifier signal, wherein each second type of word line mapping address corresponds to a second type of redundant word line group, and the second type of redundant word line group includes N=2 c The redundant word lines, the second identification signal characterizes whether a group of redundant word lines of the second type corresponding to the second type word line mapping address is damaged; in response to the c-th to (a-1)-th high-order address signal in the a-bit address signal of the word line addressing address being consistent with the high-order address signal in the (ac)-th bit of the second type word line mapping address, the word line addressing address matches the second type word line mapping address; Where a, b, and c are integers, and a is greater than b, a is greater than c, and b is not equal to c.

7. The storage device according to claim 6, characterized in that, The first type of word line mapping address also includes a (bc) bit redundant word line replacement signal, wherein the first type of redundant word line group corresponding to the first type of word line mapping address can be divided into 2 (b-c) There are N=2 redundant word line subgroups. c The redundant word lines, wherein the (bc) bit redundant word line replacement signal is used to indicate a corresponding redundant word line subgroup in the first type of redundant word line group; In response to the word line addressing address matching a first type word line mapping address and a second type word line mapping address, wherein the first type word line mapping address further includes a (bc) bit redundant word line replacement signal, the redundant word lines in the first type redundant word line group corresponding to the matched first type word line mapping address are driven to map and replace a group of ordinary word lines corresponding to the word line addressing address, and the redundant word lines in the second type redundant word line group corresponding to the matched second type word line mapping address are used to map and replace the redundant word lines in the redundant word line subgroup indicated by the (bc) bit redundant word line replacement signal in the first type redundant word line group.

8. The storage device according to claim 7, characterized in that, The first type of redundant word line group corresponding to the first type of word line mapping address includes 8 redundant word lines, where M=8; The second type of redundant word line group corresponding to the second type of word line mapping address includes 2 redundant word lines, where N=2; The word line addressing address includes a 15-bit address signal, defined as ra<14:0>, where a=15; The first type of word line mapping address includes a 12-bit high-order address signal <14:3>, a 2-bit redundant word line replacement signal G <1:0>, and a first flag signal. The first type of word line mapping address is defined as efsadd<14:3, G<1:0>, flag>, where b=3; The second type of word line mapping address includes a 14-bit high-order address signal <14:1> and a second flag signal. The second type of word line mapping address is defined as efsadd<14:1, flag>, where c=1; Wherein, the redundant word line replacement signal G<1:0> in the first type of word line mapping address is a 2-bit redundant word line replacement signal, used to indicate that the redundant word lines in one of the four redundant word line subgroups need to be replaced by the redundant word lines in the second type of redundant word line group corresponding to the second type of word line mapping address.

9. The storage device according to claim 2, characterized in that, The processing circuit further includes: A normal word line decoding circuit is coupled to the address matching circuit, wherein, in response to the address matching circuit determining that neither the word line addressing address nor the word line mapping address matches, the normal word line decoding circuit is selected and receives the word line addressing address from the address matching circuit, and generates a corresponding normal word line enable signal based on the word line addressing address to drive the normal word line corresponding to the word line addressing address.

10. The storage device according to claim 7, characterized in that, The processing circuit further includes: A redundant word line decoding circuit, wherein the redundant word line decoding circuit includes a first type of redundant word line decoding circuit and a second type of redundant word line decoding circuit, wherein... In response to the word line addressing address matching the first type word line mapping address and the first type word line mapping address further including (bc) bits of redundant word line replacement signal, the first type redundant word line decoding circuit masks the redundant word line enable signal of N redundant word lines in the redundant word line subgroup indicated by the (bc) bits of redundant word line replacement signal in the first type redundant word line group, where bc = N, and generates the redundant word line enable signal of the remaining MN redundant word lines in the M redundant word lines of the first type redundant word line group corresponding to the matching first type word line mapping address; In response to the word line addressing address matching the second type word line mapping address, the second type redundant word line decoding circuit drives N redundant word lines in the second type redundant word line group corresponding to the matched second type word line mapping address.

11. The storage device according to claim 10, characterized in that, The processing circuit further includes: An address matching circuit, wherein the address matching circuit includes a first address matching circuit and a second address matching circuit, wherein... The first address matching circuit determines whether the address signal of the higher bits (bits b to (a-1)) of the a-bit address signal of the word line addressing address is consistent with the higher bits (bits ab) of the first type of word line mapping address. The second address matching circuit determines whether the address signal of the high-order bits from the c-th to the (a-1)-th bits in the a-bit address signal of the word line addressing address is consistent with the high-order address signal of the (ac)-th bit in the second type of word line mapping address.

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