Wafer structure with plate wave suppression

Abstract

The invention provides a wafer structure with plate wave suppression, and belongs to the technical field of semiconductors and microelectronics, and the wafer structure comprises a high sound velocity layer, a functional layer, a piezoelectric layer and an interdigital electrode which are sequentially arranged on a supporting substrate layer; the thickness Hhigh of the high sound velocity layer is 0.05 lambda-1 lambda, the thickness Hfunction of the functional layer is 0.05 lambda-0. 5 lambda, and the acoustic impedance of the functional layer is smaller than that of the high sound velocity layer. The wafer structure can weaken parasitic modes of different frequency doubling plate waves, effectively inhibits high-order plate waves, does not need extra technological processes, and is suitable for industrial production.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and microelectronics, and relates to a wafer structure with plate wave suppression. Background Art

[0002] With the development of communication technology, product terminals have put forward strict requirements on the performance of various devices. Filters are key components of communication systems. With the development of technology, there are more and more types of filters, from LCR filters to cavity filters, from LTCC ceramic filters to surface acoustic wave filters. The technology of filters is constantly developing. Since entering the LTE era, the role of surface acoustic wave filters in communication systems has become increasingly important. At the same time, with the development of communication technology, the requirements for filters are getting higher and higher. Especially with the advent of the fifth-generation mobile communication technology (5th-Generation, 5G), the filter industry faces major challenges and opportunities.

[0003] In recent years, a new type of surface acoustic wave structure consisting of an extremely thin single crystal piezoelectric film bonded to a supporting substrate has been rapidly developed. This multi-layer substrate structure has a higher quality factor (Q), a higher electromechanical coupling factor (K 2 ) and smaller temperature coefficient of frequency (TCF). Compared with ordinary SAW or temperature compensated SAW on traditional piezoelectric substrates, it has superior performance. However, if the substrate is not carefully designed, multilayer SAW may produce spurious responses in out-of-band frequencies due to high-order modes guided in the layers. Due to the different impedances of different layers in the multilayer substrate structure, this will lead to the generation of parasitic modes, causing interference at high frequencies. For TF-SAW (Thin-Film Snrface Aconstic Wave) and surface acoustic wave resonators with multilayer substrate structures, their high-order modes are very serious, which seriously affects the performance of the filter. Summary of the invention

[0004] In order to solve the technical problems existing in the prior art, the present invention provides a wafer structure with plate wave suppression, which can weaken parasitic modes of plate waves of different frequency doublings, effectively suppress high-order plate waves, and does not require additional process flows, and is suitable for industrial production.

[0005] In order to achieve the above technical effects, the present invention adopts the following technical solutions:

[0006] One of the purposes of the present invention is to provide a wafer structure with plate wave suppression, the wafer structure comprising a high acoustic velocity layer, a functional layer, a piezoelectric layer and interdigital electrodes sequentially arranged by a supporting substrate layer;

[0007] The thickness of the high-speed layer H high is 0.05λ~1λ, the thickness of the functional layer H function0.05λ~0.5λ;

[0008] The thickness of the high-speed layer H high , the thickness of the functional layer H function The thickness of the piezoelectric layer H piezo Satisfy the relationship: 1 / 3H piezo ≤ H function ≤ H piezo , H function ≤ H high ≤ 2H function ;

[0009] Where λ is the wavelength, and the thicknesses of the supporting substrate layer, high acoustic velocity layer, functional layer, piezoelectric layer, and interdigital electrodes are all normalized according to the wavelength;

[0010] The acoustic impedance of the functional layer is lower than the acoustic impedance of the high acoustic velocity layer.

[0011] As a preferred technical solution of the present invention, the thickness of the high acoustic velocity layer H high , the thickness of the functional layer H function The thickness of the piezoelectric layer H piezo Satisfying the relationship H high ≈ H function ≈ H piezo .

[0012] As a preferred technical solution of the present invention, the material of the supporting substrate layer is silicon, and the crystal orientation is (100) <100> 、(100) <110> or (111) <110> .

[0013] As a preferred technical solution of the present invention, the thickness of the supporting substrate layer is 5λ~300λ.

[0014] As a preferred technical solution of the present invention, the material of the high acoustic velocity layer includes any one of polysilicon, aluminum oxide or sapphire, or a combination of at least two of them.

[0015] As a preferred technical solution of the present invention, the material of the functional layer includes any one of silicon dioxide, tantalum oxide or lithium oxide, or a combination of at least two of them.

[0016] As a preferred technical solution of the present invention, the material of the piezoelectric layer is lithium tantalate, and the lithium tantalate has an Euler angle of (0°, 48°, 0°) or (0°, 40°, 0°).

[0017] The thickness H of the piezoelectric layer piezo It is 0.05λ~0.8λ.

[0018] As a preferred technical solution of the present invention, the interdigital electrode is partially embedded in the piezoelectric layer, and the thickness H of the embedded part satisfies the relationship 0 ≤ H ≤ 3 / 2Hpiezo .

[0019] As a preferred technical solution of the present invention, the material of the interdigital electrodes is aluminum or aluminum-copper alloy, the aperture of the interdigital electrodes is 15λ~30λ, and the number of the interdigital electrodes is less than 200.

[0020] As a preferred technical solution of the present invention, a wafer structure with plate wave suppression is connected in parallel to suppress the resonator.

[0021] As a preferred technical solution of the present invention, the resonance point of the suppression resonator is located near the high-order plate wave to suppress the high-order plate wave.

[0022] Compared with the prior art, the present invention has at least the following beneficial effects:

[0023] (1) The present invention provides a wafer structure with plate wave suppression, in which a surface acoustic wave device formed on the wafer structure can suppress high-order plate wave parasitic modes without affecting the fundamental mode propagation characteristics;

[0024] (2) The present invention provides a wafer structure with plate wave suppression, which is the same as a normal multi-layer substrate structure, and has the same process and equipment precision requirements as the conventional multi-layer substrate structure, and does not require additional process flow. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic structural diagram of a wafer structure with plate wave suppression provided in Embodiments 1-5 of the present invention;

[0026] Figure 2 is the admittance characteristic curve of the resonator of the wafer structure provided in Example 1 of the present invention;

[0027] Figure 3 is the admittance characteristic curve of the resonator of the wafer structure provided in Embodiment 2 of the present invention;

[0028] Figure 4 is the admittance characteristic curve of the resonator of the wafer structure provided in Embodiment 3 of the present invention;

[0029] Figure 5 The resonator structure provided in Embodiment 4 of the present invention;

[0030] Figure 6 is the admittance characteristic curve of the resonator of the wafer structure provided in Embodiment 4 of the present invention;

[0031] Figure 7 is the admittance characteristic curve of the resonator of the wafer structure provided in Example 5 of the present invention;

[0032] Figure 8 The wafer structure provided in Comparative Example 1 of the present invention;

[0033] Fig. 9 The admittance characteristic curve of the resonator with a wafer structure provided in Comparative Example 1 of the present invention;

[0034] Fig.10 The wafer structure provided in Comparative Example 2 of the present invention;

[0035] Fig.11 The admittance characteristic curve of the resonator of the wafer structure provided in Comparative Example 2 of the present invention;

[0036] In the figure: 1-support substrate layer, 2-high acoustic velocity layer, 3-functional layer, 4-piezoelectric layer, 5-interdigital electrodes, X-original resonator, Y-suppressed resonator.

[0037] The present invention is further described in detail below. However, the following examples are only simplified examples of the present invention and do not represent or limit the scope of protection of the present invention. The scope of protection of the present invention shall be subject to the claims. DETAILED DESCRIPTION

[0038] The technical solution of the present application is further described below through specific implementation methods.

[0039] A specific embodiment of the present invention provides a wafer structure with plate wave suppression, the wafer structure comprising a high acoustic velocity layer, a functional layer, a piezoelectric layer and interdigital electrodes sequentially arranged by a supporting substrate layer;

[0040] The thickness of the high-speed layer H high is 0.05λ~1λ, the thickness of the functional layer H function 0.05λ~0.5λ;

[0041] The thickness of the high-speed layer H high , the thickness of the functional layer H function The thickness of the piezoelectric layer H piezo Satisfy the relationship: 1 / 3H piezo ≤ H function ≤ H piezo , H function ≤ H high ≤ 2H function ;

[0042] Where λ is the wavelength, and the thicknesses of the supporting substrate layer, high acoustic velocity layer, functional layer, piezoelectric layer, and interdigital electrodes are all normalized according to the wavelength;

[0043] The acoustic impedance of the functional layer is lower than the acoustic impedance of the high acoustic velocity layer.

[0044] In the present invention, the required slowness curve is obtained by changing the properties of each layer, thereby reducing the stray response and suppressing the high-order plate wave.

[0045] In one embodiment of the present invention, the thickness of the high acoustic velocity layer is It can be 0.05λ, 0.1λ, 0.15λ, 0.2λ, 0.3λ, 0.4λ, 0.5λ, 0.6λ, 0.7λ, 0.8λ, 0.9λ or 1λ, etc. The thickness of the functional layer It can be 0.05λ, 0.1λ, 0.15λ, 0.2λ, 0.3λ, 0.4λ or 0.5λ, etc., but is not limited to the listed values. Other values ​​not listed within the above numerical ranges are also applicable.

[0046] In one specific embodiment of the present invention, the thickness H of the high acoustic velocity layer is high , the thickness of the functional layer H function The thickness of the piezoelectric layer H piezo Satisfying the relationship H high ≈ H function ≈ H piezo , the suppression effect of high-order plate waves is the best. The reason is that the thickness of each layer is controlled to obtain a flat slowness curve, reduce stray responses, and suppress high-order plate waves.

[0047] In a specific embodiment of the present invention, the material of the supporting substrate layer is silicon, and the crystal orientation is (100) <100> 、(100) <110> or (111) <110> .

[0048] In a specific embodiment of the present invention, the thickness of the supporting substrate layer is 5λ~300λ, such as 5λ, 10λ, 15λ, 20λ, 50λ, 100λ, 150λ, 200λ, 250λ or 300λ, but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0049] In a specific embodiment of the present invention, the material of the high acoustic velocity layer includes any one of polysilicon, aluminum oxide or sapphire, or a combination of at least two of them.

[0050] In a specific embodiment of the present invention, the material of the functional layer includes any one of silicon dioxide, tantalum oxide or lithium oxide, or a combination of at least two of them.

[0051] In a specific embodiment of the present invention, the material of the piezoelectric layer is lithium tantalate, and the lithium tantalate has an Euler angle of (0°, 48°, 0°) or (0°, 40°, 0°).

[0052] In one embodiment of the present invention, the thickness H of the piezoelectric layer is piezoIt is 0.05λ~0.8λ, such as 0.05λ, 0.1λ, 0.15λ, 0.2λ, 0.3λ, 0.4λ, 0.5λ, 0.6λ, 0.7λ or 0.8λ, but is not limited to the listed values, and other unlisted values ​​within the numerical range are also applicable.

[0053] In a specific embodiment of the present invention, the interdigital electrode is partially embedded in the piezoelectric layer, and the thickness H of the embedded portion satisfies the relationship 0 ≤ H ≤ 3 / 2H piezo .

[0054] In the present invention, the reason for limiting the relationship between the embedding depth of the interdigital electrodes and the thickness of the piezoelectric layer is to utilize the mass loading effect to enable the piezoelectric layer to obtain different excitation efficiencies, reduce stray responses, and suppress high-order plate waves.

[0055] In a specific embodiment of the present invention, the material of the interdigital electrode is aluminum or aluminum-copper alloy, the aperture of the interdigital electrode is 15λ~30λ, and the number of the interdigital electrodes is less than 200. Among them, the aperture of the interdigital electrode can be 15λ, 16λ, 18λ, 20λ, 22λ, 25λ, 28λ or 30λ, but is not limited to the listed values, and other values ​​not listed within the numerical range are also applicable.

[0056] In a specific embodiment of the present invention, a suppression resonator is connected in parallel with a resonator of a wafer structure having plate wave suppression, and a resonance point of the suppression resonator is located near a high-order plate wave to suppress the high-order plate wave.

[0057] To better illustrate the present invention and facilitate understanding of the technical solution of the present invention, typical but non-limiting embodiments of the present invention are as follows:

[0058] Example 1

[0059] This embodiment provides a wafer structure with plate wave suppression, and its structure is as follows Figure 1 As shown, the wafer structure includes a high acoustic velocity layer 2, a functional layer 3, a piezoelectric layer 4 and interdigital electrodes 5 which are sequentially arranged on a supporting substrate layer 1;

[0060] The support substrate layer 1 is made of silicon, with a crystal orientation of (100) <100> , thickness is 50λ;

[0061] The material of the high acoustic velocity layer 2 is polysilicon, and the thicknesses are 0.2λ, 0.16λ, 0.13λ and 0.1λ;

[0062] The material of the functional layer 3 is silicon dioxide, and the thickness is 0.1λ;

[0063] The material of the piezoelectric layer 4 is lithium tantalate with an Euler angle of (0°, 48°, 0°) and a thickness of 0.13λ;

[0064] The material of the interdigital electrode 5 is aluminum-copper alloy, the aperture is 20 times the wavelength, and the embedding depth H is 0.

[0065] The resonator frequency response properties of the wafer structures with different high acoustic velocity layer thicknesses provided in this embodiment are tested, and the results are as follows: Figure 2 As shown in the figure, it can be seen that with the decrease in the thickness of the high-acoustic-velocity layer, the amplitude of the plate wave response of the resonator on the right side of the 1.5-fold frequency is significantly improved, but the amplitude of the plate wave response on the left side of the 1.5-fold frequency and around the 2-fold frequency is not improved. It can be seen that the thickness of the high-acoustic-velocity layer has a greater impact on the plate wave on the right side of the 1.5-fold frequency.

[0066] Example 2

[0067] This embodiment provides a wafer structure with plate wave suppression, the wafer structure comprising a high acoustic velocity layer 2, a functional layer 3, a piezoelectric layer 4 and interdigital electrodes 5 which are sequentially arranged on a supporting substrate layer 1;

[0068] The support substrate layer 1 is made of silicon, with a crystal orientation of (100) <100> , thickness is 50λ;

[0069] The material of the high acoustic velocity layer 2 is polysilicon; the material of the functional layer 3 is silicon dioxide; and the thicknesses of the high acoustic velocity layer 1, the functional layer 2 and the piezoelectric layer 3 are the same, which are 0.13λ, 0.08λ, 0.06λ and 0.04λ respectively;

[0070] The material of the piezoelectric layer 3 is lithium tantalate with Euler angles of (0°, 48°, 0°);

[0071] The material of the interdigital electrode 5 is aluminum-copper alloy, the aperture is 20 times the wavelength, and the embedding depth H is 0.

[0072] The resonator frequency response properties of the wafer structures with different high acoustic velocity layer thicknesses provided in this embodiment are tested, and the results are as follows: Figure 3 As shown, it can be seen that when the thickness of the high acoustic velocity layer, the functional layer and the piezoelectric layer are the same, as the thickness decreases, the plate wave response amplitude of the resonator at the 1.5th and 2nd frequencies is significantly improved; when the thickness is less than 0.04λ, the main mode will shift.

[0073] Example 3

[0074] This embodiment provides a wafer structure with plate wave suppression, the wafer structure comprising a high acoustic velocity layer 2, a functional layer 3, a piezoelectric layer 4 and interdigital electrodes 5 which are sequentially arranged on a supporting substrate layer 1;

[0075] The support substrate layer 1 is made of silicon, with a crystal orientation of (100) <100> 、(100) <110> or (111) <110> , thickness is 50λ;

[0076] The material of the high acoustic velocity layer 2 is polysilicon, and the thickness is 0.2λ;

[0077] The material of the functional layer 3 is silicon dioxide, and the thickness is 0.1λ;

[0078] The material of the piezoelectric layer 4 is lithium tantalate with an Euler angle of (0°, 48°, 0°) and a thickness of 0.13λ;

[0079] The material of the interdigital electrode 5 is aluminum-copper alloy, the aperture is 20 times the wavelength, and the embedding depth H is 0.

[0080] The resonator frequency response properties of the wafer structure provided in this embodiment are tested, and the results are as follows: Figure 4 As shown, it can be seen that for silicon support substrate layers with different crystal orientations, (111) <110> The amplitude of the plate wave response of the resonator with crystal orientation structure is significantly reduced at around 1.5 times and 2 times the frequency.

[0081] Example 4

[0082] In this embodiment, except for connecting a suppression resonator in parallel, the other conditions are the same as those in the first embodiment. Figure 5 As shown. Among them, the main mode frequency of the suppressed resonator needs to be close to the plate wave frequency.

[0083] The frequency response properties of the resonator of this embodiment are tested, and the results are as follows: Figure 6 As shown, it can be seen that after adding the parallel suppression resonator, the amplitude of the plate wave response of the resonator at around 2 times the frequency decreases.

[0084] Example 5

[0085] This embodiment provides a wafer structure with plate wave suppression, the wafer structure comprising a high acoustic velocity layer 2, a functional layer 3, a piezoelectric layer 4 and interdigital electrodes 5 which are sequentially arranged on a supporting substrate layer 1;

[0086] The support substrate layer 1 is made of silicon, with a crystal orientation of (100) <100> , thickness is 50λ;

[0087] The material of the high acoustic velocity layer 2 is polysilicon, and the thickness is 0.2λ;

[0088] The material of the functional layer 3 is silicon dioxide, and the thickness is 0.1λ;

[0089] The material of the piezoelectric layer 4 is lithium tantalate with an Euler angle of (0°, 48°, 0°) and a thickness of 0.13λ;

[0090] The material of the interdigital electrode 5 is aluminum-copper alloy, the aperture is 20 times the wavelength, and the embedding depth H is 0.065λ, 0.13λ, and 0.195λ respectively.

[0091] The resonator frequency response properties of the wafer structure provided in this embodiment are tested, and the results are as follows: Figure 7 As shown, it can be seen that when H increases, the amplitude of the plate wave response of the resonator at 2 times the frequency improves, but the amplitude of the plate wave response at around 1.5 times the frequency deteriorates slightly.

[0092] Comparative Example 1

[0093] Except that the high sound velocity layer 2 is not provided, the other conditions of this comparative example are the same as those of Example 1. Figure 8 shown.

[0094] The resonator frequency response properties of the wafer structure provided in this comparative example were tested, and the results are as follows: Fig. 9 As shown, it can be seen that for the multilayer structure without a high acoustic velocity layer, the amplitude of the plate wave response of the resonator decreases around the 2nd frequency.

[0095] Comparative Example 2

[0096] In this comparative example, except that the material of the high acoustic velocity layer 2 is polysilicon, the thickness is 0.2λ, and the functional layer 3 is not provided, the other conditions are the same as those of Example 1. Fig.10 shown.

[0097] The resonator frequency response properties of the wafer structure provided in this comparative example were tested, and the results are as follows: Fig.11 As shown, it can be seen that for the multilayer structure without a functional layer, the amplitude of the plate wave response of the resonator decreases at around 2 times the frequency, and the amplitude of the plate wave response increases at around 1.5 times the frequency.

[0098] The applicant declares that the present invention illustrates the detailed structural features of the present invention through the above-mentioned embodiments, but the present invention is not limited to the above-mentioned detailed structural features, that is, it does not mean that the present invention must rely on the above-mentioned detailed structural features to be implemented. Those skilled in the art should understand that any improvement of the present invention, equivalent replacement of the components selected by the present invention, addition of auxiliary components, selection of specific methods, etc., all fall within the protection scope and disclosure scope of the present invention.

[0099] The preferred embodiments of the present invention are described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.

[0100] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.

[0101] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims

1. A wafer structure with plate wave suppression, characterized in that: The wafer structure comprises a high acoustic velocity layer, a functional layer, a piezoelectric layer and interdigital electrodes which are sequentially arranged on a supporting substrate layer; The thickness of the high acoustic velocity layer H high is 0.05λ~1λ, and the thickness of the functional layer H function 0.05λ~0.5λ; The thickness of the high acoustic velocity layer H high , the thickness of the functional layer H function The thickness of the piezoelectric layer H piezo Satisfy the relationship: 1 / 3 H piezo ≤ H function ≤ H piezo , H function ≤ H high ≤ 2 H function ; Wherein, λ is the wavelength, and the thicknesses of the support substrate layer, the high acoustic velocity layer, the functional layer, the piezoelectric layer and the interdigital electrodes are all normalized according to the wavelength; The acoustic impedance of the functional layer is smaller than the acoustic impedance of the high acoustic velocity layer.

2. The wafer structure with plate wave suppression according to claim 1, characterized in that: The thickness of the high acoustic velocity layer H high The thickness of the functional layer H function The thickness of the piezoelectric layer H piezo Satisfy the relationship H high ≈ H function ≈ H piezo .

3. The wafer structure with plate wave suppression according to claim 1, characterized in that: The support substrate layer is made of silicon, and its crystal orientation is (100). <100> 、(100) <110> or (111) <110> ; The thickness of the supporting substrate layer is 5λ~300λ.

4. The wafer structure with plate wave suppression according to claim 1, characterized in that: The material of the high acoustic velocity layer includes any one of polysilicon, aluminum oxide or sapphire or a combination of at least two thereof; The material of the functional layer includes any one of silicon dioxide, tantalum oxide or lithium oxide, or a combination of at least two of them.

5. The wafer structure with plate wave suppression according to claim 1, characterized in that: The material of the piezoelectric layer is lithium tantalate, and the lithium tantalate has an Euler angle of (0°, 48°, 0°) or (0°, 40°, 0°).

6. The wafer structure with plate wave suppression according to claim 1, characterized in that: The thickness of the piezoelectric layer H piezo It is 0.05λ~0.8λ.

7. The wafer structure with plate wave suppression according to claim 1, characterized in that: The interdigital electrode is partially embedded in the piezoelectric layer, and the thickness H of the embedded part satisfies the relationship 0 ≤ H ≤ 3 / 2 H piezo .

8. The wafer structure with plate wave suppression according to claim 1, characterized in that: The material of the interdigital electrodes is aluminum or aluminum-copper alloy, the aperture of the interdigital electrodes is 15λ~30λ, and the number of the interdigital electrodes is less than 200.

9. The wafer structure with plate wave suppression according to claim 1, characterized in that: The wafer structure with plate wave suppression suppresses the resonator in parallel.

10. The wafer structure with plate wave suppression according to claim 9, characterized in that: The resonance point of the suppression resonator is located near the high-order plate wave to suppress the high-order plate wave.

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