A Schottky barrier diode and a method for manufacturing the same

Abstract

The invention discloses a Schottky barrier diode and a manufacturing method thereof. The trench of the diode is formed into a step shape by three cylindrical openings of upper, middle and lower parts; the trench is filled with conductive polysilicon; the dielectric layer isolates the conductive polysilicon from the epitaxial layer of the inner wall of the trench, and the dielectric layer of the side wall of the upper cylindrical opening and the inner wall of the lower cylindrical opening is relatively thick, and the dielectric layer of the side wall of the middle cylindrical opening is relatively thin, so that the dielectric layer of the inner wall of the trench forms a distribution of thick upper and lower parts and thin middle parts. Since the dielectric layer at the bottom of the trench is thicker, the voltage drop increases when reverse biased, thereby improving the reverse blocking capability of the device; the dielectric layer in the middle of the trench is thin, which is conducive to the formation of depletion pinch-off in the mesa epitaxial layer when reverse biased, thereby improving the reverse blocking performance of the device; the dielectric layer at the top of the trench is thick, and only a small amount of polysilicon is needed to complete the trench filling, thereby reducing the cost, and also increasing the distance between the polysilicon on the upper surface of the device and the epitaxial layer, thereby weakening the diffusion of polysilicon doped impurities to the epitaxial layer through the barrier metal during the barrier alloy process, thereby improving the reverse blocking leakage.

Description

Technical Field

[0001] The invention relates to a semiconductor device, and in particular to a Schottky barrier diode and a manufacturing method thereof. Background Art

[0002] As a conversion device from AC to DC, the rectifier device requires unidirectional conduction characteristics, that is, low turn-on voltage and small on-resistance when forward-biased, and high blocking voltage and small reverse leakage when reverse-biased. Schottky barrier diodes have been used in power supply applications as rectifier devices for decades. Due to their advantages of low forward turn-on voltage and fast switching speed, they are very suitable for use in switching power supplies and high-frequency applications.

[0003] Schottky barrier diode is a semiconductor device made by using the metal-semiconductor junction principle formed by the contact between metal and semiconductor. Traditional planar Schottky barrier diode devices are usually composed of low-doping concentration N － The epitaxial layer and the metal layer deposited on the top surface form a Schottky barrier contact. The work function difference between the metal and N-type single crystal silicon forms a barrier. The height of the barrier determines the characteristics of the Schottky barrier diode. A lower barrier can reduce the forward conduction turn-on voltage, but it will increase the reverse leakage and reduce the reverse blocking voltage; conversely, a higher barrier will increase the forward conduction turn-on voltage, while reducing the reverse leakage and enhancing the reverse blocking ability. However, the traditional planar Schottky barrier diode generally has large reverse leakage and low reverse blocking voltage. In response to the above problems, the trench Schottky barrier diode was invented, which has a low forward conduction turn-on voltage while overcoming the shortcomings of the above-mentioned planar Schottky barrier diode.

[0004] The notable feature of the trench Schottky barrier diode is that － There are several epitaxial layers extending into N － A trench in the epitaxial layer, an oxide layer covering the surface of the trench, and a conductive material filled therein. For example, US Pat. No. 5,365,102 discloses a trench Schottky barrier diode, wherein the device structure of one embodiment is as shown in the attached figure. Figure 1 As shown in the figure, it is a trench Schottky barrier diode structure commonly used in the current prior art. As can be seen from the figure, the silicon wafer used to make the diode is made of highly doped N + Substrate 301 and lower doped N － The epitaxial layer 302 is formed, and a series of trenches 303 are prepared in N － In the epitaxial layer 302, there is an N-type single crystal silicon mesa structure 304 between the grooves 303, a silicon dioxide layer 305 is grown on the sidewalls of the grooves 303, and a metal layer 306 covers the upper surface of the entire structure and contacts the top surface of the single crystal silicon mesa structure 304 to form a Schottky barrier contact; +A cathode metal layer 307 is deposited on the bottom surface of the substrate 301. Due to the presence of the composite structure composed of the groove 303, the silicon dioxide layer 305, and the conductive material 306 in the groove, the electric field distribution of the device changes when the device is reverse biased, the electric field intensity in the bottom area of ​​the groove appears a peak, the free carriers in the mesa structure 304 are completely exhausted, and the electric field intensity reaching the Schottky barrier is reduced, thereby enhancing the reverse voltage blocking capability of the device and reducing reverse leakage.

[0005] However, there are still some problems with the trench Schottky barrier diode structure in the prior art, the main problems exposed include: 1) when forward conduction occurs, the area occupied by the trench structure cannot conduct current, causing the current to be crowded in the semiconductor of the table, making the forward conduction voltage drop of the trench Schottky barrier diode larger; 2) when reverse biased, the electric field strength in the bottom area of ​​the trench is the largest, the curvature radius of the bottom structure is small, or the thickness of the oxide layer at the bottom of the trench is thin or uneven due to the limitation of the step coverage ability, which can lead to uneven distribution of the electric field strength and excessive local electric field strength, resulting in a decrease in the reverse voltage drop blocking ability of the device, and a decrease in the reliability and life of the device; 3) when reverse biased, it is necessary to achieve complete depletion in the table to obtain the reverse leakage and device reliability and life that meet the requirements.

[0006] In summary, the existing trench Schottky barrier diode structure still has certain defects, and its performance needs to be further optimized to improve device reliability and simplify the device manufacturing method to reduce costs. Summary of the invention

[0007] In view of the above-mentioned defects of the prior art, the object of the present invention is to provide a Schottky barrier diode and a method for manufacturing the same, so as to improve the above-mentioned deficiencies of the existing trench Schottky barrier diode, while further improving the performance and reliability of the device and optimizing the manufacturing cost.

[0008] To achieve the above object, the present invention adopts the following technical solution.

[0009] The present invention first provides a Schottky barrier diode, comprising:

[0010] A semiconductor substrate heavily doped with a first conductivity type;

[0011] A semiconductor epitaxial layer lightly doped with a first conductivity type located on the upper surface of the substrate;

[0012] A series of periodically arranged grooves located in the epitaxial layer, opening at the upper surface of the epitaxial layer and extending into the epitaxial layer; wherein the epitaxial layer between adjacent grooves forms a mesa structure;

[0013] Conductive polysilicon heavily doped with a first conductivity type filled in the trench;

[0014] A first isolation dielectric layer covering the inner wall of the trench and used to isolate the conductive polysilicon from the epitaxial layer;

[0015] A Schottky barrier metal layer covering the upper surface of the epitaxial layer in the mesa structure region;

[0016] an ohmic contact metal layer covering the upper surface of the conductive polysilicon;

[0017] A second isolation dielectric layer formed by extending upward from the first isolation dielectric layer and isolating the Schottky barrier metal layer and the ohmic contact metal layer;

[0018] an anode metal layer covering the upper surface of the Schottky barrier diode;

[0019] And a cathode metal layer is located on the lower surface of the substrate, and the lower surface of the substrate forms an ohmic contact with the cathode metal layer.

[0020] Among them, the groove is composed of three cylindrical openings connected at the top, middle and bottom, which are the upper cylindrical opening, the middle cylindrical opening and the lower cylindrical opening from top to bottom; and the inner diameters of the upper cylindrical opening and the lower cylindrical opening are both larger than the inner diameter of the middle cylindrical opening, and the inner diameter of the lower cylindrical opening is larger than the inner diameter of the upper cylindrical opening; the connecting parts of the upper cylindrical opening and the middle cylindrical opening, and the middle cylindrical opening and the lower cylindrical opening are all stepped.

[0021] The first isolation dielectric layer is composed of three parts: a first upper isolation dielectric layer, a first middle isolation dielectric layer and a first lower isolation dielectric layer, wherein the first lower isolation dielectric layer covers the inner wall of the lower cylindrical opening of the groove, the first upper isolation dielectric layer covers the side wall of the upper cylindrical opening; the first middle isolation dielectric layer covers the inner wall of the middle cylindrical opening. Compared with the first upper isolation dielectric layer and the first lower isolation dielectric layer, the thickness of the first middle isolation dielectric layer is the smallest. Furthermore, the first upper isolation dielectric layer and the first lower isolation dielectric layer are formed by synchronous process, and the thickness of the two is consistent; for example, in Embodiment 1 of the present invention, they are formed by in-situ thermal oxidation on the silicon epitaxial layer on the inner wall of the groove and subsequent oxide layer deposition, and the thickness of the two is consistent.

[0022] Further, the inner diameter of the upper cylindrical opening is 0.15 microns to 1.2 microns; the inner diameter of the middle cylindrical opening is 0.1 microns to 0.6 microns; the inner diameter of the lower cylindrical opening is 0.2 microns to 2 microns, and the difference between the inner diameter of the lower cylindrical opening and the inner diameter of the middle cylindrical opening is greater than or equal to 0.1 microns, and the difference between the inner diameter of the upper cylindrical opening and the inner diameter of the middle cylindrical opening is greater than or equal to 0.01 microns.

[0023] Furthermore, the thickness of the first middle isolation dielectric layer is 0.05 microns to 0.15 microns, the thickness of the first upper isolation dielectric layer and the first lower isolation dielectric layer is 0.1 microns to 0.6 microns, and the thickness of the first middle isolation dielectric layer is smaller than the thickness of the first upper isolation dielectric layer and the thickness of the first lower isolation dielectric layer, and is at least less than 0.01 microns.

[0024] Furthermore, a second conductivity type ion implantation region is provided in the epitaxial layer region at the bottom of the trench.

[0025] The upper cylindrical opening, the middle cylindrical opening and the lower cylindrical opening of the groove are all cylindrical. Compared with the cylindrical opening with a larger opening at the bottom of the groove, the cylindrical opening structure with a relatively reduced opening in the middle and upper parts increases the Schottky barrier area of ​​the mesa structure; at the same time, in order to improve the tip discharge enhancement that may be formed by the reduction of the upper opening, the opening size of the lower cylindrical opening of the groove is widened so that the groove bottom forms a structure with an enlarged curvature radius, thereby avoiding the tip discharge enhancement.

[0026] Furthermore, the isolation dielectric layer is an oxide layer. Furthermore, the second isolation dielectric layer and the first isolation dielectric layer are deposited and formed simultaneously.

[0027] It should be noted that, in the embodiment of the present invention, there is a cavity inside the conductive polysilicon, and the cavity is formed during the conductive polysilicon deposition process. However, in the present invention, the cavity is not necessary, and if the conductive polysilicon deposition technology can control the cavity not to be generated, eliminating the cavity does not affect the technical effect of the present invention.

[0028] Furthermore, the Schottky barrier metal layer and the ohmic contact metal layer are formed by alloying the same metal deposited simultaneously.

[0029] Furthermore, the first conductivity type is N-type, and the second conductivity type is P-type.

[0030] The present invention also provides a method for manufacturing the Schottky barrier diode, which comprises the following steps.

[0031] S1. Growing a semiconductor epitaxial layer lightly doped with a first conductivity type on a semiconductor substrate heavily doped with a first conductivity type.

[0032] S2. Forming a second dielectric layer on the upper surface of the epitaxial layer.

[0033] S3. Forming a first dielectric layer on the surface of the second dielectric layer.

[0034] S4. Perform photolithography on the first dielectric layer to define a first columnar opening pattern, wherein the lateral opening size of the first columnar opening pattern is consistent with the inner diameter of the middle columnar opening; selectively remove the first dielectric layer not protected by the photoresist to expose the second dielectric layer; selectively remove the exposed second dielectric layer to expose the epitaxial layer corresponding to the first columnar opening pattern, and then remove the photoresist on the first dielectric layer; and use the first dielectric layer retained after removing the photoresist as a first dielectric hard mask.

[0035] S5. Using the first dielectric hard mask as protection, selectively etch the exposed epitaxial layer using a dry etching method to form a first columnar opening in the epitaxial layer. At this time, the surface of the epitaxial layer between the first columnar openings is still covered by the second dielectric layer and the first dielectric hard mask thereon.

[0036] S6. Forming a third dielectric layer on the entire surface of the structure.

[0037] S7. The third dielectric layer is selectively etched by dry etching to expose the epitaxial layer at the bottom of the first columnar opening, and the third dielectric layer located above the first dielectric layer is also removed synchronously; at this time, the surface of the epitaxial layer between the first columnar openings is still covered with the second dielectric layer and the first dielectric layer thereon, i.e., the first dielectric hard mask, and at this time, the third dielectric layer covering the side wall of the first columnar opening is used as the third dielectric hard mask.

[0038] S8. Using the first dielectric hard mask and the third dielectric hard mask as protection, selectively etch the exposed epitaxial layer using a dry etching method.

[0039] S9. Continue to use the first dielectric hard mask and the third dielectric hard mask as protection, and selectively etch the exposed epitaxial layer using a xenon difluoride dry etching method to form a second columnar opening.

[0040] S10. Continue to use the first dielectric hard mask and the third dielectric hard mask as protection, and use an ion implantation method to implant second conductive type doping impurities into the exposed epitaxial layer at the bottom of the second columnar opening.

[0041] S11. selectively remove the third dielectric covering the upper portion of the first cylindrical opening sidewall by dry etching to expose the epitaxial layer on the upper portion of the first cylindrical opening sidewall, wherein the exposed height of the upper portion of the first cylindrical opening sidewall is consistent with the height of the upper cylindrical opening of the groove.

[0042] S12. Selectively remove the first dielectric hard mask by wet etching.

[0043] S13. Using the second dielectric covering the surface of the epitaxial layer between the first columnar openings as the second dielectric hard mask, and the third dielectric still retained at the lower part of the sidewall of the first columnar opening as the fourth hard mask, under the protection of the second dielectric hard mask and the fourth hard mask, adopting the thermal oxidation growth method, in-situ thermal oxidation growth of an oxide layer on the exposed epitaxial layer, i.e., preliminarily forming the first upper isolation dielectric layer and the first lower isolation dielectric layer, which respectively cover the upper part of the sidewall of the first columnar opening and the inner wall of the second columnar opening formed in step S9, at which time the formation of the upper columnar opening and the lower columnar opening is also completed synchronously, and the mesa structure composed of the epitaxial layer located between the upper columnar opening is also formed synchronously; at the same time, the thermal process of the growth of the oxide layer promotes the diffusion of the second conductive type doped impurities to form a preliminary ion implantation area.

[0044] S14. Selectively remove the second dielectric hard mask and the fourth hard mask by a wet etching method.

[0045] S15. After step S14 is completed, an oxide layer is deposited on the surface of the entire structure formed. At this time, the oxide layer deposited on the lower part of the side wall of the first columnar opening constitutes the first middle isolation dielectric layer; at this time, the final first upper isolation dielectric layer and the first lower isolation dielectric layer are also completely formed; at this time, the middle columnar opening of the trench is also formed synchronously; at the same time, in the thermal process of the growth of the oxide layer, the second conductive type doping impurities are further diffused to complete the formation of the ion implantation area.

[0046] S16. Conductive polysilicon is deposited on the surface of the entire structure formed after step S15 is completed; the conductive polysilicon outside the groove is selectively removed by dry etching, and the upper surface of the conductive polysilicon filled in the groove is made flush with the upper surface of the epitaxial layer of the mesa structure; since the first upper dielectric isolation layer located on the side wall of the upper columnar opening has a large thickness, only a small amount of polysilicon is needed to fill the groove; at the same time, during the polysilicon deposition process, the above-mentioned voids may be formed inside the conductive polysilicon filling the groove.

[0047] S17. Adopt dry etching or wet etching to selectively remove the oxide layer on the surface of the mesa structure, and retain the oxide layer extending upward from the first upper isolation dielectric layer and surrounding the upper surface opening of the groove. The retained oxide layer constitutes the second isolation dielectric layer, which is used to isolate the Schottky barrier metal layer and the ohmic contact metal layer to be formed.

[0048] S18. After step S17 is completed, a first metal layer is deposited on the surface of the entire structure. After the alloying process, the first metal layer forms a Schottky barrier contact with the upper surface of the epitaxial layer of the mesa structure, that is, the Schottky barrier metal layer is formed, and forms an ohmic contact with the upper surface of the conductive polysilicon filled in the groove, that is, the ohmic contact metal layer is formed.

[0049] S19. Depositing an anode metal layer on the entire surface of the structure after step S18 is completed.

[0050] S20. Thinning the substrate by grinding and etching the lower surface of the substrate, and then depositing a cathode metal layer on the lower surface of the substrate.

[0051] In the above manufacturing process, the lateral size of the second cylindrical opening formed in step S9 is larger than the lateral opening size of the first cylindrical opening formed in step S5; and the lateral opening size of the first cylindrical opening formed in step S5 is 0.1-0.6 microns; in the step S13, the inner diameters of the upper cylindrical opening and the lower cylindrical opening formed are 0.15-1.2 microns and 0.2-2 microns respectively.

[0052] Further, the second cylindrical opening formed in step S9 and the first cylindrical opening formed in step S5 are both cylindrical.

[0053] Further, in step S15, the thickness of the first middle isolation dielectric layer formed is 0.05-0.15 microns; and after step S15 is completed, the thickness of the first upper isolation dielectric layer and the first lower isolation dielectric layer is 0.1-0.6 microns; and the thickness of the first middle isolation dielectric layer is smaller than the thickness of the first upper isolation dielectric layer and the thickness of the first lower isolation dielectric layer, and is at least less than 0.01 microns.

[0054] Due to the application of the above technical solution, the present invention has the following advantages and technical effects compared with the prior art.

[0055] 1). The overall structure of the periodically arranged grooves presents a stepped structure design with a small upper opening and a large lower opening. The inner diameters of the upper cylindrical opening and the middle cylindrical opening of the groove are smaller than those of the lower cylindrical opening, which reduces the chip area occupied by the non-conductive structure, increases the conductive semiconductor area during forward conduction, reduces the current density during forward conduction, reduces the forward conduction voltage drop, and also reduces the junction temperature during forward conduction, thereby improving the forward conduction performance, device reliability and life of the device.

[0056] 2). The inner diameter of the lower cylindrical opening is larger than the inner diameter of the upper cylindrical opening and the middle cylindrical opening of the groove, thereby avoiding the tip discharge effect that may be deteriorated by the small curvature radius of the groove bottom when the device is reverse biased, thereby improving the reverse blocking performance of the device and increasing the reliability and life of the device.

[0057] 3) The isolation dielectric layer in the trench adopts a three-stage structure, with different thicknesses in the upper, middle and lower sections, which can adjust the forward and reverse performance of the device in different areas. Since the isolation dielectric layer covering the inner wall of the lower columnar opening is thicker, the voltage drop borne by the isolation dielectric layer increases when reverse biased, thereby improving the reverse blocking capability of the device; while the isolation dielectric layer covering the inner wall of the middle columnar opening is thinner, which is conducive to the formation of depletion pinch-off in the epitaxial layer of the table when reverse biased, thereby improving the reverse blocking performance, device reliability and life of the device; the isolation dielectric layer at the top of the trench sidewall is thicker, and only a small amount of polysilicon is needed to complete the columnar hole filling, reducing the manufacturing cycle and cost of the device; and the thicker isolation dielectric layer at the top can also increase the distance between the conductive polysilicon on the upper surface of the device and the epitaxial layer, weaken the diffusion of impurities doped in the conductive polysilicon through the Schottky barrier metal to the epitaxial layer during the Schottky barrier alloy process, and improve the leakage, device reliability and life of the device during reverse blocking.

[0058] 4). A second conductive type injection region is set in the epitaxial layer at the bottom of the trench, and the first conductive type doping concentration in the local area is reduced through compensation, which helps to broaden the electric field strength distribution in the bottom epitaxial layer when the device is reverse biased, and reduce the electric field strength in the local area, thereby improving the reverse blocking performance of the device, device reliability and life. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 It is a trench Schottky barrier diode disclosed in US Pat. No. 5,365,102 and is also a schematic structural diagram of a trench Schottky barrier diode commonly used in the prior art.

[0060] in, Figure 1 In the above example, 301 is N. + Substrate, 302 for N － Epitaxial layer, 303 is a trench, 304 is an N-type single crystal silicon mesa structure, 305 is a silicon dioxide layer, 306 is a metal layer, and 307 is a cathode metal layer.

[0061] Figure 2 It is a schematic diagram of a top view structure of a Schottky barrier diode manufactured according to various embodiments of the present invention.

[0062] Figure 3 The Schottky barrier diode of each embodiment of the present invention is Figure 2 Schematic diagram of the cross-sectional structure at position A1-A2.

[0063] Figure 4 It is a cross-sectional schematic diagram of the device structure formed after step S6 in embodiment 1 of the present invention is completed.

[0064] Figure 5 It is a cross-sectional schematic diagram of the device structure formed after step S10 in embodiment 1 of the present invention is completed.

[0065] Figure 6 It is a cross-sectional schematic diagram of the device structure formed after step S12 in embodiment 1 of the present invention is completed.

[0066] Figure 7 It is a cross-sectional schematic diagram of the device structure formed after step S13 in embodiment 1 of the present invention is completed.

[0067] Figure 8 It is a cross-sectional schematic diagram of the device structure formed after step S16 in embodiment 1 of the present invention is completed.

[0068] Fig. 9 It is a cross-sectional schematic diagram of the device structure formed after step S18 in embodiment 1 of the present invention is completed.

[0069] in, Figure 2-Figure 9 In the figure: 10 is a cathode metal layer, 20 is a first conductive type heavily doped substrate, 30 is a first conductive type lightly doped epitaxial layer, 30a is a table structure, 31 is a stepped trench, 31a is an upper cylindrical opening, 31b is a lower cylindrical opening, 31d is a middle cylindrical opening, 31D is a first cylindrical opening, 31B is a second cylindrical opening, 32 is conductive polysilicon, 33a is a first upper isolation dielectric layer, 33d is a first middle isolation dielectric layer, 33b is a first lower isolation dielectric layer, 33c is a second isolation dielectric layer, 34 is a cavity, 35 is an ion implantation region, 35a is a second conductive type doped impurity, 40 is a functional metal layer, 40a is a Schottky barrier metal layer, 40b is an ohmic contact metal layer, and 50 is an anode metal layer; 61 is a first dielectric layer, 62 is a second dielectric layer, and 63 is a third dielectric layer. DETAILED DESCRIPTION

[0070] In order to more clearly illustrate the technical solution and purpose of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0071] like Figure 2 A schematic diagram of a top view of a Schottky barrier diode manufactured according to various embodiments of the present invention is shown in FIG. Figure 3 The Schottky barrier diode of each embodiment is Figure 2 Schematic diagram of the cross-sectional structure at the A1-A2 position. Figure 2-Figure 3 It can be seen that the Schottky barrier diode of the present invention comprises, from bottom to top, a cathode metal layer 10, a semiconductor first conductivity type heavily doped substrate 20, a semiconductor first conductivity type lightly doped epitaxial layer 30, a functional metal layer 40, and an anode metal layer 50 covering the top layer of the entire Schottky barrier diode structure; and further comprises a series of step-shaped grooves 31 located in the epitaxial layer 30, the step-shaped grooves 31 opening on the upper surface of the epitaxial layer 30 and extending into the epitaxial layer 30; Figure 2 , Figure 3 It can be seen that the step-shaped groove in the figure is composed of three cylindrical openings connected at the top, middle and bottom, namely the upper cylindrical opening 31a, the middle cylindrical opening 31d and the lower cylindrical opening 31b. The inner diameter of the middle cylindrical opening 31d is smaller than the inner diameter of the upper cylindrical opening 31a and the inner diameter of the lower cylindrical opening 31b, and the inner diameter of the lower cylindrical opening 31b is the largest; the first conductive type heavily doped conductive polysilicon 32 is filled in the groove; on the inner wall of the step-shaped groove 31, the oxide layer is covered as the first middle isolation dielectric layer 33d, the first upper isolation dielectric layer 3 3a and a first lower isolation dielectric layer 33b are used to isolate the conductive polysilicon 32 and the epitaxial layer constituting the inner wall of the groove, wherein the first lower isolation dielectric layer 33b covers the inner wall of the lower cylindrical opening 31b, the first middle isolation dielectric layer 33d covers the inner wall of the middle cylindrical opening 31d, and the first upper isolation dielectric layer 33a covers the side wall of the upper cylindrical opening 31a; an unfilled cavity 34 is also contained in the interior of the conductive polysilicon 32; and a second conductive type ion implantation region 35 is contained in the epitaxial layer near the bottom of the stepped groove 31. Among them, the epitaxial layer between adjacent grooves forms a mesa structure 30a, and the functional metal layer 40 covering the upper surface of the epitaxial layer of the mesa structure 30a is a Schottky barrier metal layer 40a that forms a Schottky barrier contact with the epitaxial layer; and the functional metal layer 40 covering the upper surface of the conductive polysilicon 32 is an ohmic contact metal layer 40b that forms an ohmic contact with the heavily doped conductive polysilicon; the first upper isolation dielectric layer 33a extends upward to between the Schottky barrier metal layer 40a and the ohmic contact metal layer 40b, forming a second isolation dielectric layer 33c for isolating the two.

[0072] The Schottky barrier diode of the present invention and its specific manufacturing process are described in more detail below through specific embodiments.

[0073] Example 1

[0074] In this embodiment, the heavily doped substrate is N + Single crystal silicon wafer, epitaxial layer is grown on N + Lightly doped N on single crystal silicon wafer - The silicon epitaxial layer, the ion implantation area is a P-type ion implantation area, and the silicon oxide layer is used as an isolation oxide layer. The dimensions of the three cylindrical openings constituting the step-shaped groove are as follows: the inner diameter of the upper cylindrical opening is 0.15 microns, the inner diameter of the middle cylindrical opening is 0.12 microns, and the inner diameter of the lower cylindrical opening is 0.5 microns. The thickness of the first upper isolation dielectric layer and the first lower isolation dielectric layer are formed synchronously by in-situ thermal oxidation of the epitaxial layer and subsequent oxide layer deposition, both of which are 0.1 microns. The first middle isolation dielectric layer is relatively thin, and its deposition thickness is 0.06 microns.

[0075] The specific process flow for manufacturing the Schottky barrier diode of this embodiment is as follows:

[0076] S1, prepare semiconductor N + The single crystal silicon wafer is used as the first conductivity type heavily doped substrate 20, and the first conductivity type lightly doped epitaxial layer N is grown on the substrate 20. - Silicon epitaxial layer 30 .

[0077] S2, forming a second dielectric layer 62 on the upper surface of the epitaxial layer.

[0078] S3, forming a first dielectric layer 61 on the surface of the second dielectric layer.

[0079] S4, photolithography is performed on the first dielectric layer to define the pattern of the first cylindrical opening 31D. In this embodiment, the lateral opening size of the first cylindrical opening 31D is consistent with the inner diameter of the finally formed middle cylindrical opening 31d; the first dielectric layer not protected by the photoresist is selectively removed to expose the second dielectric layer; the exposed second dielectric layer is selectively removed to expose the epitaxial layer corresponding to the first cylindrical opening pattern, and then the photoresist on the first dielectric layer is removed; the first dielectric layer retained after removing the photoresist is used as a first dielectric hard mask.

[0080] S5, using the first dielectric hard mask as protection, selectively etching the exposed epitaxial layer 30 by dry etching to form a first cylindrical opening 31D in the epitaxial layer; at this time, the upper surface of the epitaxial layer between the first cylindrical openings 31D is still covered by the second dielectric layer and the first dielectric hard mask thereon.

[0081] S6, after completing step S5, a third dielectric layer 63 is formed on the entire surface of the structure. At this time, a schematic diagram of the cross-section of the structure is obtained as shown in FIG. Figure 4 shown.

[0082] S7, selectively etching the third dielectric layer 63 by dry etching to expose the epitaxial layer on the bottom surface of the first cylindrical opening 31D, and simultaneously removing the third dielectric layer 63 located above the first dielectric layer 61; at this time, the upper surface of the epitaxial layer between the first cylindrical openings 31D is still covered with the second dielectric layer and the first dielectric layer 61, i.e., the first dielectric hard mask, and at this time, the third dielectric layer 63 covering the side wall of the first cylindrical opening 31D is used as the third dielectric hard mask.

[0083] S8, using the first dielectric hard mask and the third dielectric hard mask as protection, selectively etching the exposed epitaxial layer using a dry etching method.

[0084] S9, continuing to use the first dielectric hard mask and the third dielectric hard mask as protection, adopting a xenon difluoride dry etching method to selectively etch the exposed epitaxial layer to form a second cylindrical opening 31B.

[0085] S10, continue to use the first dielectric hard mask and the third dielectric hard mask as protection, and use the ion implantation method to implant the second conductive type doping impurities 35a into the exposed epitaxial layer. At this time, the cross-sectional schematic diagram of the obtained structure is as shown in FIG. Figure 5 shown.

[0086] S11, using a dry etching method to selectively remove the third dielectric covering the upper part of the side wall of the first cylindrical opening 31D, exposing the epitaxial layer on the upper part of the side wall of the first cylindrical opening 31D, and the exposed height of the upper part of the side wall of the first cylindrical opening 31D is consistent with the height of the upper cylindrical opening 31a of the groove.

[0087] S12, selectively remove the first dielectric layer 61, i.e., the first dielectric hard mask, by wet etching. The cross-sectional schematic diagram of the structure obtained at this time is as follows Figure 6 shown.

[0088] S13, using the second dielectric 62 covering the upper surface of the epitaxial layer between the first cylindrical openings as the second dielectric hard mask, and the third dielectric 63 still retained at the lower part of the side wall of the first cylindrical opening 31D as the fourth hard mask, under the protection of the second dielectric hard mask and the fourth hard mask, an oxide layer is grown on the exposed epitaxial layer by adopting the method of in-situ thermal oxidation growth of the epitaxial layer, that is, a first upper isolation dielectric layer 33a and a first lower isolation dielectric layer 33b are preliminarily formed, which respectively cover the upper part of the side wall of the first cylindrical opening 31D and the inner wall of the second cylindrical opening 31B formed in step S9. At this time, the formation of the upper cylindrical opening 31a and the lower cylindrical opening 31b is completed synchronously, and the mesa structure 30a composed of the epitaxial layer between the upper cylindrical opening 31a is also formed synchronously. At the same time, in the thermal process of the growth of the oxide layer, the diffusion of the second conductive type doping impurities 35a is promoted to form a preliminary ion implantation area. At this time, the structural cross-sectional schematic diagram is obtained as shown in FIG. Figure 7 shown.

[0089] S14, selectively removing the second dielectric hard mask and the fourth hard mask by a wet etching method.

[0090] S15, an oxide layer is deposited on the surface of the entire structure formed after step S14 is completed. At this time, the oxide layer deposited on the lower part of the side wall of the first cylindrical opening 31D constitutes the first middle isolation dielectric layer 33d; at this time, the final first upper isolation dielectric layer 33a and the first lower isolation dielectric layer 33b are also completely formed; at this time, the middle cylindrical opening 31d of the step-shaped groove 31 is also formed synchronously. At the same time, the thermal process of the growth of the oxide layer promotes the further diffusion of the second conductive type doping impurities 35a to complete the formation of the ion implantation area 35.

[0091] S16, after step S15 is completed, conductive polysilicon 32 is deposited on the surface of the entire structure formed; then, the conductive polysilicon outside the groove is selectively removed by dry etching, and the upper surface of the conductive polysilicon 32 filled in the groove is made flush with the upper surface of the epitaxial layer of the mesa structure 30a; since the thickness of the first upper dielectric isolation layer located on the upper side wall of the upper cylindrical opening is large, only a small amount of polysilicon is needed to fill the groove. At the same time, during the polysilicon deposition process, a cavity 34 will be formed inside the conductive polysilicon filling the groove. At this time, the cross-sectional schematic diagram of the structure is obtained as shown in FIG. Figure 8 shown.

[0092] S17, using dry etching to selectively remove the oxide layer on the surface of the mesa structure 30a, retaining the oxide layer extending upward from the first upper isolation dielectric layer 33a and surrounding the upper surface opening of the groove. The retained oxide layer constitutes the second isolation dielectric layer 33c, which is used to isolate the Schottky barrier metal layer and the ohmic contact metal layer to be formed in the subsequent steps.

[0093] S18, after step S17 is completed, a metal layer is deposited on the surface of the entire structure. After the metal layer is alloyed, a functional metal layer 40 is formed; wherein the portion of the functional metal layer 40 in contact with the upper surface of the epitaxial layer of the mesa structure 30a forms a Schottky barrier contact, namely the Schottky barrier metal layer 40a; the portion of the functional metal layer 40 in contact with the upper surface of the conductive polysilicon filled in the trench forms an ohmic contact, namely the ohmic contact metal layer 40b. The cross-sectional schematic diagram of the structure obtained at this time is as follows Fig. 9 shown.

[0094] S19, depositing an anode metal layer 50 on the entire surface of the structure after step S18.

[0095] S20, the substrate 20 is thinned by grinding and etching the lower surface of the substrate, and then a cathode metal layer 10 is deposited on the lower surface of the substrate 20, thus completing the manufacture of the Schottky barrier diode of this embodiment. The overall structure of the diode is as shown in FIG. Figure 3 Schematic diagram of the middle section.

[0096] Example 2

[0097] The difference from Example 1 is that the dimensions of the three cylindrical openings constituting the stepped groove are as follows: the inner diameter of the upper cylindrical opening is 1.0 micron, the inner diameter of the middle cylindrical opening is 0.6 micron, and the inner diameter of the lower cylindrical opening is 2.0 micron. The thickness of the first upper isolation dielectric layer and the first lower isolation dielectric layer are formed simultaneously by thermal oxidation epitaxial layer and subsequent oxide layer deposition, both of which are 0.55 micron. The first middle isolation dielectric layer is relatively thin, and its deposition thickness is 0.15 micron. The other process steps, parameters, etc. are the same as those of Example 1.

[0098] The above is only a preferred embodiment of the present invention, and does not limit the present invention in any form. Any technician familiar with the art can use the above disclosed methods and technical contents to make many possible changes and modifications to the technical solution of the present invention without departing from the scope of the technical solution of the present invention, or modify it into an equivalent embodiment of equivalent changes to achieve the above invention effects. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still falls within the scope of protection of the technical solution of the present invention.

Claims

1. A Schottky barrier diode, characterized in that: include: A semiconductor substrate heavily doped with a first conductivity type; A semiconductor epitaxial layer lightly doped with a first conductivity type located on the upper surface of the substrate; A series of periodically arranged grooves located in the epitaxial layer, opening at the upper surface of the epitaxial layer and extending into the epitaxial layer; wherein the epitaxial layer between adjacent grooves forms a mesa structure; Conductive polysilicon heavily doped with a first conductivity type filled in the trench; A first isolation dielectric layer covering the inner wall of the trench and used to isolate the conductive polysilicon from the epitaxial layer; A Schottky barrier metal layer covering the upper surface of the epitaxial layer in the mesa structure region; an ohmic contact metal layer covering the upper surface of the conductive polysilicon; A second isolation dielectric layer formed by extending upward from the first isolation dielectric layer and isolating the Schottky barrier metal layer and the ohmic contact metal layer; an anode metal layer covering the upper surface of the Schottky barrier diode; and a cathode metal layer located on the lower surface of the substrate, wherein the lower surface of the substrate forms an ohmic contact with the cathode metal layer; The groove is composed of three cylindrical openings connected at the top, the middle and the bottom, which are the upper cylindrical opening, the middle cylindrical opening and the lower cylindrical opening from top to bottom; the inner diameters of the upper cylindrical opening and the lower cylindrical opening are both larger than the inner diameter of the middle cylindrical opening, and the inner diameter of the lower cylindrical opening is larger than the inner diameter of the upper cylindrical opening; the connecting parts of the upper cylindrical opening and the middle cylindrical opening, and the connecting parts of the middle cylindrical opening and the lower cylindrical opening are all stepped; Among them, the first isolation dielectric layer is composed of three parts: a first upper isolation dielectric layer, a first middle isolation dielectric layer and a first lower isolation dielectric layer, wherein the first lower isolation dielectric layer covers the inner wall of the lower columnar opening of the groove, and the first upper isolation dielectric layer covers the side wall of the upper columnar opening; the first middle isolation dielectric layer covers the inner wall of the middle columnar opening; and compared with the first upper isolation dielectric layer and the first lower isolation dielectric layer, the thickness of the first middle isolation dielectric layer is the smallest.

2. A Schottky barrier diode according to claim 1, characterized in that: The inner diameter of the upper cylindrical opening is 0.15 microns to 1.2 microns; the inner diameter of the middle cylindrical opening is 0.1 microns to 0.6 microns; the inner diameter of the lower cylindrical opening is 0.2 microns to 2 microns, and the difference between the inner diameter of the lower cylindrical opening and the inner diameter of the middle cylindrical opening is greater than or equal to 0.1 microns, and the difference between the inner diameter of the upper cylindrical opening and the inner diameter of the middle cylindrical opening is greater than or equal to 0.01 microns.

3. A Schottky barrier diode according to claim 2, characterized in that: The thickness of the first middle isolation dielectric layer is 0.05 microns to 0.15 microns; the thickness of the first upper isolation dielectric layer and the first lower isolation dielectric layer is 0.1 microns to 0.6 microns; the thickness of the first middle isolation dielectric layer is smaller than the thickness of the first upper isolation dielectric layer, and the thickness difference between the first middle isolation dielectric layer and the first upper isolation dielectric layer is greater than or equal to 0.01 microns; at the same time, the thickness of the first middle isolation dielectric layer is smaller than the thickness of the first lower isolation dielectric layer, and the thickness difference between the first middle isolation dielectric layer and the first lower isolation dielectric layer is greater than or equal to 0.01 microns.

4. A Schottky barrier diode according to claim 1, characterized in that: The upper cylindrical opening, the middle cylindrical opening and the lower cylindrical opening of the groove are all cylindrical openings.

5. The Schottky barrier diode according to claim 1, characterized in that: The second isolation dielectric layer and the first isolation dielectric layer are deposited and formed simultaneously.

6. A Schottky barrier diode according to claim 1, characterized in that: The first upper isolation dielectric layer and the first lower isolation dielectric layer are formed by a synchronous process and have the same thickness.

7. The Schottky barrier diode according to claim 1, characterized in that: A second conductive type ion implantation region is provided in the epitaxial layer region at the bottom of the trench.

8. The Schottky barrier diode according to claim 1, characterized in that: The Schottky barrier metal layer and the ohmic contact metal layer are formed by alloying the same metal deposited simultaneously.

9. The method for manufacturing a Schottky barrier diode according to any one of claims 1 to 8, characterized in that: The steps include: S1, growing a semiconductor epitaxial layer lightly doped with a first conductivity type on a semiconductor substrate heavily doped with a first conductivity type; S2, forming a second dielectric layer on the upper surface of the epitaxial layer; S3, forming a first dielectric layer on the surface of the second dielectric layer; S4, performing photolithography on the first dielectric layer to define a first columnar opening pattern, wherein the lateral opening size of the first columnar opening pattern is consistent with the inner diameter of the middle columnar opening; Selectively removing the first dielectric layer not protected by the photoresist to expose the second dielectric layer; Selectively removing the exposed second dielectric layer to expose the epitaxial layer corresponding to the first columnar opening pattern, and then removing the photoresist on the first dielectric layer; The first dielectric layer retained after removing the photoresist is used as a first dielectric hard mask; S5, using the first dielectric hard mask as protection, selectively etching the exposed epitaxial layer by dry etching to form a first columnar opening in the epitaxial layer; at this time, the surface of the epitaxial layer between the first columnar openings is still covered by the second dielectric layer and the first dielectric hard mask thereon; S6, forming a third dielectric layer on the entire structure surface; S7, selectively etching the third dielectric layer by dry etching to expose the epitaxial layer on the bottom surface of the first cylindrical opening, and simultaneously removing the third dielectric layer on the first dielectric layer; at this time, the surface of the epitaxial layer between the first cylindrical openings is still covered with the second dielectric layer and the first dielectric layer thereon, i.e., the first dielectric hard mask, and at this time, the third dielectric layer covered by the sidewall of the first cylindrical opening is used as the third dielectric hard mask; S8, using the first dielectric hard mask and the third dielectric hard mask as protection, selectively etching the exposed epitaxial layer by dry etching; S9, continuing to use the first dielectric hard mask and the third dielectric hard mask as protection, selectively etching the exposed epitaxial layer by using a xenon difluoride dry etching method to form a second columnar opening; S10, continuing to use the first dielectric hard mask and the third dielectric hard mask as protection, using an ion implantation method to implant second conductive type doping impurities into the epitaxial layer where the bottom of the second columnar opening is exposed; S11, selectively removing the third dielectric covering the upper portion of the sidewall of the first cylindrical opening by dry etching to expose the epitaxial layer on the upper portion of the sidewall of the first cylindrical opening, wherein the height of the exposed upper portion of the sidewall of the first cylindrical opening is consistent with the height of the upper cylindrical opening of the groove; S12, selectively removing the first dielectric hard mask by wet etching; S13, using the second dielectric covering the surface of the epitaxial layer between the first columnar openings as the second dielectric hard mask, and the third dielectric still retained at the lower part of the sidewall of the first columnar opening as the fourth hard mask, under the protection of the second dielectric hard mask and the fourth hard mask, in-situ thermal oxidation growth of an oxide layer on the exposed epitaxial layer, that is, preliminarily forming the first upper isolation dielectric layer and the first lower isolation dielectric layer, respectively covering the upper part of the sidewall of the first columnar opening and the inner wall of the second columnar opening formed in step S9, at this time, the formation of the upper columnar opening and the lower columnar opening is also completed synchronously, and the mesa structure composed of the epitaxial layer located between the upper columnar opening is also formed synchronously; at the same time, the thermal process of the in-situ thermal oxidation growth of the oxide layer promotes the diffusion of the second conductive type doping impurities to form a preliminary ion implantation area; S14, selectively removing the second dielectric hard mask and the fourth hard mask by a wet etching method; S15, depositing an oxide layer on the surface of the entire structure formed after step S14, wherein the oxide layer deposited on the lower part of the sidewall of the first columnar opening constitutes the first isolation dielectric layer; At this time, the final first upper isolation dielectric layer and the first lower isolation dielectric layer are also completely formed; at this time, the central columnar opening of the trench is also synchronously formed; at the same time, in the thermal process of depositing the oxide layer, the second conductive type doping impurities are further diffused to complete the formation of the ion implantation area; S16, depositing conductive polysilicon on the surface of the entire structure formed after step S15; Then, selectively removing the conductive polysilicon outside the trench by dry etching, and making the upper surface of the conductive polysilicon filled in the trench flush with the upper surface of the epitaxial layer of the mesa structure; S17, selectively removing the oxide layer on the surface of the mesa structure by dry etching or wet etching, and retaining the oxide layer extending upward from the first upper isolation dielectric layer and surrounding the upper surface opening of the trench, wherein the retained oxide layer constitutes the second isolation dielectric layer for isolating the Schottky barrier metal layer and the ohmic contact metal layer to be formed; S18, depositing a first metal layer on the surface of the entire structure after step S17 is completed, and after the alloying process, the first metal layer forms a Schottky barrier contact with the upper surface of the epitaxial layer of the mesa structure, that is, the Schottky barrier metal layer is formed, and forms an ohmic contact with the upper surface of the conductive polysilicon filled in the trench, that is, the ohmic contact metal layer is formed; S19, depositing an anode metal layer on the entire surface of the structure after step S18; S20, thinning the substrate by grinding and etching the lower surface of the substrate, and then depositing a cathode metal layer on the lower surface of the substrate; that is, forming the Schottky barrier diode.

10. The method for manufacturing a Schottky barrier diode according to claim 9, characterized in that: The first conductivity type is N type, and the second conductivity type is P type.

11. The method for manufacturing a Schottky barrier diode according to claim 9, characterized in that: The lateral dimension of the second cylindrical opening formed in step S9 is greater than the lateral opening dimension of the first cylindrical opening formed in step S5.

12. The method for manufacturing a Schottky barrier diode according to claim 11, characterized in that: The lateral opening size of the first columnar opening formed in step S5 is 0.1-0.6 micrometers; in step S13, the inner diameters of the upper columnar opening and the lower columnar opening formed are 0.15-1.2 micrometers and 0.2-2 micrometers respectively.

13. The method for manufacturing a Schottky barrier diode according to claim 11, characterized in that: The second cylindrical opening formed in step S9 and the first cylindrical opening formed in step S5 are both cylindrical.

14. The method for manufacturing a Schottky barrier diode according to claim 9, characterized in that: In step S15, the thickness of the first middle isolation dielectric layer formed is 0.05-0.15 microns; and after step S15 is completed, the thickness of the first upper isolation dielectric layer and the first lower isolation dielectric layer is 0.1-0.6 microns; the thickness of the first middle isolation dielectric layer is smaller than the thickness of the first upper isolation dielectric layer, and the thickness difference between the first middle isolation dielectric layer and the first upper isolation dielectric layer is greater than or equal to 0.01 microns; at the same time, the thickness of the first middle isolation dielectric layer is smaller than the thickness of the first lower isolation dielectric layer, and the thickness difference between the first middle isolation dielectric layer and the first lower isolation dielectric layer is greater than or equal to 0.01 microns.

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