Method for manufacturing stacked transistor, stacked transistor, and semiconductor device

Abstract

The present application provides a method for manufacturing a stacked transistor, a stacked transistor, and a semiconductor device. The method includes: etching a stacked structure in one step on a semiconductor substrate, the stacked structure including an active structure and a first sacrificial layer; forming a dummy gate structure covering the stacked structure within a gate region; etching the stacked structure not covered by the dummy gate structure to form a first deep trench; epitaxially growing a first source / drain structure inside and outside the first deep trench based on the first active structure within the gate region; removing the dummy gate structure and the first sacrificial layer to expose the active structure within the gate region; depositing a gate dielectric material on the exposed active structure to form a gate dielectric layer; depositing a metal material on the first gate dielectric layer to form a first gate electrode layer; flipping the wafer and removing the semiconductor substrate; epitaxially growing a second source / drain structure inside and outside the first deep trench based on the second active structure within the gate region; depositing a metal material on the second gate dielectric layer to form a second gate electrode layer.

Description

Technical Field

[0001] The present application relates to the field of semiconductor chip manufacturing, and particularly to a method for manufacturing a stacked transistor, a stacked transistor, and a semiconductor device. Background Art

[0002] At present, with the continuous deepening of Moore's Law, continuously promoting the miniaturization of transistor size is a hot issue in the current industry research and development. By integrating two or more layers of transistors in the vertical space, the stacked transistor can further improve the transistor integration density, and has become one of the important technologies to continue the miniaturization of the integrated circuit size.

[0003] In some solutions for manufacturing a stacked transistor, the active regions of the upper and lower layers of homologous transistors are formed by etching, and the stacked transistor is fabricated on the front and back sides of the wafer by flipping the wafer. This can also be called the "self-aligned flip transistor" solution. However, in the "self-aligned flip transistor" solution, the high aspect ratio process needs to be used multiple times, which will lead to problems such as high processing difficulty, easy occurrence of voids, uneven etching rate, and insufficient bottom etching. Therefore, there is a certain room for optimization in the "self-aligned flip transistor" solution. Summary of the Invention

[0004] The present application provides a method for manufacturing a stacked transistor, a stacked transistor, and a semiconductor device to optimize the "self-aligned flip transistor" solution.

[0005] In a first aspect, an embodiment of the present application provides a method for fabricating a stacked transistor, including: etching to form a stacked structure on a semiconductor substrate at one time, where the stacked structure includes an active structure and a first sacrificial layer, and the active structure includes a first active structure and a second active structure; the first active structure, the second active structure, and the first sacrificial layer are stacked in sequence in a first direction, the first active structure is farther from the semiconductor substrate than the first sacrificial layer, and the first direction is a direction perpendicular to the semiconductor substrate; in the gate region of the stacked transistor, form a dummy gate structure covering the stacked structure; etch the stacked structure not covered by the dummy gate structure to form a first deep trench; based on the first active structure in the gate region, epitaxially grow a first source-drain structure inside and outside the first deep trench; remove the dummy gate structure and the first sacrificial layer to expose the active structure in the gate region; deposit a gate dielectric material on the exposed active structure to form a gate dielectric layer, the gate dielectric layer includes a first gate dielectric layer and a second gate dielectric layer, the first gate dielectric layer wraps the first active structure, and the second gate dielectric layer wraps the second active structure; deposit a metal material on the first gate dielectric layer to form a first gate electrode layer, and the first gate dielectric layer and the first gate electrode layer together form a first gate structure; flip the wafer and remove the semiconductor substrate; based on the second active structure in the gate region, epitaxially grow a second source-drain structure inside and outside the first deep trench; deposit a metal material on the second gate dielectric layer to form a second gate electrode layer, and the second gate dielectric layer and the second gate electrode layer together form a second gate structure.

[0006] In some possible implementation manners, before epitaxially growing the first source-drain structure inside and outside the first deep trench based on the first active structure in the gate region, the method further includes: depositing an oxide material in the first deep trench to form a first filling structure, the height of the first filling structure is less than the height of the first active structure and greater than the height of the second active structure; depositing an insulating material on the first filling structure to form an isolation layer, and the isolation layer is used to isolate the first source-drain structure and the second source-drain structure; before epitaxially growing the second source-drain structure inside and outside the first deep trench based on the second active structure in the gate region, the method further includes: removing the first filling structure in the first deep trench to expose the second active structure in the gate region.

[0007] In some possible implementation manners, the active structure further includes: a second sacrificial layer, and the second sacrificial layer is located between the first active structure and the second active structure; etching the stacked structure not covered by the dummy gate structure to form a first deep trench includes: etching the first active structure, the second sacrificial layer, the second active structure, and the first sacrificial layer not covered by the dummy gate structure to form a first deep trench; in the gate region, deposit an insulating material at the position where the second sacrificial layer is removed to form an isolation structure.

[0008] In some possible embodiments, a stacked structure is etched on a semiconductor substrate at one time, including: forming an initial stacked structure and an initial barrier layer on the semiconductor substrate, wherein the initial barrier layer is located between the initial stacked structure and the semiconductor substrate; etching the initial stacked structure and the initial barrier layer at one time to form a stacked structure and a barrier layer; depositing an oxide material on the semiconductor substrate to form a shallow trench isolation structure, and the shallow trench isolation structure wraps the barrier layer; after etching the stacked structure not covered by the dummy gate structure to form a first deep trench, the method further includes: etching the barrier layer at the bottom of the first deep trench to form an etched barrier layer, wherein the etched barrier layer is located in the gate region; depositing an oxide material at the position where the barrier layer is etched to form a second filling structure; flipping the wafer and removing the semiconductor substrate, including: flipping the wafer and removing the semiconductor substrate to expose the etched barrier layer and the shallow trench isolation structure; removing the shallow trench isolation structure and retaining the etched barrier layer; before epitaxially growing a second source / drain structure inside and outside the first deep trench based on a second active structure in the gate region, the method further includes: etching the second filling structure and the first filling structure not covered by the etched barrier layer in sequence until the isolation layer is exposed.

[0009] In some possible embodiments, when the stacked transistor is a fully-depleted surround gate field-effect transistor, both the first active structure and the second active structure are formed by alternately stacking a channel layer and a sacrificial layer; after etching the stacked structure not covered by the dummy gate structure to form a first deep trench, the method further includes: laterally etching the sacrificial layer in the active structure in the gate region to a preset depth; depositing an insulating material at the position where the sacrificial layer is etched to form an inner sidewall, and the inner sidewall includes a first inner sidewall and a second inner sidewall, the first inner sidewall faces the first active structure, and the second inner sidewall faces the second active structure; after removing the dummy gate structure and the first sacrificial layer to expose the active structure in the gate region, the method further includes: removing the sacrificial layer in the gate region.

[0010] In some possible embodiments, the method further includes: after forming the first gate structure, removing the third gate structure in the first gate structure by using a gate cut process, and depositing an insulating material at the position where the third gate structure is removed to form a first gate isolation structure; wherein, in a second direction, the third gate structure is located at both ends of the first gate structure; the second direction is perpendicular to the first direction; and / or, after forming the second gate structure, removing the fourth gate structure in the second gate structure by using a gate cut process, and depositing an insulating material at the position where the fourth gate structure is removed to form a second gate isolation structure; wherein, in the second direction, the fourth gate structure is located at both ends of the second gate structure.

[0011] In some possible embodiments, after epitaxially growing a first source / drain structure inside and outside a first deep trench based on a first active structure within a gate region, the method further includes: depositing a dielectric material on the first source / drain structure to form a first interlayer dielectric layer; after depositing a metal material on the first gate dielectric layer to form a first gate electrode layer, the method further includes: depositing a dielectric material on the first gate electrode layer and the first interlayer dielectric layer to form a first dielectric layer; etching the first dielectric layer and the first interlayer dielectric until the first source / drain structure is exposed to form a first via; depositing a metal material in the first via to form a first source / drain metal.

[0012] In some possible embodiments, the first source / drain structure and the first gate structure together constitute a first transistor, and the second source / drain structure and the second gate structure together constitute a second transistor; the first transistor or the second transistor is any one of the following: fin field-effect transistor, gate-all-around field-effect transistor, vertical field-effect transistor, complementary field-effect transistor, crossbar transistor, and planar field-effect transistor.

[0013] In a second aspect, an embodiment of the present application provides a stacked transistor, which includes: a first transistor; a second transistor, the first transistor and the second transistor are disposed back to back, and the first active structure of the first transistor and the second active structure of the second transistor form an active structure; the first gate structure of the first transistor and the second gate structure of the second transistor are self-aligned.

[0014] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: the stacked transistor as described in the above embodiment.

[0015] In the embodiments of the present disclosure, by etching once on a semiconductor substrate to form a stacked structure, and the stacked structure includes an active structure, it is possible to achieve self-alignment of the active regions of the front and back two-layer transistors in the stacked transistor. Subsequently, a pseudo-gate structure shared by the front and back two-layer transistors is formed. After the first source / drain structure in the source / drain region is formed, the pseudo-gate structure and the first sacrificial layer are removed, and the self-aligned active structure within the gate region can be exposed. Subsequently, a self-aligned gate dielectric layer can be formed based on the self-aligned active structure exposed in the gate region, and finally, complete self-alignment of the front and back transistors is achieved.

[0016] In this way, on the one hand, fewer high aspect ratio processes can be adopted, which is more compatible with the complete self-alignment flip-chip stacking of various types of transistors, and further optimizes the "self-aligned flip transistor" solution; on the other hand, by preferentially preparing the gate dielectric layer, it can be ensured that the subsequent structures no longer bear a higher thermal budget, effectively improving the structural performance.

[0017] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. Brief Description of the Drawings

[0018] The drawings herein are incorporated into and form a part of this specification, showing embodiments consistent with the present application, and are used together with the specification to explain the principles of the present application.

[0019] Figure 1 It is a schematic flowchart of an implementation process of a method for manufacturing a stacked transistor according to an embodiment of the present application;

[0020] Figure 2 It is a top view of a stacked transistor according to an embodiment of the present application;

[0021] Figures 3 to 38 It is a schematic diagram of a manufacturing process of a stacked transistor according to an embodiment of the present application.

[0022] In the above figures: 10, stacked transistor; 11, first transistor; 12, second transistor; 112, first source-drain structure; 113, first interlayer dielectric layer; 114, first gate structure; 115, first source-drain metal; 116, first metal interconnect layer; 122, second source-drain structure; 123, second interlayer dielectric layer; 124, second gate structure; 125, second source-drain metal; 126, second metal interconnect layer; 20, semiconductor substrate; 21, initial stacked structure; 22, initial barrier layer; 23, stacked structure; 24, barrier layer; 25, shallow trench isolation structure; 26, dummy gate structure; 27, dummy gate sidewall; 28, first gate isolation structure; 29, first active structure; 30, second sacrificial layer; 31, second active structure; 32, first sacrificial layer; 33, isolation structure; 34, sacrificial layer; 35, channel layer; 36, inner sidewall; 37, filling structure; 37a, first filling structure; 37b, second filling structure; 38, isolation layer; 39, gate dielectric layer; 39a, first gate dielectric layer; 39b, second gate dielectric layer; 40, third filling structure; 41, first gate isolation structure; 42, first dielectric layer; 43, insulating layer; 44, carrier wafer; 45, fourth filling structure; 46, second dielectric layer; 47, second gate isolation structure; 48, first deep trench. Detailed Description of the Embodiments

[0023] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application.

[0024] In the current context of the continuous deepening of Moore's Law, continuously promoting the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in the vertical space through three-dimensional transistor stacking, which helps to further improve the transistor integration density and circuit performance, and is considered one of the important technologies to continue the miniaturization of integrated circuit size.

[0025] In one embodiment, there are two schemes for the preparation process of stacked transistors. The first is the monolithic scheme, and the second is the sequential scheme.

[0026] For the first scheme, N field effect transistors (NFETs) and P field effect transistors (PFETs) are fabricated on the same substrate without using wafer bonding technology. This determines that the transistors in the same layer must be of the same type, that is, NFETs or PFETs. Moreover, the upper and lower layer transistors must be strictly in the same planar space without alignment deviation. The advantage of this scheme is better integration density. The disadvantages of this scheme include the following two points: (1) The process is complex and requires a large amount of process technology development and optimization; (2) The polarity of each layer of transistors is fixed, and a basic complementary metal-oxide-semiconductor (CMOS) circuit must rely on two layers of transistors, resulting in poor design flexibility.

[0027] For the second scheme, it is based on wafer bonding and processed layer by layer. Specifically, the upper layer of transistors is fabricated by bonding a wafer on top of the previously fabricated lower layer of transistors, stacking two transistors vertically. However, the temperature needs to be strictly controlled during the thermal process of fabricating the upper layer of transistors to avoid affecting the lower layer of transistors and the interconnect lines. The advantage of this scheme is that due to wafer bonding, the device structures, channel crystal orientations, and even channel materials used for the upper and lower layers of transistors can be optimized accordingly to obtain better and more matching device performance.

[0028] To solve the technical problems existing in the above two schemes, a flip-chip scheme for realizing self-aligned stacked transistors is proposed. This flip-chip scheme forms the active regions of the upper and lower layer homologous transistors through etching, and realizes the fabrication of stacked transistors on the front and back sides of the wafer through flipping the wafer to overcome the disadvantages of the above two schemes. This can also be called the "self-aligned flip-chip transistor" scheme.

[0029] However, in the "self-aligned flip-chip transistor" solution, the high aspect ratio process needs to be adopted multiple times, which will lead to problems such as high processing difficulty, easy occurrence of voids, uneven etching rate, and insufficient bottom etching. Therefore, there is a certain room for optimization in the "self-aligned flip-chip transistor" solution.

[0030] To solve the above technical problems, an embodiment of the present application provides a method for manufacturing a stacked transistor to optimize the "self-aligned flip-chip transistor" solution.

[0031] Figure 1 For a schematic flowchart of an implementation process of a method for manufacturing a stacked transistor shown in an embodiment of the present application, see Figure 1 As shown, the method for manufacturing a stacked transistor may include:

[0032] Step S101: Etch once on a semiconductor substrate to form a stacked structure, where the stacked structure includes an active structure and a first sacrificial layer, and the active structure includes a first active structure and a second active structure; the first active structure, the second active structure, and the first sacrificial layer are stacked in sequence in a first direction, the first active structure is farther from the semiconductor substrate than the first sacrificial layer, and the first direction is a direction perpendicular to the semiconductor substrate;

[0033] Step S102: In the gate region of the stacked transistor, form a dummy gate structure covering the stacked structure;

[0034] Step S103: Etch the stacked structure not covered by the dummy gate structure to form a first deep trench;

[0035] Step S104: Based on the first active structure in the gate region, epitaxially grow a first source / drain structure inside and outside the first deep trench;

[0036] Step S105: Remove the dummy gate structure and the first sacrificial layer to expose the active structure in the gate region;

[0037] Step S106: Deposit a gate dielectric material on the exposed active structure to form a gate dielectric layer, where the gate dielectric layer includes a first gate dielectric layer and a second gate dielectric layer, the first gate dielectric layer wraps the first active structure, and the second gate dielectric layer wraps the second active structure;

[0038] Step S107: Deposit a metal material on the first gate dielectric layer to form a first gate electrode layer, and the first gate dielectric layer and the first gate electrode layer together form a first gate structure;

[0039] Step S108: Flip the wafer and remove the semiconductor substrate;

[0040] Step S109: Based on the second active structure in the gate region, epitaxially grow a second source / drain structure inside and outside the first deep trench;

[0041] Step S110: Deposit a metal material over the second gate dielectric layer to form a second gate electrode layer, and the second gate dielectric layer and the second gate electrode layer together constitute a second gate structure.

[0042] It can be understood that the first direction can be the height direction of the active structure, the third direction can be the extending direction of the active structure, such as the width direction of the gate structure. The second direction can be a direction perpendicular to the extending direction of the active structure, such as the length direction of the gate structure. In the third direction, the gate regions and the source / drain regions of the stacked transistors are arranged alternately in sequence, and the gate structures and the source / drain structures of the stacked transistors are arranged alternately in sequence.

[0043] It should be noted that Figure 1 the steps shown in are not exclusive, and other steps may also be executed before, after, or between any of the shown operations; Figure 1 the steps shown in can be adjusted in sequence according to actual requirements.

[0044] It can be understood that by etching once on the semiconductor substrate to form a stacked structure, and the stacked structure includes an active structure, the active regions of the forward and reverse two-layer transistors in the stacked transistors can be self-aligned. Subsequently, a dummy gate structure shared by the forward and reverse two-layer transistors is formed. After the first source / drain structure in the source / drain region is formed, the dummy gate structure is removed, and the self-aligned active structure in the gate region can be exposed. Subsequently, a self-aligned gate dielectric layer can be formed based on the self-aligned active structure in the exposed gate region, and finally, the complete self-alignment of the front and back transistors can be achieved.

[0045] In this way, on the one hand, fewer high aspect ratio processes can be adopted, which is more compatible with the complete self-alignment flip-chip stacking of various types of transistors, and the "self-aligned flip transistor" solution can be further optimized; on the other hand, by preferentially preparing the gate dielectric layer, it can be ensured that the subsequent structure no longer bears a higher thermal budget, effectively improving the structure performance.

[0046] Figure 2 FIG. is a top view of a stacked transistor according to an embodiment of the present application. Refer to Figure 2 As shown, only the nanosheet structure, the gate structure, and the source / drain structure of the stacked transistor 10 are shown in the top view.

[0047] In one embodiment, the stacked transistor 10 includes a first transistor and a second transistor, and the first transistor and the second transistor are self-aligned, that is, the first source / drain structure of the first transistor and the second source / drain structure of the second transistor are self-aligned, and the first gate structure of the first transistor and the second gate structure of the second transistor are self-aligned.

[0048] In one embodiment, the first transistor and the second transistor may be transistors of the same type. For example, both the first transistor and the second transistor may be fin field-effect transistors.

[0049] In one embodiment, depending on the type of the stacked transistors, the active structures in the stacked transistors 10 may be different. In one example, when the stacked transistors 10 are fin field-effect transistors, the active structure may be a fin structure. When the stacked transistors 10 are gate-all-around nanosheet (GAA Nanosheet) field-effect transistors, the active structure may be a nanosheet structure; wherein, the nanosheet structure may be formed by alternately depositing silicon layers and silicon germanium layers. When the stacked transistors 10 are planar transistors, the active structure may be a bulk structure.

[0050] In one embodiment, Figure 2 The illustrated stacked transistors 10 are gate-all-around nanosheet field-effect transistors, and their active structure is a nanosheet structure.

[0051] Figures 3 to 38 FIG. is a schematic diagram of a manufacturing process of a stacked transistor according to an embodiment of the present application. For ease of understanding, Figures 3 to 38 (a) in shows a cross-sectional view along the Figure 2 dashed line A-A' direction in, Figures 3 to 38 (b) in shows a cross-sectional view along the Figure 2 dashed line B-B' direction in, Figures 3 to 38 (c) in shows a cross-sectional view along the Figure 2 dashed line C-C' direction in. The manufacturing method of the stacked transistor provided by the embodiment of the present application and the manufactured stacked transistors 10 will be described below by way of example with reference to Figures 1 to 38 .

[0052] In step S101, a stacked structure 23 is etched and formed on the semiconductor substrate 20 at one time. Refer to Figure 5 shown.

[0053] It can be understood that, on the semiconductor substrate 20, processes such as material layer deposition, epitaxial growth, and photolithography can be performed to form multiple material layers. Subsequently, the multiple material layers can be etched using a photolithography process to form the stacked structure 23 at one time.

[0054] In one embodiment, the steps of the photolithography process in the embodiment of the present application may include: depositing a photoresist material, exposing and developing the photoresist material, removing a part of the photoresist material, etching to remove the material layer corresponding to the part of the photoresist material, etc.

[0055] In one embodiment, the stacked structure 23 includes an active structure and a first sacrificial layer 32. The active structure includes a first active structure 29 and a second active structure 31. The first active structure 29, the second active structure 31, and the first sacrificial layer 32 are stacked in sequence in a first direction. The first active structure 29 is farther from the semiconductor substrate 20 than the first sacrificial layer 32. The first direction is perpendicular to the semiconductor substrate 20.

[0056] It can be understood that the stacked structure 23 includes an active structure and a first sacrificial layer 32, and the first sacrificial layer 32 is disposed between the active structure and the semiconductor substrate 20. The active structure includes a first active structure 29 and a second active structure 31. The first active structure 29 is used to form the active region of the first transistor 11 (front transistor) of the stacked transistor 10; the second active structure 31 stacked with the first active structure 29 in the first direction is used to form the active region of the second transistor 12 (back transistor) of the stacked transistor 10. The first sacrificial layer 32 can be removed in subsequent steps. After removal, the space originally occupied by the first sacrificial layer 32 is used to fill with a metal material to form the second gate structure 124 of the second transistor 12.

[0057] In one embodiment, the first sacrificial layer 32 can be formed of a material different from that of the active structure; alternatively, the first sacrificial layer 32 can be formed of the same material as the active structure; the embodiments of the present application do not make specific limitations thereto.

[0058] In one example, the active structure is a nanosheet structure, the nanosheet structure can be formed by alternately depositing silicon layers and silicon germanium layers, and the first sacrificial layer 32 can be formed of silicon germanium.

[0059] In some embodiments, when lithographically forming the first active structure 29 and the second active structure 31, a relatively large etching depth can be used. For example, the height of the etched nanosheet structure (which can also be a fin structure or a bulk structure) can be greater than 100 nm. It should be noted that the height of the nanosheet structure can be set according to actual circumstances, and the embodiments of the present application do not make specific limitations thereto.

[0060] In some embodiments, after lithographically forming the first active structure 29 and the second active structure 31, ion implantation can be performed in the middle part between the first active structure 29 and the second active structure 31 to electrically isolate the first active structure 29 and the second active structure 31.

[0061] In one embodiment, the ions implanted in the middle part between the first active structure 29 and the second active structure 31 include P-type ions, N-type ions, or oxygen ions. Among them, the P-type ions include one or more of boron ions, gallium ions, and indium ions; the N-type ions include one or more of phosphorus ions, arsenic ions, and antimony ions.

[0062] In some embodiments, the stacked structures 23 in the regions on both sides of the stacked transistor 10 can be removed through a fin cutting process, so that the active structures of multiple standard transistor units are disconnected from each other, and the isolation between adjacent transistor units is completed.

[0063] In some embodiments, step S101 includes: forming an initial stacked structure 21 and an initial barrier layer 22 on a semiconductor substrate 20, wherein the initial barrier layer 22 is located between the initial stacked structure 21 and the semiconductor substrate 20; etching the initial stacked structure 21 and the initial barrier layer 22 once to form a stacked structure 23 and a barrier layer 24; depositing an oxide material on the semiconductor substrate 20 to form a shallow trench isolation structure 25, and the shallow trench isolation structure 25 wraps the barrier layer 24, see Figures 3 to 5 as shown.

[0064] It can be understood that an initial barrier layer 22 can be formed on the semiconductor substrate 20, and an initial stacked structure 21 can be formed on the initial barrier layer 22. After the initial barrier layer 22 and the initial stacked structure 21 are formed, the initial stacked structure 21 and the initial barrier layer 22 can be lithographed once from top to bottom to form a stacked structure 23 and a barrier layer 24 at one time. At this time, the barrier layer 24 is located between the stacked structure 23 and the semiconductor substrate 20. An oxide material is deposited on the semiconductor substrate 20, and the shallow trench isolation structure 25 formed by the oxide material can wrap the barrier layer 24, while the stacked structure 23 is exposed outside the shallow trench isolation structure 25.

[0065] It can be understood that the barrier layer 24 and the stacked structure 23 are formed by a single etching process, and the positions of the barrier layer 24 and the stacked structure 23 are opposite. After flipping the wafer, the position of the active structure can be obtained according to the position of the barrier layer 24, which is beneficial to the alignment of the front and back sides of the stacked transistor 10.

[0066] In one embodiment, the material of the formed barrier layer 24 can have a certain hardness. In one example, the material of the formed barrier layer 24 can be silicon germanium. In one example, the silicon germanium forming the barrier layer 24 is different from the silicon germanium forming the nanosheet structure. For example, the atomic percentage of germanium in the silicon germanium can be different.

[0067] In one embodiment, the oxide forming the shallow trench isolation structure 25 can be: silicon-based oxide (SiOx, where x is the number of oxygen atoms), such as silicon dioxide (SiO 2 ) etc.

[0068] In step S102, a dummy gate structure 26 covering the stacked structure 23 is formed in the gate region of the stacked transistor 10, see Figure 6 as shown.

[0069] It can be understood that, based on the stacked structure 23 formed in step S101, a dummy gate structure 26 can be formed in the gate region of the stacked transistor 10 by using a semiconductor manufacturing process, and the dummy gate structure 26 can cover the stacked structure 23.

[0070] In one embodiment, the dummy gate structure 26 is a dummy gate structure 26 shared by the first active structure 29 and the second active structure 31.

[0071] In some embodiments, after the dummy gate structure 26 is formed, a dummy gate sidewall 27 can be deposited and formed on the semiconductor substrate 20. In one embodiment, the dummy gate sidewall 27 covers the sidewalls of the dummy gate structure 26. In one embodiment, the dummy gate sidewall 27 covers the structures in the source / drain regions of the stacked transistor 10. For example, the dummy gate sidewall 27 can cover the stacked structure 23 in the source / drain regions.

[0072] In some embodiments, the material for forming the dummy gate structure 26 can be polysilicon, amorphous silicon, or other materials.

[0073] In step S103, the stacked structure 23 not covered by the dummy gate structure 26 is etched to form a first deep trench 48, as shown in Figure 13 shown.

[0074] It can be understood that the dummy gate structure 26 covers the stacked structure 23 in the gate region and does not cover the stacked structure 23 in the source / drain regions. By etching the stacked structure 23 not covered by the dummy gate structure 26, a first deep trench 48 can be formed at the source / drain regions between two adjacent gate regions.

[0075] In some embodiments, the sidewalls of the first deep trench 48 are formed by the stacked structure 23 in the gate region, and the bottom of the first deep trench 48 is formed by the structure at the bottom of the stacked structure 23 in the source / drain regions.

[0076] In some embodiments, the active structure further includes: a second sacrificial layer 30, and the second sacrificial layer 30 is located between the first active structure 29 and the second active structure 31.

[0077] It can be understood that the second sacrificial layer 30, the first active structure 29, and the second active structure 31 can be formed by the same etching process.

[0078] In some embodiments, the material for forming the second sacrificial layer 30 can be set according to actual requirements, and the embodiments of the present application do not make specific limitations in this regard. In one embodiment, the material for forming the second sacrificial layer 30 can be silicon germanium. In one embodiment, the silicon germanium for forming the second sacrificial layer 30 is different from the silicon germanium for forming the nanosheet structure. For example, the atomic percentage of germanium in the silicon germanium is different.

[0079] In some embodiments, step S103 includes: etching the first active structure 29, the second sacrificial layer 30, the second active structure 31, and the first sacrificial layer 32 that are not covered by the dummy gate structure 26 to form a first deep trench 48; depositing an insulating material at a position where the second sacrificial layer 30 is removed within the gate region to form an isolation structure 33, see Figures 6 to 13 as shown.

[0080] It can be understood that the stacked structure 23 in the source / drain region is not covered by the dummy gate structure 26. By sequentially etching the first active structure 29, the second sacrificial layer 30, the second active structure 31, and the first sacrificial layer 32 in the source / drain region, the first deep trench 48 can be formed. Here, after etching the first active structure 29 in the source / drain region, the second sacrificial layer 30 can be exposed; subsequently, the second sacrificial layer 30 in the source / drain region and the gate region is selectively removed, and the second active structure 31 in the source / drain region can be exposed. Subsequently, etching the second active structure 31 in the source / drain region can expose the first sacrificial layer 32. Subsequently, etching the first sacrificial layer 32 in the source / drain region can form the first deep trench 48.

[0081] It can be understood that selectively removing the second sacrificial layer 30 between the first active structure 29 and the second active structure 31 in the gate region can form an unfilled space between the first active structure 29 and the second active structure 31 in the gate region. Subsequently, filling the unfilled space with an insulating material can form the isolation structure 33.

[0082] In some embodiments, the isolation structure 33 is used to electrically isolate the first active structure 29 and the second active structure 31 in the gate region.

[0083] In some embodiments, before step S104 and after step S103, it includes: depositing an oxide material in the first deep trench 48 to form a first filling structure 37a. Depositing an insulating material on the first filling structure 37a to form an isolation layer 38, see Figures 14 to 16 as shown.

[0084] It can be understood that the first active structure 29 and the second active structure 31 can be formed before and after flipping the wafer, respectively. Then, before forming the first active structure 29, an oxide material can be deposited in the first deep trench 48 to form the first filling structure 37a. The height of the first filling structure 37a is less than the height of the first active structure 29 and greater than the height of the second active structure 31. The first filling structure 37a completes the shielding of the second active structure 31 in the gate region, thereby ensuring that only the first active structure 29 is formed in the source / drain region before flipping the wafer. Subsequently, depositing an insulating material on the first filling structure 37a can form the isolation layer 38. The isolation layer 38 is used to isolate the subsequent generated first source / drain structure 112 and second source / drain structure 122.

[0085] In some embodiments, when a barrier layer 24 is formed between the stacked structure 23 and the semiconductor substrate 20, after step S103, it includes: etching the barrier layer 24 at the bottom of the first deep trench 48 to form the etched barrier layer 24. An oxide material is deposited at the position where the barrier layer 24 is etched to form the second filling structure 37b.

[0086] It can be understood that when a barrier layer 24 is formed on the semiconductor substrate 20, after the first deep trench 48 is formed, the barrier layer 24 (the barrier layer 24 within the source-drain region) at the bottom of the first deep trench 48 can be etched to form the etched barrier layer 24. The etched barrier layer 24 is located within the gate region. Subsequently, an oxide material is deposited at the position where the barrier layer 24 is etched, and the second filling structure 37b can be formed.

[0087] In one embodiment, after flipping the wafer, according to the position of the etched barrier layer 24, the position of the gate region can be located, facilitating the self-alignment of the stacked transistor 10.

[0088] In some embodiments, an oxide material is deposited within the first deep trench 48, and the first filling structure 37a and the second filling structure 37b can be formed simultaneously, as shown in Figure 15 shown.

[0089] In some embodiments, when the stacked transistor 10 is a fully surrounding gate field-effect transistor, both the first active structure 29 and the second active structure 31 are formed by alternately stacking a channel layer 35 and a sacrificial layer 34. Step S103 includes: laterally etching the sacrificial layer 34 in the active structure within the gate region to a preset depth. An insulating material is deposited at the position where the sacrificial layer 34 is etched to form the inner sidewall 36.

[0090] It can be understood that when the stacked transistor 10 is a fully surrounding gate field-effect transistor, forming the first deep trench 48 can expose the active structure within the gate region. Subsequently, the sacrificial layer 34 in the exposed active structure can be etched until the preset depth. An insulating material can be deposited at the position where the sacrificial layer 34 is etched to form the inner sidewall 36 of the fully surrounding gate transistor.

[0091] In some embodiments, the inner sidewall 36 of the fully surrounding gate transistor is used to electrically isolate the source-drain structure and the gate structure, ensuring the stability of the transistor structure.

[0092] In some embodiments, the inner sidewall 36 includes a first inner sidewall and a second inner sidewall. The first inner sidewall is opposite to the first active structure 29, and the second inner sidewall is opposite to the second active structure 31.

[0093] It can be understood that after the first deep trench 48 is formed, the inner sidewalls 36 in the first transistor 11 and the second transistor 12 can be formed simultaneously. The first inner sidewall of the first transistor 11 is used to isolate the first source / drain structure 112 and the first gate structure 114. The second inner sidewall of the second transistor 12 is used to isolate the second source / drain structure 122 and the second gate structure 124.

[0094] In one embodiment, the material for forming the inner sidewall 36 is the same as the material for forming the dummy gate sidewall 27.

[0095] Step S104, based on the first active structure 29 in the gate region, epitaxially grow the first source / drain structure 112 inside and outside the first deep trench 48, as shown in Figure 17 shown.

[0096] It can be understood that after the first deep trench 48 is formed, the first source / drain structure 112 can be epitaxially grown based on the first active structure 29 in the gate region. Here, the epitaxial growth direction is perpendicular to the first direction, and the epitaxial growth direction is from the gate region to the source / drain region. After the epitaxial growth is completed, the first source / drain structure 112 can be formed inside the first deep trench 48.

[0097] In one embodiment, after the first source / drain structure 112 is formed, a dielectric material can be deposited on the first source / drain structure 112 to form the first interlayer dielectric layer 113, as shown in Figure 18 shown.

[0098] It can be understood that the first interlayer dielectric layer 113 wraps the first source / drain structure 112 and can electrically isolate the first source / drain structure 112 from other structures.

[0099] Step S105, remove the dummy gate structure 26 and the first sacrificial layer 32 to expose the active structure in the gate region, as shown in Figure 19 shown.

[0100] It can be understood that after the first source / drain structure 112 is formed, the dummy gate structure 26 can be removed to expose the stacked structure 23 covered by the dummy gate structure 26. Subsequently, the first sacrificial layer 32 in the exposed stacked structure 23 is removed to completely expose the active structure, as shown in Figure 20 shown.

[0101] In some embodiments, when the stacked transistor 10 is a fully surrounding gate field effect transistor, after step S105, the method further includes: removing the sacrificial layer 34 in the active structure in the gate region and retaining the channel layer 35 in the active structure, so as to completely expose the channel layer 35 in the gate region.

[0102] Step S106, deposit a gate dielectric material on the exposed active structure to form a gate dielectric layer 39, as shown in Figure 21 the figure.

[0103] It can be understood that after the active structure in the gate region is exposed through step S105, a gate dielectric material can be deposited on the exposed active structure to form a gate dielectric layer 39.

[0104] In one embodiment, the gate dielectric layer 39 is located between the gate electrode layer and the active structure (channel). The gate dielectric layer 39 is used to prevent the gate current from directly flowing into the channel.

[0105] In one embodiment, the gate dielectric material for forming the gate dielectric layer 39 can be set according to actual needs, and the embodiments of the present application do not limit this. In one example, the gate dielectric layer 39 can be composed of a silicon oxide layer and a hafnium oxide layer with a high dielectric constant (high-k), and the thicknesses of the silicon oxide layer and the hafnium oxide layer can be determined according to the polarity and performance of the first transistor 11. In one example, the gate dielectric layer 39 can include: a 0.6nm silicon oxide layer and a 1.7nm hafnium oxide layer.

[0106] In some embodiments, the gate dielectric layer 39 includes a first gate dielectric layer 39a and a second gate dielectric layer 39b. The first gate dielectric layer 39a wraps the first active structure 29, and the second gate dielectric layer 39b wraps the second active structure 31.

[0107] Step S107, deposit a metal material on the first gate dielectric layer 39a to form a first gate electrode layer, as shown in Figure 23 the figure.

[0108] It can be understood that after the gate dielectric layer 39 is formed, a metal material can be deposited on the first gate dielectric layer 39a to form a first gate electrode layer.

[0109] In one embodiment, the first gate dielectric layer 39a and the first gate electrode layer are jointly used to form a first gate structure 114. The first gate structure 114 is the gate structure in the first transistor 11.

[0110] In one embodiment, the metal material for forming the gate electrode layer can be set according to actual needs, and the embodiments of the present application do not limit this. In one embodiment, the gate electrode layer can be composed of multiple layers of electrode materials, and each layer of electrode material includes but is not limited to hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).

[0111] In some embodiments, before step S107, it includes: depositing an oxide material within the gate region to form a third filling structure 40, where the third filling structure 40 wraps the second active structure 31 and the gate dielectric layer 39, and exposes the first active structure 29 and the first gate dielectric layer 39a. On the exposed first gate dielectric layer 39a, a first gate structure 114 can be formed, see Figure 22 as shown.

[0112] In some embodiments, after step S107, it includes: depositing a dielectric material on the first gate electrode layer and the first interlayer dielectric layer 113 to form a first dielectric layer 42; etching the first dielectric layer 42 and the first interlayer dielectric layer 113 until the first source / drain structure 112 is exposed to form a first via; depositing a metal material in the first via to form a first source / drain metal 115.

[0113] It can be understood that after the first gate structure 114 is formed, a first dielectric layer 42 can also be formed on the first gate structure 114 and the first interlayer dielectric layer 113. The first dielectric layer 42 is used for electrically isolating the source / drain metal and the gate oxide (such as the gate dielectric layer 39), thereby eliminating the adverse electrical effects caused by the direct contact between the source / drain metal and the gate oxide layer. After the first dielectric layer 42 is formed, the first dielectric layer 42 and the first interlayer dielectric layer 113 in the source / drain region can be etched to form source / drain metal vias. Subsequently, a metal material can be deposited in the source / drain metal vias to form a first source / drain metal 115, see Figure 25 as shown.

[0114] In some embodiments, after step S107, the method further includes: after the first gate structure 114 is formed, removing the third gate structure in the first gate structure 114 by using a gate cut process, and depositing an insulating material at the position where the third gate structure is removed to form a first gate isolation structure 41, see Figure 24 as shown.

[0115] In one embodiment, in the second direction, the third gate structure is located at both ends of the first gate structure 114.

[0116] It can be understood that after the first gate structure 114 is formed, the third gate structure in the first gate structure 114 can be removed. The third gate structure is a structure located at both ends of the first gate structure 114 in the second direction, and can also be understood as a structure located at both ends of the stacked transistor 10 in the second direction. After the third gate structure is removed, an insulating material can be deposited at the position where the third gate structure is removed to form a first gate isolation structure 41.

[0117] In some embodiments, the insulating material forming the first gate isolation structure 41 can be selected according to actual requirements, and the embodiments of the present application do not limit this.

[0118] In some embodiments, when removing the third gate structure in the first gate structure 114 by using a gate cut process, the third interlayer dielectric layer in the first interlayer dielectric layer 113 can be removed simultaneously, and the projection of the third interlayer dielectric layer in the third direction coincides with the projection of the third gate structure in the third direction. After the third interlayer dielectric layer is removed, an insulating material can be deposited at the position where the third interlayer dielectric layer is removed to form a continuous first gate isolation structure 41 in the third direction.

[0119] In one embodiment, after forming the first gate structure 114 and the first source / drain metal 115, a first metal interconnect layer 116 can be formed on the first gate structure 114 and the first source / drain metal 115 by using standard back-end processes in semiconductor manufacturing (such as deposition of interconnection dielectric, formation of metal lines, formation of lead pads, etc.), as shown in Figure 26 shown.

[0120] In some embodiments, after the first metal interconnect layer 116 is formed, the first transistor 11 can be formed.

[0121] It should be noted that, for the sake of convenience of description, the first source / drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the first source structure and / or the first drain structure. In addition, the second source / drain structure, the first source / drain metal, the second source / drain metal, etc. are similar to the first source / drain groove, and the "source / drain" therein is an abbreviation for "source and / or drain".

[0122] Step S108, flip the wafer and remove the semiconductor substrate 20, as shown in Figure 28 shown.

[0123] It can be understood that after obtaining the first transistor 11, the first transistor 11 can be flipped so that the prepared first transistor 11 is at the bottom and the second active structure 31 of the uncompleted second transistor 12 can be at the upper part, which is convenient for subsequent preparation of the second transistor 12.

[0124] In one embodiment, after completing the back-end process of the first transistor 11, the first transistor 11 can be bonded to the carrier wafer 44. For example, an insulating material (such as silicon oxide) can be deposited on the first transistor 11 to form an insulating layer 43, and the insulating layer 43 can be bonded to the carrier wafer 44. Then flip the wafer. After flipping, the first transistor 11 is at the bottom, as shown in Figure 27 shown.

[0125] In the embodiment of the present application, after the wafer 44 is bonded, it can provide physical support for the flipped first transistor 11 after the wafer is flipped, effectively preventing the first transistor 11 from being broken by external force during the process of manufacturing the second transistor 12.

[0126] In some embodiments, when a barrier layer 24 is provided between the stacked structure 23 and the semiconductor substrate 20, step S108 includes: flipping the wafer and removing the semiconductor substrate 20 to expose the etched barrier layer 24 and the shallow trench isolation structure 25. Remove the shallow trench isolation structure 25 and retain the etched barrier layer 24, as shown in Figure 29 shown.

[0127] It can be understood that after the wafer is flipped, processes such as polishing treatment or chemical mechanical planarization treatment can be used to remove the semiconductor substrate 20 to expose the etched barrier layer 24 and the shallow trench isolation structure 25. Subsequently, the shallow trench isolation structure 25 can be selectively etched to expose the etched barrier layer 24 and the structure protected by the etched barrier layer 24.

[0128] It can be understood that the etched barrier layer 24 is located within the gate region, so that the etched barrier layer 24 can protect the structures within the gate region from being affected by etching.

[0129] It can be understood that the gate region of the stacked transistor 10 can be located through the etched barrier layer 24, thereby realizing the self-alignment of the gate regions and the source-drain regions of the front and back two layers of transistors.

[0130] Step S109, based on the second active structure 31 within the gate region, epitaxially grow a second source-drain structure 122 inside and outside the first deep trench 48, as shown in Figure 32 shown.

[0131] It can be understood that after the second active structure 31 is exposed, a second source-drain structure 122 can be epitaxially grown inside and outside the first deep trench 48 based on the second active structure 31 within the gate region.

[0132] Here, the step of epitaxially growing the second source-drain structure 122 is the same as the step of epitaxially growing the first source-drain structure 112. For the sake of simplicity of the specification, it will not be elaborated here.

[0133] In some embodiments, during the process of manufacturing the first transistor 11, if a first filling structure 37a is filled into the first deep trench 48, then before step S109, the method further includes: removing the first filling structure 37a within the first deep trench 48 to expose the second active structure 31 within the gate region, as shown in Figure 31 shown.

[0134] It can be understood that by removing the first filling structure 37a in the first deep groove 48, the second active structure 31 in the gate region can be exposed, and thus, based on the exposed active structure, the second source-drain structure 122 can be formed.

[0135] In some embodiments, before step S109, it includes: sequentially etching the second filling structure 37b and the first filling structure 37a that are not covered by the etched barrier layer 24 until the isolation layer 38 is exposed.

[0136] It can be understood that the second filling structure 37b and the first filling structure 37a that are not covered by the etched barrier layer 24 can be etched during the etching process. During this process, the etched barrier layer 24 is used as a hard mask to protect the structure covered by the etched barrier layer 24.

[0137] Step S110, deposit a metal material on the second gate dielectric layer 39b to form a second gate electrode layer, as shown in Figure 35 shown.

[0138] It can be understood that the second gate dielectric layer 39b can be formed simultaneously with the first gate dielectric layer 39a. After flipping the wafer, only need to deposit a metal material on the second gate dielectric layer 39b to form a second gate electrode layer, and then form the second gate structure 124.

[0139] In one embodiment, the second gate dielectric layer 39b and the second gate electrode layer are jointly used to form the second gate structure 124. The second gate structure 124 is the gate structure in the second transistor 12.

[0140] In some embodiments, before step S110, it includes: removing the filling structure 37 formed in the gate region to expose the second active structure 31 and the second gate dielectric layer 39b. On the exposed second gate dielectric layer 39b, the second gate structure 124 can be formed.

[0141] In some embodiments, after step S107, it includes: depositing a dielectric material on the second gate electrode layer and the second interlayer dielectric layer 123 to form a second dielectric layer 46; etching the second dielectric layer 46 and the second interlayer dielectric until the second source-drain structure 122 is exposed to form a second via; depositing a metal material in the second via to form a second source-drain metal 125, as shown in Figure 37 shown.

[0142] It can be understood that after the second gate structure 124 is formed, a second dielectric layer 46 can also be formed on the second gate structure 124 and the second interlayer dielectric layer 123. The function of the second dielectric layer 46 is the same as that of the first dielectric layer 42. After the second dielectric layer 46 is formed, the second dielectric layer 46 and the second interlayer dielectric layer 123 in the source-drain region can be etched to form source-drain metal vias. Subsequently, a metal material can be deposited in the source-drain metal vias to form the second source-drain metal 125.

[0143] In some embodiments, after step S107, the method further includes: after the second gate structure 124 is formed, the fourth gate structure in the second gate structure 124 is removed by a gate cut process, and an insulating material is deposited at the position where the fourth gate structure is removed to form a second gate isolation structure 47, see Figure 36 as shown.

[0144] In one embodiment, in the second direction, the fourth gate structure is located at both ends of the second gate structure 124.

[0145] It can be understood that after the second gate structure 124 is formed, the fourth gate structure in the second gate structure 124 can be removed. The fourth gate structure is a structure located at both ends of the second gate structure 124 in the second direction, and can also be understood as a structure located at both ends of the stacked transistor 10 in the second direction. After the fourth gate structure is removed, an insulating material can be deposited at the position where the fourth gate structure is removed to form a second gate isolation structure 47.

[0146] In some embodiments, the insulating material for forming the second gate isolation structure 47 can be selected according to actual needs, and the embodiments of the present application do not limit this.

[0147] In some embodiments, when the fourth gate structure in the second gate structure 124 is removed by a gate cut process, the fourth interlayer dielectric layer in the second interlayer dielectric layer 123 can be removed at the same time. The projection of the fourth interlayer dielectric layer in the third direction coincides with the projection of the fourth gate structure in the third direction. After the fourth interlayer dielectric layer is removed, an insulating material can also be deposited at the position where the fourth interlayer dielectric layer is removed to form a second gate isolation structure 47 that is continuous in the third direction.

[0148] In some embodiments, the first gate isolation structure 41 and the second gate isolation structure 47 are disposed opposite to each other.

[0149] In one embodiment, after forming the second gate structure 124 and the second source / drain metal 125, a second metal interconnect layer 126 can be formed on the second gate structure 124 and the second source / drain metal 125 by using standard back-end processes in semiconductor manufacturing (such as inter-metal dielectric deposition, metal line formation, lead pad formation, etc.), as shown in Figure 38 shown.

[0150] In some embodiments, after the second metal interconnect layer 126 is formed, a second transistor 12 can be formed.

[0151] Thus, the fabrication of the stacked transistors is completed. It should be noted that the first source / drain structure and the first gate structure together constitute the first transistor, and the second source / drain structure and the second gate structure together constitute the second transistor; the first transistor or the second transistor is any one of the following: fin field-effect transistor, gate-all-around field-effect transistor, vertical field-effect transistor, complementary field-effect transistor, crossbar transistor, and planar field-effect transistor, which are not limited in the embodiments of the present application.

[0152] In the embodiments of the present disclosure, by etching once on a semiconductor substrate to form a stacked structure, and the stacked structure includes an active structure, it can be realized that the active regions of the front and back transistors in the stacked transistors are self-aligned. Subsequently, a dummy gate structure shared by the front and back transistors is formed. After the first source / drain structure in the source / drain region is formed, the dummy gate structure is removed, and the self-aligned active structure in the gate region can be exposed. Subsequently, a self-aligned gate dielectric layer can be formed based on the self-aligned active structure in the exposed gate region, and finally, the complete self-alignment of the front and back transistors is realized.

[0153] In this way, on the one hand, fewer high aspect ratio processes can be used, which is more compatible with the complete self-alignment flip-chip stacking of various types of transistors, and the "self-aligned flip-chip transistor" solution can be further optimized; on the other hand, by preferentially preparing the gate dielectric layer, it can be ensured that the subsequent structure no longer bears a higher thermal budget, effectively improving the structure performance.

[0154] Next, in combination with Figures 2 to 31 the manufacturing process of the stacked transistors shown, a specific example is used to illustrate the manufacturing method of the stacked transistors in the present application.

[0155] In one example, the manufacturing process of the stacked transistors may include the following steps:

[0156] The first step: Epitaxially grow silicon germanium and silicon on a semiconductor substrate 20 (formed of silicon) to form an initial stacked structure 21 and an initial barrier layer 22, obtaining a structure as shown in Figure 3 shown.

[0157] It is understandable that the initial barrier layer 22 is located between the semiconductor substrate 20 and the initial stack structure 21.

[0158] Here, the initial stack structure 21 is formed by alternately arranging silicon germanium layers and silicon layers.

[0159] The second step: Through photolithography, the stack structure 23 and the barrier layer 24 are formed by one-time etching to obtain the structure as Figure 4 shown.

[0160] It is understandable that in the cross-sectional views in the A-A' direction and the B-B' direction, the parts on both sides of the initial stack structure 21 are etched to form the stack structure 23 for fabricating a fully-depleted surround gate field-effect transistor.

[0161] In some embodiments, the material for forming the barrier layer 24 can have a certain hardness, so that the barrier layer 24 can be used as an etch stop layer after wafer flipping.

[0162] The third step, an oxide material is deposited on the semiconductor substrate 20 to form a shallow trench isolation structure 25 to obtain the structure as Figure 5 shown.

[0163] Here, the shallow trench isolation structure 25 wraps the barrier layer 24, and the stack structure 23 is exposed outside the shallow trench isolation structure 25.

[0164] The fourth step, a dummy gate structure 26 that wraps the stack structure 23 is formed. After the dummy gate structure 26 is formed, a dummy gate sidewall 27 is deposited to obtain the structure as Figure 6 shown.

[0165] It is understandable that the dummy gate structure 26 is a dummy gate structure shared by two layers of crystals in the positive and negative directions. When the dummy gate sidewall 27 is formed by an isotropic deposition process, the dummy gate sidewall 27 can cover the sidewalls of the dummy gate structure 26 in the gate region and the stack structure 23 in the source / drain region.

[0166] The fifth step, the dummy gate sidewall 27 is etched until the first active structure 29 and the second sacrificial layer 30 in the stack structure 23 in the source / drain region are exposed to obtain the structure as Figure 7 shown.

[0167] It is understandable that the exposure of the first active structure 29 and the second sacrificial layer 30 can be achieved by an anisotropic etching process.

[0168] It should be noted that as Figure 7 shown, after the first active structure 29 and the second sacrificial layer 30 are exposed, in the cross-sectional view in the C-C' direction, a part of the dummy gate sidewall 27 remains on the sidewalls of the dummy gate structure 26. This dummy gate sidewall 27 can be used as a hard mask in subsequent fabrication processes.

[0169] Step 6: Etch the first active structure 29 in the source / drain region to obtain the structure as shown in Figure 8 the figure.

[0170] It can be understood that by using the pseudo-gate structure 26 and the pseudo-gate sidewall 27 as hard masks, the first active structure 29 located in the source / drain region can be selectively etched.

[0171] Step 7: Selectively remove the second sacrificial layer 30 to isolate the first active structure 29 and the second active structure 31, and obtain the structure as shown in Figure 9 the figure.

[0172] It can be understood that by removing the second sacrificial layer 30 formed of silicon germanium, electrical isolation between the first active structure 29 and the second active structure 31 can be achieved.

[0173] Step 8: Deposit an insulating material such as silicon nitride, and perform a chemical mechanical planarization process on the isolation structure 33 formed of the silicon nitride material to obtain the structure as shown in Figure 10 the figure.

[0174] Step 9: Use an anisotropic etching process to remove the redundant isolation structure 33, and retain the isolation structure 33 between the first active structure 29 and the second active structure 31 in the gate region, to obtain the structure as shown in Figure 11 the figure.

[0175] It can be understood that after removing the redundant isolation structure 33, an isolation structure 33 can be formed at the position where the second sacrificial layer 30 is removed.

[0176] Step 10: Laterally etch the sacrificial layer 34 in the first active structure 29 to a certain depth. Deposit a silicon nitride insulating material at the position where the sacrificial layer 34 is removed to form the internal sidewall 36 of the first transistor 11, and obtain the structure as shown in Figure 12 the figure.

[0177] It can be understood that in this embodiment, the stacked transistor 10 is a fully surrounding gate field effect transistor. Therefore, it is necessary to form the internal sidewall 36. When the stacked transistor 10 is a fin field effect transistor, a planar field effect transistor, etc., there is no need to form the internal sidewall 36.

[0178] Step 11: Use an anisotropic etching process to etch the second active structure 31 in the source / drain region. Subsequently, laterally etch the sacrificial layer 34 in the second active structure 31 to a certain depth. Deposit a silicon nitride insulating material at the position where the sacrificial layer 34 is removed to form the internal sidewall 36 of the second transistor 12. Subsequently, use an anisotropic etching process to etch the first sacrificial layer 32 located at the bottom of the second active structure 31, and obtain the structure as shown in Figure 13 the figure.

[0179] In some embodiments, the inner sidewall 36 of the second transistor 12 may be fabricated after wafer flipping. For example, after removing the filling structure 37 in the first deep trench, the sacrificial layer 34 in the second active structure 31 is etched laterally to a certain depth, and a silicon nitride insulating material is deposited at the position where the sacrificial layer 34 is removed to form the inner sidewall 36 of the second transistor 12.

[0180] The twelfth step is to perform anisotropic etching on the barrier layer 24 and the shallow trench isolation structure 25 located in the source-drain region to obtain a structure as Figure 14 shown.

[0181] It can be understood that after performing anisotropic etching on the barrier layer 24 located in the source-drain region, an etched barrier layer 24 is formed. The etched barrier layer 24 is located in the gate region. After wafer flipping, the position of the gate region can be obtained based on the etched barrier layer 24.

[0182] The thirteenth step is to deposit a filling material in the source-drain region to form a filling structure 37 to obtain a structure as Figure 15 shown.

[0183] In one embodiment, the filling structure 37 includes a first filling structure 37a and a second filling structure 37b. The first filling structure 37a is opposite to the position of the second active structure 31, and the second filling structure 37b is opposite to the position of the etched barrier layer 24.

[0184] In one embodiment, as Figure 15 shown, the height of the top surface of the filling structure 37 is lower than the height of the top surface of the isolation structure 33 and higher than the height of the bottom surface of the isolation structure 33.

[0185] The fourteenth step is to deposit an insulating material in the source-drain region to form an isolation layer 38 to obtain a structure as Figure 16 shown.

[0186] It can be understood that the isolation layer 38 is used to electrically isolate the first source-drain structure 112 and the second source-drain structure 122.

[0187] The fifteenth step is to epitaxially form a first source-drain structure 112 in the source-drain region based on the first active structure 29 in the gate region to obtain a structure as Figure 17 shown.

[0188] The sixteenth step is to deposit an interlayer dielectric material in the source-drain region to form a first interlayer dielectric layer 113 to obtain a structure as Figure 18 shown.

[0189] The seventeenth step is to remove the dummy gate structure 26 to obtain a structure as Figure 19 shown.

[0190] It can be understood that after removing the dummy gate structure 26, the active structure within the gate region can be exposed.

[0191] In the eighteenth step, the sacrificial layer 34 and the first sacrificial layer 32 in the active structure within the gate region are removed to obtain the structure as Figure 20 shown.

[0192] In the nineteenth step, a gate dielectric material is deposited on the remaining channel layer 35 to form a gate dielectric layer 39, obtaining the structure as Figure 21 shown.

[0193] It can be understood that in this step, the gate dielectric layers 39 of both the positive and negative transistors can be formed simultaneously, thereby improving the thermal budget for fabricating subsequent structures.

[0194] It should be noted that the isolation structure 33 between the first gate structure 114 and the second gate structure 124 will also be wrapped by the gate dielectric layer 39.

[0195] In the twentieth step, an oxide material is deposited to form an initial filling structure. Subsequently, a chemical mechanical planarization process is used to planarize the initial filling structure and etch it to a preset height to form a third filling structure 40 that wraps the second active structure 31, obtaining the structure as Figure 22 shown.

[0196] In the twenty - first step, a metal material is deposited to form the first gate electrode layer of the first transistor 11. The first gate electrode layer and the first gate dielectric layer 39a jointly form the first gate structure 114, obtaining the structure as Figure 23 shown.

[0197] In the twenty - second step, a first gate isolation structure 41 is formed, obtaining the structure as Figure 24 shown.

[0198] It can be understood that in the cross - sectional view in the A - A' direction and the cross - sectional view in the B - B' direction, the first gate isolation structure 41 is located on both sides.

[0199] In the twenty - third step, a dielectric material is deposited on the first interlayer dielectric layer 113 and the first gate structure 114 to form a first dielectric layer 42. Subsequently, the first dielectric layer 42 and the first interlayer dielectric layer 113 are etched until the first source - drain structure 112 is exposed, and then a first source - drain metal 115 is deposited, obtaining the structure as Figure 25 shown.

[0200] In the twenty - fourth step, a first metal interconnect layer 116 is formed, obtaining the structure as Figure 26 shown.

[0201] Step 25: Deposit an insulating material (such as silicon oxide) on the first metal interconnect layer 116 to form an insulating layer 43, and bond the insulating layer 43 to the carrier wafer 44. Then, flip the wafer. After flipping, the structure as shown in Figure 27 is obtained.

[0202] Step 26: Remove the semiconductor substrate 20 to obtain the structure as shown in Figure 28 is obtained.

[0203] It can be understood that after removing the semiconductor substrate 20, the etched barrier layer 24 and the filling structure 37 in the source / drain region can be exposed.

[0204] Step 27: Selectively etch away the shallow trench isolation structure 25 that wraps the etched barrier layer to obtain the structure as shown in Figure 29 is obtained.

[0205] Step 28: Deposit polysilicon at the position where the shallow trench isolation structure 25 is removed to form a fourth filling structure 45, and obtain the structure as shown in Figure 30 is obtained.

[0206] Here, the fourth filling structure 45 is located around the etched barrier layer.

[0207] In some embodiments, the material for forming the fourth filling structure 45 can be the same as the material for forming the third filling structure 40. The material for forming the third filling structure 40 is different from the material for forming the barrier layer 24.

[0208] Step 29: Remove the filling structure 37 in the source / drain region until the isolation layer 38 is exposed to obtain the structure as shown in Figure 31 is obtained.

[0209] It can be understood that the etched barrier layer 24 is located in the gate region, and the position of the source / drain region can be determined according to the position of the etched barrier layer 24.

[0210] Step 30: Based on the second active structure 31 in the gate region, epitaxially grow a second source / drain structure 122 inside and outside the source / drain region, and deposit a dielectric material on the second source / drain structure 122 to form a second interlayer dielectric layer 123, and obtain the structure as shown in Figure 32 is obtained.

[0211] In some embodiments, before forming the second source / drain structure 122, the sacrificial layer 34 in the second active structure 31 can be laterally etched to a certain depth, and a silicon nitride insulating material can be deposited at the position where the sacrificial layer 34 is removed to form an inner sidewall 36 of the second transistor 12.

[0212] Step 31: Thin the semiconductor structure until the etched barrier layer 24 is removed to obtainFigure 33 The structure shown.

[0213] In the thirty-second step, the third filling structure 40 is thinned to be lower than the bottom of the second active structure 31 to expose the second active structure 31 in the gate region. After the third filling structure 40 is thinned, it can be used as the isolation structure between the first gate structure 114 and the second gate structure 124, obtaining the structure as Figure 34 The structure shown.

[0214] It can be understood that the second gate dielectric layer 39b wraps the second active structure 31.

[0215] In the thirty-third step, a metal material is deposited on the second gate dielectric layer 39b to form a second gate electrode layer, obtaining the structure as Figure 35 The structure shown.

[0216] It can be understood that the second gate dielectric layer 39b and the second gate electrode layer together form the second gate structure 124.

[0217] In the thirty-fourth step, a second gate isolation structure 47 is formed, obtaining the structure as Figure 36 The structure shown.

[0218] It can be understood that in the cross-sectional view in the A - A' direction and the cross-sectional view in the B - B' direction, the second gate isolation structure 47 is located on both sides.

[0219] In the thirty-fifth step, a dielectric material is deposited on the second interlayer dielectric layer 123 and the second gate structure 124 to form a second dielectric layer 46. Subsequently, the second dielectric layer 46 and the second interlayer dielectric layer 123 are etched until the second source / drain structure 122 is exposed, and then a second source / drain metal 125 is deposited, obtaining the structure as Figure 37 The structure shown.

[0220] In the thirty-sixth step, a second metal interconnect layer 126 is formed, obtaining the structure as Figure 38 The structure shown.

[0221] It can be understood that after the second metal interconnect layer is formed, the stacked transistor in the embodiment of the present application is fabricated.

[0222] In the embodiment of the present disclosure, by fabricating the first transistor before flipping the wafer and the second transistor after flipping the wafer, a complementary flip-chip stacked transistor can be formed. The dummy gate structures of the first transistor and the second transistor are integrally formed, enabling the use of fewer deep aspect ratio processes and more compatibly achieving the complete self-aligned flip-chip stacking of various forms of transistors. Further, the gate dielectric layers of the first transistor and the second transistor can be integrally formed before flipping the wafer, enabling the generation of the gate dielectric layer to be completed before most of the transistor structures are formed, which can reduce the damage to the transistor caused by high temperature.

[0223] In an embodiment of the present disclosure, a stacked transistor is provided, and the stacked transistor can be fabricated by the method in one or more corresponding embodiments. Refer to Figure 1 as shown below. The stacked transistor 10 includes: Figure 38 as shown. The stacked transistor 10 includes:

[0224] A first transistor 11 and a second transistor 12, the first transistor and the second transistor 12 are arranged back to back, a first active structure 29 of the first transistor 11 and a second active structure 31 of the second transistor 12 form an active structure; the first transistor 11 includes a first gate structure 114, and the second transistor 12 includes a second gate structure 124. The first gate structure 114 of the first transistor 11 and the second gate structure 124 of the second transistor 12 are self-aligned.

[0225] In some embodiments, the first transistor 11 or the second transistor 12 is any one of the following: fin field effect transistor, gate-all-around field effect transistor, vertical field effect transistor, complementary field effect transistor, crossbar transistor, and planar field effect transistor. The embodiments of the present application do not limit this.

[0226] It can be understood that the flip-chip stacked transistor solution in the embodiments of the present application has self-alignment. On the one hand, it solves the long-term problems such as complex processes and difficult alignment existing in the existing mainstream technical solutions of stacked transistors, and realizes the promotion of the industrialization of transistor stacking technology. On the other hand, through the self-aligned "back-to-back" active structure and gate structure, the upper and lower transistors can have independent signal and power supply networks, and are interconnected through the stacked transistors, greatly releasing the metal wiring resources.

[0227] Finally, the solution of realizing the upper and lower transistors by flipping the chip is compatible with the existing mainstream device architectures, and can realize the front and back stacking of including planar transistors, FinFETs, GAA Nanosheets, Forksheet (crossbar transistors), and even vertical transistors (VTFETs), without the need for special process development for specific device architectures, with strong flexibility and strong extensibility from the perspective of semiconductor process node iteration. The flip-chip transistor is very advanced in concept, has important industrial value, and has strong practicability and broad development prospects.

[0228] An embodiment of the present application provides a semiconductor device, including: the stacked transistor as described in the above embodiment. For the specific definition of the stacked transistor, reference can be made to the stacked transistor shown above Figure 38 and will not be elaborated here.

[0229] An embodiment of the present application provides an electronic device, including: a circuit board and a semiconductor device as described in the above embodiment, and the semiconductor device is disposed on the circuit board. The semiconductor device includes the above-mentioned stacked transistors. For the specific definition of the stacked transistors, reference may be made to the structure shown in the above Figure 38 and will not be elaborated here.

[0230] In the description of the present application, the description with reference to terms such as "an embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic expression of the above terms is not necessarily directed to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art may combine the different embodiments or examples described in the present application and the features of the different embodiments or examples.

[0231] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application may have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a stacked transistor, characterized in that: The method comprises: Etching once on a semiconductor substrate to form a stacked structure, wherein the stacked structure includes an active structure and a first sacrificial layer, and the active structure includes a first active structure and a second active structure; the first active structure, the second active structure and the first sacrificial layer are stacked in sequence in a first direction, the first active structure is farther away from the semiconductor substrate than the first sacrificial layer, and the first direction is a direction perpendicular to the semiconductor substrate; In the gate region of the stacked transistor, forming a dummy gate structure covering the stacked structure; Etching the stacked structure not covered by the dummy gate structure to form a first deep trench; Based on the first active structure in the gate region, epitaxially growing a first source-drain structure in the first deep trench; removing the dummy gate structure and the first sacrificial layer to expose the active structure in the gate region; Depositing a gate dielectric material on the exposed active structure to form a gate dielectric layer, wherein the gate dielectric layer includes a first gate dielectric layer and a second gate dielectric layer, wherein the first gate dielectric layer wraps the first active structure, and the second gate dielectric layer wraps the second active structure; Depositing a metal material on the first gate dielectric layer to form a first gate electrode layer, wherein the first gate dielectric layer and the first gate electrode layer together constitute a first gate structure; Flipping and removing the semiconductor substrate; Based on the second active structure in the gate region, epitaxially growing a second source-drain structure in the first deep trench; A metal material is deposited on the second gate dielectric layer to form a second gate electrode layer. The second gate dielectric layer and the second gate electrode layer together constitute a second gate structure.

2. The preparation method according to claim 1, characterized in that: Before epitaxially growing a first source-drain structure in the first deep trench based on the first active structure in the gate region, the method further includes: Depositing an oxide material in the first deep trench to form a first filling structure, wherein a height of the first filling structure is smaller than a height of the first active structure and larger than a height of the second active structure; Depositing an insulating material on the first filling structure to form an isolation layer, wherein the isolation layer is used to isolate the first source-drain structure from the second source-drain structure; Before epitaxially growing a second source-drain structure in the first deep trench based on the second active structure in the gate region, the method further includes: The first filling structure in the first deep trench is removed to expose the second active structure in the gate region.

3. The preparation method according to claim 2, characterized in that: The active structure further includes: a second sacrificial layer, the second sacrificial layer being located between the first active structure and the second active structure; The etching of the stacked structure not covered by the dummy gate structure to form a first deep trench comprises: Etching the first active structure, the second sacrificial layer, the second active structure, and the first sacrificial layer that are not covered by the dummy gate structure to form the first deep trench; In the gate region, an insulating material is deposited at a position where the second sacrificial layer is removed to form an isolation structure.

4. The preparation method according to claim 2, characterized in that: The method of etching a semiconductor substrate once to form a stacked structure comprises: forming an initial stacking structure and an initial barrier layer on a semiconductor substrate, wherein the initial barrier layer is located between the initial stacking structure and the semiconductor substrate; Etching the initial stacking structure and the initial barrier layer at one time to form the stacking structure and the barrier layer; Depositing an oxide material on the semiconductor substrate to form a shallow trench isolation structure, wherein the shallow trench isolation structure wraps the barrier layer; After etching the stacked structure not covered by the dummy gate structure to form a first deep trench, the method further includes: Etching the barrier layer at the bottom of the first deep trench to form an etched barrier layer, wherein the etched barrier layer is located in the gate region; depositing an oxide material at the location where the barrier layer is etched to form a second filling structure; The flipping and removing of the semiconductor substrate comprises: Flipping and removing the semiconductor substrate to expose the etched barrier layer and the shallow trench isolation structure; Removing the shallow trench isolation structure and retaining the etched barrier layer; Before epitaxially growing a second source-drain structure in the first deep trench based on the second active structure in the gate region, the method further includes: The second filling structure and the first filling structure not covered by the etched barrier layer are sequentially etched until the isolation layer is exposed.

5. The preparation method according to claim 1, characterized in that: When the stacked transistor is a full-surround gate field effect transistor, the first active structure and the second active structure are both formed by alternately stacking channel layers and sacrificial layers; After etching the stacked structure not covered by the dummy gate structure to form a first deep trench, the method further includes: Laterally etching the sacrificial layer in the active structure in the gate region to a preset depth; Depositing an insulating material at a position where the sacrificial layer is etched to form an inner spacer, wherein the inner spacer comprises a first inner spacer and a second inner spacer, wherein the first inner spacer is opposite to the first active structure, and the second inner spacer is opposite to the second active structure; After removing the dummy gate structure and the first sacrificial layer to expose the active structure in the gate region, the method further includes: The sacrificial layer in the gate region is removed.

6. The preparation method according to claim 1, characterized in that: The method further comprises: After the first gate structure is formed, a third gate structure in the first gate structure is removed by a gate cutting process, and an insulating material is deposited at a position where the third gate structure is removed to form a first gate isolation structure; wherein, in a second direction, the third gate structure is located at two ends of the first gate structure; and the second direction is perpendicular to the first direction; and / or, After the second gate structure is formed, a gate cutting process is used to remove the fourth gate structure in the second gate structure, and an insulating material is deposited at the position where the fourth gate structure is removed to form a second gate isolation structure; wherein, in the second direction, the fourth gate structure is located at both ends of the second gate structure.

7. The preparation method according to claim 1, characterized in that: After epitaxially growing a first source-drain structure in the first deep trench based on the first active structure in the gate region, the method further includes: Depositing a dielectric material on the first source-drain structure to form a first interlayer dielectric layer; After depositing a metal material on the first gate dielectric layer to form a first gate electrode layer, the method further includes: Depositing a dielectric material on the first gate electrode layer and the first interlayer dielectric layer to form a first dielectric layer; Etching the first dielectric layer and the first interlayer dielectric until the first source-drain structure is exposed to form a first through hole; A metal material is deposited in the first through hole to form a first source-drain metal.

8. The preparation method according to claim 1, characterized in that: The first source-drain structure and the first gate structure together constitute a first transistor, and the second source-drain structure and the second gate structure together constitute a second transistor; The first transistor or the second transistor is any one of the following: FinFET, gate-all-around FET, vertical FET, complementary FET, forkplate FET, and planar FET.

9. A stacked transistor, prepared using the preparation method according to any one of claims 1 to 8, characterized in that: include: a first transistor; a second transistor, wherein the first transistor and the second transistor are arranged opposite to each other, and a first active structure of the first transistor and a second active structure of the second transistor form an active structure; The first gate structure of the first transistor and the second gate structure of the second transistor are self-aligned.

10. A semiconductor device, characterized in that: include: The stacked transistor as claimed in claim 9.

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