A method for reducing fin misalignment in transistor and transistor structure thereof

Abstract

The present invention relates to a method for reducing the misalignment of fins in transistors and a transistor structure thereof, comprising: providing a substrate; depositing a shallow trench isolation dielectric film on the substrate; forming a fin on the substrate, and the fin protruding from the upper surface of the shallow trench isolation dielectric film; depositing a gate on the substrate, the gate spanning the fin; forming a gate cut-off structure in the gate for cutting the gate into independent gate segments; the gate cut-off structure is an inverted trapezoidal structure, and the gate cut-off structure is filled with a stacked film formed by stacked deposition of a nitrogen source and a silicon source. By optimizing the design of the shallow trench isolation dielectric film and the gate cut-off structure, the stress distribution of the upper part of the fin in the gate and the lower part in the shallow trench isolation dielectric film in the MOS tube is reduced, so as to reduce the warping misalignment between the upper and lower parts caused by stress.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuit design and manufacturing, and in particular relates to a method for reducing fin misalignment in a transistor and a transistor structure thereof. Background Art

[0002] In large-scale integrated circuits, fin field-effect transistors are controlled by gates through fins as channels, which can greatly enhance static circuit control and reduce the impact of leakage and short channel effects.

[0003] However, as the size shrinks, the structure of the fin gradually develops towards a narrower and taller direction, which will amplify some structural weaknesses, such as fin misalignment and fin warping. Fin field effect transistors at more advanced nodes will be more sensitive to these weaknesses, causing increased leakage, and these weaknesses are usually caused by structural stress and physical damage. Among them, the asymmetric stress of the shallow trench isolation dielectric film (STI FCVD) and the gate cut structure (Poly Cut) can cause the warping of the fin, especially in the structure of a single fin. For details, please refer to Figure 2 The stress distribution (indicated by arrows) between the upper part of the fin located in the gate (Poly) and the lower part located in the shallow trench isolation dielectric film (STI FCVD) causes the warping misalignment between the upper and lower parts of the fin.

[0004] In current fin field effect transistors, the gate cut-off structure generally adopts a square structure, and the shallow trench isolation dielectric film is generally cured by ozone irradiation (O3curve). No attention has been paid to the fin misalignment and warping problems caused by the shear stress brought by the gate cut-off structure and the shallow trench isolation dielectric film. Summary of the invention

[0005] In order to solve all or part of the problems of the above-mentioned prior art, the present invention provides a method for reducing fin misalignment in a transistor and a transistor structure thereof, which can reduce the total amount of shear stress of the fin (Fin) by optimizing the design of a shallow trench isolation dielectric film (STI FCVD) and a gate cut-off structure (Poly Cut), thereby reducing the probability of fin misalignment defects.

[0006] In order to achieve the above objectives, in a first aspect, the present invention provides a method for reducing fin misalignment in a transistor, comprising:

[0007] providing a substrate;

[0008] A shallow trench isolation dielectric film is deposited on the substrate;

[0009] A fin is formed on the substrate, and the fin protrudes from the upper surface of the shallow trench isolation dielectric film;

[0010] A gate is also deposited on the substrate, and the gate spans across the fin;

[0011] A gate cut-off structure is formed in the gate for cutting the gate into independent gate segments; the gate cut-off structure is an inverted trapezoidal structure, and the gate cut-off structure is filled with a stacked film formed by stacked deposition of a nitrogen source and a silicon source.

[0012] In some of the embodiments, the inverted trapezoidal structure of the gate cut-off structure means that a cross section of the gate cut-off structure obtained by analyzing along the gate extension direction is an inverted trapezoidal structure;

[0013] The two inner angles on the lower base of the inverted trapezoidal structure satisfy 95° to 125°;

[0014] The ratio of the additional depth to the height of the gate cut-off structure is less than a preset ratio;

[0015] The additional depth refers to the depth of the gate cut-off structure below the shallow trench isolation dielectric film.

[0016] In some of the embodiments, the stacked film includes a film formed by sequentially growing silicon nitride and silicon dioxide layers;

[0017] The stacked film includes at least one of a NO structure film, a NON structure film and a NONO structure film;

[0018] The NO structure film refers to a film formed by sequentially stacking silicon nitride and silicon dioxide; wherein the thickness of the silicon dioxide accounts for 5% to 30% of the total thickness of the NO structure film;

[0019] The NON structure film refers to a film formed by sequentially stacking silicon nitride, silicon dioxide and silicon nitride; wherein the thickness of the outermost silicon nitride layer accounts for 50% to 90% of the total thickness of the NON structure film; the thickness of the middle silicon dioxide layer accounts for 5% to 30% of the total thickness of the NON structure film; the thickness of the inner silicon nitride layer accounts for 5% to 20% of the total thickness of the NON structure film;

[0020] The NONO structure film refers to a film formed by sequentially stacking silicon nitride, silicon dioxide, silicon nitride and silicon dioxide; wherein the thickness of the outermost silicon nitride layer accounts for 50% to 80% of the total thickness of the NONO structure film; the thickness of the second outermost silicon dioxide layer accounts for 5% to 20% of the total thickness of the NONO structure film; the thickness of the second inner silicon nitride layer accounts for 5% to 20% of the total thickness of the NONO structure film; and the thickness of the inner silicon dioxide layer accounts for 5% to 20% of the total thickness of the NONO structure film.

[0021] In some embodiments, the gate cut-off structure is filled with a stacked film formed by stacked deposition of a nitrogen source and a silicon source, including:

[0022] During the stacking deposition, the molar ratio of the nitrogen source to the silicon source satisfies 0.8:1 to 2:1; wherein the silicon source is at least one of SiH4, SiHCl4, and SiH2Cl2; and the nitrogen source is at least one of NH3 and N2;

[0023] The deposition method of the laminated film is chemical vapor deposition or plasma enhanced chemical vapor deposition; the deposition temperature satisfies 550° to 700°;

[0024] The molar ratio of the atmosphere gas to the sum of the nitrogen source and the silicon source during the stacking deposition satisfies 10% to 50%, and the atmosphere gas is at least one of N2 and NO2.

[0025] In some embodiments, the gate cut-off structure is filled with a stacked film formed by stacked deposition of a nitrogen source and a silicon source, including:

[0026] After the stack is deposited, the stacked film is also subjected to thermal annealing;

[0027] The thermal annealing treatment adopts at least one of soak annealing, spike annealing and laser annealing; the temperature of the thermal annealing treatment satisfies 400° to 800°.

[0028] In some embodiments, a shallow trench isolation dielectric film is deposited on the substrate, comprising:

[0029] The shallow trench isolation dielectric film is cured by ultraviolet irradiation;

[0030] After deposition, the shallow trench isolation dielectric film is subjected to thermal annealing treatment, and the power of the thermal annealing treatment meets 600W to 2000W.

[0031] In a second aspect, the present invention provides a transistor structure for reducing fin dislocation, wherein a shallow trench isolation dielectric film, a fin and a gate are formed on a substrate;

[0032] The fin protrudes from the upper surface of the shallow trench isolation dielectric film;

[0033] The gate crosses the fin;

[0034] A gate cut-off structure is formed in the gate for cutting the gate into independent gate segments; the gate cut-off structure is an inverted trapezoidal structure; and the gate cut-off structure is filled with a stacked film formed by stacked deposition of a nitrogen source and a silicon source.

[0035] In some of the embodiments, the inverted trapezoidal structure of the gate cut-off structure means that a cross section of the gate cut-off structure obtained by analyzing along the gate extension direction is an inverted trapezoidal structure;

[0036] The two inner angles on the lower base of the inverted trapezoidal structure satisfy 95° to 125°;

[0037] The ratio of the additional depth to the height of the gate cut-off structure is less than a preset ratio;

[0038] The additional depth refers to the depth of the gate cut-off structure below the shallow trench isolation dielectric film.

[0039] In some of the embodiments, the stacked film includes a film formed by sequentially growing silicon nitride and silicon dioxide layers;

[0040] The stacked film includes at least one of a NO structure film, a NON structure film and a NONO structure film;

[0041] The NO structure film refers to a film formed by sequentially stacking silicon nitride and silicon dioxide; wherein the thickness of the silicon dioxide accounts for 5% to 30% of the total thickness of the NO structure film;

[0042] The NON structure film refers to a film formed by sequentially stacking silicon nitride, silicon dioxide and silicon nitride; wherein the thickness of the outermost silicon nitride layer accounts for 50% to 90% of the total thickness of the NON structure film; the thickness of the middle silicon dioxide layer accounts for 5% to 30% of the total thickness of the NON structure film; the thickness of the inner silicon nitride layer accounts for 5% to 20% of the total thickness of the NON structure film;

[0043] The NONO structure film refers to a film formed by sequentially stacking silicon nitride, silicon dioxide, silicon nitride and silicon dioxide; wherein the thickness of the outermost silicon nitride layer accounts for 50% to 80% of the total thickness of the NONO structure film; the thickness of the second outermost silicon dioxide layer accounts for 5% to 20% of the total thickness of the NONO structure film; the thickness of the second inner silicon nitride layer accounts for 5% to 20% of the total thickness of the NONO structure film; and the thickness of the inner silicon dioxide layer accounts for 5% to 20% of the total thickness of the NONO structure film.

[0044] In some of the embodiments, the steps of the method for reducing fin misalignment in a transistor described in the first aspect are used for manufacturing.

[0045] The above-mentioned method for reducing the misalignment of the fin in the transistor and the transistor structure can reduce the stress distribution of the upper part of the fin (Fin) located in the gate (poly) and the lower part located in the shallow trench isolation dielectric film (STI FCVD) in the MOS tube by optimizing the design of the shallow trench isolation dielectric film (STI FCVD) and the gate cut-off structure (Poly Cut), so as to reduce the warping misalignment between the upper and lower parts caused by stress. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0047] Figure 1 FIG. 1 is a schematic diagram of a single fin layout according to an embodiment.

[0048] Figure 2 for Figure 1 Schematic diagram of the cross-section of the existing fin obtained by analyzing along the dotted line.

[0049] Figure 3 for Figure 1 Schematic diagram of the cross-section of the improved fin obtained by analyzing along the dotted line.

[0050] Figure 4 FIG. 4 is a schematic diagram of a layout of multiple fins according to another embodiment. DETAILED DESCRIPTION

[0051] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0053] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the general meaning understood by people with general skills in the technical field to which this application belongs. The words "one", "a", "the", "these" and the like in this application do not indicate a quantitative limitation, and they may be singular or plural. The terms "include", "comprise", "have" and any variants thereof involved in this application are intended to cover non-exclusive inclusions; for example, a process, method and system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, "A and / or B" may mean: A exists alone, A and B exist at the same time, and B exists alone. Generally, the character " / " indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", "third", etc. in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0054] Embodiment 1

[0055] The asymmetric stress of shallow trench isolation dielectric film (STI FCVD) and gate cut structure (poly cut) will cause the fin (Fin) to warp, especially in the single fin structure. Please refer to the following Figure 1 , Figure 2 The upper part of the Fin structure is located in the poly and the lower part is located in the STI FCVD. The stress distribution between the two causes the warping misalignment between the upper and lower parts of the fin.

[0056] In order to reduce or even isolate possible fin misalignment defects, a method for reducing fin misalignment in a transistor is provided. For details, please refer to Figure 1 and Figure 3, including: providing a substrate (Si-substrate); depositing a shallow trench isolation dielectric film (STI FCVD) on the substrate; forming a fin on the substrate, and the fin protrudes from the upper surface of the shallow trench isolation dielectric film; depositing a gate on the substrate, and the gate spans the fin; forming a gate cut-off structure (polycut) in the gate, used to cut the gate into independent gate segments; the gate cut-off structure is an inverted trapezoidal structure, and the gate cut-off structure is filled with a stacked film formed by stacked deposition of a nitrogen source and a silicon source. The method for reducing the misalignment of the fin in the transistor improves the gate cut-off structure into an inverted trapezoidal shape, improves the stress distribution of the gate cut-off structure on the upper part of the fin, reduces the shear stress, and at the same time, optimizes the filling of the gate cut-off structure, and the use of the stacked growth of the nitrogen source and the silicon source can effectively adjust the stress composition; by understanding the source of the shear stress from the root, and reducing the total stress of the two parts that cause the shear stress, the shear stress is reduced, thereby reducing or even isolating possible fin misalignment defects. Based on industrial application examples, the above method can effectively reduce the bending and dislocation of single Fin structure caused by shear stress of STI FCVD and poly cut. The above method can also improve the multi-Fin structure. The single Fin structure and multi-Fin structure can refer to Figure 1 , Figure 4 .

[0057] In this embodiment, the inverted trapezoidal structure of the gate cut-off structure refers to the gate cut-off structure obtained by analyzing along the extension direction of the gate, and the cross-section is an inverted trapezoidal structure; the two inner angles located on the lower base in the inverted trapezoidal structure meet 95° to 125°; the ratio of the additional depth to the height of the gate cut-off structure is less than a preset ratio, wherein the additional depth refers to the depth of the gate cut-off structure below the shallow trench isolation dielectric film. For example, in some specific application scenarios, the additional depth is generally required to be less than 10% of the height. The shear stress is reduced by further structural optimization of these gate cut-off structures. However, in other embodiments, only one of the structural optimizations may be adopted, or only multiple of the structural optimizations may be adopted, or even none of these structural optimizations may be performed. This can be determined based on the specific application scenario requirements, and this application does not make specific limitations.

[0058] In this embodiment, the stacked film includes a film formed by sequentially growing silicon nitride and silicon dioxide layers, which satisfies the isolation effect of the gate cut-off structure and changes the filling composition in the existing structure. The use of stacked growth of silicon nitride and silicon dioxide can effectively adjust the stress composition.

[0059] Specifically, the laminated film includes but is not limited to: at least one of NO structure film, NON structure film and NONO structure film; through the isolation effect verification, the isolation effect of the filling methods such as NO structure film, NON structure film and NONO structure film can meet the requirements. Among them:

[0060] The NO structure film refers to a film formed by sequentially stacking silicon nitride and silicon dioxide; the thickness of the silicon dioxide accounts for 5% to 30% of the total thickness of the NO structure film.

[0061] The NON structure film refers to a film formed by sequentially stacking silicon nitride, silicon dioxide and silicon nitride; the thickness of the outermost silicon nitride layer accounts for 50% to 90% of the total thickness of the NON structure film, the thickness of the middle layer silicon dioxide accounts for 5% to 30% of the total thickness of the NON structure film, and the thickness of the inner layer silicon nitride accounts for 5% to 20% of the total thickness of the NON structure film.

[0062] The NONO structure film refers to a film formed by sequentially stacking growth of silicon nitride, silicon dioxide, silicon nitride and silicon dioxide; the thickness of the outermost silicon nitride layer accounts for 50% to 80% of the total thickness of the NONO structure film, the thickness of the next outermost silicon dioxide layer accounts for 5% to 20% of the total thickness of the NONO structure film, the thickness of the next inner silicon nitride layer accounts for 5% to 20% of the total thickness of the NONO structure film, and the thickness of the inner silicon dioxide layer accounts for 5% to 20% of the total thickness of the NONO structure film.

[0063] It should be noted that, in the stacked film, the outer layer refers to the layer deposited first, and the inner layer refers to the layer deposited later; that is, the outermost layer of silicon nitride refers to the portion of the stacked film that contacts the shallow trench isolation dielectric film.

[0064] In this embodiment, the gate cut-off structure is filled with a stacked film formed by stacked deposition of nitrogen source and silicon source, including: the gas source ratio of silicon source and nitrogen source will affect the composition and properties of silicon nitride SiNx film, lowering the ratio of nitrogen source can effectively reduce stress, and the molar ratio of nitrogen source and silicon source is 0.8:1-2:1 during stacked deposition; the silicon source can be but not limited to at least one of SiH4, SiHCl4, SiH2Cl2; the nitrogen source can be but not limited to at least one of NH3 and N2. The deposition method of the stacked film is but not limited to chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD). The deposition temperature directly affects the stress of silicon nitride, and a lower deposition temperature, that is, a deposition temperature of 550°-700°, helps to reduce the stress of the film. The atmosphere gas during stacked deposition can affect and regulate the reaction environment, affect the film composition and the formation of nitrogen clusters, and increase the proportion of the atmosphere gas in the reaction chamber, even if the molar ratio of the atmosphere gas to the sum of the nitrogen source and the silicon source meets 10% to 50%, which can help reduce stress. Among them, the atmosphere gas can be selected from but not limited to at least one of N2 and NO2. Adding a heat treatment step after deposition can promote the release of stress in the film, thereby reducing the stress level. The thermal annealing treatment can be adopted and is not limited to at least one of soak annealing, spike annealing, and laser annealing. The temperature of the thermal annealing treatment meets 400° to 800°.

[0065] It should be noted that in other embodiments, only one of the above-mentioned process optimization conditions for stacked deposition may be adopted, or only multiple of the process optimization conditions for stacked deposition may be adopted, or none of these process optimization conditions for stacked deposition may be adopted. It can be determined based on the needs of specific application scenarios, and even other process optimization conditions for stacked deposition may be adopted. For example, the deposition rate in the actual deposition process will also affect the density and microstructure of the film, and thus affect the stress. Maintaining a slightly faster deposition rate can help reduce stress. This application does not make specific limitations.

[0066] In this embodiment, a shallow trench isolation dielectric film is deposited on the substrate, including: the shallow trench isolation dielectric film is cured by ultraviolet irradiation (UV curve) instead of ozone irradiation (O3curve), which can directly destroy the Si-H and Si-N bonds in the precursor. After deposition, the shallow trench isolation dielectric film is thermally annealed, and the power of the thermal annealing is appropriately lowered to meet 600W~2000W, which can effectively reduce volume shrinkage, thereby reducing oxide stress after annealing, and can effectively reduce stress warping and dislocation caused by asymmetric stress from STI FCVD and poly cut, improve the stability of the Fin structure, and have higher practical application significance in more advanced nodes. However, in other embodiments, only one of the above-mentioned shallow trench isolation dielectric film process optimization conditions can be used, or only multiple of the shallow trench isolation dielectric film process optimization conditions can be used, or these shallow trench isolation dielectric film process optimization conditions can not be used, which can be determined based on the specific application scenario requirements, and this application does not make specific limitations.

[0067] Embodiment 2

[0068] Based on the steps of the method for reducing the misalignment of the fin in the transistor in the first embodiment, a transistor structure for reducing the misalignment of the fin is manufactured, wherein a shallow trench isolation dielectric film, a fin and a gate are formed on the substrate; the fin protrudes from the upper surface of the shallow trench isolation dielectric film, the gate crosses the fin, and a gate cut-off structure is formed in the gate for cutting the gate into independent gate segments; the gate cut-off structure is an inverted trapezoidal structure, and the gate cut-off structure is filled with a stacked film formed by stacked deposition of a nitrogen source and a silicon source. This transistor structure for reducing the misalignment of the fin optimizes the Fin shear stress by defining the structure and material of the gate cut-off structure, and can effectively reduce the bending and misalignment of the fin in the transistor caused by the shear stress of STI FCVD and poly cut.

[0069] In this embodiment, the inverted trapezoidal structure of the gate cut-off structure means that the cross section of the gate cut-off structure obtained by analyzing along the gate extension direction is an inverted trapezoidal structure, and the two inner angles located on the lower base of the inverted trapezoidal structure meet 95° to 125°; the ratio of the additional depth to the height of the gate cut-off structure is less than a preset ratio, and the additional depth refers to the depth of the gate cut-off structure below the shallow trench isolation dielectric film. Through further structural optimization of these gate cut-off structures, the shear stress is reduced.

[0070] In this embodiment, the laminated film includes a film formed by sequentially growing silicon nitride and silicon dioxide layers, specifically including at least one of a NO structure film, a NON structure film, and a NONO structure film. Under the condition of satisfying the isolation effect of the gate cut-off structure, the filling composition in the existing structure is changed, and the laminated growth of silicon nitride and silicon dioxide can effectively adjust the stress composition. Among them:

[0071] NO structure film refers to a film formed by the sequential growth of silicon nitride and silicon dioxide. The thickness of silicon dioxide accounts for 5% to 30% of the total thickness of the NO structure film.

[0072] NON structure film refers to a film formed by the sequential growth of silicon nitride, silicon dioxide and silicon nitride. The thickness of the outermost layer of silicon nitride accounts for 50% to 90% of the total thickness of the NON structure film; the thickness of the middle layer of silicon dioxide accounts for 5% to 30% of the total thickness of the NON structure film; the thickness of the inner layer of silicon nitride accounts for 5% to 20% of the total thickness of the NON structure film.

[0073] NONO structure film refers to a film formed by the sequential growth of silicon nitride, silicon dioxide, silicon nitride and silicon dioxide. The thickness of the outermost silicon nitride layer accounts for 50% to 80% of the total thickness of the NONO structure film; the thickness of the second outer silicon dioxide layer accounts for 5% to 20% of the total thickness of the NONO structure film; the thickness of the second inner silicon nitride layer accounts for 5% to 20% of the total thickness of the NONO structure film; the thickness of the inner silicon dioxide layer accounts for 5% to 20% of the total thickness of the NONO structure film.

[0074] It should be understood that the specific embodiments described herein are only used to explain the application, rather than to limit it. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of this application.

[0075] Obviously, the drawings are only some examples or embodiments of the present application. For ordinary technicians in the field, the present application can also be applied to other similar situations based on these drawings without creative work. In addition, it is understandable that although the work done in this development process may be complicated and lengthy, for ordinary technicians in the field, certain changes in design, manufacturing or production based on the technical content disclosed in this application are only conventional technical means and should not be regarded as insufficient content disclosed in this application.

[0076] The term "embodiment" in this application refers to a specific feature, structure or characteristic described in conjunction with the embodiment that can be included in at least one embodiment of the present application. The appearance of this phrase in various locations in the specification does not necessarily mean the same embodiment, nor does it mean that it is mutually exclusive with other embodiments and is independent or optional. It is clearly or implicitly understood by those of ordinary skill in the art that the embodiments described in this application can be combined with other embodiments without conflict.

[0077] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for reducing fin misalignment in a transistor, characterized in that: include: providing a substrate; A shallow trench isolation dielectric film is deposited on the substrate; A fin is formed on the substrate, and the fin protrudes from the upper surface of the shallow trench isolation dielectric film; A gate is also deposited on the substrate, and the gate spans across the fin; A gate cut-off structure is formed in the gate for cutting the gate into independent gate segments; the gate cut-off structure is an inverted trapezoidal structure, and the gate cut-off structure is filled with a stacked film formed by stacked deposition of a nitrogen source and a silicon source; Wherein, the laminated film comprises a film formed by sequentially growing silicon nitride and silicon dioxide layers; The stacked film includes at least one of a NO structure film, a NON structure film and a NONO structure film; The NO structure film refers to a film formed by sequentially stacking silicon nitride and silicon dioxide; wherein the thickness of the silicon dioxide accounts for 5% to 30% of the total thickness of the NO structure film; The NON structure film refers to a film formed by sequentially stacking silicon nitride, silicon dioxide and silicon nitride; wherein the thickness of the outermost silicon nitride layer accounts for 50% to 90% of the total thickness of the NON structure film; the thickness of the middle silicon dioxide layer accounts for 5% to 30% of the total thickness of the NON structure film; the thickness of the inner silicon nitride layer accounts for 5% to 20% of the total thickness of the NON structure film; The NONO structure film refers to a film formed by sequentially stacking silicon nitride, silicon dioxide, silicon nitride and silicon dioxide; wherein the thickness of the outermost silicon nitride layer accounts for 50% to 80% of the total thickness of the NONO structure film; the thickness of the second outermost silicon dioxide layer accounts for 5% to 20% of the total thickness of the NONO structure film; the thickness of the second inner silicon nitride layer accounts for 5% to 20% of the total thickness of the NONO structure film; and the thickness of the inner silicon dioxide layer accounts for 5% to 20% of the total thickness of the NONO structure film.

2. The method for reducing fin misalignment in a transistor according to claim 1, characterized in that: The inverted trapezoidal structure of the gate cut-off structure means that the cross section of the gate cut-off structure obtained by analyzing along the gate extension direction is an inverted trapezoidal structure; The two inner angles on the lower base of the inverted trapezoidal structure satisfy 95° to 125°; The ratio of the additional depth to the height of the gate cut-off structure is less than a preset ratio; The additional depth refers to the depth of the gate cut-off structure below the shallow trench isolation dielectric film.

3. The method for reducing fin misalignment in a transistor according to claim 1, characterized in that: The gate cut-off structure is filled with a stacked film formed by stacked deposition of a nitrogen source and a silicon source, including: During the stacking deposition, the molar ratio of the nitrogen source to the silicon source satisfies 0.8:1 to 2:1; wherein the silicon source is at least one of SiH4, SiHCl4, and SiH2Cl2; and the nitrogen source is at least one of NH3 and N2; The deposition method of the laminated film is chemical vapor deposition or plasma enhanced chemical vapor deposition; the deposition temperature satisfies 550° to 700°; The molar ratio of the atmosphere gas to the sum of the nitrogen source and the silicon source during the stacking deposition satisfies 10% to 50%, and the atmosphere gas is at least one of N2 and NO2.

4. The method for reducing fin misalignment in a transistor according to claim 1, characterized in that: The gate cut-off structure is filled with a stacked film formed by stacked deposition of a nitrogen source and a silicon source, including: After the stack is deposited, the stacked film is also subjected to thermal annealing; The thermal annealing treatment adopts at least one of soak annealing, spike annealing and laser annealing; the temperature of the thermal annealing treatment satisfies 400° to 800°.

5. The method for reducing fin misalignment in a transistor according to claim 1, characterized in that: A shallow trench isolation dielectric film is deposited on the substrate, comprising: The shallow trench isolation dielectric film is cured by ultraviolet irradiation; After deposition, the shallow trench isolation dielectric film is subjected to thermal annealing treatment, and the power of the thermal annealing treatment meets 600W to 2000W.

6. A transistor structure for reducing fin misalignment, characterized in that: A shallow trench isolation dielectric film, a fin and a gate are formed on the substrate; The fin protrudes from the upper surface of the shallow trench isolation dielectric film; The gate crosses the fin; A gate cut-off structure is formed in the gate for cutting the gate into independent gate segments; the gate cut-off structure is an inverted trapezoidal structure; and the gate cut-off structure is filled with a stacked film formed by stacked deposition of a nitrogen source and a silicon source; Wherein, the laminated film comprises a film formed by sequentially growing silicon nitride and silicon dioxide layers; The stacked film includes at least one of a NO structure film, a NON structure film and a NONO structure film; The NO structure film refers to a film formed by sequentially stacking silicon nitride and silicon dioxide; wherein the thickness of the silicon dioxide accounts for 5% to 30% of the total thickness of the NO structure film; The NON structure film refers to a film formed by sequentially stacking silicon nitride, silicon dioxide and silicon nitride; wherein the thickness of the outermost silicon nitride layer accounts for 50% to 90% of the total thickness of the NON structure film; the thickness of the middle silicon dioxide layer accounts for 5% to 30% of the total thickness of the NON structure film; the thickness of the inner silicon nitride layer accounts for 5% to 20% of the total thickness of the NON structure film; The NONO structure film refers to a film formed by sequentially stacking silicon nitride, silicon dioxide, silicon nitride and silicon dioxide; wherein the thickness of the outermost silicon nitride layer accounts for 50% to 80% of the total thickness of the NONO structure film; the thickness of the second outermost silicon dioxide layer accounts for 5% to 20% of the total thickness of the NONO structure film; the thickness of the second inner silicon nitride layer accounts for 5% to 20% of the total thickness of the NONO structure film; and the thickness of the inner silicon dioxide layer accounts for 5% to 20% of the total thickness of the NONO structure film.

7. The transistor structure for reducing fin misalignment according to claim 6, characterized in that: The inverted trapezoidal structure of the gate cut-off structure means that the cross section of the gate cut-off structure obtained by analyzing along the gate extension direction is an inverted trapezoidal structure; The two inner angles on the lower base of the inverted trapezoidal structure satisfy 95° to 125°; The ratio of the additional depth to the height of the gate cut-off structure is less than a preset ratio; The additional depth refers to the depth of the gate cut-off structure below the shallow trench isolation dielectric film.

8. The transistor structure for reducing fin misalignment according to claim 6, characterized in that: The method for reducing fin misalignment in a transistor is manufactured using the steps of any one of claims 1 to 5.

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