A chip, a chip manufacturing method, a computing device, and a signal transmission method

Abstract

Embodiments of the present application disclose a chip, a chip manufacturing method, a computing device and a signal transmission method. The chip has a base pattern unit with six signal pins on a packaging substrate of the chip, first, second, third and fourth pins of the base pattern unit are arranged in a first direction in sequence with a spacing, and fifth and sixth pins of the base pattern unit are arranged in a second direction with a spacing; the fifth and sixth pins are respectively located on two sides of a line connecting the second and third pins; the first, fourth, fifth and sixth pins are data signal pins, and the second and third pins are control signal pins. According to the scheme, the data signal pins are arranged at four outer extending ends of the cross-shaped pattern unit, the data signal pins are far away from each other, each data signal pin has no adjacent data signal pin that can form a crosstalk source, and the electromagnetic crosstalk between the pins can be effectively reduced; meanwhile, the density of pin arrangement can be improved, and the packaging area can be reduced.

Description

Technical Field

[0001] This application relates to the field of electronic device packaging, and more particularly to a chip, a chip manufacturing method, a computing device, and a signal transmission method. Background Technology

[0002] With the continuous development of storage technology, double data rate synchronous dynamic random access memory (DDR SDRAM) systems have been widely used in computing products, such as, but not limited to, server products. However, with the evolution of DDR generations, the performance improvement of DDR systems has placed higher demands on chip packaging technology.

[0003] In DDR systems, the number of channels and I / O (input / output) pins is increasing, leading to larger chip package sizes. Larger package sizes typically mean greater volume and weight. Soldering the chip to the PCB (Printed Circuit Board) generates more heat. Since the chip package and PCB often have different coefficients of thermal expansion, this results in a larger soldering temperature gradient, causing thermal stress and fatigue, and increasing the risk of solder joint defects. Furthermore, the deformation of large packages is difficult to control, increasing the risk of soldering defects and poor connections, directly impacting product cost and yield.

[0004] On the other hand, the DDR interface speed is getting faster and faster, which has a greater impact on crosstalk between adjacent signals. In order to reduce electromagnetic crosstalk between pins, a typical approach is to place grounded solder balls around the pins of the chip package substrate. This can reduce the impact of electromagnetic crosstalk, but the placement of grounded solder balls will increase the chip size.

[0005] Therefore, the pin arrangement of chip packaging substrates needs to take into account two trending design requirements: high-density arrangement and low crosstalk, in order to meet the performance requirements of the product. Summary of the Invention

[0006] This application provides a chip, a chip manufacturing method, a computing device, and a signal transmission method, which can improve the layout density and effectively reduce electromagnetic crosstalk.

[0007] A first aspect of this application provides a chip, the chip's die being disposed on its packaging substrate, the packaging substrate serving as a carrier for die packaging. A plurality of pin arrangement pattern units are provided in the pin area of ​​the packaging substrate, at least two of these pin arrangement pattern units being basic pattern units including six signal pins. Specifically, the first, second, third, and fourth pins of the six signal pins of the basic pattern unit are arranged sequentially and spaced apart in a first direction, and the fifth and sixth pins are arranged spaced apart in a second direction, the first direction being different from the second direction, and the fifth and sixth pins are respectively located on opposite sides of the line connecting the second and third pins. Furthermore, the first, fourth, fifth, and sixth pins are data signal pins, and the second and third pins are control signal pins.

[0008] This configuration arranges the pins of the basic graphics unit in a cross shape, with the four data signal pins positioned at the four extended ends of the cross-shaped graphics unit and the control signal pins located in the center. This spacing ensures that the data signal pins are far apart, eliminating any adjacent data signal pins that could become sources of crosstalk, effectively avoiding electromagnetic crosstalk between adjacent data signal pins. Based on this pinmap solution, on the one hand, it effectively reduces electromagnetic crosstalk between pins, supporting higher DDR operating speeds; on the other hand, it increases pin density, saving package area and providing technical support for further improving product yield and reducing processing costs.

[0009] For example, each pin in the pin area of ​​the packaging substrate can be a solder ball structure, which is electrically connected to the corresponding pad on the circuit board by soldering. Each pin in the pin area of ​​the packaging substrate can also be a metal contact structure, with corresponding metal springs provided on the circuit board. The metal contacts and metal springs can be configured one-to-one. The assembled metal contacts press against the metal springs, and the deformed metal springs maintain a reliable electrical connection with the matching metal contacts.

[0010] In practical applications, the pin arrangement pattern units in the pin area of ​​the packaging substrate can be configured into different pin arrangement methods according to actual functional needs. For example, some of the pin arrangement pattern units are configured as the basic pattern unit of the cross shape to build the channel of the DDR memory system; other pin arrangement pattern units are configured as pattern units including other patterns to realize electrical connection with the corresponding external circuits. In other words, the pin arrangement in the pin area of ​​the packaging substrate can be obtained by combining and arranging several pattern units.

[0011] Based on the first aspect, this application also provides a first implementation of the first aspect: wherein the fifth pin and the sixth pin are arranged on the perpendicular line of the line connecting the second pin and the third pin, where the first direction is perpendicular to the second direction. Further, the fifth pin and the sixth pin can be arranged on the perpendicular line of the line connecting the second pin and the third pin, which has good structural symmetry and can achieve a more compact overall layout in the pin area.

[0012] In practical applications, the connection between the fifth and sixth pins can also be set to intersect the connection between the second and third pins at other angles, which can also keep the data signal pins away from each other and reduce electromagnetic crosstalk.

[0013] Based on the first aspect, or the first implementation of the first aspect, this application also provides a second implementation of the first aspect: the basic graphic unit adopts a centrally symmetrical structure or an axisymmetric structure. This allows for full utilization of the pin area to achieve high-density arrangement, and while effectively reducing electromagnetic crosstalk between pins, it also enables more reasonable control of the package size.

[0014] Based on the first aspect, or the first implementation of the first aspect, or the second implementation of the first aspect, this application also provides a third implementation of the first aspect: the pins of the packaging substrate pin area are arranged in an array, wherein the pins between rows and columns are staggered, that is, each row of pins and each column of pins are staggered with each other, so that as many pins as possible can be arranged in a limited arrangement space, and the cross-shaped arrangement pattern units can be tightly alternated, and the pin arrangement density can be further improved.

[0015] Based on the first aspect, or the first embodiment of the first aspect, or the second embodiment of the first aspect, this application also provides a fourth embodiment of the first aspect: the pins of the packaging substrate pin area are arranged in a triangular grid pattern, and the lines connecting the pins and their adjacent two pins form an equilateral triangle. This further enables a tight, alternating arrangement of the cross-shaped pattern units, increasing the pin density.

[0016] Based on the first aspect, or the first implementation of the first aspect, or the second implementation of the first aspect, or the third implementation of the first aspect, or the fourth implementation of the first aspect, this application also provides a fifth implementation of the first aspect: the basic graphic unit further includes a ground pin, which is arranged around the six signal pins. Thus, based on the arrangement of the ground pin, a low-impedance grounding path can be provided, forming a uniform ground potential, thereby guiding the energy of the electromagnetic field to the ground plane, reducing electromagnetic crosstalk between signal pins, helping to maintain signal integrity, and reducing noise.

[0017] For example, the grounding pin can be a solder ball structure or a metal contact point structure.

[0018] Based on the fifth implementation of the first aspect, this application also provides a sixth implementation of the first aspect: the basic graphic unit has fourteen grounding pins, arranged around the six signal pins, with the fourteen grounding pins arranged alternately; overall, the fourteen grounding pins are arranged alternately to form a fourteen-sided polygon; the data signal pins adjacent to two adjacent grounding pins, and the lines connecting these two adjacent grounding pins, form an equilateral triangle. This arrangement fully utilizes the space of the pin area where pins are staggered between rows and columns, constructing a pinmap unit according to the alternating arrangement rule, ensuring that the distance between any two adjacent pins is consistent. While providing the return ground function, it can improve the pin arrangement density and achieve a high signal-to-ground ratio.

[0019] Based on the fifth or sixth implementation of the first aspect, this application also provides a seventh implementation of the first aspect: two basic graphic units are arranged adjacent to each other, one of which is a first basic graphic unit and the other is a second basic graphic unit. The adjacent sides of the first and second basic graphic units share a grounding pin; in other words, the grounding pins of the adjacent sides of the two basic graphic units are shared. This effectively reduces electromagnetic crosstalk and results in a more compact and reasonable pin layout density.

[0020] In practical applications, based on the staggered arrangement of pins in the pin area of ​​the packaging substrate, different forms of pin arrangement combination units can be formed by translation or rotation and splicing. For example, a cross-shaped pin arrangement graphic unit can transmit one half-byte of data, and a pin arrangement combination unit formed by splicing two pin arrangement graphic units can transmit one byte of data.

[0021] For example, one of the two pin arrangement graphic units of the pin arrangement assembly unit can be a graphic unit formed by translating relative to the other; or, the other can be a graphic unit formed by rotating and translating relative to the other.

[0022] Based on the seventh implementation of the first aspect, this application also provides an eighth implementation of the first aspect: the first basic graphic unit and the second basic graphic unit are translational graphics to each other, the translation can be a translation in a first direction, the first basic graphic unit and the second basic graphic have a common ground pin, the first pin, the second pin, the third pin and the fourth pin of the first basic graphic unit are arranged in the same direction as the first pin, the second pin, the third pin and the fourth pin of the second basic graphic unit; the common ground pin is located between the fourth pin of the first basic graphic unit and the first pin of the second basic graphic unit.

[0023] Based on the seventh implementation of the first aspect, this application also provides a ninth implementation of the first aspect: the first basic graphic unit and the second basic graphic unit are translational graphics to each other, the translation can be a translation in a second direction, the fifth and sixth pins of the first basic graphic unit are arranged in the same direction as the fifth and sixth pins of the second basic graphic unit; the first basic graphic unit and the second basic graphic unit have two spaced-apart common grounding pins, the two common grounding pins are located between the sixth pin of the first basic graphic unit and the fifth pin of the second basic graphic unit.

[0024] Based on the seventh implementation of the first aspect, this application also provides a tenth implementation of the first aspect: the first basic graphic unit and the second basic graphic unit are translational graphics to each other, and the translation can be a translation in a direction that forms an angle with the first direction and the second direction respectively; the first pin, the second pin, the third pin and the fourth pin of the first basic graphic unit are arranged in the same direction as the sixth pin of the second basic graphic unit; the first basic graphic unit and the second basic graphic unit have two spaced common grounding pins, and the two common grounding pins are located between the fourth pin of the first basic graphic unit and the first pin of the second basic graphic unit.

[0025] Based on the seventh embodiment of the first aspect, this application also provides an eleventh embodiment of the first aspect: the first basic graphic unit and the second basic graphic unit are translational graphics to each other, the translation can be a translation in a direction that forms an angle with the first direction and the second direction respectively; the fifth and sixth pins of the first basic graphic unit are arranged in the same direction as the first pin of the second basic graphic unit; the fourth pin of the first basic graphic unit is arranged in the same direction as the fifth and sixth pins of the second basic graphic unit; the first basic graphic unit and the second basic graphic unit have four common grounding pins; the four common grounding pins are arranged sequentially at intervals, wherein two common grounding pins are located between the sixth pin of the first basic graphic unit and the first pin of the second basic graphic unit, and the other two common grounding pins are located between the fourth pin of the first basic graphic unit and the fifth pin of the second basic graphic unit.

[0026] Based on the seventh embodiment of the first aspect, this application also provides a twelfth embodiment of the first aspect: the first basic graphic unit and the second basic graphic unit are translational graphics to each other, and the translation can be a translation in a direction that forms an angle with the first direction and the second direction respectively; the fourth pin of the first basic graphic unit is arranged in the same direction as the first pin of the second basic graphic unit; the sixth pin of the first basic graphic unit is arranged in the same direction as the fifth pin of the second basic graphic unit; the first basic graphic unit and the second basic graphic unit have four common grounding pins; the four common grounding pins are arranged sequentially at intervals, wherein two common grounding pins are located between the fourth pin of the first basic graphic unit and the fifth pin of the second basic graphic unit, and the other two common grounding pins are located between the sixth pin of the first basic graphic unit and the first pin of the second basic graphic unit.

[0027] Based on the seventh embodiment of the first aspect, this application also provides a thirteenth embodiment of the first aspect: the first basic graphic unit and the second basic graphic unit are translational and rotated graphics of each other; the first pin and the fifth pin of the first basic graphic unit are arranged in the same direction as the fifth pin and the sixth pin of the second basic graphic unit; the sixth pin and the fourth pin of the first basic graphic unit are arranged in the same direction as the first pin of the second basic graphic unit; the first basic graphic unit and the second basic graphic unit have four common grounding pins; the four common grounding pins are arranged sequentially at intervals, wherein two common grounding pins are adjacent to the fifth pin of the first basic graphic unit, and the other two common grounding pins are adjacent to the fourth pin of the first basic graphic unit.

[0028] Based on the fifth embodiment of the first aspect, this application also provides a fourteenth embodiment of the first aspect: the basic graphic unit has fourteen ground pins, which are arranged sequentially and at intervals around the six signal pins; and in the first direction, the first ground pin is located beside the first pin, the eighth ground pin is located beside the fourth pin, and the second, third, fourth, fifth, sixth, and seventh ground pins are arranged sequentially between the first and eighth ground pins; the ninth, tenth, eleventh, twelfth, thirteenth, and fourteenth ground pins are arranged sequentially between the eighth ground pin and the first ground pin. The overall layout is more compact and reasonable.

[0029] Based on the fourteenth implementation of the first aspect, this application also provides a fifteenth implementation of the first aspect: two basic graphic units are arranged adjacent to each other, one of the two basic graphic units is a first basic graphic unit, and the other of the two basic graphic units is a second basic graphic unit, and the adjacent sides of the first basic graphic unit and the second basic graphic unit share a grounding pin.

[0030] Based on the fifteenth implementation of the first aspect, this application also provides a sixteenth implementation of the first aspect: the first basic graphic unit and the second basic graphic unit are translational graphics to each other, wherein the eighth grounding pin of the first basic graphic unit and the first grounding pin of the second basic graphic unit are shared grounding pins.

[0031] Based on the fifteenth implementation of the first aspect, this application also provides a sixteenth implementation of the first aspect: the first basic graphic unit and the second basic graphic unit are translational graphics to each other, wherein the twelfth grounding pin of the first basic graphic unit and the fourth grounding pin of the second basic graphic unit are shared grounding pins; wherein the eleventh grounding pin of the first basic graphic unit and the fifth grounding pin of the second basic graphic unit are shared grounding pins.

[0032] Based on the fifteenth embodiment of the first aspect, this application also provides a sixteenth embodiment of the first aspect: the first basic graphic unit and the second basic graphic unit are translational graphics to each other, wherein the seventh grounding pin of the first basic graphic unit and the first grounding pin of the second basic graphic unit are shared grounding pins; wherein the eighth grounding pin of the first basic graphic unit and the fourteenth grounding pin of the second basic graphic unit are shared grounding pins.

[0033] Based on the fifteenth embodiment of the first aspect, this application also provides a sixteenth embodiment of the first aspect: the first basic graphic unit and the second basic graphic unit are translational graphics, wherein the twelfth grounding pin of the first basic graphic unit and the second grounding pin of the second basic graphic unit are shared grounding pins; wherein the eleventh grounding pin of the first basic graphic unit and the third grounding pin of the second basic graphic unit are shared grounding pins; wherein the tenth grounding pin of the first basic graphic unit and the fourth grounding pin of the second basic graphic unit are shared grounding pins; wherein the ninth grounding pin of the first basic graphic unit and the fifth grounding pin of the second basic graphic unit are shared grounding pins.

[0034] Based on the fifteenth embodiment of the first aspect, this application also provides a sixteenth embodiment of the first aspect: the first basic graphic unit and the second basic graphic unit are translational graphics to each other, wherein the eleventh grounding pin of the first basic graphic unit shares a grounding pin with the first grounding pin of the second basic graphic unit; wherein the tenth grounding pin of the first basic graphic unit shares a grounding pin with the second grounding pin of the second basic graphic unit; wherein the ninth grounding pin of the first basic graphic unit shares a grounding pin with the third grounding pin of the second basic graphic unit; wherein the eighth grounding pin of the first basic graphic unit shares a grounding pin with the fourth grounding pin of the second basic graphic unit.

[0035] Based on the fifteenth embodiment of the first aspect, this application also provides a sixteenth embodiment of the first aspect: the first basic graphic unit and the second basic graphic unit are translational and rotated graphics of each other; wherein, the fifth grounding pin of the first basic graphic unit and the fifth grounding pin of the second basic graphic unit are shared grounding pins; wherein, the sixth grounding pin of the first basic graphic unit and the fourth grounding pin of the second basic graphic unit are shared grounding pins; wherein, the seventh grounding pin of the first basic graphic unit and the third grounding pin of the second basic graphic unit are shared grounding pins; wherein, the eighth grounding pin of the first basic graphic unit and the second grounding pin of the second basic graphic unit are shared grounding pins.

[0036] Based on the first aspect, or the first embodiment of the first aspect, or the second embodiment of the first aspect, or the third embodiment of the first aspect, or the fourth embodiment of the first aspect, or the fifth embodiment of the first aspect, or the sixth embodiment of the first aspect, or the seventh embodiment of the first aspect, or the eighth embodiment of the first aspect, or the ninth embodiment of the first aspect, or the tenth embodiment of the first aspect, or the eleventh embodiment of the first aspect, or the twelfth embodiment of the first aspect, or the thirteenth embodiment of the first aspect, or the fourteenth embodiment of the first aspect, or the fifteenth embodiment of the first aspect, or the sixteenth embodiment of the first aspect, this application The embodiment also provides a seventeenth implementation of the first aspect: For a basic graphic unit including six signal pins, its first, fourth, fifth, and sixth pins are single-ended signal pins used to transmit DQ data signals; its second and third pins are differential signal pins used to transmit DQS signals. In this way, when the two control signal pins transmit DQS differential clock signals, the polarity of the differential signal pair is opposite during transmission, that is, the signal amplitudes transmitted on the two pins of the differential signal pair are opposite. As a result, the interference to the two single-ended signal pins adjacent to it in the second direction can be completely canceled, and the crosstalk to the two single-ended signal pins on the left and right in the first direction can be partially canceled, reducing the total crosstalk amount received by the single-ended signals.

[0037] In practical applications, such as in X8 scenarios, differential signal pins can be configured as channels for multiplexing DM signals to transmit DM signals, providing shielding and selective writing for each data bit. When control signal pins are used to transmit DM signals, the actual electromagnetic crosstalk generated is low and will not affect the data transmission of data signal pins.

[0038] Based on the first aspect, this application also provides an eighteenth implementation of the first aspect: the chip can be a central processing unit (CPU), wherein the CPU is configured with multiple memory channels, specifically, each memory channel includes multiple byte units, each byte unit corresponding to at least two of the basic graphics units (GPUs), and the data signal pins in the GPUs are used to transmit the data signals of the corresponding byte units. Thus, by effectively reducing electromagnetic crosstalk between pins, higher data transmission speeds and higher access efficiency can be achieved.

[0039] A second aspect of this application provides an electronic device, including a housing and a circuit board disposed within the housing, wherein a chip is disposed on the circuit board; the chip is the chip described above, and the signal pins of the chip are electrically connected to the circuit board.

[0040] In practical applications, this electronic device can be a computing device such as a server, supercomputer, or Ethernet switch, or a terminal device such as a mobile phone, learning machine, or laptop.

[0041] A third aspect of this application provides a chip manufacturing method. This method involves placing a die on a packaging substrate and assembling the die and the packaging substrate together to form the chip. Specifically, a plurality of pin arrangement pattern units are provided in the pin area of ​​the packaging substrate. At least two of these pin arrangement pattern units are basic pattern units comprising six signal pins. The first, second, third, and fourth pins of the six signal pins of the basic pattern unit are arranged sequentially and spaced apart in a first direction, and the fifth and sixth pins are arranged spaced apart in a second direction. The first direction is different from the second direction, and the fifth and sixth pins are located on opposite sides of the line connecting the second and third pins. The first, fourth, fifth, and sixth pins are data signal pins, and the second and third pins are control signal pins. The method includes the following steps: transmitting data signals through the first, fourth, fifth, and sixth pins, and transmitting control signals through the second and third pins. Based on the basic graphic unit arranged in a cross shape, the chip ensures correct signal transmission through excellent anti-crosstalk performance, thus providing technical support for high-performance and reliable system applications.

[0042] Based on the third aspect, the present application also provides a first implementation of the third aspect: wherein the fifth pin and the sixth pin are disposed on the perpendicular line of the line connecting the second pin and the third pin, and here, the first direction is perpendicular to the second direction.

[0043] Based on the first implementation of the third aspect, this application also provides a second implementation of the third aspect: the fifth pin and the sixth pin are arranged on the vertical line of the line connecting the second pin and the third pin, and the basic graphic unit adopts a centrally symmetrical structure, or an axisymmetric structure.

[0044] Based on the third aspect, or the first embodiment of the third aspect, or the second embodiment of the third aspect, this application also provides a third embodiment of the third aspect: the pins of the packaging substrate pin area are arranged in a triangular grid pattern, specifically, the lines connecting the pins and their adjacent two pins form an equilateral triangle. This further enables a close alternating arrangement of the cross-shaped pattern units, increasing the pin density.

[0045] Based on the third implementation of the third aspect, this application also provides a fourth implementation of the third aspect: two basic graphic units are arranged adjacent to each other, one of the two basic graphic units is a first basic graphic unit, and the other of the two basic graphic units is a second basic graphic unit, and the adjacent sides of the first basic graphic unit and the second basic graphic unit share a grounding pin, in other words, the grounding pins of the adjacent sides of the two basic graphic units are shared. In this way, in addition to effectively reducing electromagnetic crosstalk, the pin layout density is more compact and reasonable.

[0046] Based on the fourth implementation of the third aspect, this application also provides a fifth implementation of the third aspect: the first basic graphic unit and the second basic graphic unit are translational graphics to each other, the translation can be a translation in a first direction, the first basic graphic unit and the second basic graphic have a common grounding pin, the common grounding pin is located between the fourth pin of the first basic graphic unit and the first pin of the second basic graphic unit.

[0047] Based on the fourth implementation of the third aspect, this application also provides a sixth implementation of the third aspect: the first basic graphic unit and the second basic graphic unit are translational graphics to each other, and the translation can be a translation in a second direction. The first basic graphic unit and the second basic graphic have two spaced common grounding pins, which are located between the sixth pin of the first basic graphic unit and the fifth pin of the second basic graphic unit.

[0048] Based on the fourth implementation of the third aspect, this application also provides a seventh implementation of the third aspect: the first basic graphic unit and the second basic graphic unit are translational graphics to each other, and the translation can be a translation in a direction that forms an angle with the first direction and the second direction respectively. The first basic graphic unit and the second basic graphic have two spaced common grounding pins, and the two common grounding pins are located between the fourth pin of the first basic graphic unit and the first pin of the second basic graphic unit.

[0049] Based on the fourth implementation of the third aspect, this application also provides an eighth implementation of the third aspect: the first basic graphic unit and the second basic graphic unit are translational graphics to each other, and the translation can be a translation in a direction that forms an angle with the first direction and the second direction respectively. The first basic graphic unit and the second basic graphic have four common grounding pins; the four common grounding pins are arranged sequentially at intervals, wherein two common grounding pins are located between the sixth pin of the first basic graphic unit and the first pin of the second basic graphic unit, and the other two common grounding pins are located between the fourth pin of the first basic graphic unit and the fifth pin of the second basic graphic unit.

[0050] Based on the fourth implementation of the third aspect, this application also provides a ninth implementation of the third aspect: the first basic graphic unit and the second basic graphic unit are translational graphics to each other, and the translation can be a translation in a direction that forms an angle with the first direction and the second direction respectively. The first basic graphic unit and the second basic graphic have four common grounding pins; the four common grounding pins are arranged sequentially at intervals, wherein two common grounding pins are located between the fourth pin of the first basic graphic unit and the fifth pin of the second basic graphic unit, and the other two common grounding pins are located between the sixth pin of the first basic graphic unit and the first pin of the second basic graphic unit.

[0051] Based on the fourth implementation of the third aspect, this application also provides a tenth implementation of the third aspect: the first basic graphic unit and the second basic graphic unit are translational and rotated graphics of each other, and the first basic graphic unit and the second basic graphic have four common grounding pins; the four common grounding pins are arranged sequentially at intervals, wherein two common grounding pins are adjacent to the fifth pin of the first basic graphic unit, and the other two common grounding pins are adjacent to the fourth pin of the first basic graphic unit.

[0052] A fourth aspect of this application provides a signal transmission method applied to a chip. Specifically, the chip includes a packaging substrate, and a plurality of pin arrangement pattern units are disposed in the pin area of ​​the packaging substrate. At least two of the plurality of pin arrangement pattern units are basic pattern units including six signal pins. The first, second, third, and fourth pins of the six signal pins of the basic pattern unit are arranged sequentially and spaced apart in a first direction, and the fifth and sixth pins are arranged spaced apart in a second direction. The first direction is different from the second direction, and the fifth and sixth pins are located on opposite sides of the line connecting the second and third pins, respectively. The first, fourth, fifth, and sixth pins are data signal pins, and the second and third pins are control signal pins. The method includes the following steps: transmitting data signals through the first, fourth, fifth, and sixth pins, and transmitting control signals through the second and third pins. Based on the basic graphic unit arranged in a cross shape, the chip ensures correct signal transmission through excellent anti-crosstalk performance, thus providing technical support for high-performance and reliable system applications.

[0053] Based on the fourth aspect, the present application also provides a first implementation of the fourth aspect: wherein the fifth pin and the sixth pin are disposed on the perpendicular line of the line connecting the second pin and the third pin, and here, the first direction is perpendicular to the second direction.

[0054] Based on the first implementation of the fourth aspect, this application also provides a second implementation of the fourth aspect: the fifth pin and the sixth pin are arranged on the vertical line of the line connecting the second pin and the third pin, and the basic graphic unit adopts a centrally symmetrical structure, or an axisymmetric structure.

[0055] Based on the fourth aspect, or the first embodiment of the fourth aspect, or the second embodiment of the fourth aspect, this application also provides a third embodiment of the fourth aspect: the pins of the packaging substrate pin area are arranged in a triangular grid pattern, specifically, the lines connecting the pins and their adjacent two pins form an equilateral triangle. This further enables a tight, alternating arrangement of the cross-shaped pattern units, increasing the pin density.

[0056] Based on the third implementation of the fourth aspect, this application also provides a fourth implementation of the fourth aspect: two basic graphic units are arranged adjacent to each other, one of the two basic graphic units is a first basic graphic unit, and the other of the two basic graphic units is a second basic graphic unit, and the adjacent sides of the first basic graphic unit and the second basic graphic unit share a grounding pin, in other words, the grounding pins of the adjacent sides of the two basic graphic units are shared. In this way, in addition to effectively reducing electromagnetic crosstalk, the pin layout density is more compact and reasonable.

[0057] Based on the fourth implementation of the fourth aspect, this application also provides a fifth implementation of the fourth aspect: the first basic graphic unit and the second basic graphic unit are translational graphics to each other, the translation can be a translation in a first direction, the first basic graphic unit and the second basic graphic have a common grounding pin, the common grounding pin is located between the fourth pin of the first basic graphic unit and the first pin of the second basic graphic unit.

[0058] Based on the fourth implementation of the fourth aspect, this application also provides a sixth implementation of the fourth aspect: the first basic graphic unit and the second basic graphic unit are translational graphics to each other, and the translation can be a translation in a second direction. The first basic graphic unit and the second basic graphic have two spaced common grounding pins, which are located between the sixth pin of the first basic graphic unit and the fifth pin of the second basic graphic unit.

[0059] Based on the fourth implementation of the fourth aspect, this application also provides a seventh implementation of the fourth aspect: the first basic graphic unit and the second basic graphic unit are translational graphics to each other, and the translation can be a translation in a direction that forms an angle with the first direction and the second direction respectively. The first basic graphic unit and the second basic graphic have two spaced common grounding pins, and the two common grounding pins are located between the fourth pin of the first basic graphic unit and the first pin of the second basic graphic unit.

[0060] Based on the fourth implementation of the fourth aspect, this application also provides an eighth implementation of the fourth aspect: the first basic graphic unit and the second basic graphic unit are translational graphics to each other, and the translation can be a translation in a direction that forms an angle with the first direction and the second direction respectively. The first basic graphic unit and the second basic graphic have four common grounding pins; the four common grounding pins are arranged sequentially at intervals, wherein two common grounding pins are located between the sixth pin of the first basic graphic unit and the first pin of the second basic graphic unit, and the other two common grounding pins are located between the fourth pin of the first basic graphic unit and the fifth pin of the second basic graphic unit.

[0061] Based on the fourth implementation of the fourth aspect, this application also provides a ninth implementation of the fourth aspect: the first basic graphic unit and the second basic graphic unit are translational graphics to each other, and the translation can be a translation in a direction that forms an angle with the first direction and the second direction respectively. The first basic graphic unit and the second basic graphic have four common grounding pins; the four common grounding pins are arranged sequentially at intervals, wherein two common grounding pins are located between the fourth pin of the first basic graphic unit and the fifth pin of the second basic graphic unit, and the other two common grounding pins are located between the sixth pin of the first basic graphic unit and the first pin of the second basic graphic unit.

[0062] Based on the fourth implementation of the fourth aspect, this application also provides a tenth implementation of the fourth aspect: the first basic graphic unit and the second basic graphic unit are translational and rotated graphics of each other, the first basic graphic unit and the second basic graphic have four common grounding pins; the four common grounding pins are arranged sequentially at intervals, wherein two common grounding pins are adjacent to the fifth pin of the first basic graphic unit, and the other two common grounding pins are adjacent to the fourth pin of the first basic graphic unit.

[0063] A fifth aspect of this application provides a method for a CPU to read and send data. The CPU includes a packaging substrate, and the pin area of ​​the packaging substrate includes data signal pins and data strobe signal pins. The data signal pins and data strobe signal pins are arranged according to a pin arrangement pattern unit. The pin arrangement pattern unit includes six signal pins. The first, fourth, fifth, and sixth pins of the six signal pins are data signal pins, and the second and third pins of the six signal pins are data strobe signal pins. The first, second, third, and fourth pins are arranged in a first direction... The fifth and sixth pins are spaced apart in the second direction, and are positioned on the perpendicular line connecting the second and third pins, respectively, on opposite sides of the second and third pins. The CPU's method for reading and sending data includes the following steps: responding to a write or read instruction from the DDR signal; sending data to the DDR memory via the data signal pin according to the write instruction, and outputting a data strobe signal via the data strobe signal pin; or receiving data from the DDR memory via the data signal pin according to the read instruction, and reading the data strobe signal via the data strobe signal pin.

[0064] A sixth aspect of this application provides a method for a CPU to read data. The CPU includes a packaging substrate, and the pin area of ​​the packaging substrate includes data signal pins and data strobe signal pins. The data signal pins and data strobe signal pins are arranged according to a pin arrangement pattern unit, which includes six signal pins. The first, fourth, fifth, and sixth pins of the six signal pins are data signal pins, and the second and third pins of the six signal pins are data strobe signal pins. The first, second, third, and fourth pins are arranged sequentially at intervals in a first direction, and the fifth and sixth pins are arranged in a second direction. The fifth and sixth pins are arranged at intervals, positioned on the perpendicular line connecting the second and third pins, and located on either side of the second and third pins, respectively. The method for the CPU to read data includes the following steps: responding to a write command from the DDR signal. In a specific implementation, when the CPU or other devices need to read data from memory, the memory controller sends a read command to the memory module, specifying the address to be read; according to the write command, data is sent to the DDR memory through the data signal pin, and a data strobe signal is output through the data strobe signal pin, that is, a data clock signal is provided to the DDR memory so that the DDR memory can correctly receive and parse the data sent by the CPU.

[0065] A seventh aspect of this application provides a method for a CPU to transmit data. The CPU includes a packaging substrate, and the pin area of ​​the packaging substrate includes data signal pins and data strobe signal pins. The data signal pins and data strobe signal pins are arranged according to a pin arrangement pattern unit, which includes six signal pins. The first, fourth, fifth, and sixth pins of the six signal pins are data signal pins, and the second and third pins of the six signal pins are data strobe signal pins. The first, second, third, and fourth pins are arranged sequentially at intervals in a first direction, and the fifth and sixth pins are arranged at intervals in a second direction. The fifth and sixth pins are configured on the perpendicular line connecting the second and third pins, and are located on both sides of the second and third pins, respectively. The method for the CPU to read and send data includes the following steps: responding to the read instruction of the DDR signal. In a specific implementation, when the CPU or other devices need to write data to the memory, the memory controller sends a write command to the memory module and provides the data to be written and the target address; according to the read instruction, data is received from the DDR memory through the data signal pin, and the data strobe signal is read through the data strobe signal pin, that is, the data clock signal is provided to the CPU so that the CPU can correctly sample and parse the data transmitted from the DDR memory. Attached Figure Description

[0066] Figure 1 A partial structural schematic diagram of an electronic device provided in an embodiment of this application;

[0067] Figure 2 This is a schematic diagram of the pin arrangement of a packaging substrate provided in an embodiment of this application;

[0068] Figure 3 This is a schematic diagram of the pin arrangement structure of the packaging substrate provided in the embodiments of this application;

[0069] Figure 4 A schematic diagram illustrating the construction relationship of the basic graphic units provided in the embodiments of this application;

[0070] Figure 5 This is a schematic diagram illustrating a combination method of basic graphic units provided in an embodiment of this application;

[0071] Figures 6 to 10 These are schematic diagrams illustrating five additional combinations of basic graphic units provided in the embodiments of this application;

[0072] Figure 11 A schematic diagram of the hardware architecture of the CPU DDR interface provided in an embodiment of this application;

[0073] Figure 12This is a schematic diagram illustrating the relationship between the CPU DDR interface and the basic graphics unit as described in an embodiment of this application;

[0074] Figure 13 Schematic diagrams illustrating two other ways of combining multiple basic graphic units provided in embodiments of this application;

[0075] Figure 14 This is a schematic flowchart illustrating a method for CPU to read and send data according to an embodiment of this application;

[0076] Figure 15 This application provides a schematic diagram of pin configuration in a CPU application scenario.

[0077] Figure 16 A schematic diagram of pin configuration for another CPU application scenario provided in this application embodiment;

[0078] Figure 17 A schematic diagram of pin configuration for another CPU application scenario provided in this application embodiment;

[0079] Figure 18 This is a schematic diagram of the architecture of an electronic device provided in an embodiment of this application. Detailed Implementation

[0080] This application provides a chip packaging substrate pin arrangement scheme, which can effectively reduce crosstalk between pins by reasonably controlling the package size by increasing the pin arrangement density.

[0081] Please see Figure 1 This is a partial structural diagram of an electronic device provided in an embodiment of this application. The electronic device 100 includes a circuit board 10 and a chip 20 disposed on the circuit board 10. In specific implementations, the electronic device can be a communication terminal device, a server, a supercomputer, or a router, switch, or other similar device.

[0082] The chip 20 may include a packaging substrate 1 and a chip 2. The packaging substrate 1 serves as the carrier for packaging the chip 2, and the packaging is achieved through a housing 3. Here, a chip refers to a die formed by processing and dicing a wafer. The packaging substrate is the carrier for semiconductor chip packaging, and the external pins of the semiconductor package are formed on the packaging substrate. Current development directions for packaging substrates focus on achieving multi-pin configurations, reducing the size of packaged products, achieving high-density pin designs, and improving the electrical performance of physical interfaces.

[0083] During semiconductor chip packaging, chip 2 can be placed on packaging substrate 1, with the upper surface of packaging substrate 1 serving as the chip placement area. Specifically, during the manufacturing process of chip 20, the chip can be packaged using packaging technology to assemble it into a semiconductor package, i.e., a chip product, to provide functions such as protection, thermal management, mechanical support, and electrical connection.

[0084] Specifically, in the fabrication of semiconductor packages, the die is typically placed on a packaging substrate. The die's pins are then electrically connected to the solder balls or pads of the packaging substrate using methods such as gold wire bonding, flip-chip bonding, or automated carrier soldering. The die and packaging substrate are then packaged to form a semiconductor package, which is essentially a different chip product. The chip's external pins can be electrically connected to the PCB, enabling the die to connect to external circuits. Furthermore, the die can also be electrically connected to other devices via PCB traces.

[0085] like Figure 1 As shown, the pins on chip 2 are connected to the solder balls or pads on the packaging substrate 1 via flip-chip technology. In other specific implementations, the pins on chip 2 can also be connected to the solder balls or pads on the packaging substrate 1 via gold wire bonding technology, which is not limited in this application embodiment.

[0086] A packaging filler 4 can also be provided between the packaging substrate 1 and the housing 3. The packaging filler 4 can be used to wrap the chip 2 to reduce the adverse effects of external dust, impurities and other factors on the performance of the chip 2. On the other hand, it can also couple the packaging substrate 1, housing 3 and chip 2 into one unit to improve the structural strength of the chip 20.

[0087] The external pins of chip 20 are located on the packaging substrate 1, and the lower surface of the packaging substrate 1 is the pin area. Correspondingly, the circuit board 10 can be provided with pin interfaces for connecting to chip 20. The signal pins 11 on the packaging substrate 1 can be solder ball structures as shown in the figure, which are electrically connected to the corresponding pads on the circuit board 10 by soldering, and connected to other devices based on the wires on the circuit board 10, thereby realizing the connection between chip 2 and external circuits.

[0088] As is understandable, signal pins are used to establish signal transmission and data exchange between chips. Signal pins include data signal pins and control signal pins, which can be applied to different parallel bus transmission modes to transmit large amounts of data and control signals. Data signal pins are used to transmit DQ (Data Input / Output) signals to transmit data bits or bytes. Control signal pins can transmit corresponding control signals depending on the application scenario. For example, but not limited to, based on the DDR bus protocol, control signal pins can be used to transmit DQS (Data Strobe) signals to indicate the data sampling time; control signal pins can also be used to transmit DM (Input Data Mask) signals to indicate the validity of each data signal bit (DQ), enabling masking and selective writing of each data bit; or, based on the ONFI (Open NAND Flash Interface) bus protocol for flash memory, these control signal pins are used to transmit signals controlling data transmission for data transfer and communication between the flash memory controller and the flash memory chip.

[0089] In a specific implementation, the signal pins on chip 20 can also be metal contacts located on the packaging substrate 1, with corresponding metal springs provided on the circuit board 10. The metal contacts on the chip 20 side and the metal springs on the circuit board 10 side are arranged one-to-one (not shown in the figure). After the chip 20 is fixed in its mounting position on the circuit board 10, the metal contacts press against the metal springs, and the deformed metal springs maintain reliable contact with the matching metal contacts, thus achieving electrical connection of the corresponding pins. It is understood that the specific connection structure between the external pins of chip 20 and the circuit board 10 can be configured according to the actual application scenario, and this embodiment does not limit it.

[0090] Typically, a key performance indicator for chip packaging technology is the ratio of chip area (die area) to package area. When the die area is constant, a smaller ratio indicates a larger package area, meaning a larger chip size. This leads to lower manufacturing yield and increased production costs. Conversely, a ratio closer to 1 indicates a smaller package area, resulting in higher manufacturing yield and lower production costs. For the packaging substrate 1, the pin density is a crucial factor affecting the package area. However, increasing the pin density can lead to electromagnetic crosstalk between pins, impacting chip performance.

[0091] In addition, to reduce electromagnetic crosstalk between pins, ground pins are placed around the pins of the chip package substrate to provide a ground connection. Specifically, in the chip pinmap, the arrangement of ground pins provides a low-impedance ground path, forming a uniform ground potential. This guides the energy of the electromagnetic field to the ground plane, thereby reducing electromagnetic crosstalk (also known as mutual interference) between signal pins, helping to maintain signal integrity and reducing noise. However, the placement of ground pins increases the chip size; therefore, it is necessary to further increase the pin density to reduce the package area.

[0092] Based on this, this application provides a pinmap layout scheme. Please refer to [link to relevant documentation]. Figure 2 This figure is a schematic diagram of a pin arrangement on a packaging substrate provided in an embodiment of this application. For ease of description, two arrangement directions are defined herein for the pin area of ​​the packaging substrate 1: the first direction X is the left-right arrangement direction of the pins shown in the figure, and the second direction Y is the up-down arrangement direction of the pins shown in the figure. It should be understood that the use of the above directional terms does not constitute a substantial limitation on the technical solution described in this application.

[0093] Multiple pin map patterns are provided in the pin area on the main body of the packaging substrate 1. For example... Figure 2 As shown, the pin arrangement graphic unit is a basic graphic unit P including six signal pins 11. The first pin 111, second pin 112, third pin 113, and fourth pin 114 of the six signal pins 11 are arranged sequentially at intervals in the first direction X. The fifth pin 115 and sixth pin 116 of the six signal pins are arranged at intervals in the second direction Y. The fifth pin 115 and sixth pin 116 are located on the perpendicular bisector L2 of the line L1 connecting the second pin 112 and the third pin 113, respectively located on both sides of the line L1. Specifically, the first pin 111, fourth pin 114, fifth pin 115, and sixth pin 116 are data signal pins a (pins shown with solid fill in the figure), and the second pin 111 and third pin 113 are control signal pins b (pins shown with diagonal fill in the figure).

[0094] Overall, the pins of this Pinmap Pattern are arranged in a cross-shaped pattern unit. Four data signal pins (a) are positioned at the four extended ends of the cross-shaped pattern unit, while the control signal pin (b) is positioned in the center. This arrangement keeps the data signal pins (a) far apart, ensuring that no adjacent data signal pin (a) can become a source of crosstalk, effectively avoiding electromagnetic crosstalk between adjacent data signal pins (a). Based on this Pinmap solution, on the one hand, it effectively reduces electromagnetic crosstalk between pins, supporting higher parallel bus operating speeds, such as, but not limited to, DDR buses or flash ONFI buses, for high-speed data and control signal transmission; on the other hand, it increases pin density, saves package area, and provides technical support for further improving product yield and reducing processing costs.

[0095] Here, in Figure 2 In the following figures, the dashed lines connecting each signal pin 11 are only used to indicate the positional relationship of each pin, and the dashed lines surrounding each signal pin 11 are only used to indicate the arrangement area of ​​the basic graphic unit P. The corresponding dashed lines do not exist in the structure of the packaging substrate and do not limit the specific structure of the packaging substrate.

[0096] In other specific implementations, the multiple pin arrangement pattern units in the pin area of ​​the packaging substrate 1 can be configured with different pin arrangement methods according to actual functional needs. For example, for a CPU chip, some of the basic pattern units P can be configured as cross-shaped pattern units as shown in the figure to build a parallel bus channel; while other pin arrangement pattern units can be configured as pattern units with other arrangement patterns (not shown in the figure) to realize electrical connection with the corresponding external circuits. That is to say, the pin arrangement in the pin area of ​​the packaging substrate 1 can be obtained by combining and arranging several pattern units, rather than being limited to... Figure 2 The examples shown are all configured with graphic units arranged in a cross shape.

[0097] In this embodiment, the fifth pin 115 and the sixth pin 116 are arranged on the perpendicular bisector of the line connecting the second pin 112 and the third pin 113. That is, the distance from the second pin 112 and the third pin 113 to the line connecting the fifth pin 115 and the sixth pin 116 is equal. The cross-shaped arrangement of the graphic unit is a centrally symmetrical structure.

[0098] In a specific implementation, the distances between the second pin 112 and the third pin 113 and the line connecting the fifth pin 115 and the sixth pin 116 can be unequal (not shown in the figure). In other words, the fifth pin 115 and the sixth pin 116 are located on either side of the line connecting the second pin 112 and the third pin 113, which also achieves the goal of ensuring that no adjacent crosstalk source forms for each data signal pin. Furthermore, in other implementations, the line connecting the fifth pin 115 and the sixth pin 116 can intersect the line connecting the second pin 112 and the third pin 113 at other angles (not shown in the figure).

[0099] In comparison, the implementation where the fifth pin 115 and the sixth pin 116 are positioned on the perpendicular bisector of the line connecting the second pin 112 and the third pin 113 can maximize the pin density while effectively reducing electromagnetic crosstalk. Please refer to [link / reference]. Figure 3 This figure is a schematic diagram of the pin arrangement structure of the packaging substrate provided in an embodiment of this application. Combined with... Figure 3 As shown, the pins in the pin area of ​​the packaging substrate 1 are arranged in an array, and the pins in each row and column are staggered. This staggered arrangement means that the pins in each row (X1~X15) and each column (Y1~Y9) are interleaved, allowing for the arrangement of as many pins as possible within a limited space. In other words, the pins in the pin area are arranged in a triangular grid pattern, with each pin and the line connecting it to its two adjacent pins forming an equilateral triangle. This allows for a tight, alternating arrangement of cross-shaped pattern units, increasing the pin density.

[0100] It should be noted that for each pin in the pin area of ​​the packaging substrate 1, the pin and the other two adjacent pins are arranged in an equilateral triangle. This includes equilateral triangle arrangements with well controlled form and position tolerances, as well as triangle arrangements with dimensional tolerances due to the influence of processing precision. In other words, it also includes cases where there is a certain deviation within the range of process precision limitations, and the arrangement is not completely equilateral but roughly in an equilateral triangle.

[0101] Furthermore, a ground (GND) pin can be provided around the six signal pins 11 of the cross-shaped graphic unit. Please refer to [link / reference]. Figure 4 This figure is a schematic diagram of the construction relationship of the basic graphic units provided in the embodiments of this application.

[0102] As shown in the figure, corresponding to the six signal pins 11 of the cross-shaped graphic unit, the basic graphic unit P is provided with fourteen grounding pins 12 (pins c shown as single-line circles in the figure). Centered on the two control signal pins b, four data signal pins a are arranged at the closest positions to the two control signal pins b in the top, bottom, left, and right. Finally, grounding pins c are arranged on the periphery to form a return ground around each signal pin 11, thereby reducing electromagnetic interference with other pins.

[0103] Figure 4 The fourteen grounding pins 12 described herein surround the six signal pins 11, and the fourteen grounding pins 12 are arranged in a 14-sided polygon with intervals between them. In the first direction X, the first grounding pin 1201 is located next to the first pin 111, the eighth grounding pin 1208 is located next to the fourth pin 114, and the second grounding pin 1202, the third grounding pin 1203, the fourth grounding pin 1204, the fifth grounding pin 1205, the sixth grounding pin 1206 and the seventh grounding pin 1207 are arranged sequentially between the first grounding pin 1201 and the eighth grounding pin 1208; the ninth grounding pin 1209, the tenth grounding pin 1210, the eleventh grounding pin 1211, the twelfth grounding pin 1212, the thirteenth grounding pin 1213 and the fourteenth grounding pin 1214 are arranged sequentially between the eighth grounding pin 1208 and the first grounding pin 1201.

[0104] In this diagram, the data signal pins a adjacent to two adjacent grounding pins 12 form an equilateral triangle S with the line connecting the two adjacent grounding pins 12. Each data signal pin a is located on the perpendicular bisector of the line connecting its two adjacent grounding pins 12. For simplicity, only the first pin 111 is used as an example to illustrate its relative positional relationship with its two adjacent grounding pins 12. This fully utilizes the pin area space where pins are staggered between rows and columns, constructing pinmap units according to alternating arrangement rules, ensuring consistent distance between any two adjacent pins. While providing a return ground function, it increases pin density and achieves a high signal-to-ground ratio. Here, "signal-to-ground ratio" refers to the ratio of the number of signal pins 11 to the number of grounding pins 12 per unit area. It is understood that in other specific implementations, the number of grounding pins 12 can be determined as needed, and this embodiment does not limit this.

[0105] In the specific implementation, one basic graphics unit P can correspond to one Nibbel (half-byte) signal pin. The data of each Nibbel can be transmitted using four DQ data signals and a pair of DQS differential clock signals. Among the six signal pins 11, four data signal pins a are single-ended signal pins used to transmit DQ data signals; two control signal pins b are differential signal pins used to transmit DQS signals.

[0106] When the two control signal pins (pin 112 and pin 113) transmit the DQS differential clock signal, the differential signal pair has opposite polarities during transmission, that is, the signal amplitudes transmitted on the two pins of the differential signal pair are opposite. As a result, the interference to the second direction Y and its two adjacent single-ended signal pins (pin 115 and pin 116) can be completely canceled, and the crosstalk to the first direction X and its two left and right single-ended signal pins (pin 111 and pin 114) can be partially canceled, thereby reducing the total crosstalk of the single-ended signal.

[0107] In DDR system scenarios, based on the definition of DDR signals, data signals are typically divided into bytes. Each byte unit is transmitted using four DQ data signals and a pair of DQS differential clock signals. Based on the aforementioned basic graphics unit P, a combined unit formed by two basic graphics units P can be used to transmit one byte of data. That is, in DDR pinmap design, a byte is usually used as the basic unit for arrangement.

[0108] Please see Figure 5 This figure is a schematic diagram illustrating a combination method of a basic graphic unit P provided in an embodiment of this application. The figure shows a combined unit formed by splicing two basic graphic units P, capable of transmitting data in units of one byte. Based on... Figure 4 The described basic graphic unit P is composed of two basic graphic units P spliced ​​together to form a pin arrangement combination unit corresponding to one byte unit. The adjacent sides of the first basic graphic unit P1 and the second basic graphic unit P2 share a ground pin.

[0109] like Figure 5As shown, the first basic graphic unit P1 and the second basic graphic unit P2 are translated graphics, that is, one of the two basic graphic units P is a graphic unit formed by translating relative to the other. Specifically, the fifth pin 115 of the first basic graphic unit P1 is arranged in the same direction as the first pin 111, second pin 112, third pin 113, and fourth pin 114 of the second basic graphic unit P2; the first pin 111, second pin 112, third pin 113, and fourth pin 114 of the first basic graphic unit P1 are arranged in the same direction as the sixth pin 116 of the second basic graphic unit P2.

[0110] In this implementation, the first basic graphic unit P1 and the second basic graphic unit P2 share two grounding pins 12, and these two shared grounding pins 12 are located between the fourth pin 114 of the first basic graphic unit P1 and the first pin 111 of the second basic graphic unit P2. Specifically, the seventh grounding pin 1207 of the first basic graphic unit P1 and the first grounding pin 1201 of the second basic graphic unit P2 share a grounding pin, and the eighth grounding pin 1208 of the first basic graphic unit P1 and the fourteenth grounding pin 1214 of the second basic graphic unit P2 share a grounding pin. This effectively reduces electromagnetic crosstalk and results in a more compact and reasonable pin layout density.

[0111] In the specific implementation, the eight data signal pins a of the two basic graphics units P can correspond to the eight data pins on the data bus: DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6 and DQ7, respectively sending or receiving data bits 0 to 7; the four control signal pins of the two basic graphics units P correspond to the four data clock signal pins on the data bus: DQS0, DQS1, DQS2 and DQS3, where DQS0 and DQS1 are a differential pair, and DQS2 and DQS3 are a differential pair, respectively used for timing and synchronizing data during data transmission.

[0112] Based on the staggered arrangement of pins in the pin area of ​​the packaging substrate 1, different forms of pin arrangement combination units can be formed by translating or rotating them. Please refer to [link to relevant documentation]. Figures 6 to 10 Five different ways of combining basic graphic units are shown, among which, Figure 6 , Figure 7 , Figure 8 and Figure 10 The assembled unit shown consists of two basic graphic units P, one of which is a graphic unit formed by translating relative to the other. Figure 9 The assembled unit shown has two basic graphic units P, one of which is a graphic unit formed by rotating and translating relative to the other.

[0113] like Figure 6 As shown, the first basic graphic unit P1 and the second basic graphic unit P2 are translational graphics of each other. The fifth pin 115 and the sixth pin 116 of the first basic graphic unit P1 are arranged in the same direction as the fifth pin 115 and the sixth pin 116 of the second basic graphic unit P2.

[0114] In this implementation, the two basic graphic units share two grounding pins 12 arranged at intervals. The two shared grounding pins 12 are located between the sixth pin 116 of the first basic graphic unit P1 and the fifth pin 115 of the second basic graphic unit P2. Specifically, the twelfth grounding pin 1212 of the first basic graphic unit P1 and the fourth grounding pin 1204 of the second basic graphic unit P2 are shared grounding pins, and the eleventh grounding pin 1211 of the first basic graphic unit P1 and the fifth grounding pin 1205 of the second basic graphic unit P2 are shared grounding pins.

[0115] like Figure 7 As shown, the first basic graphic unit P1 and the second basic graphic unit P2 are translational graphics of each other. The first pin 111, the second pin 112, the third pin 113 and the fourth pin 114 of the first basic graphic unit P1 are arranged in the same direction as the first pin 111, the second pin 112, the third pin 113 and the fourth pin 114 of the second basic graphic unit P2.

[0116] In this implementation, the two basic graphic units share a grounding pin 12. The shared grounding pin 12 is located between the fourth pin 114 of the first basic graphic unit P1 and the first pin 111 of the second basic graphic unit P2. Specifically, the eighth grounding pin 1208 of the first basic graphic unit P1 and the first grounding pin 1201 of the second basic graphic unit P2 are shared grounding pins.

[0117] like Figure 8 As shown, the first basic graphic unit P1 and the second basic graphic unit P2 are translational graphics of each other. The fifth pin 115 and the sixth pin 116 of the first basic graphic unit P1 are arranged in the same direction as the first pin 111 of the second basic graphic unit P2; the fourth pin 114 of the first basic graphic unit P1 is arranged in the same direction as the fifth pin 115 and the sixth pin 116 of the second basic graphic unit P2.

[0118] In this implementation, the two basic graphic units share four grounding pins 12 arranged sequentially at intervals. Two of these shared grounding pins 12 are located between the sixth pin 116 of the first basic graphic unit P1 and the first pin 111 of the second basic graphic unit P2, and the other two shared grounding pins 12 are located between the fourth pin 114 of the first basic graphic unit P1 and the fifth pin 115 of the second basic graphic unit P2. Specifically, the twelfth grounding pin 1212 of the first basic graphic unit P1 and the second grounding pin 1202 of the second basic graphic unit P2 are shared grounding pins; the eleventh grounding pin 1211 of the first basic graphic unit P1 and the third grounding pin 1203 of the second basic graphic unit P2 are shared grounding pins; the tenth grounding pin 1210 of the first basic graphic unit P1 and the fourth grounding pin 1204 of the second basic graphic unit P2 are shared grounding pins; and the ninth grounding pin 1209 of the first basic graphic unit P1 and the fifth grounding pin 1205 of the second basic graphic unit P2 are shared grounding pins.

[0119] like Figure 9 As shown, the first basic graphic unit P1 and the second basic graphic unit P2 are translational and rotational graphics of each other. The first pin 111 and the fifth pin 115 of the first basic graphic unit P1 are arranged in the same direction as the fifth pin 115 and the sixth pin 116 of the second basic graphic unit P2. The sixth pin 116 and the fourth pin 114 of the first basic graphic unit P1 are arranged in the same direction as the first pin 111 of the second basic graphic unit P2.

[0120] In this implementation, the two basic graphic units share four grounding pins 12 arranged at intervals in sequence. Two of the shared grounding pins 12 are located between the fifth pin 115 of the first basic graphic unit P1 and the fifth pin 115 of the second basic graphic unit P2. The other two shared grounding pins 12 are located between the fourth pin 114 of the first basic graphic unit P1 and the first pin 111 of the second basic graphic unit P2. Specifically, the fifth grounding pin 1205 of the first basic graphic unit P1 and the fifth grounding pin 1205 of the second basic graphic unit P2 are shared grounding pins; the sixth grounding pin 1206 of the first basic graphic unit P1 and the fourth grounding pin 1204 of the second basic graphic unit P2 are shared grounding pins; the seventh grounding pin 1207 of the first basic graphic unit P1 and the third grounding pin 1203 of the second basic graphic unit P2 are shared grounding pins; and the eighth grounding pin 1208 of the first basic graphic unit P1 and the second grounding pin 1202 of the second basic graphic unit P2 are shared grounding pins.

[0121] like Figure 10As shown, the first basic graphic unit P1 and the second basic graphic unit P2 are translational graphics of each other. The fourth pin 114 of the first basic graphic unit P1 is arranged in the same direction as the first pin 111 of the second basic graphic unit P2; the sixth pin 116 of the first basic graphic unit P1 is arranged in the same direction as the fifth pin 115 of the second basic graphic unit P2.

[0122] Both share four grounding pins 12 arranged sequentially at intervals. Two of these shared grounding pins 12 are located between the sixth pin 116 of the first basic graphic unit P1 and the first pin 111 of the second basic graphic unit P2. The other two shared grounding pins 12 are located between the fourth pin 114 of the first basic graphic unit P1 and the fifth pin 115 of the second basic graphic unit P2. Specifically, the eleventh grounding pin 1211 of the first basic graphic unit P1 and the first grounding pin 1201 of the second basic graphic unit P2 are shared grounding pins; the tenth grounding pin 1210 of the first basic graphic unit P1 and the second grounding pin 1202 of the second basic graphic unit P2 are shared grounding pins; the ninth grounding pin 1209 of the first basic graphic unit P1 and the third grounding pin 1203 of the second basic graphic unit P2 are shared grounding pins; and the eighth grounding pin 1208 of the first basic graphic unit P1 and the fourth grounding pin 1204 of the second basic graphic unit P2 are shared grounding pins.

[0123] It is understandable that the configuration mentioned above Figure 2 , Figure 3 and Figure 4 The described basic graphic unit P's packaging substrate, and the substrate configured with... Figures 5 to 10 The described pin arrangement combination unit packaging substrate can be used to match chips such as CPU (central processing unit), GPU (graphics processing unit), or NPU (neural-network processing unit). That is, the pinmap formed on the pin area of ​​the packaging substrate described in the foregoing embodiments, based on the basic graphics unit P, can be used for the DDR interface on the CPU chip, NPU chip, or GPU chip. For the CPU chip, the DDR signal can be connected to the memory chip (DIMM) on the memory module (DIMM) through signal pin 11 and PCB traces.

[0124] The following is a brief explanation of how the pin arrangement on the aforementioned packaging substrate matches the CPU chip.

[0125] Please see Figure 11 The figure is a schematic diagram of the hardware architecture of the CPU DDR interface provided in an embodiment of this application.

[0126] like Figure 11 As shown, the CPU chip 21 includes multiple memory channels (DDR channels) 22, each of which can drive and connect to a corresponding memory module 30. Without loss of generality, Figure 11 The example shown is a CPU chip 21 with eight memory channels 22. It should be understood that in other specific implementations, the number of channels of the CPU and the number of memory modules connected to each channel can be set according to actual needs, and can be implemented based on existing technology, so it will not be elaborated on here.

[0127] Each memory channel 22 may include multiple DDR Byte units 23, and each Byte includes two Nibbles 24. The memory bandwidth of a memory channel 22 is typically 32-bit or 64-bit. It can be understood that a 32-bit bandwidth memory channel 22 can be composed of four Byte units 23, and a 64-bit bandwidth memory channel 22 can be composed of eight Byte units 23. This application does not limit the scope of the embodiments.

[0128] Please see also Figure 12 The figure is a schematic diagram showing the relationship between the CPU DDR interface and the basic graphics unit P in an embodiment of this application.

[0129] like Figure 12 As shown, each Nibble 24 contains six data signals: four DQ data signals and a pair of DQS differential clock signals. Here, the six data signals of each Nibble 24 and its surrounding GND pin can be combined using the cross-shaped pin arrangement unit P described in the aforementioned embodiments. Alternatively, each Byte 23 contains twelve data signals: eight DQ data signals and two pairs of DQS differential clock signals. Correspondingly, the twelve data signals of each Byte 23 and its surrounding GND pin can be combined using the cross-shaped pin arrangement unit P described in the aforementioned embodiments. Figures 5 to 10 The Pinmap Pattern combination unit described.

[0130] In a specific implementation, the pins corresponding to all memory channels 22 of the CPU chip 21 can be arranged in a combination of signal pins and their peripheral ground pins based on a Nibble array, forming a complete DDR Channel Pinmap. This ensures a high pin density in the memory channel 22 area of ​​the CPU chip 21 and minimizes electromagnetic crosstalk between signal pins, thereby guaranteeing stable signal transmission between the CPU 21 and the memory module 30. In a specific implementation, the memory module 30 can be a dual-inline-memory module (DIMM), but this embodiment is not limited to this.

[0131] Please see Figure 13 This figure is a schematic diagram of two ways of combining multiple basic graphic units provided in the embodiments of this application. Figure 13 In the combination shown in Figure (a), each basic graphic unit P is spliced ​​together after translation. For two adjacent columns of basic graphic units P, the fourth pin of each basic graphic unit P belonging to the left column and the first pin of each basic graphic unit P belonging to the right column are arranged alternately along the second direction. Figure 13 In the combination shown in Figure (b), some basic graphic units P are spliced ​​together by translation, and other basic graphic units P are spliced ​​together by rotation and translation.

[0132] like Figure 13 As shown, based on the staggered arrangement of pins in the pin area of ​​the packaging substrate 1, and using the DDR Channel Pinmap formed by combining the basic graphic units provided in this application embodiment, each group of adjacent basic graphic units P can share a peripheral ground pin, resulting in a more compact and reasonable overall pin layout density. Utilizing the structural characteristics of the cross-shaped pin arrangement graphic units, the data signal pins a of the DDR Channel Pinmap are kept far apart from each other, and each data signal pin a has no adjacent crosstalk sources, effectively avoiding the influence of electromagnetic crosstalk between adjacent data signal pins a.

[0133] The CDU chip described in the foregoing embodiments can be used in different generations of DDR systems to store and retrieve data. For example, but not limited to, DDR4 SDRAM (4th generation Double Data Rate Synchronous Dynamic Random Access Memory) and DDR5 SDRAM (5th generation Double Data Rate Synchronous Dynamic Random Access Memory). Based on different DDR chip data bus widths, DDR4 SDRAM includes two types: X8 and X16, while DDR5 SDRAM includes three types: X4, X8, and X16. Among them, the chip width of X4 devices is 4 bits, the chip width of X8 devices is 8 bits, and the chip width of X16 devices is 16 bits.

[0134] For the control signal pin b of the basic graphics unit P, it is usually defined as the DQS signal pin on the CDU chip side. In other specific implementations, such as in the x8 scenario, if the DM signal needs to be transmitted, the DQS0~DQS3 pins can be configured as channels for multiplexing the DM signal. The DM signal is used to indicate the validity of each DQ data signal to provide masking and selective writing for each data bit. During a write operation (WR OP), the CPU sends the DM signal, DQ signal, and DQS signal to the DRAM simultaneously. At this time, the DM signal and DQ signal are sampled together at the rising / falling edge of the DQS clock signal. When the control signal pin is used to transmit the DM signal, the DM is sampled as low, resulting in low electromagnetic crosstalk, which will not affect the data transmission of the DQ data signal pin.

[0135] It should be noted that the aforementioned cross-shaped basic graphic unit P can be applied to the chip packaging structure design for information connection with DDR memory. In addition to CPU chips, GPU chips or NPU chips, it can also be applied to other chips or connectors based on DDR interface. Through good anti-crosstalk performance, it ensures correct signal transmission and data reading and writing, thus providing technical guarantee for high-performance and reliable DDR systems.

[0136] Of course, for other parallel bus scenarios, the Pinmap formed by the aforementioned cross-shaped basic graphic unit P is used for the corresponding physical line interface, such as, but not limited to, parallel cameras, parallel external storage devices, or parallel printers, which are input and output devices that transmit data and control signals through parallel buses.

[0137] based on Figure 11 The hardware architecture of the CPU DDR interface shown in this application embodiment also provides a method for the CPU to read and send data. Please refer to [link to relevant documentation]. Figure 14 This figure is a schematic flowchart of a method for CPU to read and send data according to an embodiment of this application.

[0138] like Figure 14 As shown, the method includes the following steps:

[0139] Step 101: Respond to the write or read command of the DDR signal;

[0140] In practical implementation, when the CPU or other devices need to read data from memory, the memory controller sends a read command to the memory module, specifying the address to be read. When the CPU or other devices need to write data to memory, the memory controller sends a write command to the memory module, providing the data to be written and the target address. Here, the memory controller, either a part of the CPU or a separate chip on the motherboard, is used to control the read and write operations of the memory module and to handle memory access requests from the CPU or other devices.

[0141] Step 102: According to the write instruction, data is sent to the DDR memory through the DQ pin, and a data strobe signal is output through the DQS pin, which provides a data clock signal to the DDR memory so that the DDR memory can correctly receive and parse the data sent by the CPU; or, according to the read instruction, data is received from the DDR memory through the DQ pin, and a data strobe signal is read through the DQS pin, which provides a data clock signal to the CPU so that the CPU can correctly sample and parse the data transmitted from the DDR memory.

[0142] Specifically, during data transmission, there is a timing relationship between the DQS pin and the corresponding DQ pin. Data sampling and transmission occur at the edge (rising or falling edge) of the data clock signal. When sending data, the memory module receives a command and writes the data to the memory cell at the specified address. When reading data, the memory module receives a command and transmits the requested data to the CPU via the data bus.

[0143] The CPU chip's DQ pins (data signal pins) and DQS pins (data strobe signal pins) are arranged in a basic graphic unit, which includes six signal pins: pin 111, pin 112, pin 113, pin 114, pin 115, and pin 116. Among them, pins 111, 114, 115, and 116 are DQ pins (pins shown as solid circles in the figure), and pins 111 and 113 are DQS pins (pins shown as diagonal lines in the figure). The six signal pins are arranged in a cross shape. The first pin 111, the second pin 112, the third pin 113 and the fourth pin 114 are arranged alternately in the first direction X. The fifth pin 115 and the sixth pin 116 are arranged alternately in the second direction Y. The fifth pin 115 and the sixth pin 116 are located on the perpendicular line connecting the second pin 112 and the third pin 113, and are located on both sides of the second pin 112 and the third pin 113, respectively.

[0144] Taking a pin arrangement unit corresponding to one byte as an example, its eight data signal pins: DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, and DQ7 are used to send or receive data bits 0 to 7 respectively; its four data clock signal pins: DQS0, DQS1, DQS2, and DQS3, DQS0 and DQS1 are a differential pair of pins, and DQS2 and DQS3 are a differential pair of pins, used for timing and synchronizing data during data transmission respectively.

[0145] Please see Figure 15 The figure is a schematic diagram of pin configuration in a CPU application scenario provided by an embodiment of this application.

[0146] For X4 particle scenarios, the pin configuration is as follows: Figure 15 As shown, the specific behavior of each signal pin during write and read operations (WR OP / RD OP) is as follows:

[0147] Write operation: The CPU sends the DQ signal and the DQS signal to the DRAM. The DQS signal is aligned with the center of the DQ signal. On the DRAM side, the DQ signal is sampled at the rising and falling edges of the DQS clock signal, and the sampled signal is stored in the DRAM.

[0148] Read operation: DRAM sends DQ and DQS signals to the CPU. The edges of the DQS signal are aligned with those of the DQ signal. The CPU first adjusts the phase relationship between the DQS and DQ signals to align the centers of the DQS and DQ signals, then samples the signal and sends the sampled signal to the backend for processing.

[0149] Please see Figure 16 This figure is a schematic diagram of pin configuration in another CPU application scenario provided by an embodiment of this application.

[0150] For X8 chip scenarios, the pin configuration is as follows: Figure 16 As shown, during write and read operations (WR OP / RD OP), the RFU pin is a reserved pin for future use. The specific behaviors of the other signal pins are as follows:

[0151] Write operation: The CPU sends the DQ, DM, and DQS signals to the DRAM. The DQS signal is center-aligned with the DQ and DM signals. On the DRAM side, the DQ and DM signals are sampled at the rising and falling edges of the DQS signal, and the sampled signals are stored in the DRAM. It should be understood that when the DM signal is sampled as low, the DQ signal sampled together with it is masked and not written to the DRAM.

[0152] Read operation: DRAM sends DQ and DQS signals to the CPU. The edges of the DQS signal are aligned with those of the DQ signal. The CPU first adjusts the phase relationship between DQS and DQ to align the centers of the DQS and DQ signals, then samples the signal and sends the sampled signal to the backend for processing.

[0153] In practical applications, the basic graphic unit based on the cross-shaped pattern can increase the density of pin arrangement, save package area, and effectively reduce electromagnetic crosstalk between pins, thus supporting higher DDR operating speeds.

[0154] It should be noted that, in specific implementations, the aforementioned signal pins can employ different pin configurations and signal allocation methods, which can be determined based on the type and specifications of the CPU chip and DDR chip, as well as the control mechanism of the corresponding memory controller. This application's embodiments do not impose limitations on these methods.

[0155] Please see Figure 17 This figure is a schematic diagram of pin configuration in another CPU application scenario provided by an embodiment of this application. For example... Figure 17 As shown, the pin arrangement combination unit formed by two basic graphic units P can support the mixed arrangement of DQ signals of different Nibble / Byte. Specifically, the four data signal pins corresponding to Nibble0 are DQ0, DQ1, DQ2, and DQ3, and the four data signal pins corresponding to Nibble1 are DQ4, DQ5, DQ6, and DQ7. Nibble0's DQ0, DQ1, and DQ2 are configured with Nibble1's DQ4 in one basic graphic unit P, while Nibble0's DQ3 and Nibble1's DQ5, DQ6, and DQ7 are configured with another basic graphic unit P.

[0156] Furthermore, based on the chip 20 with cross-shaped basic pattern units as described in the foregoing embodiments, this application also provides a signal transmission method applied to the chip. The chip 20's packaging substrate 4 has a plurality of pin arrangement pattern units in its pin area; at least two of the plurality of pin arrangement pattern units are basic pattern units P, each basic pattern unit P including six signal pins 11; wherein, the first pin 111, the second pin 112, the third pin 113, and the fourth pin 114 are... 14 is arranged sequentially at intervals in the first direction X, and the fifth pin 115 and the sixth pin 116 of the six signal pins 11 are arranged at intervals in the second direction Y; the fifth pin 115 and the sixth pin 116 are respectively located on both sides of the line connecting the second pin 112 and the third pin 113; wherein, the first pin 111, the fourth pin 114, the fifth pin 115 and the sixth pin 116 are data signal pins, and the second pin 112 and the third pin 113 are control signal pins; the first direction X is different from the second direction Y. In a specific implementation, the chip can be a CPU chip as described above, or it can be other chips or connectors based on a DDR interface, and the embodiments of this application are not limited thereto.

[0157] The signal transmission method includes the following steps: transmitting data signals through first pin 111, fourth pin 1114, fifth pin 115, and sixth pin 116, and transmitting control signals through second pin 112 and third pin 113. Based on the aforementioned cross-shaped basic graphic unit P, the chip's correct signal transmission is ensured through excellent crosstalk prevention performance, thus providing technical support for high-performance and reliable system applications.

[0158] This application also provides an electronic device; please refer to [link to relevant documentation]. Figure 18 This figure is a schematic diagram of the architecture of an electronic device provided in an embodiment of this application. The electronic device 100a includes a housing 40a, a circuit board 10a disposed within the housing 40a, and a CPU 20a. The CPU 20a is disposed on the circuit board 10a, and the pin area on the packaging substrate of the CPU 20a may include those described above. Figure 2 , Figure 3 and Figure 4 The described basic graphics unit P, or may include Figures 5 to 10 The described pin arrangement combination unit. Based on the cross-shaped basic graphic unit provided in this embodiment, its pin arrangement can increase the pin density, save package area, reduce DDR memory signal crosstalk, and improve the computing performance of computing devices.

[0159] It should be understood that other functions of the computing device are not the core inventive point of this application, and therefore will not be elaborated upon here.

[0160] The cross-shaped pin arrangement pattern unit provided in this implementation scheme is an important technical means of chip packaging technology and has broad application prospects. It will play an increasingly important role in different electronic devices, such as, but not limited to, computing devices such as servers, supercomputers, and Ethernet switches, and can also be applied to terminal devices such as automobiles, mobile phones, and laptops.

[0161] The ordinal numbers "first" and "second" used herein are only for describing the composition or structure of the same function in the technical solution. It is understood that the use of the ordinal numbers "first" and "second" above does not constitute a limitation on the understanding of the technical solution for which protection is sought in this application.

[0162] The above are merely preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A chip, characterized in that, It includes a core and a packaging substrate, wherein the core is disposed on the packaging substrate, and the pin area of ​​the packaging substrate is provided with multiple pin arrangement pattern units; Among the plurality of pin arrangement graphic units, at least two pin arrangement graphic units are basic graphic units including six signal pins; Among the six signal pins, the first pin, the second pin, the third pin, and the fourth pin are arranged sequentially at intervals in the first direction, and the fifth pin and the sixth pin are arranged at intervals in the second direction, with the fifth pin and the sixth pin located on both sides of the line connecting the second pin and the third pin, respectively. Wherein, the first pin, the fourth pin, the fifth pin, and the sixth pin are data signal pins, and the second pin and the third pin are control signal pins; the first direction is different from the second direction.

2. The chip according to claim 1, characterized in that, The fifth and sixth pins are located on the perpendicular line of the line connecting the second and third pins, and the first direction is perpendicular to the second direction.

3. The chip according to claim 2, characterized in that, The fifth and sixth pins are located on the perpendicular bisector of the line connecting the second and third pins.

4. The chip according to any one of claims 1 to 3, characterized in that, The basic graphic unit is either centrally symmetric or axially symmetric.

5. The chip according to any one of claims 1 to 4, characterized in that, The pins in the pin area are arranged in an array, and the pins in the rows and columns are staggered.

6. The chip according to any one of claims 1 to 5, characterized in that, The pins in the pin area are arranged in a triangular grid pattern, wherein the line connecting the pin and the two adjacent pins forms an equilateral triangle.

7. The chip according to any one of claims 1 to 6, characterized in that, The basic graphic unit also includes a ground pin, which is arranged around the six signal pins.

8. The chip according to claim 7, characterized in that, The basic graphic unit has fourteen grounding pins, which are arranged sequentially and at intervals around the six signal pins. In the first direction, the first grounding pin is located next to the first pin, the eighth grounding pin is located next to the fourth pin, and the second, third, fourth, fifth, sixth, and seventh grounding pins are arranged sequentially between the first grounding pin and the eighth grounding pin. The ninth, tenth, eleventh, twelfth, thirteenth, and fourteenth grounding pins are arranged sequentially between the eighth grounding pin and the first grounding pin.

9. The chip according to claim 8, characterized in that, The two basic graphic units are arranged adjacent to each other, one being the first basic graphic unit and the other being the second basic graphic unit. The adjacent sides of the first basic graphic unit and the second basic graphic unit share a grounding pin.

10. The chip according to claim 9, characterized in that, The first basic graphic unit and the second basic graphic unit are translational graphics of each other, and the eighth grounding pin of the first basic graphic unit and the first grounding pin of the second basic graphic unit are shared grounding pins.

11. The chip according to claim 9, characterized in that, The first basic graphic unit and the second basic graphic unit are translational graphics of each other. The twelfth grounding pin of the first basic graphic unit and the fourth grounding pin of the second basic graphic unit are shared grounding pins. The eleventh grounding pin of the first basic graphic unit and the fifth grounding pin of the second basic graphic unit are shared grounding pins.

12. The chip according to claim 9, characterized in that, The first basic graphic unit and the second basic graphic unit are translational graphics of each other. The seventh grounding pin of the first basic graphic unit and the first grounding pin of the second basic graphic unit are shared grounding pins. The eighth grounding pin of the first basic graphic unit and the fourteenth grounding pin of the second basic graphic unit are shared grounding pins.

13. The chip according to claim 9, characterized in that, The first basic graphic unit and the second basic graphic unit are translational graphics of each other. The twelfth grounding pin of the first basic graphic unit and the second grounding pin of the second basic graphic unit share a common grounding pin. The eleventh grounding pin of the first basic graphic unit and the third grounding pin of the second basic graphic unit share a common grounding pin. The tenth grounding pin of the first basic graphic unit and the fourth grounding pin of the second basic graphic unit share a common grounding pin. The ninth grounding pin of the first basic graphic unit and the fifth grounding pin of the second basic graphic unit share a common grounding pin.

14. The chip according to claim 9, characterized in that, The first basic graphic unit and the second basic graphic unit are translational graphics of each other. The eleventh grounding pin of the first basic graphic unit and the first grounding pin of the second basic graphic unit are shared grounding pins. The tenth grounding pin of the first basic graphic unit and the second grounding pin of the second basic graphic unit are shared grounding pins. The ninth grounding pin of the first basic graphic unit and the third grounding pin of the second basic graphic unit are shared grounding pins. The eighth grounding pin of the first basic graphic unit and the fourth grounding pin of the second basic graphic unit are shared grounding pins.

15. The chip according to claim 9, characterized in that, The first basic graphic unit and the second basic graphic unit are translational and rotated graphics of each other. The fifth grounding pin of the first basic graphic unit and the fifth grounding pin of the second basic graphic unit are shared grounding pins. The sixth grounding pin of the first basic graphic unit and the fourth grounding pin of the second basic graphic unit are shared grounding pins. The seventh grounding pin of the first basic graphic unit and the third grounding pin of the second basic graphic unit are shared grounding pins. The eighth grounding pin of the first basic graphic unit and the second grounding pin of the second basic graphic unit are shared grounding pins.

16. The chip according to any one of claims 8 to 15, characterized in that, In the basic graphic unit, the data signal pins adjacent to the two adjacent ground pins and the line connecting the two adjacent ground pins form an equilateral triangle.

17. The chip according to any one of claims 1 to 16, characterized in that, The first pin, the fourth pin, the fifth pin, and the sixth pin are single-ended signal pins, and the second pin and the third pin are a pair of differential signal pins.

18. The chip according to any one of claims 1 to 17, characterized in that, The chip is a central processing unit, which is configured with multiple memory channels. Each memory channel includes multiple byte units, and each byte unit corresponds to two basic graphics units. The data signal pins in the basic graphics units are used to transmit the data signals of the corresponding byte units.

19. An electronic device, characterized in that, The device includes a housing and a circuit board disposed within the housing. A chip is disposed on the circuit board, and the chip is the chip described in claim 1 or 18. The signal pins of the chip are electrically connected to the circuit board.

20. A chip manufacturing method, characterized in that, The chip manufacturing method includes: placing a chip on a packaging substrate and assembling the chip and the packaging substrate to form the chip; wherein the pin area of ​​the packaging substrate is provided with a plurality of pin arrangement pattern units; Among the plurality of pin arrangement graphic units, at least two pin arrangement graphic units are basic graphic units including six signal pins; Among the six signal pins, the first pin, the second pin, the third pin, and the fourth pin are arranged sequentially at intervals in the first direction, and the fifth pin and the sixth pin are arranged at intervals in the second direction, with the fifth pin and the sixth pin located on both sides of the line connecting the second pin and the third pin, respectively. Wherein, the first pin, the fourth pin, the fifth pin, and the sixth pin are data signal pins, and the second pin and the third pin are control signal pins; the first direction is different from the second direction.

21. The chip manufacturing method according to claim 20, characterized in that, The fifth and sixth pins are located on the perpendicular line of the line connecting the second and third pins, and the first direction is perpendicular to the second direction.

22. The chip manufacturing method according to claim 21, characterized in that, The fifth and sixth pins are positioned on the perpendicular bisector of the line connecting the second and third pins. The basic graphic unit is either centrally symmetric or axially symmetric.

23. The chip manufacturing method according to any one of claims 20 to 22, characterized in that, The pins in the pin area are arranged in an array, and the pins in the rows and columns are staggered; the pins in the pin area are arranged in a triangular grid, wherein the line connecting the pin and the two adjacent pins forms an equilateral triangle.

24. The chip manufacturing method according to any one of claims 20 to 23, characterized in that, The basic graphic unit also includes fourteen grounding pins, which are arranged sequentially and at intervals around the six signal pins. In the first direction, the first grounding pin is located next to the first pin, the eighth grounding pin is located next to the fourth pin, and the second, third, fourth, fifth, sixth, and seventh grounding pins are arranged sequentially between the first grounding pin and the eighth grounding pin. The ninth, tenth, eleventh, twelfth, thirteenth, and fourteenth grounding pins are arranged sequentially between the eighth grounding pin and the first grounding pin.

25. The chip manufacturing method according to claim 24, characterized in that, The two basic graphic units are arranged adjacent to each other, one of which is the first basic graphic unit and the other is the second basic graphic unit. The adjacent sides of the first basic graphic unit and the second basic graphic unit share a grounding pin.

26. The chip manufacturing method according to claim 25, characterized in that, The first basic graphic unit and the second basic graphic unit are translational graphics of each other, and the eighth grounding pin of the first basic graphic unit and the first grounding pin of the second basic graphic unit are shared grounding pins.

27. The chip manufacturing method according to claim 25, characterized in that, The first basic graphic unit and the second basic graphic unit are translational graphics of each other. The twelfth grounding pin of the first basic graphic unit and the fourth grounding pin of the second basic graphic unit are shared grounding pins. The eleventh grounding pin of the first basic graphic unit and the fifth grounding pin of the second basic graphic unit are shared grounding pins.

28. The chip manufacturing method according to claim 25, characterized in that, The first basic graphic unit and the second basic graphic unit are translational graphics of each other. The seventh grounding pin of the first basic graphic unit and the first grounding pin of the second basic graphic unit are shared grounding pins. The eighth grounding pin of the first basic graphic unit and the fourteenth grounding pin of the second basic graphic unit are shared grounding pins.

29. The chip manufacturing method according to claim 25, characterized in that, The first basic graphic unit and the second basic graphic unit are translational graphics of each other. The twelfth grounding pin of the first basic graphic unit and the second grounding pin of the second basic graphic unit share a common grounding pin. The eleventh grounding pin of the first basic graphic unit and the third grounding pin of the second basic graphic unit share a common grounding pin. The tenth grounding pin of the first basic graphic unit and the fourth grounding pin of the second basic graphic unit share a common grounding pin. The ninth grounding pin of the first basic graphic unit and the fifth grounding pin of the second basic graphic unit share a common grounding pin.

30. The chip manufacturing method according to claim 25, characterized in that, The first basic graphic unit and the second basic graphic unit are translational graphics of each other. The eleventh grounding pin of the first basic graphic unit and the first grounding pin of the second basic graphic unit are shared grounding pins. The tenth grounding pin of the first basic graphic unit and the second grounding pin of the second basic graphic unit are shared grounding pins. The ninth grounding pin of the first basic graphic unit and the third grounding pin of the second basic graphic unit are shared grounding pins. The eighth grounding pin of the first basic graphic unit and the fourth grounding pin of the second basic graphic unit are shared grounding pins.

31. The chip manufacturing method according to claim 25, characterized in that, The first basic graphic unit and the second basic graphic unit are translational and rotated graphics of each other. The fifth grounding pin of the first basic graphic unit and the fifth grounding pin of the second basic graphic unit are shared grounding pins. The sixth grounding pin of the first basic graphic unit and the fourth grounding pin of the second basic graphic unit are shared grounding pins. The seventh grounding pin of the first basic graphic unit and the third grounding pin of the second basic graphic unit are shared grounding pins. The eighth grounding pin of the first basic graphic unit and the second grounding pin of the second basic graphic unit are shared grounding pins.

32. A signal transmission method, characterized in that, The signal transmission method is applied to a chip, the chip including a packaging substrate, the pin area of ​​the packaging substrate being provided with a plurality of pin arrangement pattern units; among the plurality of pin arrangement pattern units, at least two pin arrangement pattern units are basic pattern units including six signal pins; wherein, the first pin, second pin, third pin, and fourth pin of the six signal pins are arranged sequentially at intervals in a first direction, and the fifth pin and sixth pin of the six signal pins are arranged at intervals in a second direction; the fifth pin and the sixth pin are respectively located on both sides of the line connecting the second pin and the third pin; wherein, the first pin, the fourth pin, the fifth pin, and the sixth pin are data signal pins, and the second pin and the third pin are control signal pins; the first direction is different from the second direction; the method includes the following steps: Data signals are transmitted through the first pin, the fourth pin, the fifth pin, and the sixth pin, and control signals are transmitted through the second pin and the third pin.

33. The signal transmission method according to claim 32, characterized in that, The fifth and sixth pins are located on the perpendicular line of the line connecting the second and third pins, and the first direction is perpendicular to the second direction.

34. The signal transmission method according to claim 33, characterized in that, The fifth and sixth pins are positioned on the perpendicular bisector of the line connecting the second and third pins. The basic graphic unit is either centrally symmetric or axially symmetric.

35. The signal transmission method according to any one of claims 32 to 34, characterized in that, The pins in the pin area are arranged in an array, and the pins in the rows and columns are staggered; the pins in the pin area are arranged in a triangular grid, wherein the line connecting the pin and the two adjacent pins forms an equilateral triangle.

36. The signal transmission method according to any one of claims 32 to 35, characterized in that, The basic graphic unit also includes fourteen grounding pins, which are arranged sequentially and at intervals around the six signal pins. In the first direction, the first grounding pin is located next to the first pin, the eighth grounding pin is located next to the fourth pin, and the second, third, fourth, fifth, sixth, and seventh grounding pins are arranged sequentially between the first grounding pin and the eighth grounding pin. The ninth, tenth, eleventh, twelfth, thirteenth, and fourteenth grounding pins are arranged sequentially between the eighth grounding pin and the first grounding pin.

37. The signal transmission method according to claim 36, characterized in that, The two basic graphic units are arranged adjacent to each other, one of which is the first basic graphic unit and the other is the second basic graphic unit. The adjacent sides of the first basic graphic unit and the second basic graphic unit share a grounding pin.

38. The signal transmission method according to claim 37, characterized in that, The first basic graphic unit and the second basic graphic unit are translational graphics of each other, and the eighth grounding pin of the first basic graphic unit and the first grounding pin of the second basic graphic unit are shared grounding pins.

39. The signal transmission method according to claim 37, characterized in that, The first basic graphic unit and the second basic graphic unit are translational graphics of each other. The twelfth grounding pin of the first basic graphic unit and the fourth grounding pin of the second basic graphic unit are shared grounding pins. The eleventh grounding pin of the first basic graphic unit and the fifth grounding pin of the second basic graphic unit are shared grounding pins.

40. The signal transmission method according to claim 37, characterized in that, The first basic graphic unit and the second basic graphic unit are translational graphics of each other. The seventh grounding pin of the first basic graphic unit and the first grounding pin of the second basic graphic unit are shared grounding pins. The eighth grounding pin of the first basic graphic unit and the fourteenth grounding pin of the second basic graphic unit are shared grounding pins.

41. The signal transmission method according to claim 37, characterized in that, The first basic graphic unit and the second basic graphic unit are translational graphics of each other. The twelfth grounding pin of the first basic graphic unit and the second grounding pin of the second basic graphic unit share a common grounding pin. The eleventh grounding pin of the first basic graphic unit and the third grounding pin of the second basic graphic unit share a common grounding pin. The tenth grounding pin of the first basic graphic unit and the fourth grounding pin of the second basic graphic unit share a common grounding pin. The ninth grounding pin of the first basic graphic unit and the fifth grounding pin of the second basic graphic unit share a common grounding pin.

42. The signal transmission method according to claim 37, characterized in that, The first basic graphic unit and the second basic graphic unit are translational graphics of each other. The eleventh grounding pin of the first basic graphic unit and the first grounding pin of the second basic graphic unit are shared grounding pins. The tenth grounding pin of the first basic graphic unit and the second grounding pin of the second basic graphic unit are shared grounding pins. The ninth grounding pin of the first basic graphic unit and the third grounding pin of the second basic graphic unit are shared grounding pins. The eighth grounding pin of the first basic graphic unit and the fourth grounding pin of the second basic graphic unit are shared grounding pins.

43. The signal transmission method according to claim 37, characterized in that, The first basic graphic unit and the second basic graphic unit are translational and rotated graphics of each other. The fifth grounding pin of the first basic graphic unit and the fifth grounding pin of the second basic graphic unit are shared grounding pins. The sixth grounding pin of the first basic graphic unit and the fourth grounding pin of the second basic graphic unit are shared grounding pins. The seventh grounding pin of the first basic graphic unit and the third grounding pin of the second basic graphic unit are shared grounding pins. The eighth grounding pin of the first basic graphic unit and the second grounding pin of the second basic graphic unit are shared grounding pins.

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