Semiconductor optical amplifier chip with long carrier lifetime

Abstract

The application relates to the technical field of semiconductor optical amplification, and particularly provides a semiconductor optical amplifier chip with long carrier lifetime, which comprises, from bottom to top, a substrate, a lower cladding layer, an N-type carrier confinement layer, an N-type carrier storage layer, a lower waveguide layer, a tunneling lower confinement layer, a lower confinement layer, a source layer, an upper confinement layer, a tunneling upper confinement layer, an upper waveguide layer, a P-type carrier storage layer, a P-type carrier confinement layer, an upper cladding layer and an upper contact layer; the semiconductor material structure is optimized and designed, the stored band structure material layers are respectively limited, the carrier lifetime of the optical amplifier chip is improved, the nonlinear effect of the optical amplifier chip is greatly reduced, the nonlinear characteristics of the SOA are obviously improved, signal distortion is reduced, and therefore better application effects can be achieved in the fields of optical communication and sensing, which will bring higher efficiency, stability and economy to future optical communication technology, and make the SOA become a new generation of optical amplifier technology capable of replacing the EDFA.

Description

Technical Field

[0001] This invention relates to the field of semiconductor optical amplification technology, and more specifically to a semiconductor optical amplification chip with a long carrier lifetime. Background Technology

[0002] Optical amplifiers play a crucial role in applications such as optical fiber communication and optical sensing. Currently, erbium-doped fiber amplifiers (EDFAs) are the most widely used optical amplifiers in optical communication due to their excellent characteristics of high carrier lifetime, low nonlinearity, high saturation power, and low noise. However, with the continuous expansion of future application scenarios, EDFAs also face a series of challenges in some areas, such as high cost, high power consumption, and large size.

[0003] In contrast, semiconductor optical amplifiers (SOAs) are gaining increasing attention and application due to their low power consumption, small size, and low cost. SOAs have shown great potential, especially in space-constrained and energy-sensitive applications. However, SOAs still lag significantly behind EDFAs in performance, particularly in terms of nonlinear characteristics caused by their short carrier lifetime. Specifically, due to the characteristics of their semiconductor PN junctions, SOAs typically have a very short carrier lifetime, generally on the order of 0.1 nanoseconds (ns), while EDFAs have a much longer carrier lifetime, typically on the order of milliseconds (ms). This difference makes SOAs prone to significant optical signal distortion and degradation during optical signal amplification, thus affecting their application in high-performance optical communications.

[0004] The charge carriers in a chip include holes and electrons. Holes and electrons are two types of charge carriers in semiconductors, and there is a close relationship between them. The generation mechanism of holes and electrons is as follows:

[0005] Electrons: In semiconductors, when the temperature rises (e.g., at room temperature) or is affected by external factors such as light, the valence electrons in some covalent bonds will gain enough energy to break free from the covalent bond and jump to the conduction band, becoming free electrons. For example, in pure silicon materials, if pentavalent elements (such as phosphorus, arsenic, or antimony) are added, the excess electrons of these impurity atoms can also easily become free electrons. The resulting semiconductor is called an n-type semiconductor, in which electrons are the majority carriers.

[0006] Holes: When valence electrons transition to the conduction band and become free electrons, they leave an equal number of vacancies in the covalent bonds. These vacancies are called holes. Doping pure silicon with trivalent elements (such as boron, aluminum, or indium) creates a situation where electrons are lacking, thus generating holes. This type of semiconductor is called a p-type semiconductor, and holes are the majority carriers.

[0007] Electrons carry a negative charge, while holes carry a positive charge; their charges are equal. Without an applied electric field, the movement of charge carriers is random and directionless, so no current can be formed. Under an applied electric field, electrons move against the direction of the field, forming an electron current; holes move differently. Because they are positively charged, their movement is opposite to that of electrons, moving along the direction of the electric field. Furthermore, valence electrons in nearby covalent bonds easily jump over to fill holes, causing holes to transfer to nearby covalent bonds. This sequential filling of holes by valence electrons is similar to holes moving along the electric field, forming a hole current. In a pure semiconductor, electrons and holes are constantly generated and recombine. When the temperature rises or external energy excitation occurs, more electron-hole pairs are generated; simultaneously, electrons and holes meet and recombine, reducing their numbers. At a certain temperature, the generation and recombination rates of electrons and holes reach a dynamic equilibrium, at which point the concentration of charge carriers remains relatively stable. The conductivity of a semiconductor depends on the concentration and mobility of charge carriers. In n-type semiconductors, the electron concentration is high, and electrons are the main charge carriers. Therefore, the movement of electrons contributes significantly to the current. In p-type semiconductors, the hole concentration is high, and holes are the main charge carriers. The movement of holes determines the magnitude of the current.

[0008] Therefore, in order to improve the overall performance of SOA, extending its carrier lifetime has become a key research direction. Summary of the Invention

[0009] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a semiconductor optical amplifier chip with a long carrier lifetime, so as to solve the problem of short carrier lifetime in the prior art semiconductor optical amplifiers.

[0010] To achieve the above and other related objectives, the present invention provides a semiconductor optical amplifier chip with a long carrier lifetime, comprising, from bottom to top, the following components:

[0011] N-type doped InP substrate;

[0012] N-type doped InP undercoat;

[0013] N-type doped InGaAsP waveguide layer;

[0014] Undoped InGaAsP confinement layer;

[0015] Undoped InGaAsP active layer;

[0016] Undoped InGaAsP confinement layer;

[0017] P-type doped InGaAsP waveguide layer;

[0018] P-type doped InP cladding;

[0019] P-type doped InGaAsP contact layer;

[0020] The semiconductor optical amplifier chip also includes:

[0021] N-type carrier confinement layer of N-type doped InP-InGaAsP;

[0022] N-type carrier storage layer of N-type doped InGaAsP;

[0023] Undoped InGaAsP tunneling lower confinement layer;

[0024] Undoped InGaAsP tunnels through a confinement layer;

[0025] P-type carrier storage layer of P-type doped InGaAsP;

[0026] P-type doped InGaAsP-InP P-type carrier confinement layer;

[0027] The N-type carrier storage layer is disposed above the N-type carrier confinement layer, and the N-type carrier confinement layer is disposed above the lower cladding layer;

[0028] The tunneling lower confinement layer is located between the lower waveguide layer and the lower confinement layer;

[0029] The tunneling confinement layer is located between the upper confinement layer and the upper waveguide layer;

[0030] The P-type carrier confinement layer is located above the P-type carrier storage layer, and the P-type carrier storage layer is located above the upper waveguide layer.

[0031] In one embodiment of the present invention, the N-type doped impurity is silicon, and the P-type doped impurity is zinc.

[0032] In one embodiment of the present invention, the substrate has a thickness of 400-550 μm and an N-type doping concentration greater than 2E+18cm. -3 ;

[0033] The thickness of the lower cladding layer is 150-230 nm, and its N-type doping concentration is 2E+18 cm⁻¹. -3 ;

[0034] The thickness of the lower waveguide layer is 80-120 nm, and its N-type doping concentration is 5E+17 cm⁻¹. -3 ;

[0035] The thickness of the lower confinement layer is 40-60 nm;

[0036] The thickness of the active layer is 20-35 nm;

[0037] The thickness of the upper confining layer is 40-60 nm;

[0038] The upper waveguide layer has a thickness of 90-110 nm and a P-type doping concentration of 5E+17 cm⁻¹. -3 ;

[0039] The thickness of the upper cladding layer is 1900-2100 nm, and its P-type doping concentration is 1E+18 cm⁻¹. -3 ;

[0040] The thickness of the upper contact layer is 180-210 nm, and its P-type doping concentration is greater than 1E+19 cm⁻¹. -3 .

[0041] In one embodiment of the present invention, the thickness of the N-type carrier confinement layer is 90-110 nm, and its N-type doping concentration is 1E+18 cm⁻¹. -3 ;

[0042] The thickness of the N-type carrier storage layer is 490-510 nm, and its N-type doping concentration is 7E+17 cm⁻¹. -3 ;

[0043] The thickness of the lower confinement layer is 8-12 nm;

[0044] The thickness of the upper confinement layer is 8-12 nm;

[0045] The thickness of the P-type carrier storage layer is 450-520 nm, and its P-type doping concentration is 7E+17 cm⁻¹. -3 ;

[0046] The thickness of the p-type carrier confinement layer is 80-120 nm, and its p-type doping concentration is 1E+18 cm⁻¹. -3 .

[0047] In one embodiment of the present invention, the material structure of the N-type carrier confinement layer is gradually distributed from bottom to top, ranging from InP to InGaAsP.

[0048] In one embodiment of the present invention, the material structure of the P-type carrier confinement layer is gradually distributed from bottom to top from InGaAsP to InP.

[0049] As described above, the semiconductor optical amplifier chip with long carrier lifetime of the present invention has the following beneficial effects:

[0050] 1. This invention optimizes the semiconductor material structure by setting a tunneling upper confinement layer, a tunneling lower confinement layer, a P-type carrier storage layer, a P-type carrier confinement layer, an N-type carrier storage layer, and an N-type carrier confinement layer. These layers confine the stored band structure material layers. The tunneling upper confinement layer, in conjunction with the P-type carrier storage layer and the P-type carrier confinement layer, enables temporary storage of holes, slowing down their recombination time in the active region and thus significantly increasing hole lifetime. Similarly, the tunneling lower confinement layer, in conjunction with the N-type carrier storage layer and the N-type carrier confinement layer, enables temporary storage of electrons, slowing down their recombination time in the active region and thus significantly increasing electron lifetime. This, in turn, extends carrier lifetime, significantly improves the nonlinear characteristics of the SOA, reduces signal distortion, and achieves better application results in optical communication and sensing fields.

[0051] 2. This invention optimizes the semiconductor material structure by restricting the storage band structure material layers, thereby increasing the carrier lifetime of the optical amplifier chip by 10 to 100 times, significantly reducing the nonlinear effects of the optical amplifier chip, and significantly improving the nonlinear characteristics of SOA. While maintaining miniaturization and low cost, it also has high-performance optical signal amplification characteristics, effectively reducing signal distortion, thus achieving better application results in the fields of optical communication and sensing. This will bring higher efficiency, stability and economy to future optical communication technologies, making SOA a new generation of optical amplifier technology that can replace EDFA. Attached Figure Description

[0052] Figure 1 This diagram shows the material structure of a semiconductor optical amplifier chip in the prior art.

[0053] Figure 2 The diagram shows the material structure of the semiconductor optical amplifier chip with long carrier lifetime disclosed in this invention.

[0054] Figure 3 The diagram shows the energy band structure of the active layer P-side material as measured in Example 3.

[0055] Figure 4 The diagram shows the energy band structure of the N-side material of the active layer as measured in Example 3.

[0056] Figure 5 The diagram shown is a cross-sectional schematic of a typical ridge waveguide semiconductor optical amplifier chip disclosed in this invention.

[0057] Figure 6 The diagram shown is a typical cross-sectional schematic of a buried heterojunction semiconductor optical amplifier disclosed in this invention.

[0058] Figure 7The diagram shows the carrier distribution of the semiconductor optical amplifier chip with long carrier lifetime disclosed in this invention in an equilibrium state.

[0059] Figure 8 The diagram shown is a simulation of the effect of the carrier storage layer band width on carrier lifetime as disclosed in Example 4.

[0060] Figure 9 The diagram shown is a simulation of the effect of carrier storage layer thickness on carrier lifetime as disclosed in Example 4.

[0061] Component designation explanation

[0062] Substrate 1; Lower cladding 2; N-type carrier confinement layer 3; N-type carrier storage layer 4; Lower waveguide layer 5; Tunneling lower confinement layer 6; Lower confinement layer 7; Active layer 8; Upper confinement layer 9; Tunneling upper confinement layer 10; Upper waveguide layer 11; P-type carrier storage layer 12; P-type carrier confinement layer 13; Upper cladding 14; Upper contact layer 15. Detailed Implementation

[0063] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0064] Please see Figures 1 to 9 It should be understood that the structures, proportions, sizes, etc., illustrated in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportions, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed in the present invention.

[0065] Example 1, please refer to Figure 2 , Figure 5 , Figure 6 , Figure 7 , Figure 7 The X-axis represents the location of the material layers: 601 is the P-type carrier storage layer, 602 is the active layer, 603 is the N-type carrier storage layer, 604 shows the P-type carrier concentration distribution, and 605 shows the N-type carrier concentration distribution. The Y-axis represents the carrier concentration, in cm³. -3This embodiment provides a semiconductor optical amplifier chip with a long carrier lifetime, comprising, from bottom to top, an N-type doped InP substrate 1, an N-type doped InP lower cladding layer 2, an N-type doped InGaAsP lower waveguide layer 5, an undoped InGaAsP lower confinement layer 7, an undoped InGaAsP active layer 8, an undoped InGaAsP upper confinement layer 9, a P-type doped InGaAsP upper waveguide layer 11, a P-type doped InP upper cladding layer 14, and a P-type doped InGaAsP upper contact layer 15; the semiconductor optical amplifier chip also includes an N-type carrier confinement layer 3 of N-type doped InP-InGaAsP, an N-type carrier storage layer 4 of N-type doped InGaAsP, an undoped InGaAsP tunneling lower confinement layer 6, an undoped InGaAsP tunneling upper confinement layer 10, a P-type doped InGaAsP P-type carrier storage layer 12, and a P-type doped InGaAsP upper contact layer 15. The InGaAsP-InP structure consists of a P-type carrier confinement layer 13; an N-type carrier storage layer 4 is disposed above the N-type carrier confinement layer 3, which is disposed above the lower cladding layer 2. The material structure of the N-type carrier confinement layer 3 gradually changes from InP to InGaAsP from bottom to top; a tunneling lower confinement layer 6 is disposed between the lower waveguide layer 5 and the lower confinement layer 7. On the P-doped side of the active region, i.e., at the upper end of the active region, by setting the tunneling upper confinement layer 10, the P-type carrier storage layer 12, and the P-type carrier confinement layer 13, temporary storage of holes can be achieved, slowing down the time for holes to enter the active region for recombination, thereby significantly increasing the hole lifetime. The P-type carrier storage layer 12 and the P-type carrier confinement layer 13 can play the role of storing holes, and the tunneling upper confinement layer 10 can reduce the probability of holes entering the active region and reduce the probability of electrons escaping from the active region to the P-doped region. The tunneling upper confinement layer 10 is disposed between the upper confinement layer 9 and the upper waveguide layer 11; the P-type carrier confinement layer 13 is disposed above the P-type carrier storage layer 12, and the P-type carrier storage layer 12 is disposed above the upper waveguide layer 11. The material structure of the P-type carrier confinement layer 13 gradually changes from InGaAsP to InP from bottom to top. On the N-doped side of the active region, i.e. the lower end of the active region, by setting the tunneling lower confinement layer 6, the N-type carrier storage layer 4 and the N-type carrier confinement layer 3, temporary storage of electrons can be achieved, slowing down the time for electrons to enter the active region for recombination, thereby greatly increasing the lifetime of electrons. The N-type carrier storage layer 4 and the N-type carrier confinement layer 3 can play the role of storing electrons, and the tunneling upper confinement layer 10 can reduce the probability of electrons entering the active region and reduce the probability of holes escaping from the active region to the N-doped region.

[0066] The substrate 1 has a thickness of 400-550 μm and an N-type doping concentration greater than 2E+18 cm⁻¹. -3 The thickness of the lower cladding layer 2 is 150-230 nm, and its N-type doping concentration is 2E+18 cm⁻¹.-3 The lower waveguide layer 5 has a thickness of 80-120 nm and an N-type doping concentration of 5E+17 cm⁻¹. -3 The thickness of the lower confinement layer 7 is 40-60 nm; the thickness of the active layer 8 is 20-35 nm; the thickness of the upper confinement layer 9 is 40-60 nm; the thickness of the upper waveguide layer 11 is 90-110 nm, and its P-type doping concentration is 5E+17 cm⁻¹. -3 The thickness of the upper cladding layer 14 is 1900-2100 nm, and its P-type doping concentration is 1E+18 cm⁻¹. -3 The upper contact layer 15 has a thickness of 180-210 nm and its P-type doping concentration is greater than 1E+19 cm⁻¹. -3 The thickness of the N-type carrier confinement layer 3 is 90-110 nm, and its N-type doping concentration is 1E+18 cm⁻¹. -3 The thickness of the N-type carrier storage layer 4 is 490-510 nm, and its N-type doping concentration is 7E+17 cm⁻¹. -3 The thickness of the lower confinement layer is 8-12 nm; the thickness of the upper confinement layer is 8-12 nm; the thickness of the P-type carrier storage layer 12 is 450-520 nm, and its P-type doping concentration is 7E+17 cm⁻¹. -3 The p-type carrier confinement layer 13 has a thickness of 80-120 nm and a p-type doping concentration of 1E+18 cm⁻¹. -3 .

[0067] This invention optimizes the semiconductor material structure by incorporating a tunneling upper confinement layer 10, a tunneling lower confinement layer 6, a P-type carrier storage layer 12, a P-type carrier confinement layer 13, an N-type carrier storage layer 4, and an N-type carrier confinement layer 5. These layers confine the stored band structure material layers. The tunneling upper confinement layer 10, in conjunction with the P-type carrier storage layers 12 and 13, enables temporary storage of holes, slowing down their recombination time in the active region and significantly increasing hole lifetime. Similarly, the tunneling lower confinement layer 6, in conjunction with the N-type carrier storage layers 4 and 5, enables temporary storage of electrons, slowing down their recombination time in the active region and significantly increasing electron lifetime. This, in turn, extends carrier lifetime, significantly improves the nonlinear characteristics of the SOA (Optical Signal Amplifier), reduces signal distortion, and thus achieves better application results in optical communication and sensing fields.

[0068] Example 2, based on Example 1, provides a 1.55µm semiconductor optical amplifier chip with a long carrier lifetime. This 1.55µm semiconductor optical amplifier chip is an optical amplification device operating in a 1.55µm wavelength window, mainly used in optical fiber communication systems to amplify optical signals. This chip features high gain, low noise, and a wide spectral response, making it suitable for long-distance, high-capacity optical fiber communication systems. Its material structure is shown in Table 1 below:

[0069]

[0070]

[0071] Table 1

[0072] The substrate 1 has a thickness of 500 μm and an N-type doping concentration greater than 2E+18 cm⁻¹. -3 The thickness of the lower cladding layer 2 is 200 nm, and its N-type doping concentration is 2E+18 cm⁻¹. -3 The lower waveguide layer 5 has a thickness of 100 nm and an N-type doping concentration of 5E+17 cm⁻¹. -3 The thickness of the lower confinement layer is 50 nm; the thickness of the active layer 8 is 30 nm; the thickness of the upper confinement layer is 50 nm; the thickness of the upper waveguide layer 11 is 100 nm, and its P-type doping concentration is 5E+17 cm⁻¹. -3 The upper cladding layer 14 has a thickness of 2000 nm and a P-type doping concentration of 1E+18 cm⁻¹. -3 The upper contact layer 15 has a thickness of 200 nm and its P-type doping concentration is greater than 1E+19 cm⁻¹. -3 The thickness of the N-type carrier confinement layer 3 is 100 nm, and its N-type doping concentration is 1E+18 cm⁻¹. -3 The thickness of the N-type carrier storage layer 4 is 500 nm, and its N-type doping concentration is 7E+17 cm⁻¹. -3 The thickness of the lower confinement layer is 10 nm; the thickness of the upper confinement layer is 10 nm; the thickness of the P-type carrier storage layer 12 is 500 nm, and its P-type doping concentration is 7E+17 cm⁻¹. -3 The p-type carrier confinement layer 13 has a thickness of 100 nm and a p-type doping concentration of 1E+18 cm⁻¹. -3 .

[0073] Example 3, please refer to Figure 3 , Figure 4 , Figure 3 , Figure 4In this diagram, the X-axis represents the position of the material layer, and the Y-axis represents the band width, measured in Eg. This embodiment provides a testing method for testing the band widths of different material layers in the 1.55µm semiconductor optical amplifier chip prepared in Example 2. Specifically, in the multilayer InGaAsP epitaxial structure, the composition and band width of different material layers are analyzed using transmission electron microscopy energy-dispersive spectroscopy (TEM-EDS). The required equipment is as follows:

[0074] (1) Transmission electron microscope (TEM): Used for high-resolution imaging and analysis of the microstructure of multilayer structures. It is recommended to use a transmission electron microscope equipped with high spatial resolution (such as JEOL JEM-2100F).

[0075] (2) Energy dispersive spectroscopy (EDS): Usually integrated with TEM, used to detect the elemental composition of different material layers.

[0076] (3) Sample preparation equipment: including ion milling, focused ion beam (FIB) system, etc., used to prepare thin-layer samples suitable for TEM observation.

[0077] The specific testing steps are as follows:

[0078] (1) Sample preparation

[0079] Ultrathin sections suitable for TEM observation are prepared using mechanical grinding and ion thinning, typically with a thickness of less than 100 nm. For higher resolution, focused ion beam (FIB) can also be used to finely prepare thin-layer samples, ensuring sample integrity and interface quality.

[0080] (2) TEM test preparation

[0081] The thin-film sample is mounted on the TEM sample holder, ensuring that the multilayer structure of the sample is parallel to the electron beam direction to obtain a clear image of the interlayer interfaces. The sample is then placed into the TEM chamber and a vacuum is applied to eliminate interference from impurities.

[0082] (3) TEM imaging

[0083] First, low-magnification imaging is performed to observe the overall layered structure and determine the distribution of different material layers. Gradually, the magnification is increased to high resolution to observe the interfaces between layers at the atomic resolution, thus confirming the sample's layers and thickness.

[0084] (4) EDS point analysis

[0085] The electron beam is focused onto the target layer, and EDS analysis is initiated. The EDS detector detects the elemental composition of each material layer, identifying elements such as In, Ga, As, and P through energy peaks. The chemical composition of each layer is analyzed layer by layer, recording the content of In, Ga, As, and P in each layer, and calculating their component ratios.

[0086] (5) Bandwidth analysis

[0087] Based on the chemical composition analysis results from EDS, the band width of each layer was calculated using physical formulas and models (such as the relationship between band width and composition in the material). Electron energy loss spectroscopy (EELS) was then used to further obtain local band structure information to verify the accuracy of the EDS analysis results.

[0088] (6) Data Processing and Analysis

[0089] Based on the elemental content measured by EDS, the distribution maps of In, Ga, As, and P in different layers were analyzed and plotted, thereby calculating the band width of InGaAsP in each layer, and the results were calibrated in conjunction with EELS data.

[0090] As can be seen from this embodiment, the 1.55µm semiconductor optical amplifier chip prepared by the present invention can significantly reduce the nonlinear effect of optical amplifier chips compared with traditional chips.

[0091] Example 4, please refer to Figure 8 , Figure 9 , Figure 8 The X-axis represents the carrier storage layer band width in eV, the Y-axis represents the carrier lifetime in ns, and a represents the carrier lifetime curve. Figure 9 In the figure, the X-axis represents the carrier storage layer thickness in nm, the Y-axis represents the carrier lifetime in ns, and 'a' represents the carrier lifetime curve. This embodiment provides a simulation method to test the influence of the carrier storage layer bandwidth on the carrier lifetime of the 1.55µm semiconductor optical amplifier chip prepared in Example 2, as well as the influence of the carrier storage layer thickness on the carrier lifetime. The simulation method is as follows:

[0092] 1) Based on the known doping concentration and band gap information of InGaAsP material, a material model is established using the k·p model. The concentrations of electrons and holes are then calculated according to the doping type (n-type or p-type) and doping concentration.

[0093] 2) Use Matlab numerical simulation software to write custom code, set up a physical model, and set up a solver that includes the drift-diffusion equation, Poisson equation, and recombination rate equation.

[0094] 3) Set boundary conditions based on the physical structure of the device, including injection current density and temperature. Initial conditions typically include the initial carrier concentration and the light injection intensity of the optical amplifier.

[0095] 4) Run numerical simulations to calculate the recombination rate under different carrier concentrations. Combine the carrier concentrations output by the simulation to calculate the spontaneous recombination coefficient. Then, based on the spontaneous recombination coefficient and the carrier concentration, obtain the carrier lifetime τ = 1 / (B×n), where B is the spontaneous recombination coefficient and n is the carrier concentration.

[0096] As can be seen from this embodiment, the 1.55um semiconductor optical amplifier chip prepared by the present invention can improve the carrier lifetime of optical amplifier chips by 10 times to 100 times compared with traditional chips.

[0097] In summary, this invention optimizes the semiconductor material structure by restricting the storage band structure material layers, thereby increasing the carrier lifetime of the optical amplifier chip by 10 to 100 times, significantly reducing the nonlinear effects of the optical amplifier chip, and substantially improving the nonlinear characteristics of the SOA. While maintaining miniaturization and low cost, it also possesses high-performance optical signal amplification characteristics and effectively reduces signal distortion, thus achieving better application results in optical communication and sensing fields. This will bring higher efficiency, stability, and economy to future optical communication technologies, making SOA a next-generation optical amplifier technology capable of replacing EDFA. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0098] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A semiconductor optical amplifier chip with a long carrier lifetime, comprising, from bottom to top, the following components arranged sequentially: N-type doped InP substrate; N-type doped InP undercoat; N-type doped InGaAsP waveguide layer; Undoped InGaAsP confinement layer; Undoped InGaAsP active layer; Undoped InGaAsP confinement layer; P-type doped InGaAsP waveguide layer; P-type doped InP cladding; P-type doped InGaAsP contact layer; The semiconductor optical amplifier chip is characterized in that it further includes: N-type carrier confinement layer of N-type doped InP-InGaAsP; N-type carrier storage layer of N-type doped InGaAsP; Undoped InGaAsP tunneling lower confinement layer; Undoped InGaAsP tunnels through a confinement layer; P-type carrier storage layer of P-type doped InGaAsP; P-type doped InGaAsP-InP P-type carrier confinement layer; The N-type carrier storage layer is disposed above the N-type carrier confinement layer, and the N-type carrier confinement layer is disposed above the lower cladding layer; The tunneling lower confinement layer is located between the lower waveguide layer and the lower confinement layer; The tunneling confinement layer is located between the upper confinement layer and the upper waveguide layer; The P-type carrier confinement layer is disposed above the P-type carrier storage layer, and the P-type carrier storage layer is disposed above the upper waveguide layer; The thickness of the N-type carrier confinement layer is 90-110 nm, and its N-type doping concentration is 1E+18 cm⁻¹. -3 ; The thickness of the N-type carrier storage layer is 490-510 nm, and its N-type doping concentration is 7E+17 cm⁻¹. -3 ; The thickness of the tunneling lower confinement layer is 8-12 nm; The thickness of the tunneling confinement layer is 8-12 nm; The thickness of the P-type carrier storage layer is 450-520 nm, and its P-type doping concentration is 7E+17 cm⁻¹. -3 ; The thickness of the p-type carrier confinement layer is 80-120 nm, and its p-type doping concentration is 1E+18 cm⁻¹. -3 ; The material structure of the N-type carrier confinement layer is gradually distributed from bottom to top, ranging from InP to InGaAsP. The material structure of the P-type carrier confinement layer is gradually distributed from bottom to top, from InGaAsP to InP.

2. The semiconductor optical amplifier chip with long carrier lifetime according to claim 1, characterized in that: The N-type doped impurity is silicon, and the P-type doped impurity is zinc.

3. The semiconductor optical amplifier chip with long carrier lifetime according to claim 2, characterized in that: The substrate has a thickness of 400-550 μm and an N-type doping concentration greater than 2E+18 cm⁻¹. -3 ; The thickness of the lower cladding layer is 150-230 nm, and its N-type doping concentration is 2E+18 cm⁻¹. -3 ; The thickness of the lower waveguide layer is 80-120 nm, and its N-type doping concentration is 5E+17 cm⁻¹. -3 ; The thickness of the lower confinement layer is 40-60 nm; The thickness of the active layer is 20-35 nm; The thickness of the upper confining layer is 40-60 nm; The upper waveguide layer has a thickness of 90-110 nm and a P-type doping concentration of 5E+17 cm⁻¹. -3 ; The thickness of the upper cladding layer is 1900-2100 nm, and its P-type doping concentration is 1E+18 cm⁻¹. -3 ; The thickness of the upper contact layer is 180-210 nm, and its P-type doping concentration is greater than 1E+19 cm⁻¹. -3 .

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