Integrated power conversion topology circuit based on apfc and ahh

Abstract

The application relates to the field of power electronics, in particular to an integrated power conversion topology circuit based on APFC and AHB. The power conversion topology circuit comprises an alternating current source AC1 which is rectified into a sine half-wave voltage through a bridge rectifier BR1 and a filter capacitor C1; an energy storage inductor L1 which is connected with a second switch tube Q2 in series, and the energy storage inductor L1 is charged and stored energy through a first diode D1 when the second switch tube Q2 is turned on; a first switch tube Q1 which is connected with an output filter capacitor C2 in series and parallel into a loop, and zero voltage switching is realized by setting a dead time. The application integrates the APFC active power factor correction function and the AHB asymmetric half-bridge soft switching topology in one circuit, significantly simplifies the circuit structure, reduces the number of components, and greatly reduces the cost of the power converter.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, specifically to an integrated power conversion topology circuit based on APFC and AHB. Background Technology

[0002] In recent years, the field of power electronics has developed rapidly. Various advanced soft-switching power converter topologies have gradually replaced traditional hard-switching topologies, enabling power converters to have higher power density and conversion efficiency. However, in order to reduce harmonic pollution to the power grid and increase the grid's energy utilization rate, active power factor correction (APFC) circuits are needed to address these issues.

[0003] Therefore, many high-power power converters typically combine active power factor correction (PFC) circuits with soft-switching topologies to meet the precise power requirements of various electrical devices. However, this combination undoubtedly leads to higher costs and increased circuit complexity. In the context of increasingly fierce global industrialization and commercial competition, there is an urgent need to resolve the contradiction between achieving efficient PFC and soft-switching conversion while simultaneously reducing power converter costs. Summary of the Invention

[0004] This invention provides an integrated power conversion topology circuit based on APFC and AHB to solve the technical problem of how to reduce the cost of power converter while achieving PFC power factor correction and high-efficiency soft-switching conversion.

[0005] The technical solution of the present invention to solve the above-mentioned technical problems is as follows:

[0006] An integrated power conversion topology based on APFC and AHB is provided, the power conversion topology comprising:

[0007] The AC source (AC1) is rectified into a sinusoidal half-wave voltage through a bridge rectifier (BR1) and a filter capacitor (C1);

[0008] An energy storage inductor (L1) is connected in series with a second switch (Q2). When the second switch (Q2) is turned on, the energy storage inductor (L1) is charged and stored through a first diode (D1).

[0009] The first switching transistor (Q1) is connected in series with the output filter capacitor (C2) and then connected to the circuit. Zero voltage switching is achieved by setting the dead time.

[0010] The transformer (T1) has its primary winding (NP) coupled to the output filter capacitor (C2) through a coupling capacitor (C3). The secondary winding (NS) of the transformer (T1) is rectified and filtered by a second diode (D2) and the output filter capacitor (C4) to generate the output voltage (VOUT).

[0011] And a third diode (D3), which is connected in parallel with the filter capacitor (C1) through the energy storage inductor (L1), is used to clamp the reverse voltage at -1V to ensure circuit stability.

[0012] Furthermore, the operation of the power conversion topology circuit includes a first switching cycle and a second switching cycle;

[0013] The steps of the first switching cycle include:

[0014] When the second switch (Q2) is turned on, the first diode (D1) charges the energy storage inductor (L1) to store energy.

[0015] When the second switch (Q2) is turned off, the induced voltage of the energy storage inductor (L1) is superimposed on the voltage on the filter capacitor (C1), and the output filter capacitor (C2) is charged and stored through the first diode (D1) and the first switch (Q1).

[0016] The first switch (Q1) is turned on after the dead time to reduce circuit loss;

[0017] The steps of the second switching cycle include:

[0018] The first switch (Q1) is turned off, and the second switch (Q2) is turned on after a dead time, repeating the energy storage process of the energy storage inductor (L1). At the same time, the primary winding (NP) is coupled to the voltage stored on the output filter capacitor (C2) through the coupling capacitor (C3) for energy storage.

[0019] When the second switch (Q2) is turned off, the energy storage inductor (L1) and the primary winding (NP) are out of phase, and the first switch (Q1) is turned on with zero voltage.

[0020] The energy storage inductor (L1) repeatedly charges and stores energy in the output filter capacitor (C2), and the primary winding (NP) and leakage inductance are clamped and magnetically reset by the coupling capacitor (C3).

[0021] The energy stored in the transformer (T1) is coupled through the secondary winding (NS), and after rectification and filtering by the second diode (D2) and the output filter capacitor (C4), the output voltage (VOUT) is output.

[0022] After the energy is released, the first switch (Q1) is turned off, the primary winding (NP) is reversed, and the second switch (Q2) is turned on with zero voltage.

[0023] Furthermore, the turn-on and turn-off processes of the first switch (Q1) and the second switch (Q2) are precisely controlled by the dead time to achieve zero-voltage switching (ZVS);

[0024] The drain of the first switching transistor (Q1) is connected to the positive terminal of the output filter capacitor (C2), and the negative terminal of the filter capacitor (C2) is grounded; the source of the second switching transistor (Q2) is grounded, and its drain is connected to the source of the first switching transistor (Q1).

[0025] The first switch (Q1) and the second switch (Q2) are turned on and off by complementary PWM control signals;

[0026] Dead time is set between the first switch (Q1) being turned off and the second switch (Q2) being turned on, and between the second switch (Q2) being turned off and the first switch (Q1) being turned on, respectively, so that the switch can be turned on in a state of zero voltage or near zero voltage.

[0027] Furthermore, by adjusting the on-time ratio of the first switch (Q1) and the second switch (Q2), an asymmetric half-bridge (AHB) can be implemented.

[0028] The conduction time of the first switch (Q1) accounts for 99%-40% of the total switching cycle, and the conduction time of the second switch (Q2) accounts for 1%-60% of the total switching cycle.

[0029] By controlling the charging and discharging process of the energy storage inductor (L1), a sinusoidal waveform of the input current is achieved by utilizing the inductor in discontinuous mode with equal conduction time, which is used for active power factor correction (APFC).

[0030] One end of the energy storage inductor (L1) is connected to the positive terminal of the bridge rectifier (BR1), and the other end is connected to the anode of the first diode (D1).

[0031] Furthermore, the voltage waveform between the primary winding (NP) and the secondary winding (NS) is adjusted by the coupling capacitor (C3), and the capacitance value C3 is determined as follows:

[0032] Where ω is the angular frequency of the switching frequency, and L T This is the leakage inductance value of the transformer.

[0033] Furthermore, the power conversion topology circuit also includes a control algorithm for adjusting the duty cycle of the PWM control signal according to load changes;

[0034] The control algorithm includes the following steps:

[0035] Detect the output voltage (VOUT) and output current (IOUT);

[0036] Calculate the current output power: POUT = VOUT × IOUT;

[0037] Based on the current output power, the optimal duty cycle D is determined using a lookup table or interpolation method. opt ;

[0038] Calculate the deviation between the current duty cycle and the optimal duty cycle: ΔD = D current -D opt ;

[0039] Calculate the duty cycle adjustment using a PI controller:

[0040] ΔD adj =K p ·ΔD+K i ·∫ΔDdt, where K p K is the proportionality coefficient. i The integral coefficient;

[0041] Update the duty cycle of the PWM control signal: D new =D current +ΔD adj ;

[0042] The updated duty cycle is limited to within the effective range;

[0043] Apply the updated duty cycle to the PWM controller;

[0044] The above process is repeated periodically;

[0045] The power conversion topology circuit also includes:

[0046] An overcurrent protection mechanism is in place. When the output current (IOUT) is detected to exceed a preset threshold, the first switch (Q1) and the second switch (Q2) are immediately turned off, and then restarted after a delay.

[0047] The soft-start mechanism means that when the power is on, the duty cycle of the PWM control signal starts from 0 and gradually increases to the normal operating value according to a preset slope, so as to avoid the large current surge at the moment of startup.

[0048] Furthermore, the power conversion topology circuit also includes an output voltage feedback control loop for adjusting the output voltage (VOUT) by adjusting the duty cycle of the PWM control signal;

[0049] The control loop includes:

[0050] The voltage sampling circuit uses a voltage divider resistor network to sample the output voltage (VOUT);

[0051] The error amplifier compares the sampled voltage with the reference voltage and outputs an error signal.

[0052] The PWM comparator compares the error signal with the triangular wave to generate the PWM control signal;

[0053] The driving circuit converts the PWM control signal into the level and timing of driving the first switch (Q1) and the second switch (Q2).

[0054] Furthermore, the position change method of the coupling capacitor (C3) is as follows:

[0055] The first end of the coupling capacitor (C3) is connected to the positive terminal of the output filter capacitor (C2), and the second end of the coupling capacitor (C3) is connected to the first end of the primary winding (NP).

[0056] Furthermore, the power conversion topology circuit also includes a reverse polarity connection, wherein the reverse polarity connection is configured as follows:

[0057] The output terminal 3 of the bridge rectifier (BR1) serves as the first connection point, and the output terminal 4 serves as the second connection point. The first terminal of the filter capacitor (C1), the anode of the third diode (D3), the drain of the first switching transistor (Q1), the positive terminal of the output filter capacitor (C2), and the first terminal of the primary winding (NP) are all connected to the first connection point. The second terminal of the filter capacitor (C1) and the first terminal of the energy storage inductor (L1) are both connected to the second connection point. The second terminal of the energy storage inductor (L1) serves as the third connection point. The cathodes of the first diode (D1) and the third diode (D3) are both connected to the third connection point; the anode of the first diode (D1) serves as the fourth connection point, and the source of the first switching transistor (Q1), the drain of the second switching transistor (Q2), and the first terminal of the coupling capacitor (C3) are all connected to the fourth connection point, while the second terminal of the coupling capacitor (C3) is connected to the second terminal of the primary winding (NP); the source of the second switching transistor (Q2) and the negative terminal of the output filter capacitor (C2) are both grounded.

[0058] Furthermore, the power conversion topology circuit also includes a reverse polarity connection and a changed position of the coupling capacitor (C3), wherein the changed position is as follows:

[0059] The first terminal of the coupling capacitor (C3) is connected to the negative terminal of the output filter capacitor (C2), and the second terminal of the coupling capacitor (C3) is connected to the first terminal of the primary winding (NP).

[0060] The beneficial effects of this invention are:

[0061] This invention integrates the APFC active power factor correction function with the AHB asymmetric half-bridge soft-switching topology into a single circuit, significantly simplifying the circuit structure, reducing the number of components, and thus substantially lowering the cost of the power converter. By using a single PWM control signal to control two switching transistors, ZVS (zero-voltage switching) is achieved, improving power conversion efficiency and reducing switching losses and electromagnetic interference.

[0062] Furthermore, by precisely controlling the dead time and the on-time ratio of the switching transistors, this invention achieves both the active power factor correction (APFC) function and ensures the efficient operation of the AHB asymmetric half-bridge soft-switching topology, solving the problem of the difficulty in simultaneously achieving APFC and soft-switching in traditional circuits. The circuit structure of this invention is simple, highly reliable, easy to manufacture, and suitable for industrial production. At the same time, the use of a single control signal simplifies EMI filtering design and further reduces costs.

[0063] In addition, the present invention provides a variety of circuit variations, such as C3 position change, reverse polarity connection, and reverse polarity connection with C3 position change, which increases the flexibility of circuit design and can adapt to the needs of different scenarios. Attached Figure Description

[0064] Figure 1 This is a power conversion topology circuit diagram in one embodiment of the present invention;

[0065] Figure 2 This is a simulation diagram of a power conversion topology circuit in one embodiment of the present invention;

[0066] Figure 3 This is a diagram illustrating the effect of APFC active power factor correction function in one embodiment of the present invention.

[0067] Figure 4 This is a diagram illustrating the ZVS implementation effect of the switching transistor in one embodiment of the present invention;

[0068] Figure 5 This is a power conversion topology circuit diagram with varying position of coupling capacitor C3 in one embodiment of the present invention;

[0069] Figure 6This is a power conversion topology circuit diagram with reverse polarity connection in one embodiment of the present invention;

[0070] Figure 7 This is a power conversion topology circuit diagram with reverse polarity connection and changing position of coupling capacitor C3 in one embodiment of the present invention. Detailed Implementation

[0071] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0072] The term "comprising," and any variations thereof, used in the specification and claims of this application, is intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those explicitly listed, but may include other steps or units not explicitly listed or inherent to such process, method, product, or apparatus. Furthermore, the use of "and / or" in the specification and claims indicates at least one of the connected objects, such as A and / or B, indicating the inclusion of A alone, B alone, or both A and B.

[0073] In embodiments of the present invention, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design described as "exemplary" or "for example" in embodiments of the present invention should not be construed as being more preferred or advantageous than other embodiments or designs. Rather, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0074] The present invention provides the following preferred embodiments:

[0075] Example 1

[0076] To address the high cost issue caused by the separation of APFC and soft-switching topologies in traditional power converters, this embodiment provides an integrated power conversion topology circuit based on APFC and AHB. This integrated power conversion topology circuit integrates APFC functionality and AHB soft-switching topology, achieving both circuit simplification and cost reduction.

[0077] like Figures 1 to 4 As shown, the power conversion topology circuit includes:

[0078] AC source AC1 is rectified into a sinusoidal half-wave voltage through bridge rectifier BR1 and filter capacitor C1;

[0079] The energy storage inductor L1 is connected in series with the second switch Q2. When the second switch Q2 is turned on, the energy storage inductor L1 is charged and stored through the first diode D1.

[0080] The first switching transistor Q1 is connected in series with the output filter capacitor C2 and then connected in parallel in the circuit. Zero voltage switching is achieved by setting the dead time.

[0081] Transformer T1 has its primary winding NP coupled to the output filter capacitor C2 via coupling capacitor C3. The secondary winding NS of transformer T1 is rectified and filtered by the second diode D2 and the output filter capacitor C4 to generate the output voltage VOUT.

[0082] The third diode, D3, is connected in parallel with the filter capacitor C1 through the energy storage inductor L1 to clamp the reverse voltage at -1V to ensure circuit stability.

[0083] Specifically, AC source AC1 is rectified into a sinusoidal half-wave voltage through bridge rectifier BR1 and filter capacitor C1. This process is the first step of power conversion, providing the foundation for subsequent APFC functions. It is important to understand that the capacitance value of filter capacitor C1 can be optimized based on parameters such as input voltage and power.

[0084] Furthermore, the energy storage inductor L1 is connected in series with the second switch Q2. When the second switch Q2 is turned on, the energy storage inductor L1 is charged and stored through the first diode D1. This design realizes the functional part of APFC, such as... Figure 3 As shown, the 4-channel waveform is the input current waveform. The current envelope is sinusoidal and in phase with the voltage waveform of the input AC source (channel 1), which proves that the APFC active power factor correction function is realized. By controlling the charging and discharging process of the energy storage inductor, the input current waveform can be made approximately sinusoidal, thereby improving the power factor.

[0085] Furthermore, the first switching transistor Q1 is connected in series with the output filter capacitor C2 and then connected in parallel in the circuit. By setting an appropriate dead time, the first switching transistor Q1 can achieve zero-voltage switching (ZVS), such as... Figure 4 As shown, channel 3 displays the DS waveform of the lower half-bridge switch, and channel 2 shows the drive waveform of that switch, confirming that the switch conducts at zero voltage, thus achieving ZVS (Zero Voltage Switching). It is understandable that ZVS technology can significantly reduce switching losses and improve power conversion efficiency.

[0086] Furthermore, the primary winding NP of transformer T1 is coupled to the output filter capacitor C2 via coupling capacitor C3. The secondary winding NS of transformer T1 is rectified and filtered via the second diode D2 and the output filter capacitor C4, ultimately generating a stable output voltage VOUT. This design achieves voltage isolation and transformation, while the introduction of coupling capacitor C3 helps optimize energy transfer efficiency.

[0087] Furthermore, the third diode D3 is connected in parallel with the filter capacitor C1 through the energy storage inductor L1. Its main function is to clamp the reverse voltage at approximately -1V to ensure stable circuit operation. This design effectively prevents potential damage to circuit components from reverse voltage spikes.

[0088] The benefits of this embodiment are that by integrating the APFC function with the AHB soft-switching topology into a single circuit, the circuit structure is significantly simplified, the number of components is reduced, and thus the cost of the power converter is lowered. Simultaneously, the application of ZVS technology improves power efficiency and reduces electromagnetic interference. Furthermore, the use of a single PWM control signal simplifies the control strategy and EMI filtering design.

[0089] Example 2

[0090] To address the issues of complex circuit structure and high cost in traditional APFC and AHB power converters, this embodiment further refines the working process of the integrated power conversion topology circuit based on APFC and AHB, making it more efficient and stable.

[0091] In this embodiment, the circuit operation is divided into two switching cycles, each handling different charging and storage tasks. During the first switching cycle, the second switch Q2 is turned on, and the first diode D1 charges and stores energy through the energy storage inductor L1. When the second switch Q2 is turned off, the induced voltage of the energy storage inductor L1, superimposed on the voltage across the filter capacitor C1, charges and stores energy in the output filter capacitor C2 through the first diode D1 and the body diode of the first switch Q1. Subsequently, the first switch Q1 is turned on, achieving zero-voltage switching (ZVS) and further reducing loop losses. This process utilizes the interaction between inductors and capacitors to precisely control the transfer and storage of electrical energy.

[0092] It's important to understand that the second switching cycle begins after the first switching cycle ends. When the first switch Q1 is turned off, the second switch Q2 turns on after a dead time, repeating the energy storage process of the energy storage inductor L1 in the first switching cycle. Simultaneously, the primary winding NP of transformer T1 stores energy through the voltage stored on the output filter capacitor C2 via coupling capacitor C3. After energy storage is complete, the second switch Q2 turns off, and the energy storage inductor L1 and the primary winding NP of transformer T1 are out of phase, causing the body diode of the first switch Q1Q1 to conduct. The first switch Q1Q1 then again achieves zero-voltage switching (ZVS) after a dead time. This process not only repeats the charging and energy storage of the output filter capacitor C2 but also utilizes the characteristics of the primary winding and leakage inductance of transformer T1, clamping and magnetically resetting through coupling capacitor C3, enabling efficient energy transfer.

[0093] It is important to understand that the energy stored in transformer T1 is coupled through the secondary winding NS, and after rectification and filtering by the second diode D2 and the output filter capacitor C4, a stable DC output voltage VOUT is generated. The capacitance range of these filter capacitors needs to be considered in light of the power requirements in the actual application and optimized to ensure a smooth and stable output voltage.

[0094] Understandably, by precisely setting the dead time, the first switch Q1 and the second switch Q2 can achieve zero-voltage conduction after being turned off. This design significantly reduces switching losses and improves power conversion efficiency. Simultaneously, the dead time control of the second switch Q2 not only allows it to repeat the energy storage process in the first switching cycle, but also enables the primary winding of transformer T1 and its leakage inductance to achieve better magnetic reset during operation, ensuring efficient and stable energy transfer.

[0095] Furthermore, this embodiment optimizes the dead time setting to adapt to current variations under different operating conditions. Specifically, when the first switch Q1 is turned off, the primary winding of transformer T1 reverses phase, causing the body diode of the second switch Q2 to conduct. After the dead time, the second switch Q2 can also achieve zero-voltage conduction. This process repeats continuously, realizing the integrated power conversion of APFC and AHB, and achieving the full ZVS soft-switching process of the switching transistors.

[0096] The advantage of this embodiment lies in achieving efficient power factor correction (APFC) and asymmetric half-bridge AHB power conversion through a precise switching control strategy. The extensive application of ZVS soft-switching technology further improves power conversion efficiency, reduces operating temperature and electromagnetic interference, and enhances the overall performance of the power converter. Simultaneously, the precise control of dead time and switching transistors in the circuit enables this embodiment to provide efficient, stable, and reliable power conversion solutions in various application scenarios.

[0097] Example 3

[0098] To address the issues of high switching losses and low conversion efficiency in traditional power converters, this embodiment further optimizes the switching control strategy and circuit connection method in the integrated power conversion topology circuit based on APFC and AHB, achieving high-efficiency zero-voltage switching (ZVS) operation.

[0099] In this embodiment, a precise dead-time control method is used to achieve zero-voltage switching between the first switch Q1 and the second switch Q2. This control strategy can significantly reduce switching losses and improve power conversion efficiency. It is important to understand that the dead-time setting needs to consider factors such as the characteristics of the switching transistors, circuit parameters, and load conditions. In practical applications, the optimal dead-time can be determined through experimental testing or simulation analysis to achieve the best ZVS effect.

[0100] Furthermore, this embodiment optimizes the connection method of the switching transistors. The drain of the first switching transistor Q1 is connected to the positive terminal of the output filter capacitor C2, and the negative terminal of the filter capacitor C2 is grounded; the source of the second switching transistor Q2 is grounded, and its drain is connected to the source of the first switching transistor Q1. This connection method allows the first switching transistor Q1 to effectively control the charging and discharging process of the output filter capacitor C2. Simultaneously, the source of the second switching transistor Q2 is connected to the negative terminal of the filter capacitor C1, and its drain is connected to one end of the energy storage inductor L1. This connection method allows the second switching transistor Q2 to precisely control the charging and discharging process of the energy storage inductor L1, thereby achieving effective power factor correction.

[0101] Furthermore, this embodiment controls the on / off state of the first switch Q1 and the second switch Q2 using complementary PWM control signals. The rising edge of the PWM control signal triggers the first switch Q1 to turn on, and the falling edge triggers the second switch Q2 to turn on. This control method simplifies the control circuit, reduces control complexity, and also reduces potential control signal interference. It is understood that the frequency and duty cycle of the PWM control signal can be adjusted according to actual application requirements to achieve optimal power conversion performance.

[0102] Furthermore, in this embodiment, dead times are set between the turn-off of the first switch Q1 and the turn-on of the second switch Q2, and between the turn-off of the second switch Q2 and the turn-on of the first switch Q1. These dead times allow the switches to conduct at or near-zero voltage, thereby significantly reducing switching losses and improving conversion efficiency. It is important to note that the dead time setting requires a trade-off between switching losses and conduction losses. An excessively long dead time may increase conduction losses, while an excessively short dead time may not achieve effective zero-voltage switching (ZVS).

[0103] Furthermore, the control circuit in this embodiment can be implemented using a digital controller or an analog controller. Digital controllers, such as DSPs or FPGAs, can provide more flexible control strategies and more precise dead-time adjustment, while analog controllers may have lower costs and faster response times. The choice of controller needs to be determined based on the specific application scenario and performance requirements.

[0104] Furthermore, to improve the reliability of ZVS, this embodiment can add an auxiliary inductor or capacitor network to the circuit. These auxiliary components can help create more ideal switching conditions, ensuring effective ZVS operation under various load conditions. Simultaneously, an adaptive dead-time control algorithm can be considered to dynamically adjust the dead time based on real-time detected circuit parameters to adapt to the optimal ZVS conditions under different operating states.

[0105] The advantage of this embodiment lies in achieving efficient zero-voltage switching operation through precise control of dead time and optimized switching transistor connections. The use of a single PWM control signal simplifies the control circuitry and improves system reliability. This design not only reduces switching losses and improves power conversion efficiency but also reduces electromagnetic interference (EMI), enhancing the overall performance of the power converter.

[0106] Example 4

[0107] To address the challenge of efficiently integrating asymmetric half-bridge (AHB) and active power factor correction (APFC) functions in traditional power converters, this embodiment further optimizes the control strategy and circuit design of the integrated power conversion topology based on APFC and AHB, thereby achieving a more efficient and flexible power conversion solution.

[0108] Furthermore, this embodiment achieves the asymmetric half-bridge AHB function by precisely adjusting the on-time ratio of the first switch Q1 and the second switch Q2. Specifically, the on-time of the first switch Q1 accounts for 99%-40% of the total switching cycle, while the on-time of the second switch Q2 accounts for 1%-60% of the total switching cycle. This asymmetric control strategy can effectively expand the operating range of the transformer and improve the adaptability of the power converter under different input voltage and load conditions. It should be understood that the specific selection of the on-time ratio needs to be optimized based on factors such as the actual application scenario, input voltage range, and load characteristics. In practical applications, the on-time ratio can be dynamically adjusted to adapt to different operating conditions, thereby achieving the best conversion efficiency.

[0109] Furthermore, this embodiment achieves active power factor correction (APFC) by precisely controlling the charging and discharging process of the energy storage inductor L1 and utilizing the inductor in discontinuous mode with equal conduction time. One end of the energy storage inductor L1 is connected to the positive terminal of the bridge rectifier BR1, and the other end is connected to the drain of the second switch Q2 and the anode of the first diode D1. This connection allows the energy storage inductor L1 to store energy when the second switch Q2 is on and release the energy to the output terminal when the second switch Q2 is off, thereby achieving continuous conduction mode (CCM) of the input current. It is understood that the inductance value of the energy storage inductor L1 has a direct impact on APFC performance. The selection of the inductance value needs to comprehensively consider factors such as the input voltage range, output power, switching frequency, and desired current ripple.

[0110] Furthermore, to optimize the design of the energy storage inductor L1, the following formula can be used for preliminary calculations:

[0111]

[0112] Among them, V in_min Where is the minimum input voltage, D is the maximum duty cycle, and f is the minimum input voltage. s P is the switching frequency. in For input power, ΔI L The percentage represents the desired current ripple. The inductance value calculated using this formula can serve as a starting point for the design, which can then be further optimized through simulation and experimentation. In practical applications, materials such as magnetic powder cores or iron-silicon-aluminum cores can be selected to fabricate the energy storage inductor L1 to obtain good high-frequency characteristics and low losses.

[0113] Furthermore, the control circuit in this embodiment can employ a digital controller such as a DSP or MCU to implement complex control algorithms. The controller can monitor the input voltage, output voltage, and current in real time, and dynamically adjust the on-time ratio of the first switch Q1 and the second switch Q2 based on these parameters, as well as optimize the APFC control strategy. In addition, the controller can also implement safety functions such as soft start, overvoltage protection, and overcurrent protection, improving the reliability of the power converter.

[0114] Furthermore, to improve the performance of APFC, this embodiment can introduce feedforward compensation and current predictive control into the control algorithm. Feedforward compensation can quickly adjust control parameters based on changes in input voltage, improving the system's dynamic response. Current predictive control can predict the current value for the next switching cycle based on the current circuit state, thereby achieving more precise current control and reducing current distortion. This advanced control strategy can reduce the total harmonic distortion (THD) of the input current to below 5% and improve the power factor to above 0.99.

[0115] Furthermore, this embodiment can also consider adding an auxiliary winding in the circuit to provide power to the control circuit, achieving bootstrap power supply. This design can simplify the power supply system and improve overall efficiency. Simultaneously, the auxiliary winding can also be used to achieve synchronous rectification, further improving conversion efficiency. In practical applications, suitable synchronous rectification MOSFETs can be selected, such as devices with low on-resistance and fast switching characteristics, to maximize the effect of synchronous rectification.

[0116] The advantage of this embodiment lies in achieving efficient integration of APFC and AHB functions through optimized asymmetric half-bridge control strategy and energy storage inductor design. This design not only improves the power factor of the power converter and reduces input current harmonics, but also expands the operating range of the transformer, improving system adaptability and efficiency. Simultaneously, this embodiment offers strong flexibility, allowing for adjustments to control parameters to adapt to different application requirements, providing a reliable technical solution for various high-efficiency, high-power-factor power supply applications. Through the implementation of this embodiment, high-efficiency DC-DC conversion and high-performance power factor correction can be simultaneously achieved in a single topology, providing strong support for the miniaturization and efficiency improvement of modern power electronic systems.

[0117] Example 5

[0118] To address the adaptability of the integrated power conversion topology based on APFC and AHB under different output voltage requirements, and to optimize the parameter selection of key components in the circuit, this embodiment further refines the design scheme of the transformer winding ratio and the parameters of each capacitor.

[0119] Furthermore, the voltage waveform between the primary winding NP and the secondary winding NS is adjusted by the coupling capacitor C3. The capacitance value of the coupling capacitor C3 is determined as follows:

[0120] Where ω is the angular frequency of the switching frequency, and L T This represents the leakage inductance value of the transformer. It's understandable that the coupling capacitor C3 plays a role in energy transfer and isolation within the circuit. Therefore, its selection requires a balance between energy transfer efficiency and isolation effectiveness. A larger coupling capacitor can improve energy transfer efficiency but may reduce isolation; a smaller coupling capacitor can provide better isolation but may limit energy transfer. In practical applications, the optimal coupling capacitor value can be determined through simulation and experimentation to achieve the best balance between energy transfer efficiency and isolation.

[0121] Furthermore, to further optimize circuit performance, film capacitors or ceramic capacitors with low ESR and high-frequency characteristics can be selected for filter capacitor C1 and coupling capacitor C3. For output filter capacitors C2 and C4, low-ESR aluminum electrolytic capacitors or solid-state electrolytic capacitors can be selected to improve ripple suppression capability and reliability.

[0122] Furthermore, this embodiment can also consider adding a temperature compensation network to the circuit to address the issue of capacitance parameters changing with temperature. For example, resistors or thermistors with a positive temperature coefficient can be added at critical nodes to compensate for the tendency of capacitance parameters to decrease as temperature increases, thereby maintaining the stability of the circuit at different temperatures.

[0123] The advantage of this embodiment lies in improving the flexibility and adaptability of the power conversion topology by optimizing the transformer winding ratio and capacitor parameters. A reasonable winding ratio design allows the circuit to meet various output voltage requirements, while the optimized capacitor parameter selection ensures good performance under various operating conditions. Through the implementation of this embodiment, not only is the efficiency and stability of the power converter improved, but its applicability in different application scenarios is also enhanced.

[0124] Example 6

[0125] To address the efficiency and stability issues of integrated power conversion topologies based on APFC and AHB under varying load conditions, and to improve the safety and reliability of the circuit, this embodiment further optimizes the control algorithm and introduces protection mechanisms and soft-start functionality.

[0126] Furthermore, this embodiment designs an adaptive control algorithm to dynamically adjust the duty cycle of the PWM control signal according to load changes, thereby optimizing circuit efficiency and stability. The core idea of ​​this control algorithm is to calculate the current output power by real-time monitoring of the output voltage VOUT and output current IOUT, and adjust the duty cycle of the PWM signal accordingly, ensuring the circuit always operates at its optimal efficiency point. It is important to understand that this adaptive control method can effectively cope with load changes and input voltage fluctuations, maintaining high-efficiency circuit operation.

[0127] Further, the specific implementation steps of the control algorithm are as follows: First, detect the output voltage VOUT and output current IOUT, and calculate the current output power POUT = VOUT × IOUT. Then, based on the current output power, determine the optimal duty cycle Dot using a pre-established lookup table or interpolation method. This lookup table or interpolation function can be obtained through extensive experimental data or theoretical analysis, reflecting the optimal operating point under different output powers. Next, calculate the deviation ΔD = D between the current duty cycle and the optimal duty cycle. current -Dopt And use a PI controller to calculate the duty cycle adjustment:

[0128] ΔD adj =K p ·∫ΔD+K i ·∫ΔDdt

[0129] Where Kp is the proportional coefficient and Ki is the integral coefficient. It is understandable that the selection of PI controller parameters directly affects the response speed and stability of the control system, and needs to be optimized according to the actual system characteristics.

[0130] Furthermore, the algorithm updates the duty cycle D of the PWM control signal. new =D current +ΔD adj The updated duty cycle is then limited to an effective range, such as 30%–70%. This limitation prevents circuit malfunctions caused by excessively high or low duty cycles. Finally, the updated duty cycle is applied to the PWM controller, and the above process is repeated periodically to achieve real-time adjustment of the system.

[0131] Furthermore, to improve the robustness and adaptability of the algorithm, an adaptive PI parameter adjustment mechanism can be introduced. For example, the values ​​of Kp and Ki can be dynamically adjusted according to the magnitude and speed of load changes. Kp can be increased to improve response speed when the load changes rapidly, while Ki can be increased to reduce steady-state error when the load is stable. Additionally, feedforward control can be introduced to pre-adjust the duty cycle based on changes in the input voltage, further enhancing the system's dynamic response capability.

[0132] Furthermore, this embodiment also introduces an overcurrent protection mechanism. When the output current IOUT is detected to exceed a preset threshold, the first switch Q1 and the second switch Q2 are immediately turned off, and then restarted after a delay. This protection mechanism can effectively prevent the circuit from being damaged due to short circuits or overloads. It is understood that the setting of the overcurrent protection threshold needs to comprehensively consider the circuit's rated power, the component's tolerance, and the actual application requirements. In practical implementation, a fast-response current detection circuit, such as a Hall current sensor or a precision shunt resistor, can be used to ensure that overcurrent conditions can be detected in a timely manner.

[0133] Furthermore, this embodiment also incorporates a soft-start mechanism. When the circuit is powered on, the duty cycle of the PWM control signal starts from 0 and gradually increases to the normal operating value at a preset slope to avoid large current surges during startup. This soft-start mechanism effectively protects circuit components and extends system lifespan. It is understood that the selection of the soft-start slope requires a trade-off between startup time and current surge suppression effectiveness. In practical applications, the optimal soft-start parameters can be determined experimentally based on circuit characteristics and load requirements.

[0134] Furthermore, to further improve system reliability, this embodiment may also consider introducing a temperature protection mechanism. For example, temperature sensors can be placed near critical components, such as switching transistors and transformers. When the detected temperature exceeds a safe threshold, the system operating frequency can be reduced or the system can be temporarily shut down to prevent overheating damage.

[0135] The advantage of this embodiment is that, by implementing an adaptive control algorithm, the efficiency and stability of the power conversion topology circuit under different load conditions are significantly improved. At the same time, the introduced overcurrent protection and soft-start mechanism enhance the circuit's safety and reliability.

[0136] Example 7

[0137] To address the issues of output voltage stability and precise control in integrated power conversion topologies based on APFC and AHB, this embodiment further optimizes the design of the output voltage feedback control loop, achieving precise adjustment and rapid response of the output voltage.

[0138] Furthermore, this embodiment designs a complete output voltage feedback control loop, which precisely adjusts the output voltage VOUT by changing the duty cycle of the PWM control signal. The control loop generates a corresponding PWM control signal by continuously comparing the actual output voltage with the desired voltage, thereby achieving closed-loop control of the output voltage. It should be understood that this closed-loop control method can effectively suppress the impact of load changes and input voltage fluctuations on the output voltage, ensuring the stability of the power supply output.

[0139] Furthermore, the voltage sampling circuit uses a voltage divider resistor network to sample the output voltage VOUT. Understandably, the choice of voltage divider resistors directly affects sampling accuracy and power consumption. Typically, thin-film resistors with an accuracy of 0.1% or higher can be selected as voltage divider resistors to ensure sampling accuracy. Simultaneously, the voltage division ratio design needs to consider the input voltage range of the subsequent error amplifier. For example, if the reference voltage of the error amplifier is 2.5V and the output voltage is 12V, a voltage division ratio of 5:1 can be designed. Additionally, a small ceramic capacitor, such as 100pF, can be connected in parallel with the voltage divider network to filter out high-frequency noise and improve the quality of the sampled signal.

[0140] Furthermore, the error amplifier compares the sampled voltage with the reference voltage and outputs an error signal. The selection of the error amplifier requires consideration of parameters such as bandwidth, open-loop gain, and input bias current. An integrated programmable precision reference source such as the TL431 and error amplifier can be used, or a high-precision operational amplifier such as the OPA277 can be combined with a precision reference voltage source such as the REF3025 to construct the error amplifier circuit. In practical designs, a compensation network, such as a Type III compensation network, can be added to the feedback loop of the error amplifier to optimize the system's frequency response characteristics and improve the stability and dynamic response capability of the control loop.

[0141] Furthermore, the PWM comparator compares the error signal with a triangular wave to generate the PWM control signal. The frequency of the triangular wave generator directly determines the switching frequency, typically selectable within the range of 50kHz to 500kHz, depending on power requirements and efficiency considerations. High-speed comparators, such as the LM311 or the newer LMV7219, can be used to ensure accurate timing and low jitter of the PWM signal. It is important to note that the selection of the PWM comparator should consider parameters such as its bandwidth, propagation delay, and output rise / fall time to ensure proper operation at the selected switching frequency.

[0142] Furthermore, the driver circuit converts the PWM control signal into the level and timing parameters for driving the first switch Q1 and the second switch Q2. Considering the specific characteristics of the AHB topology, the driver circuit needs to provide isolation and level shifting capabilities. Integrated half-bridge driver ICs, such as the IR2110 or the newer Si8233, can be used. These drivers have built-in bootstrap circuitry and can directly drive both high-side and low-side MOSFETs. In practical applications, it may be necessary to add a small resistor and a fast recovery diode at the output of the driver circuit to control the switching speed of the transistors, suppress parasitic oscillations, and improve EMI performance.

[0143] Furthermore, to further improve the reliability and performance of the system, the following optimization measures may also be considered in this embodiment:

[0144] 1. Introduce dead-time control in the PWM control signal generation circuit to prevent shoot-through short circuits caused by simultaneous conduction of the high-side and low-side switches. The dead time can be optimized according to the switching characteristics of the selected MOSFET, typically in the range of tens to hundreds of nanoseconds.

[0145] 2. Introduce feedforward compensation in the control loop to pre-adjust the PWM duty cycle according to the changes in input voltage, thereby improving the system's response speed to changes in input voltage.

[0146] 3. Employ digital control technology, such as using microcontrollers or digital signal processors to implement control algorithms. This allows for more flexible implementation of complex control strategies, such as adaptive control and predictive control.

[0147] 4. Add overvoltage protection to the voltage sampling circuit. When the output voltage exceeds the safety threshold, immediately turn off the switching transistor to protect the downstream circuit.

[0148] The advantage of this embodiment lies in achieving precise regulation and rapid response of the output voltage through a carefully designed output voltage feedback control loop. Simultaneously, the selection of high-performance components and optimized circuit design improves system stability and reliability. This embodiment not only enhances the performance of the power converter but also strengthens its adaptability to various application scenarios, providing a technical solution for modern power electronic systems.

[0149] Example 8

[0150] To optimize the performance and reliability of the integrated power conversion topology circuit based on APFC and AHB, this embodiment further improves the position of the coupling capacitor C3. By adjusting the circuit topology, the energy transfer efficiency and circuit stability are improved.

[0151] Specifically, in this embodiment, the position of the coupling capacitor C3 has been changed. In the new topology, the coupling capacitor C3 is connected in series between the positive terminal of the output filter capacitor C2 and the primary winding NP. It should be understood that this topology change maintains the basic operating principle and function of the original circuit.

[0152] Furthermore, the design of directly connecting the coupling capacitor C3 to the primary winding NP allows C3 to bear some of the voltage stress during energy transfer. Understandably, this arrangement helps alleviate the voltage stress on the first switching transistor Q1, especially during switching. Since the coupling capacitor is connected in series with the primary winding, they jointly share the voltage fluctuations during switching, thereby reducing the peak voltage of the switching transistor and improving circuit stability.

[0153] Furthermore, this topology improves energy transfer efficiency. The coupling capacitor C3, connected in series with the primary winding NP, forms a resonant circuit. During switching, this resonant circuit enables soft switching, reducing switching losses. Understandably, soft-switching technology can significantly reduce electromagnetic interference (EMI) during switching while improving the overall circuit efficiency.

[0154] Furthermore, to fully leverage the advantages of this new topology, the coupling capacitor C3 can be a high-quality ceramic or film capacitor with a high Q factor in practical applications. For example, NPO-type ceramic capacitors or polypropylene film capacitors can be selected. These capacitors have the advantages of low loss and good high-frequency characteristics, and can maintain stable performance in high-frequency switching environments. The capacitor value needs to be matched with the inductance of the primary winding to achieve the best resonance effect. Usually, the optimal capacitor value can be determined by a combination of simulation and experimentation.

[0155] Furthermore, this change in topology also affects the circuit's EMI characteristics. Since the coupling capacitors are connected in series with the primary winding, they together form a filter network that effectively suppresses the propagation of high-frequency noise. Understandably, this built-in filtering effect helps reduce the circuit's electromagnetic interference level, decreases reliance on external EMI filters, and thus simplifies the overall circuit design.

[0156] Furthermore, to further optimize the performance of this new topology, a small inductor can be added to the series branch of the coupling capacitor C3 and the primary winding NP. This additional inductor can form an LLC resonant network with the coupling capacitor, further enhancing the soft-switching effect and widening the operating range of the soft switch. The selection of the inductor value needs to consider the switching frequency and load range, and can usually be obtained through simulation optimization.

[0157] Furthermore, this topology change also provides new control strategies for the circuit. For example, frequency modulation control can be achieved by utilizing the resonant characteristics formed by the coupling capacitor and the primary winding. By adjusting the switching frequency, energy transfer can be controlled more flexibly to adapt to different load conditions. This control method can be combined with traditional PWM control to form a hybrid control strategy, further improving the circuit's adaptability and efficiency.

[0158] The advantage of this embodiment is that by changing the position of the coupling capacitor C3, the circuit topology is optimized, which not only improves energy transfer efficiency but also enhances the circuit's EMI characteristics and reliability. This innovative topology design provides new performance improvement potential for integrated power conversion circuits based on APFC and AHB, enabling them to perform better in terms of high efficiency, low EMI, and high reliability.

[0159] Example 9

[0160] To further optimize the performance and efficiency of the integrated power conversion topology circuit based on APFC and AHB, this embodiment improves the circuit connection method by introducing a reverse polarity connection structure, thereby achieving circuit characteristics equivalent to those in Embodiment 1, only with two different implementation methods.

[0161] Furthermore, this embodiment adjusts the connection method of the energy storage inductor L1, bridge rectifier BR1, second switch Q2, and first diode D1. In the new topology, the output terminal 3 of the bridge rectifier (BR1) serves as the first connection point, and the output terminal 4 serves as the second connection point; the first terminal of the filter capacitor (C1), the anode of the third diode (D3), the drain of the first switch (Q1), the positive terminal of the output filter capacitor (C2), and the first terminal of the primary winding (NP) are all connected to the first connection point; the second terminal of the filter capacitor (C1) and the first terminal of the energy storage inductor (L1) are both connected to the second connection point; the second terminal of the energy storage inductor (L1) serves as... The third connection point is where the cathodes of both the first diode (D1) and the third diode (D3) are connected. The anode of the first diode (D1) serves as the fourth connection point, where the source of the first switching transistor (Q1), the drain of the second switching transistor (Q2), and the first terminal of the coupling capacitor (C3) are all connected. The second terminal of the coupling capacitor (C3) is connected to the second terminal of the primary winding (NP). The source of the second switching transistor (Q2) and the negative terminal of the output filter capacitor (C2) are both grounded. It is understandable that this connection method alters the charging and discharging path of the energy storage inductor, but still maintains the basic operating principle of the circuit. It is important to understand that this reverse polarity connection affects the performance and characteristics of the circuit.

[0162] Specifically, the connection method of the first diode D1 forms a new energy transfer path. It is understood that this reverse polarity connection structure changes the direction of current flow, but does not affect the basic function and operating principle of the circuit. This is also a different implementation method and should fall within the scope of protection of this invention.

[0163] Furthermore, the primary winding NP of transformer T1 maintains the same connection method as the original circuit. This design ensures that the operating mode of the AHB section remains unaffected, while allowing improvements to the APFC section to be combined with the original advantages of the AHB section. Understandably, keeping the transformer primary winding connection unchanged maximizes the preservation of the advantages of the original circuit, while performance improvements are achieved through enhancements to other parts.

[0164] Furthermore, this reverse polarity connection structure has a positive impact on the circuit's EMI characteristics. Since the energy storage inductor L1 is directly connected to the bridge rectifier BR1, the number of intermediate connection points is reduced, lowering the impact of parasitic capacitance and inductance. This design helps suppress the generation and propagation of high-frequency noise, thereby improving the circuit's electromagnetic compatibility. In practical applications, ferrite beads or common-mode inductors can be considered to further optimize EMI performance.

[0165] Furthermore, to fully leverage the advantages of this new topology, the selection and parameter optimization of components are necessary. For example, the selection of the energy storage inductor L1 needs to consider its operating characteristics under reverse polarity connection. Low-loss, high-saturation-current iron powder core or iron-silicon-aluminum core inductors can be selected to adapt to the new operating mode. The selection of the inductance value requires a trade-off between ripple current and inductor volume, and the optimal value can usually be determined through a combination of simulation and experimentation.

[0166] Furthermore, the selection of the second switch, Q2, also needs to adapt to the new topology. Since it performs the main switching function, a superjunction MOSFET or SiC MOSFET with low on-resistance and fast switching characteristics can be considered. These advanced semiconductor devices can effectively reduce switching losses and improve the overall efficiency of the circuit. At the same time, attention must be paid to the gate drive circuit design of the switch to ensure fast and reliable switching operation under the new topology.

[0167] Furthermore, to further optimize circuit performance, a small-value damping resistor and capacitor connected in parallel can be added to the connection point of the energy storage inductor L1 and the second switching transistor Q2. This absorption circuit can effectively suppress voltage spikes during switching, protecting the switching transistor from overvoltage damage, and also helps improve EMI performance. The values ​​of the resistor and capacitor need to be optimized based on the circuit's switching frequency and power rating.

[0168] Furthermore, this reverse polarity connection structure provides a new control strategy for the circuit. For example, more precise current control and power factor correction can be achieved by monitoring the voltage across the energy storage inductor L1. This method can be combined with traditional current sampling techniques to form a hybrid control strategy, further improving the circuit's dynamic response and stability.

[0169] The advantage of this embodiment lies in its optimization of circuit topology design and improvement of EMI characteristics and dynamic response capabilities through the introduction of a reverse polarity connection structure. This embodiment better meets the needs of various application scenarios, and is particularly suitable for high-end power supply systems with stringent requirements for efficiency and EMI performance.

[0170] Example 10

[0171] To further improve the performance of the integrated power conversion topology circuit based on APFC and AHB, this embodiment has made dual optimizations to the circuit structure. Not only is a reverse polarity connection adopted, but the position of the coupling capacitor C3 has also been adjusted. The performance is comparable to that of the power conversion topology circuit in the previous embodiment, which is a different implementation method and therefore should fall within the protection scope of this invention.

[0172] Specifically, the position of coupling capacitor C3 has also been adjusted in this embodiment. In the new topology, coupling capacitor C3 is connected between the primary winding NP and the negative terminal of the output filter capacitor C2. This design introduces coupling capacitor C3 into the energy transfer path, forming a resonant network. Understandably, this configuration enables soft-switching technology, reduces switching losses, and also improves the EMI characteristics of the circuit.

[0173] Furthermore, in this embodiment, the coupling capacitor C3 directly participates in the energy transfer of the main circuit, therefore its quality factor and withstand voltage characteristics need to be carefully considered. High-quality polypropylene film capacitors or ceramic capacitors can be considered, as these capacitors have the advantages of low equivalent series resistance (ESR) and good high-frequency characteristics. The capacitor value needs to be matched with the inductance of the primary winding to achieve optimal resonance and soft-switching performance.

[0174] Furthermore, the selection of switching transistors also needs to adapt to the new topology. For the first switch Q1 and the second switch Q2, next-generation wide-bandgap semiconductor devices, such as GaN HEMTs or SiC MOSFETs, can be considered. These devices have low on-resistance, fast switching characteristics, and high-temperature operating capabilities, which can fully leverage the advantages of the new topology and further improve the circuit's efficiency and power density.

[0175] Furthermore, to optimize the control performance of the circuit, adaptive algorithms can be introduced into the control strategy. For example, the frequency and duty cycle of the PWM signal can be dynamically adjusted according to changes in load conditions and input voltage to achieve the optimal operating point. This adaptive control can be implemented using a digital signal processor (DSP) or a field-programmable gate array (FPGA), thereby improving the flexibility and adaptability of the circuit.

[0176] Furthermore, to further improve circuit reliability, protection circuits can be added at critical nodes. For example, overvoltage protection and undervoltage lockout functions can be added to the gate drive circuits of the first switch Q1 and the second switch Q2 to prevent damage to the switches due to abnormal drive voltage. Simultaneously, overcurrent protection and short-circuit protection circuits can be added to the output to ensure circuit safety under abnormal operating conditions.

[0177] The advantage of this embodiment lies in achieving a comprehensive improvement in circuit performance through the combination of reverse polarity connection and optimized coupling capacitor placement. This innovative design not only improves energy conversion efficiency but also enhances the circuit's dynamic response and EMI characteristics. This embodiment provides a new solution for high-performance power systems, particularly suitable for applications with high requirements for efficiency, power density, and reliability, such as data centers and electric vehicle charging systems.

Claims

1. An integrated power conversion topology circuit based on APFC and AHB, characterized in that, The power conversion topology circuit includes: The AC source (AC1) is rectified into a sinusoidal half-wave voltage through a bridge rectifier (BR1) and a filter capacitor (C1); An energy storage inductor (L1) is connected in series with a second switch (Q2). When the second switch (Q2) is turned on, the energy storage inductor (L1) is charged and stored through a first diode (D1). The first switching transistor (Q1) is connected in series with the output filter capacitor (C2) and then connected to the circuit. Zero-voltage switching is achieved by setting the dead time. The primary winding (NP) of the transformer (T1) is coupled to the output filter capacitor (C2) through the coupling capacitor (C3). The secondary winding (NS) of the transformer (T1) is rectified and filtered by the second diode (D2) and the output filter capacitor (C4) to generate the output voltage (VOUT). And the third diode (D3), which is connected in parallel with the filter capacitor (C1) through the energy storage inductor (L1), is used to clamp the reverse voltage at -1V to ensure circuit stability; The output terminal 3 of the bridge rectifier (BR1) serves as the first connection point, and the output terminal 4 serves as the second connection point, which is grounded. The first terminal of the filter capacitor (C1) and the first terminal of the energy storage inductor (L1) are connected to the first connection point. The second terminal of the energy storage inductor (L1) serves as the third connection point, and the cathode of the third diode (D3) and the anode of the first diode (D1) are both connected to the third connection point. The second terminal of the filter capacitor (C1) and the anode of the third diode (D3) are both grounded. The cathode of a diode (D1) serves as the fourth connection point. The source of the first switching transistor (Q1), the drain of the second switching transistor (Q2), and the first terminal of the coupling capacitor (C3) are connected to the fourth connection point. The first terminal of the primary winding (NP) and the positive terminal of the filter capacitor (C2) are connected to the drain of the first switching transistor (Q1), respectively. The second terminal of the primary winding (NP) is connected to the second terminal of the coupling capacitor (C3), and the negative terminal of the filter capacitor (C2) and the source of the second switching transistor (Q2) are both grounded.

2. The integrated power conversion topology circuit based on APFC and AHB as described in claim 1, characterized in that, The operation of the power conversion topology circuit includes a first switching cycle and a second switching cycle. The steps of the first switching cycle include: When the second switch (Q2) is turned on, the first diode (D1) charges the energy storage inductor (L1) to store energy. When the second switch (Q2) is turned off, the induced voltage of the energy storage inductor (L1) is superimposed on the voltage on the filter capacitor (C1), and the output filter capacitor (C2) is charged and stored through the first diode (D1) and the first switch (Q1). The first switch (Q1) is turned on after the dead time to reduce circuit losses; The steps of the second switching cycle include: When the first switch (Q1) is turned off, the second switch (Q2) is turned on after a dead time, repeating the energy storage process of the energy storage inductor (L1). At the same time, the primary winding (NP) stores energy by coupling the voltage stored on the output filter capacitor (C2) through the coupling capacitor (C3). When the second switch (Q2) is turned off, the energy storage inductor (L1) and the primary winding (NP) are out of phase, and the first switch (Q1) is turned on with zero voltage. The energy storage inductor (L1) repeatedly charges and stores energy in the output filter capacitor (C2), and the primary winding (NP) and leakage inductance are clamped and magnetically reset by the coupling capacitor (C3). The energy stored in the transformer (T1) is coupled through the secondary winding (NS), and after rectification and filtering by the second diode (D2) and the output filter capacitor (C4), the output voltage (VOUT) is output. After the energy is released, the first switch (Q1) is turned off, the primary winding (NP) is reversed, and the second switch (Q2) is turned on with zero voltage.

3. The integrated power conversion topology circuit based on APFC and AHB as described in claim 1, characterized in that, The turn-on and turn-off processes of the first switch (Q1) and the second switch (Q2) are used to achieve zero-voltage switching (ZVS) by precisely controlling the dead time. The drain of the first switching transistor (Q1) is connected to the positive terminal of the output filter capacitor (C2), and the negative terminal of the filter capacitor (C2) is grounded; the source of the second switching transistor (Q2) is grounded, and its drain is connected to the source of the first switching transistor (Q1). The first switch (Q1) and the second switch (Q2) are turned on and off by complementary PWM control signals; Dead time is set between the first switch (Q1) being turned off and the second switch (Q2) being turned on, and between the second switch (Q2) being turned off and the first switch (Q1) being turned on, respectively, so that the switch can be turned on in a state of zero voltage or near zero voltage.

4. The integrated power conversion topology circuit based on APFC and AHB as described in claim 1, characterized in that, An asymmetric half-bridge (AHB) is achieved by adjusting the on-time ratio of the first switch (Q1) and the second switch (Q2). The conduction time of the first switch (Q1) accounts for 99%-40% of the total switching cycle, and the conduction time of the second switch (Q2) accounts for 1%-60% of the total switching cycle. By controlling the charging and discharging process of the energy storage inductor (L1), a sinusoidal waveform of the input current is achieved by utilizing the inductor in discontinuous mode with equal conduction time, which is used for active power factor correction (APFC). One end of the energy storage inductor (L1) is connected to the positive terminal of the bridge rectifier (BR1), and the other end is connected to the anode of the first diode (D1).

5. The integrated power conversion topology circuit based on APFC and AHB as described in claim 1, characterized in that, The voltage waveform between the primary winding (NP) and the secondary winding (NS) is adjusted by the coupling capacitor (C3), and the capacitance value C3 is determined as follows: Where ω is the angular frequency of the switching frequency, and L T This is the leakage inductance value of the transformer.

6. The integrated power conversion topology circuit based on APFC and AHB as described in claim 3, characterized in that, The power conversion topology circuit also includes a control algorithm for adjusting the duty cycle of the PWM control signal according to load changes; The control algorithm includes the following steps: Detect the output voltage (VOUT) and output current (IOUT); Calculate the current output power: POUT = VOUT × IOUT; Based on the current output power, the optimal duty cycle D is determined using a lookup table or interpolation method. opt ; Calculate the deviation between the current duty cycle and the optimal duty cycle: ΔD = D current -D opt ; Calculate the duty cycle adjustment using a PI controller: , where K p K is the proportionality coefficient. i The integral coefficient; Update the duty cycle of the PWM control signal: D new =D current +ΔD adj ; The updated duty cycle is limited to within the effective range; Apply the updated duty cycle to the PWM controller; The above process is repeated periodically; The power conversion topology circuit also includes: An overcurrent protection mechanism is in place. When the output current (IOUT) is detected to exceed a preset threshold, the first switch (Q1) and the second switch (Q2) are immediately turned off, and then restarted after a delay. The soft-start mechanism means that when the power is on, the duty cycle of the PWM control signal starts from 0 and gradually increases to the normal operating value according to a preset slope, so as to avoid the large current surge at the moment of startup.

7. The integrated power conversion topology circuit based on APFC and AHB as described in claim 3, characterized in that, The power conversion topology circuit also includes an output voltage feedback control loop, which is used to adjust the output voltage (VOUT) by adjusting the duty cycle of the PWM control signal. The control loop includes: The voltage sampling circuit uses a voltage divider resistor network to sample the output voltage (VOUT). The error amplifier compares the sampled voltage with the reference voltage and outputs an error signal. The PWM comparator compares the error signal with the triangular wave to generate the PWM control signal; The driving circuit converts the PWM control signal into the level and timing of driving the first switch (Q1) and the second switch (Q2).

8. The integrated power conversion topology circuit based on APFC and AHB as described in claim 3, characterized in that, The power conversion topology circuit also includes a reverse polarity connection, which is configured as follows: The output terminal 3 of the bridge rectifier (BR1) serves as the first connection point, and the output terminal 4 serves as the second connection point. The first terminal of the filter capacitor (C1), the anode of the third diode (D3), the drain of the first switching transistor (Q1), the positive terminal of the output filter capacitor (C2), and the first terminal of the primary winding (NP) are all connected to the first connection point. The second terminal of the filter capacitor (C1) and the first terminal of the energy storage inductor (L1) are both connected to the second connection point. The second terminal of the energy storage inductor (L1) serves as the third connection point. The cathodes of the first diode (D1) and the third diode (D3) are both connected to the third connection point; the anode of the first diode (D1) serves as the fourth connection point, and the source of the first switching transistor (Q1), the drain of the second switching transistor (Q2), and the first terminal of the coupling capacitor (C3) are all connected to the fourth connection point, while the second terminal of the coupling capacitor (C3) is connected to the second terminal of the primary winding (NP); the source of the second switching transistor (Q2) and the negative terminal of the output filter capacitor (C2) are both grounded.

9. The integrated power conversion topology circuit based on APFC and AHB as described in claim 8, characterized in that, The power conversion topology circuit also includes a reverse polarity connection and a change in the position of the coupling capacitor (C3), wherein the change in position is as follows: The first terminal of the coupling capacitor (C3) is connected to the negative terminal of the output filter capacitor (C2), and the second terminal of the coupling capacitor (C3) is connected to the first terminal of the primary winding (NP).

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