Semiconductor structure and forming method thereof, and memory

Abstract

This disclosure provides a semiconductor structure and its formation method, as well as a memory. The semiconductor structure formation method includes: providing an initial stacked structure, the initial stacked structure including alternating layers of first and second sacrificial layers; forming a plurality of first trenches penetrating the initial stacked structure; laterally etching along the first trenches to remove a first portion of each of the first sacrificial layers, forming a plurality of first filling regions; forming a dielectric layer in each of the first filling regions; removing the second sacrificial layers to form a plurality of second filling regions, and forming a bit line layer in each of the second filling regions; and removing the remaining second portion of each of the first sacrificial layers to form a plurality of cavities.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor structure and a method for forming the same, and a memory. Background Technology

[0002] The integration level of two-dimensional semiconductor memory devices is mainly determined by the area occupied by the memory cells, and therefore its integration level is greatly affected by the level of fine patterning technology. In order to overcome the limitation of the level of fine patterning technology on the integration level of semiconductor memory devices, three-dimensional semiconductor memory devices including three-dimensionally arranged memory cells have recently been proposed.

[0003] However, traditional three-dimensional semiconductor memory devices and their fabrication methods still have certain shortcomings. How to further improve the performance of three-dimensional semiconductor memory devices has become an urgent problem to be solved.

[0004] Public content

[0005] In view of this, embodiments of the present disclosure provide a semiconductor structure, a method for forming the same, and a memory.

[0006] According to a first aspect of this disclosure, a method for forming a semiconductor structure is provided, comprising:

[0007] An initial stacking structure is provided, the initial stacking structure comprising alternating layers of first and second sacrificial layers;

[0008] Multiple first trenches are formed that penetrate the initial stacked structure;

[0009] Laterally etch along the first trench to remove a first portion of each of the first sacrificial layers, forming a plurality of first filling regions;

[0010] A dielectric layer is formed in each of the first filled regions;

[0011] The second sacrificial layer is removed to form multiple second fill regions, and a bit line layer is formed in each of the second fill regions;

[0012] The second portion of each retained first sacrificial layer is removed to form multiple cavities.

[0013] In the above scheme, a plurality of first trenches are arranged along a first direction, the distance between the sidewall of the first trench parallel to the first direction and the edge of the initial stacking structure along the second direction is H1, the distance between two adjacent first trenches along the first direction is H2, and the ratio of H2 to H1 is greater than 2; the first direction is perpendicular to the second direction and both are perpendicular to the stacking direction of the initial stacking structure.

[0014] In the above scheme, the removal of the second sacrificial layer to form multiple second filling regions, and the formation of a bit line layer in each of the second filling regions, includes:

[0015] Laterally etch along the first trench to remove the third portion of each second sacrificial layer, forming a plurality of third filling regions;

[0016] Each of the third filling regions is filled with a conductive material; the conductive material is filled between the fourth portions of each retained second sacrificial layer;

[0017] Remove the fourth part to form multiple fourth filling regions;

[0018] The conductive material is filled in each of the fourth filling regions; the conductive material in the third filling regions and the fourth filling regions constitutes the bit line layer.

[0019] In the above scheme, after a dielectric layer is formed in each of the first filling regions, the dielectric layer fills the space between the second portions of each retained first sacrificial layer;

[0020] The removal of the fourth part and the removal of the second part include:

[0021] After each of the third filling regions is filled with conductive material, a second trench is formed that penetrates the initial stacked structure; the second trench exposes the sidewalls of the fourth portion and the sidewalls of the second portion;

[0022] Laterally etch along the second trench to remove the fourth portion;

[0023] Laterally etch along the second trench to remove the second portion.

[0024] The method in the above scheme further includes:

[0025] Before etching laterally along the first trench to remove a first portion of each of the first sacrificial layers, a third sacrificial layer is filled in at least a portion of the first trench;

[0026] After a dielectric layer is formed in each of the first filled regions, the third sacrificial layer is removed to form a fourth trench that exposes the sidewalls of the second portion.

[0027] In the above scheme, the removal of the second sacrificial layer to form multiple second filling regions, and the formation of a bit line layer in each of the second filling regions, includes:

[0028] A fourth sacrificial layer is filled in the first trench, and the fourth trench is laterally etched to remove the fifth portion of each second sacrificial layer, forming a plurality of fifth filling regions;

[0029] Each of the fifth filling regions is filled with conductive material;

[0030] Remove the fourth sacrificial layer, and remove the sixth portion of each retained second sacrificial layer along the first trench to form a plurality of sixth filling regions;

[0031] The conductive material is filled in each of the sixth filling regions; the conductive material in the fifth and sixth filling regions constitutes the bit line layer.

[0032] In the above scheme, multiple first trenches are arranged along a first direction, and the method further includes:

[0033] After a dielectric layer is formed in each of the first filling regions, a third trench is formed between two adjacent first trenches, the third trench penetrating the initial stack structure and exposing the sidewall of the second portion; the distance between the third trench and the adjacent first trench along the first direction is H3, and the distance between the sidewall of the third trench or the first trench parallel to the first direction and the edge of the initial stack structure along the second direction is H1, the ratio of H3 to H1 is greater than 2; the first direction and the second direction are perpendicular to each other and both are perpendicular to the stacking direction of the initial stack structure.

[0034] In the above scheme, the removal of the second sacrificial layer to form multiple second filling regions, and the formation of a bit line layer in each of the second filling regions, includes:

[0035] Laterally etch along the third trench to remove the seventh portion of each second sacrificial layer, forming a plurality of seventh filling regions;

[0036] Each of the seventh filling regions is filled with conductive material;

[0037] Laterally etch along the first trench to remove the eighth portion of the retained second sacrificial layer, forming a plurality of eighth filling regions;

[0038] The conductive material is filled in each of the eighth filling regions; the conductive materials in the seventh and eighth filling regions constitute the bit line layer;

[0039] The removal of a second portion of each retained first sacrificial layer includes: lateral etching along the third trench to remove a second portion of each retained first sacrificial layer.

[0040] According to a second aspect of this disclosure, a semiconductor structure is provided, comprising:

[0041] Stacked structures, including alternating layers of bit lines and dielectric layers;

[0042] The stacked structure includes a plurality of first trenches that penetrate the stacked structure;

[0043] The bit line layer has a plurality of first bit line portions located on both sides of the first trench along a first direction and a second bit line portion located on one side of the plurality of first bit line portions along a second direction, the second bit line portion extending along the first direction;

[0044] The dielectric layer between adjacent first trenches has a cavity.

[0045] In the above scheme, multiple first grooves are arranged along a first direction, the width of the second bit line portion along the second direction is H1, the width of the first bit line portion along the first direction is H2, and the ratio of H2 to H1 is greater than 2; the first direction is perpendicular to the second direction and both are perpendicular to the stacking direction of the stacked structure.

[0046] In the above scheme, the ratio of H2 to H1 ranges from 3 to 6.

[0047] In the above scheme, the cavity is located between the first bit lines adjacent to each other along the stacking direction, and the cavity and the two first trenches adjacent to each other along the first direction each have a dielectric layer.

[0048] In the above scheme, the ratio of H2 to H1 is greater than 6. The stacked structure also includes a third trench that runs through the stacked structure. The third trench is located between two adjacent first trenches. The distance between the third trench and the adjacent first trench along the first direction is H3. The ratio of H3 to H1 is between 3 and 6.

[0049] In the above scheme, the cavity is located between the first bit line portions adjacent to each other along the stacking direction and between the second bit line portions adjacent to each other along the stacking direction, and the cavity is located on both sides of the third trench along the first direction and on one side along the second direction. A dielectric layer is provided between the first trench and the cavity, and the third trench is in communication with the cavity.

[0050] According to a third aspect of this disclosure, a memory is provided, comprising a semiconductor structure as described in any of the above embodiments.

[0051] In this embodiment of the disclosure, a first trench is formed through the initial stacked structure. A first portion of the first sacrificial layer is removed by lateral etching along the first trench. A dielectric layer is filled in the region where the first portion of the first sacrificial layer has been removed. After removing the second sacrificial layer and forming a bit line layer, a second portion of the first sacrificial layer is removed. This forms a cavity between two adjacent bit line layers along the stacking direction of the initial stacked structure. This reduces the coupling effect between two adjacent bit line layers along the stacking direction of the initial stacked structure and reduces the parasitic capacitance between two adjacent bit line layers along the stacking direction of the initial stacked structure, thereby improving the performance of the semiconductor structure. Attached Figure Description

[0052] Figure 1 A schematic flowchart illustrating a method for manufacturing a semiconductor structure according to an embodiment of this disclosure;

[0053] Figures 2 to 33 This is a schematic diagram of the manufacturing process of the semiconductor structure according to an embodiment of the present disclosure;

[0054] Figure 34 This is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure. Figure 1 ;

[0055] Figure 35 This is a schematic diagram of a semiconductor structure according to an embodiment of the present disclosure. Figure 2 . Detailed Implementation

[0056] To make the technical solutions and advantages of the embodiments of this disclosure clearer, the technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this disclosure are shown in the accompanying drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the implementation methods set forth herein. Rather, these implementation methods are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art.

[0057] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0058] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.

[0059] Furthermore, for ease of description, spatial relative terms such as “on,” “above,” “above,” “upper,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0060] In embodiments of this disclosure, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, silicon carbide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

[0061] In embodiments of this disclosure, the term "layer" refers to a portion of material including a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. For example, an interconnect layer may include one or more conductor and contact sublayers (where interconnect lines and / or via contacts are formed), and one or more dielectric sublayers.

[0062] In the embodiments of this disclosure, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0063] The semiconductor structure disclosed herein is at least a portion of the structure that will be used in subsequent processes to form the final device structure. Here, the final device may include memory, including but not limited to Dynamic Random Access Memory (DRAM). The following description uses DRAM as an example only.

[0064] In current proposed architectures of 3D dynamic random access memory (DRAM), horizontal bit lines and vertical word lines are the mainstream development direction due to their easier integration. As memory density requirements continue to increase, the distance between bit lines in the horizontal bit line architecture of 3D DRAM is becoming smaller. This leads to coupling effects between adjacent bit lines and the formation of parasitic capacitances. Furthermore, to ensure low resistance in the bit lines, materials with low resistance, such as metals, are generally chosen. However, this further exacerbates the coupling effect and parasitic capacitance problems, severely impacting memory reliability. Therefore, improving the coupling effect between adjacent bit lines and reducing their parasitic capacitance has become an urgent problem to be solved.

[0065] In view of the above problems, this disclosure provides a method for forming a semiconductor structure. Figure 1 This is a schematic flowchart illustrating a method for forming a semiconductor structure according to an embodiment of this disclosure. Figure 1 As shown, the method for forming a semiconductor structure provided in this disclosure includes the following steps:

[0066] S1100: Provides an initial stacking structure, which includes alternating layers of first and second sacrificial layers;

[0067] S1200: Forms multiple first trenches that penetrate the initial stacked structure;

[0068] S1300: Lateral etching along the first trench to remove a first portion of each first sacrificial layer, forming a plurality of first filling regions;

[0069] S1400: A dielectric layer is formed in each first filled region;

[0070] S1500: Remove the second sacrificial layer to form multiple second fill regions, and form a bit line layer in each second fill region;

[0071] S1600: Remove the second part of each retained first sacrificial layer to form multiple cavities.

[0072] It should be understood that Figure 1 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 1 The steps shown can be adjusted in order according to actual needs.

[0073] Figures 2 to 33 This is a schematic diagram of the semiconductor structure formation process provided in an embodiment of this disclosure. Below, we will combine... Figure 1 , Figures 2 to 33 The method for forming a semiconductor structure provided in the embodiments of this disclosure will be described in detail.

[0074] Reference Figure 2 Step S1100 is executed to provide an initial stacking structure 101, which includes an alternately stacked first sacrificial layer 102 and a second sacrificial layer 103.

[0075] It should be noted that, Figure 2 The number of the first sacrificial layer 102 and the second sacrificial layer 103 shown is merely an example, and this disclosure does not limit the specific number of the first sacrificial layer 102 and the second sacrificial layer 103 in the initial stacked structure 101.

[0076] In some specific examples, the first sacrificial layer 102 and the second sacrificial layer 103 can be formed by deposition or epitaxy (EPI) processes, first on a substrate ( Figure 2 A first sacrificial layer 102 is formed on the first sacrificial layer 102 (not shown), and a second sacrificial layer 103 is formed on the first sacrificial layer 102. This process is repeated to form an initial stacked structure 101 in which the first sacrificial layer 102 and the second sacrificial layer 103 are alternately stacked.

[0077] It should be noted that the selection of materials for the first sacrificial layer 102 and the second sacrificial layer 103 should consider minimizing the impact on the second sacrificial layer 103 during subsequent lateral removal of the first sacrificial layer 102, and minimizing the impact on the first sacrificial layer 102 during lateral removal of the second sacrificial layer 103. In some specific examples, the material of the first sacrificial layer 102 can be silicon germanide; the material of the second sacrificial layer 103 can be silicon.

[0078] In the embodiments disclosed herein, the deposition processes include, but are not limited to, chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0079] In some specific examples, such as Figure 2 As shown, the method further includes forming a mask layer 133 on the initial stacked structure 101. The mask layer 133 may be a composite layer or a single layer. For example, the mask layer 133 may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0080] Reference Figure 3Step S1200 is executed to form a plurality of first trenches 104 penetrating the initial stacked structure 101.

[0081] In some specific examples, the method for forming the first trench 104 includes, but is not limited to, dry etching. Here, the dry etching process can be an etching process with good directionality, such as plasma etching, sputtering etching, ion beam etching, or reactive ion etching.

[0082] In this embodiment of the disclosure, such as Figure 3 As shown, a plurality of first grooves 104 are arranged along a first direction. The distance between the sidewall of the first groove 104 parallel to the first direction and the edge of the initial stacked structure 101 along the second direction is H1. The distance between two adjacent first grooves 104 along the first direction is H2. The first direction is perpendicular to the second direction and both are perpendicular to the stacking direction of the initial stacked structure 101.

[0083] In this embodiment of the disclosure, the first direction is the X direction, the second direction is the Y direction, and the stacking direction of the initial stacking structure 101 is the Z direction.

[0084] Here, this disclosure provides multiple scenarios regarding the correspondence between H2 and H1, and the corresponding methods for forming the bit line layer, dielectric layer, and cavity are also different. This disclosure provides three schemes. Scheme one will be specifically explained below, taking the case where the ratio of H2 to H1 is greater than 2 and less than 6 as an example.

[0085] Reference Figure 4 Step S1300 is executed, and the first part of each first sacrificial layer 102 is removed by lateral etching along the first trench 104 to form a plurality of first filling regions 106.

[0086] In some specific examples, the method for removing the first portion of each first sacrificial layer 102 includes, but is not limited to, wet etching processes.

[0087] like Figure 4 As shown, the remaining first sacrificial layer 102 is the second portion 109 of the first sacrificial layer 102. The retained second portion 109 of each first sacrificial layer 102 is located between adjacent first trenches 104.

[0088] It is understood that when the first sacrificial layer 102 is etched laterally along the first trench 104, the first sacrificial layer 102 between two adjacent first trenches 104 is etched simultaneously from both sides along the first direction. Therefore, the second part 109 is located on both sides of the first filling region 106 along the first direction. In this embodiment, the ratio of H2 to H1 is greater than 2 and less than 6. This allows the first sacrificial layer 102 on both sides of the first trench 104 along the second direction to be completely removed when the first sacrificial layer 102 is etched laterally along the first trench 104, while retaining the second part 109 of the first sacrificial layer 102 between two adjacent first trenches 104 along the first direction. Here, the second part 109 of the retained first sacrificial layer 102 is located between two adjacent first trenches 104 along the first direction, and the second part 109 of the retained first sacrificial layer 102 can serve as a support.

[0089] Reference Figures 5 to 6 Step S1400 is executed, in which a dielectric layer 107 is formed in each first filling region 106.

[0090] In some specific examples, the dielectric layer 107 may be made of a low-dielectric-constant material, including but not limited to silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon oxynitride.

[0091] It is understood that the use of a low dielectric constant material for the dielectric layer 107 in this embodiment can reduce the coupling effect and parasitic capacitance between two adjacent bit line layers formed subsequently along the stacking direction of the initial stacked structure 101.

[0092] It should be noted that the selection of the dielectric layer 107 material here needs to take into account the need to reduce the impact on the dielectric layer 107 when removing the remaining first sacrificial layer 102, the remaining second sacrificial layer 103 and part of the conductive material layer in subsequent processes.

[0093] In some specific examples, dielectric material layers 129 can be deposited on the first filling region 106 and the sidewalls and top of the initial stacked structure 101. Then, the dielectric material layers 129 on the sidewalls and top of the initial stacked structure 101 can be removed by etching, leaving the dielectric material layers 129 in the first filling region 106 to form dielectric layer 107.

[0094] Reference Figures 7 to 13 Step S1500 is executed to remove the second sacrificial layer 103 and form multiple second filling regions, in which a bit line layer 108 is formed.

[0095] In some embodiments, such as Figures 7 to 13As shown, the second sacrificial layer 103 is removed to form a plurality of second filling regions, and a bit line layer 108 is formed in each second filling region. The process includes: laterally etching along the first trench 104 to remove a third portion of each second sacrificial layer 103 to form a plurality of third filling regions 112; filling each third filling region 112 with a conductive material layer 113; filling the conductive material layer 113 between the remaining fourth portions 114 of each second sacrificial layer 103; removing the fourth portions 114 to form a plurality of fourth filling regions 115; filling each fourth filling region 115 with a conductive material layer 113; the conductive material layers 113 in the third filling regions 112 and the fourth filling regions 115 constitute the bit line layer 108.

[0096] It is understood that the second sacrificial layer 103 in this embodiment is removed in two steps. First, the third portion of each second sacrificial layer is removed to form a third filling region 112, and a conductive material layer 113 is filled in the third filling region 112. Then, the fourth portion 114 of the second sacrificial layer 103 is removed to form a fourth filling region 115, and a conductive material layer 113 is filled in the fourth filling region 115. When removing the third portion, the fourth portion 114 can serve as a support, and when removing the fourth portion 114, the conductive material layer 113 filled in the third filling region 112 can serve as a support.

[0097] In some specific examples, the material of the conductive material layer 113 includes, but is not limited to, tungsten. Methods for forming the conductive material layer include, but are not limited to, deposition processes.

[0098] It is understood that using tungsten as the material for the bit line layer 108 in this embodiment can reduce bit line resistance and improve memory performance.

[0099] In some specific examples, such as Figure 8 as well as Figure 9 As shown, after forming multiple third filling regions 112, conductive material layers 113 can be deposited on the third filling regions 112 and the sidewalls and top of the initial stacked structure 101. Then, the conductive material layers 113 on the sidewalls and top of the initial stacked structure 101 can be removed by etching along the stacking direction of the initial stacked structure 101, while retaining the conductive material layers 113 located in the third filling regions 112.

[0100] It should be noted that, in order to more clearly demonstrate the initial stacking structure 101 between adjacent first trenches 104, Figures 2 to 9 Only a partial view, for example Figure 9 for Figure 10 A three-dimensional view of the upper half of the image cut along the AA' direction.

[0101] In some embodiments, such as Figures 9 to 12As shown, after forming a dielectric layer 107 in each first filling region 106, the dielectric layer 107 fills between the second portions 109 of each retained first sacrificial layer 102; removing the fourth portion 114 and removing the second portion 109 includes: after filling each third filling region 112 with a conductive material layer 113, forming a second trench 116 through the initial stacked structure 101; the second trench 116 exposes the sidewalls of the fourth portion 114 and the sidewalls of the second portion 109; laterally etching along the second trench 116 to remove the fourth portion 114; and laterally etching along the second trench 116 to remove the second portion 109.

[0102] In some specific examples, such as Figure 11 As shown, the second groove 116 extends along the first direction and is connected to the first groove 104.

[0103] In some specific examples, the methods for removing part 114 include, but are not limited to, wet etching processes.

[0104] It is understood that, since the second portion 109 of the first sacrificial layer 102 is covered by the dielectric layer 107 on both sidewalls along the first direction, and the fourth portion 114 of the second sacrificial layer 103 is covered by the conductive material layer 113 on both sidewalls along the first direction, the first trench 104 does not expose the second portion 109 of the first sacrificial layer 102, nor does it expose the fourth portion 114 of the second sacrificial layer 103. Therefore, the second portion 109 and the fourth portion 114 cannot be removed through the first trench 104. In this embodiment, by forming a second trench 116 that penetrates the initial stacked structure 101, and exposing the sidewalls of the fourth portion 114 and the second portion 109, the second portion 109 and the fourth portion 114 can be removed from the second trench 116.

[0105] Reference Figure 14 Step S1600 is executed to remove the second part 109 of each retained first sacrificial layer 102, forming multiple cavities 110.

[0106] In some specific examples, the methods for removing the second part 109 include, but are not limited to, wet etching.

[0107] In some specific examples, the method also includes removing the mask layer 133 after the cavity 110 is formed.

[0108] It is understood that in this embodiment of the present disclosure, a plurality of cavities 110 are formed between two adjacent bit line layers 108 along the stacking direction of the initial stacking structure 101. This reduces the coupling effect between the two adjacent bit line layers along the stacking direction of the initial stacking structure 101 and reduces the parasitic capacitance between the two adjacent bit line layers along the stacking direction of the initial stacking structure 101, thereby improving the performance of the memory.

[0109] When the ratio of H2 to H1 is greater than 2 and less than 6, embodiments of this disclosure also provide the following method for forming the bit line layer 108, the dielectric layer 107, and the cavity 110. The following will be combined with... Figures 15 to 24 The second option will be explained in detail.

[0110] In some embodiments, such as Figures 15 to 18 As shown, the method further includes: filling at least a portion of the first trench 104 with a third sacrificial layer 117 before laterally etching along the first trench 104 to remove a first portion of each first sacrificial layer 102; and after forming a dielectric layer 107 in each first filled region 106, removing the third sacrificial layer 117 to form a fourth trench 118, the fourth trench 118 exposing the sidewalls of the second portion 109.

[0111] It should be noted that, Figure 15 The illustration only shows the case where a third sacrificial layer 117 is filled in a first trench 104, but the third sacrificial layer 117 can also be filled in a plurality of first trenches 104 consecutively along the first direction.

[0112] It is understood that in the above embodiment, the third sacrificial layer 117 is first filled in a portion of the first trench 104, a portion of the first sacrificial layer 102 is removed using the first trench 104 that is not filled with the third sacrificial layer 117, and then the second portion 109 of the first sacrificial layer 102 is removed using the fourth trench after the third sacrificial layer is removed.

[0113] In some embodiments, such as Figures 19 to 23 As shown, the second sacrificial layer 103 is removed to form a plurality of second filling regions, and a bit line layer 108 is formed in each of the second filling regions. The process includes: filling a fourth sacrificial layer 119 in a first trench 104; laterally etching along the fourth trench 118 to remove a fifth portion of each second sacrificial layer 103 to form a plurality of fifth filling regions 123; filling each fifth filling region 123 with a conductive material layer 113; removing the fourth sacrificial layer 119; removing a sixth portion 120 of each second sacrificial layer 103 retained along the first trench 104 to form a plurality of sixth filling regions 121; and filling each sixth filling region 121 with a conductive material layer 113. The conductive material layers 113 in the fifth filling regions 123 and the sixth filling regions 121 constitute the bit line layer 108.

[0114] like Figure 24 As shown, the method further includes removing the second portion 109 of each retained first sacrificial layer 102 to form a plurality of cavities 110. These cavities are connected to the fourth trench 118.

[0115] In some specific examples, the method also includes removing the mask layer 133 after the cavity 110 is formed.

[0116] The ratio of H2 to H1 can also be greater than 6, which will be discussed below. Figures 25 to 33 The process of forming bit line layer 108, dielectric layer 107 and cavity 110 in Scheme 3 is explained in detail when the ratio of H2 to H1 is greater than 6.

[0117] In some embodiments, such as Figures 25 to 28 As shown, a plurality of first trenches 104 are arranged along a first direction. The method further includes: after forming a dielectric layer 107 in each first filling region 106, forming a third trench 124 between two adjacent first trenches 104. The third trench 124 penetrates the initial stacked structure 101 and exposes the sidewall of the second portion 109. The distance between the third trench 124 and the adjacent first trench 104 along the first direction is H3. The distance between the sidewall of the third trench 124 or the first trench 104 parallel to the first direction and the edge of the initial stacked structure 101 along the second direction is H1. The ratio of H3 to H1 is greater than 2. The first direction is perpendicular to the second direction and both are perpendicular to the stacking direction of the initial stacked structure 101.

[0118] Here, after the third trench 124 is formed, the ratio of H3 to H1 is greater than 2 and less than 6.

[0119] Understandably, compared to Scheme 1, Scheme 3, when the ratio of H2 to H1 is greater than 6, after removing the first part of the first sacrificial layer 102 using the first trench 104, retains a larger amount of the first sacrificial layer 102 between two adjacent first trenches 104. After forming the dielectric layer 107 in the first filling region 106, a third trench 124 is formed between two adjacent first trenches 104. The third trench 124 exposes the sidewall of the second part 109, so that the second part 109 can be removed along the third trench 124 in subsequent processes.

[0120] In some embodiments, such as Figures 29 to 32As shown, the second sacrificial layer 103 is removed to form a plurality of second filling regions, and a bit line layer 108 is formed in each of the second filling regions. The process includes: lateral etching along the third trench 124 to remove the seventh portion of each second sacrificial layer 103 to form a plurality of seventh filling regions 126; filling each seventh filling region 126 with a conductive material layer 113; lateral etching along the first trench 104 to remove the eighth portion 127 of the remaining second sacrificial layer 103 to form a plurality of eighth filling regions 128; filling each eighth filling region 128 with a conductive material layer 113; the conductive material layers 113 in the seventh filling regions 126 and the eighth filling regions 128 constitute the bit line layer 108.

[0121] In some specific examples, when laterally etching along the third trench 124 to remove the seventh portion of each second sacrificial layer 103, a fifth sacrificial layer can be formed in the first trench 124, such that the first sacrificial layer 102 cannot be laterally etched along the first trench 104 during the lateral etching along the third trench 124. The fifth sacrificial layer in the first trench 124 is removed after each seventh filling region 126 has been filled with a conductive material layer 113.

[0122] In some embodiments, such as Figure 33 As shown, removing the second portion 109 of each retained first sacrificial layer 102 includes: laterally etching along the third trench 124 to remove the second portion 109 of each retained first sacrificial layer 102.

[0123] This disclosure provides a method for forming a semiconductor structure, comprising: providing an initial stacked structure 101, the initial stacked structure 101 including alternating layers of first sacrificial layers 102 and second sacrificial layers 103; forming a plurality of first trenches 104 penetrating the initial stacked structure 101; laterally etching along the first trenches 104 to remove a first portion of each first sacrificial layer 102 to form a plurality of first filling regions 106; forming a dielectric layer 107 in each first filling region 106; removing the second sacrificial layer 103 to form a plurality of second filling regions, and forming a bit line layer 108 in each second filling region; and removing the remaining second portion 109 of each first sacrificial layer 102 to form a plurality of cavities 110. In this embodiment of the present disclosure, a first trench 104 is formed in the initial stacked structure 101, penetrating the initial stacked structure 101. A first portion of the first sacrificial layer 102 is removed by lateral etching along the first trench 104. A dielectric layer 107 is filled in the region where the first portion of the first sacrificial layer 102 has been removed. After removing the second sacrificial layer 103 and forming the bit line layer 108, a second portion 109 of the first sacrificial layer 102 is removed. This forms a cavity 110 between two adjacent bit line layers 108 along the stacking direction of the initial stacked structure 101. This reduces the coupling effect between two adjacent bit line layers 108 along the stacking direction of the initial stacked structure 101 and reduces the parasitic capacitance between two adjacent bit line layers 108 along the stacking direction of the initial stacked structure 101, thereby providing the performance of the semiconductor structure.

[0124] Based on the same technical concept as the aforementioned semiconductor structure formation method, this disclosure provides a semiconductor structure. Figure 34 The semiconductor structure shown corresponds to Scheme 1 in the above-mentioned method for forming the semiconductor structure. Figure 35 The semiconductor structure shown corresponds to Scheme 2 and Scheme 3 in the above-mentioned semiconductor structure formation method.

[0125] like Figure 34 as well as Figure 35 As shown, the semiconductor structure includes: a stacked structure 130, including alternating bit line layers 108 and dielectric layers 107; wherein, the stacked structure 130 includes a plurality of first trenches 104 extending through the stacked structure 130; the bit line layers 108 have a plurality of first bit line portions 131 located on both sides of the first trenches 104 along a first direction and a second bit line portion 132 located on one side of the plurality of first bit line portions 131 along a second direction, the second bit line portion 132 extending along the first direction; and a cavity 110 is provided in the dielectric layer 107 between adjacent first trenches 104.

[0126] It is understood that in this embodiment of the present disclosure, there is a cavity 110 between two adjacent bit line layers 108 along the stacking direction of the stacking structure 130. This reduces the coupling effect between the two adjacent bit line layers 108 along the stacking direction of the stacking structure 130 and reduces the parasitic capacitance generated between the two adjacent bit line layers 108 along the stacking direction of the stacking structure 130, thereby effectively improving the performance of the memory.

[0127] In some specific examples, the material of bit line layer 108 includes, but is not limited to, tungsten.

[0128] It is understood that using tungsten as the material for the bit line layer 108 in this embodiment can reduce bit line resistance and improve memory performance.

[0129] In some specific examples, the dielectric layer 107 may be made of a low-dielectric-constant material, including but not limited to silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride, or silicon oxynitride. It is understood that using a low-dielectric-constant material for the dielectric layer 107 in this embodiment can further reduce the coupling effect and parasitic capacitance between two adjacent bit line layers 108 along the stacking direction of the stacked structure 130.

[0130] In some embodiments, such as Figure 34 As shown, a plurality of first grooves 104 are arranged along a first direction, the width of the second line portion 132 along the second direction is H1, the width of the first line portion 131 along the first direction is H2, and the ratio of H2 to H1 is greater than 2; the first direction is perpendicular to the second direction and both are perpendicular to the stacking direction of the stacked structure 130.

[0131] In some embodiments, the ratio of H2 to H1 ranges from 3 to 6.

[0132] In some embodiments, such as Figure 34 As shown, the cavity 110 is located between the first line portions 131 adjacent to each other along the stacking direction, and the cavity 110 and the two first trenches 104 adjacent to each other along the first direction each have a dielectric layer 107.

[0133] In some embodiments, such as Figure 35 As shown, the ratio of H2 to H1 is greater than 6. The stacked structure 130 also includes a third trench 124 that runs through the stacked structure 130. The third trench 124 is located between two adjacent first trenches 104. The distance between the third trench 124 and the adjacent first trench 104 along the first direction is H3. The ratio of H3 to H1 is in the range of 3-6.

[0134] In some embodiments, the cavity 110 is located between the first line portion 131 adjacent to each other along the stacking direction and between the second line portion 132 adjacent to each other along the stacking direction, and the cavity 110 is located on both sides of the third trench 124 along the first direction and on one side along the second direction. A dielectric layer 107 is provided between the first trench 104 and the cavity 110, and the third trench 124 communicates with the cavity 110.

[0135] Based on the above semiconductor structure, this disclosure also provides a memory, including the semiconductor structure of any of the above embodiments.

[0136] In some specific examples, the memory includes, but is not limited to, dynamic random access memory, static random access memory (SRAM), phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), resistive random access memory (RRAM), and flash memory.

[0137] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative; for example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the various components shown or discussed are coupled to each other or directly coupled.

[0138] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0139] This disclosure provides specific embodiments, but its scope of protection is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: An initial stacking structure is provided, the initial stacking structure comprising alternating layers of first and second sacrificial layers; Multiple first trenches are formed that penetrate the initial stacked structure; Laterally etch along the first trench to remove a first portion of each of the first sacrificial layers, forming a plurality of first filling regions; A dielectric layer is formed in each of the first filled regions; The second sacrificial layer is removed to form multiple second fill regions, and a bit line layer is formed in each of the second fill regions; The second portion of each retained first sacrificial layer is removed to form multiple cavities.

2. The forming method according to claim 1, characterized in that, Multiple first trenches are arranged along a first direction. The distance between the sidewall of the first trench parallel to the first direction and the edge of the initial stacked structure along the second direction is H1. The distance between two adjacent first trenches along the first direction is H2, and the ratio of H2 to H1 is greater than 2. The first direction is perpendicular to the second direction and both are perpendicular to the stacking direction of the initial stacked structure.

3. The forming method according to claim 1, characterized in that, The removal of the second sacrificial layer to form multiple second filling regions, wherein a bit line layer is formed in each second filling region, includes: Laterally etch along the first trench to remove the third portion of each second sacrificial layer, forming a plurality of third filling regions; Each of the third filling regions is filled with a conductive material; the conductive material is filled between the fourth portions of each retained second sacrificial layer; Remove the fourth part to form multiple fourth filling regions; The conductive material is filled in each of the fourth filling regions; the conductive material in the third filling regions and the fourth filling regions constitutes the bit line layer.

4. The forming method according to claim 3, characterized in that, After a dielectric layer is formed in each of the first filling regions, the dielectric layer fills the space between the second portions of each of the retained first sacrificial layers; The removal of the fourth part and the removal of the second part include: After each of the third filling regions is filled with conductive material, a second trench is formed that penetrates the initial stacked structure; the second trench exposes the sidewalls of the fourth portion and the sidewalls of the second portion; Laterally etch along the second trench to remove the fourth portion; Laterally etch along the second trench to remove the second portion.

5. The forming method according to claim 1, characterized in that, The method further includes: Before etching laterally along the first trench to remove a first portion of each of the first sacrificial layers, a third sacrificial layer is filled in at least a portion of the first trench; After a dielectric layer is formed in each of the first filled regions, the third sacrificial layer is removed to form a fourth trench that exposes the sidewalls of the second portion.

6. The forming method according to claim 5, characterized in that, The removal of the second sacrificial layer to form multiple second filling regions, wherein a bit line layer is formed in each second filling region, includes: A fourth sacrificial layer is filled in the first trench, and the fourth trench is laterally etched to remove the fifth portion of each second sacrificial layer, forming a plurality of fifth filling regions; Each of the fifth filling regions is filled with conductive material; Remove the fourth sacrificial layer, and remove the sixth portion of each retained second sacrificial layer along the first trench to form a plurality of sixth filling regions; The conductive material is filled in each of the sixth filling regions; the conductive material in the fifth and sixth filling regions constitutes the bit line layer.

7. The forming method according to claim 1, characterized in that, The method further includes: a plurality of the first trenches are arranged along a first direction. After a dielectric layer is formed in each of the first filling regions, a third trench is formed between two adjacent first trenches, the third trench penetrating the initial stack structure and exposing the sidewall of the second portion; the distance between the third trench and the adjacent first trench along the first direction is H3, and the distance between the sidewall of the third trench or the first trench parallel to the first direction and the edge of the initial stack structure along the second direction is H1, the ratio of H3 to H1 is greater than 2; the first direction and the second direction are perpendicular to each other and both are perpendicular to the stacking direction of the initial stack structure.

8. The forming method according to claim 7, characterized in that, The removal of the second sacrificial layer to form multiple second filling regions, wherein a bit line layer is formed in each second filling region, includes: Laterally etch along the third trench to remove the seventh portion of each second sacrificial layer, forming a plurality of seventh filling regions; Each of the seventh filling regions is filled with conductive material; Laterally etch along the first trench to remove the eighth portion of the retained second sacrificial layer, forming a plurality of eighth filling regions; The conductive material is filled in each of the eighth filling regions; the conductive materials in the seventh and eighth filling regions constitute the bit line layer; The removal of a second portion of each retained first sacrificial layer includes: lateral etching along the third trench to remove a second portion of each retained first sacrificial layer.

9. A semiconductor structure, characterized in that, include: Stacked structures, including alternating layers of bit lines and dielectric layers; The stacked structure includes a plurality of first trenches that penetrate the stacked structure; The bit line layer has a plurality of first bit line portions located on both sides of the first trench along a first direction and a second bit line portion located on one side of the plurality of first bit line portions along a second direction, the second bit line portion extending along the first direction; The dielectric layer between adjacent first trenches has a cavity.

10. The semiconductor structure according to claim 9, characterized in that, Multiple first grooves are arranged along a first direction, the width of the second bit line portion along the second direction is H1, the width of the first bit line portion along the first direction is H2, and the ratio of H2 to H1 is greater than 2; the first direction is perpendicular to the second direction and both are perpendicular to the stacking direction of the stacked structure.

11. The semiconductor structure according to claim 10, characterized in that, The ratio of H2 to H1 ranges from 3 to 6.

12. The semiconductor structure according to claim 11, characterized in that, The cavity is located between the first bit lines adjacent to each other along the stacking direction, and each cavity has a dielectric layer between itself and the two first trenches adjacent to each other along the first direction.

13. The semiconductor structure according to claim 10, characterized in that, The ratio of H2 to H1 is greater than 6. The stacked structure also includes a third trench that runs through the stacked structure. The third trench is located between two adjacent first trenches. The distance between the third trench and the adjacent first trench along the first direction is H3. The ratio of H3 to H1 is in the range of 3-6.

14. The semiconductor structure according to claim 13, characterized in that, The cavity is located between the first bit line portions adjacent to each other along the stacking direction and between the second bit line portions adjacent to each other along the stacking direction, and the cavity is located on both sides of the third trench along the first direction and on one side along the second direction. A dielectric layer is provided between the first trench and the cavity, and the third trench is in communication with the cavity.

15. A memory, characterized in that, Including the semiconductor structure as described in any one of claims 9-14.

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